Data transmission method

Abstract

The application is suitable for the field of communication technology, and provides a data transmission method, which comprises the following steps: obtaining original data to be sent; constructing a target data frame and sending the target data frame to a receiving end; wherein the original data comprises user data and user application layer check information; the target data frame comprises a frame header, a data payload area containing the original data, and a frame tail containing link transmission layer check information; the link transmission layer check information is used for checking the frame header and the data payload area, and the user application layer check information is used for checking the user data. The method can quickly and accurately determine the error transmission type of data in the transmission process, so as to realize accurate hierarchical positioning of link physical layer errors and user data logical errors.

Description

Technical Field

[0001] This application belongs to the field of communication technology, and in particular relates to a data transmission method. Background Technology

[0002] With the increasing demands for reliability and real-time performance in data transmission, Field-Programmable Gate Arrays (FPGAs) are widely used for high-speed data exchange between devices via point-to-point serial links due to their parallel processing and low latency characteristics. These links often employ Low-Voltage Differential Signaling (LVDS) interfaces to achieve interference-resistant transmission. However, due to hardware wiring limitations, typically only one unidirectional differential pair carries all information transmission, with no independent return path.

[0003] Traditional methods commonly include: achieving bit synchronization at the physical layer through clock data recovery and 8B / 10B encoding; using a single-layer cyclic redundancy check (CRC) to cover the entire frame data at the link layer; relying on an additional synchronization frame channel to transmit management information; or using a two-way handshake protocol for state negotiation.

[0004] However, the above-mentioned existing technologies have the following drawbacks: single-layer verification cannot distinguish between bit errors introduced by the physical transmission of the link and errors in the content of the user data itself. When the verification fails, the source of the fault cannot be located, which results in double the time required for link physical layer troubleshooting and upper layer logic checks. Summary of the Invention

[0005] This application provides a data transmission method that can quickly and accurately determine the error transmission type of data during transmission, thereby achieving precise hierarchical positioning of link physical layer errors and user data logical errors.

[0006] In a first aspect, embodiments of this application provide a data transmission method applied at a sending end, wherein the sending end is connected to a receiving end via a unidirectional communication link; the data transmission method includes: Obtain the raw data to be sent; the raw data includes user data and user application layer verification information; Construct the target data frame and send the target data frame to the receiving end; The target data frame includes a frame header, a data payload area containing the original data, and a frame trailer containing link transport layer verification information. The link transport layer verification information is used to verify the frame header and data payload area, and the user application layer verification information is used to verify the user data. The link transport layer verification information is generated by accumulating the data words in the frame header and data payload area during the transmission of the frame header and data payload area, and the link transport layer verification information is sent to the receiving end when the data payload area is completely transmitted.

[0007] In one possible implementation of the first aspect, constructing a target data frame and sending the target data frame to the receiving end includes: sequentially sending data words corresponding to the frame header and data payload area to the receiving end according to a preset data bit width; for each data word in the frame header and data payload area, when the data word begins to be sent, dividing the data word into a first part and a second part, and accumulating the first part and the second part into the total check value; when the last data word in the data payload area begins to be sent and the accumulation is completed, determining the total check value as the link transport layer check information, and sending the link transport layer check information to the receiving end according to the preset data bit width at the moment when the last data word in the data payload area is sent.

[0008] In one possible implementation of the first aspect, when the data word begins to be transmitted, the method further includes: for each clock cycle, converting at least two data bits in the data word into serial differential signals and outputting them to the receiving end through a first channel in a unidirectional communication link; generating a local differential clock based on the local clock and outputting it to the receiving end through a second channel in a unidirectional communication link so that the receiving end can recover the sampling clock.

[0009] In one possible implementation of the first aspect, before sequentially sending the data words corresponding to the frame header and data payload area to the receiving end according to the preset data bit width, the method further includes: obtaining the port number and frame length from the control element information associated with the original data; and assembling the port number, frame length, preset preamble, and current frame sequence number corresponding to the original data to form a frame header.

[0010] Secondly, embodiments of this application provide a data transmission method applied at a receiving end, wherein the receiving end is connected to the sending end via a unidirectional communication link; the data transmission method includes: The receiver receives the target data frame sent by the sending end. The target data frame includes a frame header, a data payload area containing the original data, and a frame trailer containing link transport layer verification information. The original data includes user data and user application layer verification information. The link transport layer verification information is used to verify the frame header and data payload area, and the user application layer verification information is used to verify the user data. The link transport layer verification information is generated by accumulating the data words in the frame header and data payload area during the transmission of the frame header and data payload area, and the link transport layer verification information is sent to the receiving end when the data payload area is completely transmitted. The error transmission type of the target data frame is determined based on the link transport layer verification information and the user application layer verification information.

[0011] In one possible implementation of the second aspect, determining the error transmission type of the target data frame based on the link transport layer verification information and the user application layer verification information includes: determining a local link check code based on the frame header and data payload area; determining a local user check code based on the user data; comparing the local link check code with the link transport layer check code to determine the link verification result; comparing the local user check code with the user data check code to determine the user data verification result; and determining the error transmission type of the target data frame based on the link verification result and the user data verification result.

[0012] In one possible implementation of the second aspect, determining the error transmission type of the target data frame based on the link verification result and the user data verification result includes: if the link verification result indicates that the local link check code and the link transport layer verification information are successfully matched, and the user data verification result indicates that the local user check code and the user application layer verification information are successfully matched, then the error transmission type is determined to be normal reception; if the link verification result indicates that the local link check code and the link transport layer verification information are not successfully matched, then the error transmission type is determined to be a link physical transmission error; if the link verification result indicates that the local link check code and the link transport layer verification information are successfully matched, and the user data verification result indicates that the local user check code and the user application layer verification information are not successfully matched, then the error transmission type is determined to be a user data logical error.

[0013] In one possible implementation of the second aspect, the frame header includes a preset preamble and a frame length; receiving the target data frame sent by the transmitting end includes: continuously moving the received target data frame into a sliding window buffer; determining the start position of the detected target data frame when a continuous data bit segment of the target data frame in the sliding window buffer matches a preset truncated preamble feature sequence; the truncated preamble feature sequence refers to a portion of the bit segment of the preset preamble in the frame header; at the same moment the start position is detected, extracting the frame length from the sliding window buffer and determining the total number of clock cycles required to receive the target data frame based on the frame length; starting a clock cycle count, incrementing the clock cycle count by one every clock cycle until the clock cycle count reaches the total number of clock cycles, at which point closing the sliding window buffer and triggering the step of determining the error transmission type of the target data frame based on link transport layer verification information and user application layer verification information.

[0014] In one possible implementation of the second aspect, the frame header also includes the current frame sequence number corresponding to the original data; when it is determined that the error transmission type is normal reception or user data logic error, the method further includes: determining the frame-level loss status of the original data based on the current frame sequence number and the frame sequence number of the historical received frames; when it is determined that the frame-level loss status is that the original data has been lost at the frame level, updating the packet loss count.

[0015] In one possible implementation of the second aspect, after updating the packet loss count, the method further includes: mapping the packet loss count, the first count representing a physical transmission error of the link, and the second count representing a normal reception of the link as statistical values ​​of a preset bit width; concatenating the statistical values ​​into a status value; and outputting the status value in response to a single read operation at the processor end, so that the processor end can evaluate the link quality based on the status value.

[0016] Thirdly, embodiments of this application provide a data transmission device configured at a transmitting end, the transmitting end being connected to a receiving end via a unidirectional communication link; the data transmission device includes: The acquisition module is used to acquire the raw data to be sent; the raw data includes user data and user application layer verification information. The sending module is used to construct the target data frame and send it to the receiving end. The target data frame includes a frame header, a data payload area containing the original data, and a frame trailer containing link transport layer verification information. The link transport layer verification information is used to verify the frame header and the data payload area, and the user application layer verification information is used to verify the user data. The link transport layer verification information is generated by accumulating the data words in the frame header and the data payload area during the transmission of the frame header and the data payload area, and the link transport layer verification information is sent to the receiving end when the data payload area is completely transmitted.

[0017] Fourthly, embodiments of this application provide a data transmission device configured at a receiving end, the receiving end being connected to the sending end via a unidirectional communication link; the data transmission device includes: The receiving module is used to receive the target data frame sent by the sending end. The target data frame includes a frame header, a data payload area containing the original data, and a frame trailer containing link transport layer verification information. The original data includes user data and user application layer verification information. The link transport layer verification information is used to verify the frame header and data payload area, and the user application layer verification information is used to verify the user data. The link transport layer verification information is generated by accumulating the data words in the frame header and data payload area during the transmission of the frame header and data payload area, and the link transport layer verification information is sent to the receiving end when the data payload area is completely transmitted. The identification module is used to determine the error transmission type of the target data frame based on the link transport layer verification information and the user application layer verification information.

[0018] Fifthly, embodiments of this application provide a computer device, including a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, it implements the data transmission method of any of the first aspects or the data transmission method of any of the second aspects.

[0019] Sixthly, embodiments of this application provide a computer-readable storage medium storing a computer program that, when executed by a processor, implements the data transmission method of any of the first aspects or the data transmission method of any of the second aspects.

[0020] In a seventh aspect, embodiments of this application provide a computer program product that, when run on a terminal device, causes the terminal device to execute the data transmission method of any of the first aspects or the data transmission method of any of the second aspects.

[0021] The beneficial effects of the embodiments in this application compared with the prior art are: This application provides a data transmission method in which the sending end and receiving end are connected only through a one-way communication link, without relying on any feedback channel or bidirectional handshake protocol, thus establishing the constraint that the receiving end cannot send back any status information to the sending end. Under this constraint, the sending end obtains the original data containing user data and user application layer verification information, and constructs a target data frame containing a frame header, a data payload area (carrying the original data), and a frame tail (carrying link transport layer verification information), providing a structural basis for subsequent two-layer independent verification. Specifically, the sending end designs the link transport layer verification information to verify the frame header and data payload area, while limiting the user application layer verification information to verify only the user data itself. Since the coverage of the two layers of verification information is clearly different, the receiving end can perform two sets of independent verification calculations in parallel after receiving the target data frame: on the one hand, it judges the physical transmission error of the link through the link transport layer verification information (i.e., verifies the integrity of the frame header and data payload area); on the other hand, it judges the logical correctness of the user data itself through the user application layer verification information. Based on the two verification results calculated by itself, the receiving end can distinguish the two different types of transmission errors online, without the sending end's participation or any feedback information. Furthermore, since the link transport layer verification information (LTL-C) is generated by accumulating the data words in the frame header and data payload during the transmission of the frame header and data payload, and is sent to the receiving end when the data payload transmission is completed, the generation of LTL-C is completely synchronized with the data transmission process in the time domain. This avoids the additional delay and storage overhead introduced by the sending end calculating LTL-C separately after data transmission, and ensures that the receiving end can immediately obtain the LTL-C as soon as it receives the last data word in the data payload. This allows for simultaneous frame tail detection and link layer integrity verification, ensuring that the receiving end can accurately identify link physical transmission errors in real time even without any feedback. Therefore, this application effectively overcomes the technical shortcomings of traditional single-layer verification, which cannot distinguish the source of errors and requires twice the time for fault location. It quickly and accurately determines the type of erroneous data transmission during transmission, thereby achieving precise hierarchical location of link physical layer errors and user data logic errors, and is particularly suitable for unidirectional communication scenarios without feedback constraints. Attached Figure Description

[0022] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1This is an application environment diagram of a data transmission method provided in this application; Figure 2 This is a flowchart illustrating a data transmission method applied to the sending end provided in this application; Figure 3 This is a schematic diagram of a process for constructing and sending a target data frame at the sending end, as provided in this application. Figure 4 This is a flowchart illustrating a data transmission method applied at the receiving end provided in this application; Figure 5 This is a flowchart illustrating a method for determining the type of erroneous transmission at the receiving end, as provided in this application. Figure 6 This is a schematic diagram of a process for receiving target data frames at the receiving end, as provided in this application. Figure 7 This is a schematic diagram of a data transmission device configured at the transmitting end according to this application; Figure 8 This is a schematic diagram of a data transmission device configured at the receiving end according to this application; Figure 9 This is a schematic diagram of the structure of a computer device provided in an embodiment of this application. Detailed Implementation

[0024] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of this application. However, those skilled in the art will understand that this application may also be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, apparatuses, circuits, and methods have been omitted so as not to obscure the description of this application with unnecessary detail.

[0025] It should be understood that, when used in this application specification and the appended claims, the term "comprising" indicates the presence of the described features, integrals, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or a collection thereof.

[0026] It should also be understood that the term “and / or” as used in this application specification and the appended claims means any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0027] As used in this application specification and the appended claims, the term "if" may be interpreted, depending on the context, as "when," "once," "in response to determination," or "in response to detection." Similarly, the phrase "if determined" or "if detected [the described condition or event]" may be interpreted, depending on the context, as meaning "once determined," "in response to determination," "once detected [the described condition or event]," or "in response to detection [the described condition or event]."

[0028] Furthermore, in the description of this application and the appended claims, the terms "first," "second," "third," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0029] References to "one embodiment" or "some embodiments" as described in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.

[0030] In high-reliability real-time control equipment (such as functional boards in relay protection and industrial control), different functional modules often need to exchange data at high speed through point-to-point serial links implemented within the FPGA. LVDS is widely used for such inter-board interconnection due to its strong anti-interference capabilities, low power consumption, and high transmission rate. This application scenario has two key constraints: ① A single physical differential pair carries all information transmission, with no separate return path (one-way point-to-point); ② Link-layer management messages (self-test, configuration) and application-layer service data frames are simultaneously transmitted on the link, and the two types of data have different requirements for integrity assurance.

[0031] Under these constraints, research revealed the following main problems with existing technologies: First, relying on additional physical channels to transmit management information (such as dedicated synchronization frame channels) increases hardware wiring costs. Second, relying on bidirectional feedback channels for state negotiation is unsuitable for unidirectional link scenarios. Third, it only provides physical layer clock recovery and word alignment capabilities, lacking link layer frame format design. Fourth, while single-layer whole-frame verification (such as CRC) can detect frame errors, it cannot distinguish whether the error is caused by physical transmission errors (link layer problems) or errors in the user data itself (application layer problems), exhibiting the deficiency of single-layer verification failing to pinpoint faults at different levels. Consequently, when verification fails, maintenance personnel cannot determine whether the fault source is the physical link (such as signal quality or electromagnetic interference) or upper-layer logic (such as software calculation errors), requiring double the time for both physical layer troubleshooting and upper-layer logic checks, severely reducing fault location efficiency.

[0032] To overcome the above-mentioned shortcomings, this application provides a data transmission method that can be applied to, for example... Figure 1 In the application environment shown, the processor 101 can be a central processing unit, microcontroller, digital signal processor, or embedded soft-core processor, used to generate the raw data to be transmitted and read link quality statistics (i.e., status values); the transmitter 102 and receiver 103 are the transmitting logic module and receiving logic module implemented internally by a field-programmable gate array, respectively. The processor 101 and transmitter 102 are connected via an internal bus, the transmitter 102 and receiver 103 are connected via a unidirectional communication link consisting of a pair of low-voltage differential signal differential lines, and the receiver 103 and processor 101 are connected via an internal bus.

[0033] During data transmission, the processor 101 first writes the raw data to be transmitted into the asynchronous dual-port storage unit of the transmitter 102. This raw data includes user data and user application layer verification information. Simultaneously, it writes the corresponding control metadata (including port number, frame length, and the starting address of the raw data in the asynchronous dual-port storage unit) into an asynchronous first-in-first-out queue. The transmitter 102 reads the control metadata from the asynchronous first-in-first-out queue and, based on the control metadata, reads the raw data from the asynchronous dual-port storage unit to construct the target data frame. This target data frame includes a frame header, a data payload area composed of the raw data, and a frame trailer containing link transport layer verification information. The transmitter 102 serially transmits the target data frame to the receiver 103 via a low-voltage differential signal differential line pair, while simultaneously outputting one accompanying differential clock.

[0034] The receiver 103 uses a low-voltage differential signal differential line to receive the serial differential signal of the target data frame, and uses the accompanying differential clock to recover the sampling clock, converting the serial differential signal into parallel data. It detects the start position of the target data frame by matching the truncated preamble, extracts the frame length, and dynamically manages the sliding window. Within the sliding window, it performs link layer verification and application layer verification in parallel based on link transport layer verification information and user application layer verification information. The receiver 103 distinguishes between physical transmission errors and user data logic errors based on the two-layer verification results. Simultaneously, it detects frame-level packet loss through frame sequence number continuity detection, aggregating packet loss count, bit error count (i.e., the first count of physical transmission errors), and normal reception count (i.e., the second count) into a three-dimensional link quality status register (storing status values). The processor 101 retrieves the status value from this three-dimensional link quality status register through a single read operation, using it as link quality statistics to evaluate link quality. It can also read correctly received data from the receiver 103's receive random access memory.

[0035] The processor 101, transmitter 102, and receiver 103 operate independently. There is only a unidirectional data link between transmitter 102 and receiver 103, with no feedback channel. Through the design of the data frame structure, receiver 103 can quickly and accurately distinguish between two different types of transmission errors online by verifying the frame header and data payload area verification results based on the link transport layer verification information and the user data verification results based on the user application layer verification information. This enables precise hierarchical positioning of link physical layer errors and user data logical errors, without the need for transmitter participation or any feedback information. The processor 101 is only responsible for data injection and result reading and does not participate in real-time link control, thus achieving highly reliable serial data transmission and hierarchical error diagnosis with extremely low processor overhead.

[0036] In one exemplary embodiment, such as Figure 2 As shown, a data transmission method is provided, which is applied to... Figure 1 Taking the transmitter 102 as an example, the transmitter is connected to the receiver via a one-way communication link; this data transmission method includes the following steps: S201, Obtain the raw data to be sent.

[0037] The raw data includes user data and user application layer verification information.

[0038] The transmitter 102 refers to the initiator of data transmission, responsible for acquiring data, constructing data frames, and sending data frames. The transmitter 102 is a hardware device, such as a transmission logic module integrated within an FPGA or ASIC.

[0039] Receiver 103 refers to the receiver of data transmission, responsible for receiving data frames sent by sender 102 and performing subsequent processing. Receiver 103 is also a hardware device, such as a receiving logic module integrated within an FPGA or ASIC, and is connected to sender 102 via a physical link.

[0040] A unidirectional communication link is a communication channel in which data can only be transmitted in one direction, that is, the data frame flows from the sending end 102 to the receiving end 103 without an independent return path. This unidirectional communication link can contain multiple pairs of differential signal lines, such as data differential pairs (used as the first channel to transmit data frames) and clock differential pairs (used as the second channel to transmit the clock, i.e., the accompanying differential clock), using differential signal transmission to improve anti-interference capability.

[0041] Raw data refers to the unencapsulated, initial data to be sent. This raw data contains the core information that the user needs to transmit, and its integrity and correctness are crucial for the application layer.

[0042] User data refers to the actual business information or application layer data carried in the original data, which is the data that ultimately needs to be delivered to the receiving end 103 application layer for processing.

[0043] User application layer verification information refers to information used to verify the integrity and correctness of user data. This verification information is generated by the application layer and transmitted along with the user data as part of the original data. The purpose of user application layer verification information is to ensure that user data is not tampered with or corrupted during transmission.

[0044] One possible approach is to receive raw data from an external interface, such as data packets received via an Ethernet interface, and use them as raw data after preliminary parsing. Another possible approach is to generate the raw data at the processor end 101 and store it in a specific storage unit, such as a dual-port RAM (Random Access Memory) or a FIFO (First In First Out) queue. The transmitting end 102 can periodically read data from these storage units as raw data to be transmitted. In these implementations, the raw data is treated as a whole, awaiting further encapsulation and transmission.

[0045] The raw data includes user data and user application layer verification information. User data is the actual business payload, such as video streams, sensor data, or control commands. User application layer verification information is a checksum associated with the user data, such as a CRC checksum or hash value, designed to ensure the integrity of the user data at the application layer. As one possible approach, the user data and user application layer verification information can be generated by the processor 101 and packaged together to form the raw data. For example, the image processing module of the processor 101 can generate image pixel data (user data), calculate the CRC checksum of the image data (user application layer verification information), and then merge the two to form the raw data.

[0046] As an optional implementation, in addition to the user business data such as the user data and user application layer verification information mentioned above, the raw data may also include link layer management messages, such as self-test status and configuration information.

[0047] As another optional implementation, obtaining the raw data to be sent includes: reading control metadata associated with the raw data from the asynchronous first-in-first-out queue, and reading the raw data from the asynchronous dual-port storage unit according to the control metadata; wherein, the asynchronous dual-port storage unit stores the raw data written by the processor 101; the asynchronous first-in-first-out queue stores the control metadata written by the processor 101; the control metadata includes the port number, frame length, and the starting address of the raw data in the asynchronous dual-port storage unit.

[0048] An asynchronous first-in-first-out (FIFO) queue is a type of FIFO buffer characterized by independent write and read operations, even operating in different clock domains. This asynchronous FIFO queue can decouple the timing relationship between the data writer (e.g., processor 101) and the data reader (e.g., the transmission module), effectively handling data bursts and rate mismatches. The asynchronous FIFO queue can be implemented using hardware logic, such as through dual-port RAM with read / write pointers and control logic, or by utilizing readily available FIFO IP (Intellectual Property) cores.

[0049] Control metadata refers to auxiliary information used to describe or associate raw data. Its function is to provide key parameters of the raw data, such as the destination port, data length, and the specific location of the data in the storage unit. This control metadata can be a structured data packet containing various parameters required for data transmission; or it can be configuration values ​​stored in a specific register group.

[0050] An asynchronous dual-port memory unit refers to a type of memory that allows simultaneous access from two independent ports, which can operate asynchronously. This asynchronous dual-port memory unit enables the processor 101 to write raw data to it, while the sending end 102 can simultaneously read data from it, thereby avoiding access conflicts and improving data throughput. The asynchronous dual-port memory unit can be implemented using a dual-port RAM block in hardware, or through a shared memory region combined with hardware arbitration logic.

[0051] The port number is used to uniquely identify the logical channel or target application of the data flow. It can be a specific integer value, such as a number between 0 and 65535, used to distinguish different services or applications; or it can be a predefined enumeration type, with each enumeration value corresponding to a specific functional module.

[0052] Frame length refers to the overall size of the current data frame, expressed in bytes or data words. The purpose of frame length is to enable the receiver 103 to accurately determine the end position of a data frame, thereby allowing for correct data interception and processing. Frame length can be an unsigned integer, for example, representing the total length of the data payload area plus the frame header and trailer.

[0053] The starting address refers to the physical storage location number of the original data in the asynchronous dual-port storage unit, which is used to provide the physical location of the original data in the asynchronous dual-port storage unit.

[0054] Before the transmitter 102 begins constructing the target data frame, the processor 101 has already written the raw data to be sent into the asynchronous dual-port storage unit, and simultaneously written the control metadata associated with the raw data into the asynchronous first-in-first-out queue. The control metadata includes at least the port number, frame length, and the starting address of the raw data in the storage unit. The state machine of the transmitter 102 continuously monitors whether the asynchronous first-in-first-out queue is not empty in the idle state. Once it detects that control metadata has been written, it reads the control metadata from the asynchronous first-in-first-out queue, and reads the corresponding raw data from the asynchronous dual-port storage unit based on the starting address and frame length obtained from the control metadata.

[0055] As an alternative implementation, the transmitter 102 employs a dual-buffered architecture that separates the data body (i.e., raw data) from the descriptor (i.e., control metadata). An asynchronous dual-port RAM (64-bit wide) (i.e., asynchronous dual-port storage unit) stores the data body of the message to be transmitted (i.e., raw data including user service data and link layer management messages), written by the clock domain of the processor 101. A 40-bit wide asynchronous descriptor FIFO (i.e., asynchronous first-in-first-out queue) stores only the descriptor (8-bit port number, 16-bit frame length, and 16-bit RAM start address) of each frame of the message data body to be transmitted. A FIFO write operation is triggered after the processor 101 completes the writing of the current frame of the message data body. Both are asynchronously designed; the write clock comes from the processor 101, and the read clock comes from the LVDS transmission link side (i.e., transmitter 102). This architecture minimizes the amount of data synchronized across clock domains (only 40-bit descriptors), allowing multiple frames of the message data body to be transmitted to be queued sequentially at the processor 101, enabling the transmitter 102 and processor 101 to operate in high parallel.

[0056] Through the above technical solution, this application achieves efficient and synchronous acquisition of raw data and its associated control metadata. By utilizing an asynchronous first-in-first-out queue and an asynchronous dual-port storage unit, the data generation and transmission module's data reading processes on the processor side (101) are effectively decoupled, thus avoiding data transmission bottlenecks caused by timing differences. The control metadata explicitly includes the port number, frame length, and the starting address of the raw data in the storage unit, enabling the transmission module to accurately locate and acquire the required data, significantly improving the accuracy and integrity of data transmission. This structured data acquisition mechanism provides a stable and reliable data stream for subsequent data frame construction and transmission, thereby improving the throughput and reliability of the entire data transmission system.

[0057] S202, construct the target data frame and send the target data frame to the receiving end 103.

[0058] The target data frame includes a frame header, a data payload area containing the original data, and a frame trailer containing link transport layer verification information. The link transport layer verification information is used to verify the frame header and data payload area, and the user application layer verification information is used to verify the user data. The link transport layer verification information is generated by accumulating the data words in the frame header and data payload area during the transmission of the frame header and data payload area, and the link transport layer verification information is sent to the receiving end when the data payload area is completely transmitted.

[0059] A target data frame is a data structure constructed by the sending end 102 for transmission over a unidirectional communication link. This target data frame is the basic unit of data transmission, containing components such as a frame header, data payload area, and frame trailer, used for data encapsulation, transmission, and verification.

[0060] The frame header is the beginning of the target data frame, containing control information such as frame synchronization, frame length indication, and port number. This frame header enables the receiver 103 to identify the start of the frame and parse its structure.

[0061] The data payload area refers to the portion of the target data frame used to carry the original data (including user data and user application layer verification information). This data payload area is the main body of the data frame and carries the actual transmitted content.

[0062] The frame trailer is the end portion of the target data frame, containing link transport layer verification information. This frame trailer is used to verify the frame header and data payload area to ensure data integrity during physical link transmission.

[0063] Link-transport layer check information (LTL-C) refers to information used to verify the integrity of data in the frame header and data payload area. This LTL-C is generated by the sender 102 at the LTL layer and placed at the end of the frame. The purpose of the LTL-C is to detect whether errors, such as bit flips or loss, occur during data transmission over the physical link.

[0064] A data word is the smallest transmission unit in the frame header and data payload area.

[0065] The raw data is encapsulated into a format suitable for transmission over a unidirectional communication link to construct the target data frame. As one implementation, the transmitter 102 can use a state machine to control the frame construction process, assembling the frame header, data payload area, and frame trailer sequentially according to a predetermined protocol format. For example, the state machine first writes the frame header information, then writes the raw data byte-by-byte or word-by-word into the data payload area, and finally calculates and writes the checksum information into the frame trailer. Another implementation is that the transmitter 102 can utilize hardware logic circuits, such as shift registers and multiplexers, to combine different parts of the data into the target data frame in parallel. For example, frame header generation, data payload area filling, and frame trailer generation can work in parallel, splicing their respective data into a complete target data frame at a specific timing.

[0066] The target data frame includes a frame header, a data payload area containing the original data, and a frame trailer containing transport layer check information. The frame header identifies the start of the frame and provides control information, the data payload area carries the actual original data, and the frame trailer contains transport layer check information. As one implementation, the frame header can include a fixed synchronization word, a field indicating the frame length, and a field indicating the data type. The data payload area is directly filled with the original data. The frame trailer can be a simple checksum. For example, the sender 102 can preset a 16-bit synchronization word as the frame header, followed by an 8-bit frame length field, then the original data, and finally a 16-bit CRC checksum as the frame trailer. Another implementation is that the frame header can include more complex routing information or a timestamp. The data payload area can use some encoding method (e.g., 8B / 10B encoding) to improve transmission reliability. The transport layer check information in the frame trailer can use a stronger check algorithm, such as 32-bit CRC.

[0067] This link transport layer checksum information is designed to detect errors that may occur during the transmission of the target data frame through the physical link. As one implementation, when constructing the target data frame, the sending end 102 can accumulate and calculate the sum of all data bits in the frame header and data payload area, using the resulting checksum as the link transport layer checksum information. For example, the sending end 102 can perform an XOR operation on all bytes in the frame header and data payload area, using the final result as the checksum information. Another implementation is that the sending end 102 can employ a more complex checksum algorithm, such as using CRC to calculate the data stream in the frame header and data payload area, generating a CRC code as the link transport layer checksum information. This CRC code can effectively detect burst errors and random errors during transmission.

[0068] This user application-layer verification information aims to ensure the integrity and correctness of user data at the application layer. One implementation could be a simple parity bit used to detect single-bit errors in the user data. For example, a parity bit could be appended to every 8 bits of user data. Another implementation could be a more robust checksum, such as a SHA-256 (Secure Hash Algorithm 256-bit) hash value, which provides a higher level of data integrity verification and can even be used to detect data tampering. This user application-layer verification information can be calculated during user data generation and transmitted as part of the original data.

[0069] The method described in this embodiment achieves layered verification by encapsulating user data and user application layer verification information within the original data, and further encapsulating the original data within a target data frame containing link transport layer verification information. The user application layer verification information ensures the integrity of the user data itself. Even if the link transport layer verification passes, if the user application layer verification fails, the receiver 103 can identify that the error is a logical error in the user data rather than a physical transmission error in the link. Simultaneously, the link transport layer verification information focuses on detecting whether errors occur in the frame header and data payload area during physical link transmission. This layered verification mechanism allows the receiver 103 to more accurately determine the source of the error based on different verification results when an error is detected, thus avoiding the drawback of traditional single-layer verification being unable to distinguish the type of error transmission. For example, if the link transport layer verification fails, it indicates a physical transmission error in the link; if the link transport layer verification succeeds but the user application layer verification fails, it indicates a logical error in the user data or an error introduced during application layer processing. Therefore, the method in this embodiment can accurately distinguish errors from different sources, making fault location faster and more accurate, reducing the time and cost of fault diagnosis, and thus providing a more efficient and intelligent error detection and location solution for high-speed unidirectional data transmission systems.

[0070] In actual implementation, if the calculation and transmission of the link transport layer check information are separated from the transmission of data words, that is, the check information is only calculated after all data words have been transmitted, it may also cause a delay in the transmission of check information, thereby affecting the real-time performance and efficiency of data transmission, especially in application scenarios with high bandwidth and low latency requirements.

[0071] Therefore, based on the above embodiments, in an exemplary embodiment, the process of constructing and sending the target data frame in S202 is further refined. Optionally, as... Figure 3 As shown, it may include: S301, according to the preset data bit width, sequentially send the corresponding data words of the frame header and data payload area to the receiving end 103.

[0072] The preset data bit width refers to the number of bits of data transmitted in parallel on the transmission channel, such as 8 bits, 16 bits, 32 bits, or 64 bits.

[0073] The frame header and data payload area can be divided into several data words according to a preset data bit width. Each data word is then transmitted sequentially, one after another, following their original order in the frame header and data payload area. One feasible approach is to use a parallel data bus interface with a width matching the preset data bit width, loading each data word onto the parallel data bus and transmitting it synchronously using a clock signal. Another feasible approach is to use a serial-to-parallel converter. If the width of the data word stored internally by the transmitting end 102 is greater than the preset data bit width, the serial-to-parallel converter is used to split it into multiple narrower data words of the preset data bit width before transmission. If the width of the data word stored internally by the transmitting end 102 is less than the preset bit width, a multiplexer is used to combine the multiple narrower data words into a data word of the preset bit width, which is then transmitted using the serial-to-parallel converter.

[0074] S302, for each data word in the frame header and data payload area, when the data word begins to be transmitted, the data word is divided into a first part and a second part, and the first part and the second part are added to the total check value.

[0075] The first part and the second part both refer to the data words obtained after splitting the data words.

[0076] The total check value is the sum of the first and second parts of each data word. This total check value serves as the final link transport layer check information.

[0077] This step is essentially a real-time calculation of the link transport layer checksum. At the moment each data word in the frame header and data payload begins transmission—that is, just before the data word is sent out of the transmission link—it is immediately used for checksum calculation. Specifically, the data word is split into a first part and a second part, and these parts are accumulated separately. For example, in parallel CRC calculation, a wide data word can be split into multiple narrower parts, resulting in a first part and a second part. The CRC of each part is calculated in parallel, and then the results are accumulated and combined. This method of calculating while transmitting allows the calculation of the link transport layer checksum to proceed in parallel with the transmission of the data word, significantly reducing the time required for checksum calculation.

[0078] As an optional implementation, the above process can be implemented using a hardware check generator. Specifically, when the hardware check generator receives each data word, it inputs the data word into its internal logic circuit. The data word can be split into a first part and a second part by logic gates (e.g., split according to a preset splitting bit width), and then sent to different accumulators or CRC calculation units respectively. The calculation results of the first part and the second part are then merged into the total check value. Alternatively, the above process can be implemented using an FPGA. Inside the FPGA, a dedicated logic block can be configured to perform the splitting and accumulation operations of the data word. For example, a 32-bit data word can be split into two 16-bit parts (i.e., the first part and the second part). Each part is independently XORed and shifted with the current CRC register to achieve parallel accumulation.

[0079] S303: When the last data word in the data payload area starts to be sent and the accumulation is completed, the total check value is determined as the link transport layer check information, and at the moment when the last data word in the data payload area is sent, the link transport layer check information is sent to the receiving end 103 according to the preset data bit width.

[0080] When the last data word in the data payload area begins transmission and completes its accumulation operation, the total check value already contains the check information for the frame header and all data words in the data payload area. Therefore, this total check value can be identified as the link transport layer check information, avoiding additional waiting time. Subsequently, at the moment the last data word in the data payload area is transmitted, the transmitting end 102 immediately sends the link transport layer check information to the receiving end 103 according to the preset data bit width. This step ensures that the link transport layer check information is generated and sent immediately after the data payload area is transmitted, guaranteeing that the check information follows the data to form a complete data frame, thus achieving real-time check information.

[0081] As an optional implementation, the above process can be implemented using a state machine and control logic. Specifically, the state machine tracks the transmission progress of data words. When it detects that the last data word in the data payload area has started to be transmitted and completed its accumulation operation, a signal is triggered to lock the currently accumulated total check value and use it as the link transport layer check information. Subsequently, in the next clock cycle after the last data word is transmitted, the control logic loads the link transport layer check information onto the data bus and transmits it. Alternatively, the above process can be implemented using a counter and comparator. Specifically, the counter records the number of data words transmitted. When the counter reaches a preset frame header and total number of data words in the data payload area minus one (i.e., when the last data word starts to be transmitted), the check logic completes the final accumulation and determines the final accumulation result as the link transport layer check information. When the counter reaches the total number of data words (i.e., when the last data word is transmitted), the link transport layer check information is immediately output.

[0082] As an alternative implementation, under the control of the state machine at the transmitting end 102, the above-mentioned accumulation operation is executed in parallel with the data transmission pipeline. Specifically, for the frame header word (i.e., the data word of the frame header), the state machine loads the assembled 64-bit (preset data bit width) frame header word into the shift register. In the same clock cycle as loading, the high 32 bits (i.e., the first part of the data word) and the low 32 bits (i.e., the second part) of the frame header word are fed into the adder to calculate their sum (32-bit addition, overflow is discarded). This sum is accumulated into the total check value register. Subsequently, driven by a double data rate clock, the shift register shifts right by 2 bits every clock cycle and transmits until all 64 bits are transmitted. For the data payload word (i.e., the data word in the data payload area), during the frame header word transmission, the state machine prefetches the first user data word (i.e., the first data word in the data payload area) from the asynchronous dual-port RAM. At the moment the frame header word is transmitted, the first user data word is loaded into the shift register, and the same splitting, adding, and accumulating operations are performed on it, repeating until all user data words have been processed. After the last user data word (i.e., the last data word in the data payload area) is loaded and accumulated, the value in the total check value register is the link transport layer check information. At the moment the last bit of this last user data word is transmitted, the state machine loads the total check value (padded with zeros to 64 bits, e.g., the high 32 bits are filled with 0) as a new data word into the shift register and transmits it, forming the frame tail. The shift register transmits the frame tail to the receiver 103 according to the preset data bit width. Since the accumulation operation of each data word only consumes one clock cycle (loading cycle), completely overlapping with the shift transmission, there is no additional delay during the entire transmission process.

[0083] Through the above technical solution, the transmitting end 102 can calculate the link transport layer check information in real time and in parallel during the transmission of the data frame header and data payload area, avoiding the delay caused by performing check calculation after data transmission is completed. This strategy of calculating while transmitting allows the link transport layer check information to be determined and transmitted immediately when the last data word in the data payload area is transmitted, thereby significantly improving the transmission efficiency and real-time performance of the data frame. It effectively solves the transmission delay problem that may be caused by check information generation in traditional solutions in high-speed data transmission scenarios, ensuring the continuity and low latency characteristics of the data stream.

[0084] Based on the above embodiments, in an exemplary embodiment, when the data word begins to be transmitted, the method further includes: for each clock cycle, converting at least two data bits in the data word into serial differential signals and outputting them to the receiving end 103 through a first channel in the unidirectional communication link; generating a local differential clock according to the local clock and outputting it to the receiving end 103 through a second channel in the unidirectional communication link so that the receiving end 103 can recover the sampling clock.

[0085] The clock cycle refers to a complete cycle of the clock of the transmitter 102, which can be a complete cycle of a double data rate clock, including two valid edges: the rising edge and the falling edge.

[0086] Data bits refer to the number of data bits taken from the data word in each clock cycle. They can be the two lowest bits in the data word (e.g., the 1st and 0th bits in the current shift register) and are used for serialized transmission.

[0087] Serial differential signal refers to an electrical signal that is transmitted through a pair of differential lines after parallel data is serialized bit by bit, where the voltage difference between the positive and negative lines represents a binary bit.

[0088] The first channel, also known as the data channel, refers to the pair of differential signal lines used to transmit serial differential signals in a unidirectional communication link. This pair of differential signal lines is the physical medium for transmitting differential signals and can consist of two tightly coupled wires, such as twisted-pair cables or differential traces on a PCB. This physical layout helps maintain the balance of the differential signals and further enhances noise immunity. These differential signal lines can be shielded or unshielded twisted-pair cables, suitable for short to medium-distance data transmission. Alternatively, impedance-matched differential traces can be designed on the printed circuit board to ensure signal transmission integrity and reduce reflections and crosstalk.

[0089] The local clock refers to the stable clock source generated by the phase-locked loop or crystal oscillator within the 102-chip chip at the transmitting end, which is used to generate the accompanying differential clock.

[0090] The accompanying differential clock refers to a clock signal transmitted synchronously with the serial differential signal, also transmitted through a pair of differential lines. Its frequency is related to the data transmission bit rate (typically half the bit rate, since 2 bits are transmitted per clock cycle). This accompanying differential clock can utilize the high-precision local clock inside the transmitter 102, generating a clock signal matching the data transmission rate through a clock multiplier or divider, and then converting it into differential form. Alternatively, a phase-locked loop (PLL) circuit can be used to generate a clock signal with a specific frequency and phase synchronized with the data from the local clock, and then output it differentially. This accompanying differential clock effectively solves the timing deviation problem between data and clock, especially in high-speed, long-distance transmission, significantly improving the accuracy of clock recovery at the receiver 103.

[0091] The second channel, also known as the clock channel, refers to another pair of differential signal lines in a unidirectional communication link used to transmit the accompanying differential clock.

[0092] The sampling clock is a clock signal used for timing decisions on the received serial differential signal. This sampling clock is recovered by the receiver 103 from the accompanying differential clock. Its rising and falling edges are aligned with the valid intervals of the serial data bits. The receiver 103 uses the two edges of this sampling clock to sample the data lines at double the data rate, thereby correctly extracting each bit of data and recovering it as a parallel data word. In this embodiment, the sampling clock is directly derived from the accompanying differential clock provided by the transmitter 102, without the need for additional recovery from the data stream.

[0093] When transmitter 102 begins transmitting a data word (e.g., 64-bit parallel data), the data word can first be loaded into a shift register. Subsequently, in each clock cycle of the double data rate clock, the two lowest data bits are retrieved from the data word currently stored in the shift register and immediately converted into serial differential signals: one bit is transmitted on the rising edge of the clock, and the other bit is transmitted on the falling edge of the clock, thus outputting these two data bits sequentially to receiver 103 through the first channel (a pair of differential signal lines) in the unidirectional communication link; simultaneously, the shift register shifts two bits to the right, preparing the two lowest data bits for the next clock cycle. This process is repeated, transmitting two bits each clock cycle until all bits of the entire data word have been transmitted. During data transmission, transmitter 102 can also generate a differential clock with a frequency half that of the data transmission bit rate based on a local clock (e.g., the output of an oscillator or phase-locked loop originating from the same source as the shift clock), and output it to receiver 103 in real time through the second channel (another pair of differential signal lines) in the unidirectional communication link. This avoids mutual interference between the clock signal and the data signal, ensuring the purity and stability of the clock signal. The receiver 103 uses the rising and falling edges of the accompanying differential clock to sample the serial differential signal on the first channel at double the data rate, thereby recovering the original parallel data word without having to recover the clock from the data stream.

[0094] As an optional implementation, the state machine of the transmitter 102, based on descriptor information (i.e., control metadata), sequentially executes four stages: frame header assembly, data shifting and transmission, accumulation and parallel calculation (determining link transport layer verification information), and frame tail appending, all completed within the same state machine pipeline. The state machine of the transmitter 102 maintains a 64-bit shift register. On each rising edge of a low-speed parallel clock, the lowest two bits of the data word are sent to OSERDES (Output Parallel-to-Serial Logic Resources), and the shift register is shifted right by two bits. Accumulation and calculation are completely parallel to shifting and transmission: each time a new 64-bit data word is loaded into the shift register, its high 32 bits and low 32 bits are synchronously accumulated into a 32-bit verification register. The RAM read address is sent several clock cycles in advance (using the RAM output register pipeline to mask the read delay), ensuring that the data is ready at the loading time. The state machine also maintains an 8-bit frame counter that increments with each frame and embeds it in the frame header (i.e., the current frame sequence number).

[0095] As an alternative implementation, the OSERDES primitive operates in DDR (Double Data Rate) 2:1 mode. Two bits of data input from the low-speed parallel clock are output with one bit each on the rising and falling edges of the high-speed serial clock, thus outputting two bits within one clock cycle to achieve double the data rate. The clock channel (i.e., the second channel) outputs a fixed bit type via OSERDES, which is then buffered to form a differential clock for the receiver 103 to directly recover the clock. The two parallel signals of the data channel (i.e., the first channel) pass through a one-beat synchronous shift register (constrained to IOL (Input / Output Logic / I / O Logic) unit) before entering OSERDES, eliminating timing margin issues caused by placement and routing.

[0096] By employing the aforementioned technical solution, during data word transmission, converting data bits into serial differential signals and utilizing independent differential signal lines to transmit a differential clock along with the data path significantly improves data transmission reliability and anti-interference capabilities. Differential signal transmission effectively suppresses common-mode noise and electromagnetic interference, ensuring signal integrity. Simultaneously, the introduction of a differential clock along with the data path enables the receiver 103 to accurately recover the sampling clock, avoiding timing deviations between data and clock. This is particularly beneficial in high-speed data transmission scenarios, ensuring data sampling accuracy and reducing the bit error rate. This physical layer transmission mechanism, combined with the upper-layer data word accumulation and verification mechanism, constructs a highly reliable data transmission system from the physical layer to the link layer. This effectively solves the data error problems caused by poor signal integrity and clock synchronization difficulties in high-speed data transmission, ensuring the accuracy and stability of data transmission.

[0097] Based on the above embodiments, in an exemplary embodiment, before sending the data words corresponding to the frame header and data payload area to the receiving end 103 in sequence according to the preset data bit width, the method further includes: obtaining the port number and frame length from the control element information associated with the original data; assembling the port number, frame length, preset preamble and the current frame sequence number corresponding to the original data to form a frame header.

[0098] The preamble is a fixed bit sequence that helps the receiver 103 achieve bit synchronization, frame synchronization, and frame start identification. The preamble can be a specific pattern, such as "0xAA55" or "0x55AA", to provide a clear start marker in the data stream; or it can be a more complex pseudo-random sequence to enhance the robustness of synchronization.

[0099] The current frame sequence number is used to identify the order of the original data in the entire data stream. Its function is to help the receiver 103 detect frame loss, duplication, or out-of-order conditions. The current frame sequence number can be an incrementing integer counter that increments by one for each new frame sent; or it can be a cyclic counter that restarts counting from zero after reaching its maximum value.

[0100] In its idle state, the state machine of transmitter 102 continuously monitors whether the asynchronous first-in-first-out queue is not empty. Once control metadata is detected being written, it reads the control metadata from the asynchronous first-in-first-out queue and parses out the port number and frame length, which are used respectively to fill the port identifier field in the subsequent frame header and to calculate the total number of ticks (i.e., total clock cycles) of the receiving window (i.e., the sliding window). In this way, transmitter 102 can automatically obtain the control parameters required for each frame without intervention from processor 101, realizing the separate transmission of data body and control metadata. Combining the preset preamble and the current frame sequence number, the obtained port number, frame length, and other information are combined according to a predetermined format and order to form a complete frame header. Specifically, the obtained port number, frame length, preset preamble, and current frame sequence number can be sequentially arranged into one or more data words using bit concatenation operations; alternatively, the obtained port number, frame length, preset preamble, and current frame sequence number can be assigned to the members of a predefined structure; or, the obtained port number, frame length, preset preamble, and current frame sequence number can be written into a specific hardware register, allowing the hardware logic to automatically generate the frame header. Alternatively, the read raw data can be filled into the data payload area, and link transport layer check information can be calculated as the frame trailer.

[0101] The above technical solution ensures that the frame header contains all necessary control and identification information before the actual transmission of the data frame begins. In this way, the sending end 102 can generate a structured and information-rich frame header for each data frame. This header not only provides the receiving end 103 with clear indications of synchronization and frame start, but also carries crucial routing (port number), length (frame length), and sequence (current frame number) information. This pre-assembly of the frame header allows subsequent transmission of data words in the frame header and data payload area according to the preset data bit width, directly utilizing the prepared frame header, thus guaranteeing the orderliness and parseability of data transmission. Combined with the data transmission method, this solution gives the data frame stronger self-describing capabilities and a better foundation for error detection at the link transmission layer, providing a solid guarantee for the receiving end 103 to correctly process the data.

[0102] In another exemplary embodiment, such as Figure 4 As shown, a data transmission method is provided, which is applied to... Figure 1Taking the receiver 103 as an example, the receiver 103 is connected to the sender 102 via a one-way communication link; the data transmission method includes the following steps: S401, Receive the target data frame sent by the transmitter 102.

[0103] The target data frame includes a frame header, a data payload area containing the original data, and a frame trailer containing link transport layer verification information. The original data includes user data and user application layer verification information. The link transport layer verification information is used to verify the frame header and data payload area, and the user application layer verification information is used to verify the user data. The link transport layer verification information is generated by accumulating the data words in the frame header and data payload area during the transmission of the frame header and data payload area, and the link transport layer verification information is sent to the receiving end when the data payload area is completely transmitted.

[0104] The transmitter 102 can send the target data frame to the receiver 103 in the form of a serial differential signal.

[0105] S402, determine the error transmission type of the target data frame based on the link transport layer verification information and the user application layer verification information.

[0106] Among them, the error transmission type refers to the fault category determined based on the link transport layer verification information and the user application layer verification information, including link physical transmission errors, physical transmission bit errors, and user data logic errors.

[0107] After receiving a complete target data frame and closing the sliding window, receiver 103 can execute two independent verification processes in parallel: on the one hand, it verifies the frame header and data payload area based on the link transport layer verification information extracted from the frame tail; on the other hand, it verifies the user data based on the user application layer verification information carried in the data payload area. By analyzing the combined state of the link verification result and the user data verification result, it can determine whether the erroneous transmission type is a physical transmission error, a physical transmission bit error, or a logical error in the user data.

[0108] By combining link transport layer verification information and user application layer verification information through a layered verification mechanism, the source of errors can be accurately distinguished. Since the link transport layer verification information focuses on the physical transmission integrity of the frame header and data payload, while the user application layer verification information focuses on the logical correctness of user data, the source of the fault can be clearly identified when verification fails. Compared to traditional single-layer verification methods, this embodiment does not rely on additional synchronization frame channels or bidirectional handshake protocols, and can achieve rapid error type location under unidirectional communication link conditions. This effectively solves the technical problem of not being able to locate the fault source when verification fails in the prior art, and significantly reduces the time required for link physical layer troubleshooting and upper-layer logical checks by double.

[0109] Based on the above embodiments, in an exemplary embodiment, the process of determining the error transmission type in step S402 is further refined. For example... Figure 5 As shown, it includes: S501 determines the local link checksum based on the frame header and data payload area.

[0110] The local link check code refers to a local link layer check value generated by calculating the received frame header and data payload area.

[0111] It can perform preset verification algorithms (such as cyclic redundancy check, XOR check, summation check, etc.) on all data bits in the frame header and data payload area, or use a specific hash function to generate a local link check code.

[0112] S502 determines the local user verification code based on user data.

[0113] The local user verification code refers to a local user application layer verification value generated by calculating the received user data.

[0114] It can perform preset verification algorithms (such as cyclic redundancy check, XOR check, cumulative check, etc.) on all data bits of user data, or use a specific hash function to generate a local user verification code.

[0115] S503 compares the local link check code with the link transport layer check code to determine the link check result.

[0116] The link verification result refers to the comparison result between the local link verification code and the link transport layer verification code.

[0117] The local link checksum is compared with the link transport layer checksum to determine whether the link layer transmission is complete and error-free, thus obtaining the link checksum result. The link checksum result includes whether the local link checksum and the link transport layer checksum match (i.e., the comparison is successful) and whether the local link checksum and the link transport layer checksum do not match (i.e., the comparison is unsuccessful). A successful comparison means that the data in the frame header and data payload area has not been damaged or tampered with during the physical link transmission process, and meets the expected transmission integrity; a failed comparison indicates that there may be errors in the data of the link transport layer.

[0118] S504 compares the local user verification code with the user data verification code to determine the user data verification result.

[0119] The user data verification result refers to the comparison result between the local user verification code and the user data verification code.

[0120] The local user verification code is compared with the user data verification code to determine whether the user data maintains consistency at the application layer, thus obtaining the user data verification result. The user data verification result includes whether the local user verification code matches the user data verification code (i.e., the comparison is successful) and whether the local user verification code does not match the user data verification code (i.e., the comparison is unsuccessful). A successful comparison means that the user data is complete and correct at the application layer, and no logical errors have occurred; a failed comparison indicates that the user data may contain logical errors.

[0121] S505 determines the error transmission type of the target data frame based on the link verification result and the user data verification result.

[0122] By combining the link verification results and the user data verification results, it is possible to determine whether the erroneous transmission type is a physical transmission error, a physical transmission bit error, or a logical error in the user data.

[0123] As an optional implementation, step S505 specifically includes: if the link verification result indicates that the local link verification code and the link transport layer verification information are successfully compared, and the user data verification result indicates that the local user verification code and the user application layer verification information are successfully compared, then the error transmission type is determined to be normal reception; if the link verification result indicates that the local link verification code and the link transport layer verification information are not successfully compared, then the error transmission type is determined to be a link physical transmission error; if the link verification result indicates that the local link verification code and the link transport layer verification information are successfully compared, and the user data verification result indicates that the local user verification code and the user application layer verification information are not successfully compared, then the error transmission type is determined to be a user data logical error.

[0124] If the local link checksum matches the link transport layer checksum and the local user checksum matches the user application layer checksum, it is considered a normal reception, meaning the transmission status of the target data frame is correct. This indicates that the target data frame meets expectations from physical transmission to the application logic layer and can be processed subsequently. If the local link checksum does not match the link transport layer checksum, regardless of the user data checksum result, it can be directly determined as a physical transmission error (i.e., a physical transmission error), because the link-level error has already compromised the reliability of the upper-layer data. A physical transmission error means that the target data frame experienced bit errors, packet loss, or out-of-order delivery during transmission over the physical medium, resulting in data corruption in the frame header or data payload area. If the local link checksum matches the link transport layer checksum but the local user checksum does not match the user application layer checksum, it is considered a user data logic error. This means that the physical link transmission is reliable, but the user data contained errors during generation, or a logical error occurred during user data processing at the receiving end 103, causing the user data content to be inconsistent with expectations.

[0125] As an alternative implementation, the receiver 103 internally operates two independent 32-bit accumulator circuits in parallel (a link-layer accumulator circuit and an application-layer accumulator circuit). The link-layer accumulator circuit is used to perform rolling accumulation starting from the frame header, covering the entire data payload area (including the frame header / frame tail flags of user data). When the receiving window (i.e., the sliding window buffer described below) is closed, it compares the result with the link transport layer check information in the frame tail to generate a link-layer pass / fail flag (i.e., the link check result). The application-layer accumulator circuit is used to independently accumulate data starting after the detection of the user data frame header flag (0xAAAA5555), covering only the user data (up to the user data frame tail flag 0xCCCC3333), and compares the result with the user application-layer check information to generate an application-layer pass / fail flag (i.e., the user data check result).

[0126] The decision results of the two circuits are independent of each other. When combined, they can distinguish three states: both layers pass (the frame is completely correct, i.e., normal reception), only the link layer fails (physical transmission introduces bit errors, the user data area content is invalid, i.e., the link physical transmission is wrong), and the link layer passes but the application layer fails (physical transmission is normal, but there are logical errors in the user data content, i.e., the user data is logically wrong).

[0127] As an alternative implementation, the receiver 103 also includes a receive RAM, which stores valid target data frames that have passed the verification by the receiver 103. The receiver 103 uses a ring-address-managed receive RAM as a receive buffer, generating a write enable signal at a specific bit alignment time of each clock counter, and writing the deserialized 64-bit data word by word into the memory. The start address pointer of the receive RAM will only advance when the link layer verification passes; if the verification fails, the pointer will return to its original position, which is equivalent to discarding the current frame without additional operation, thereby avoiding erroneous data from contaminating subsequent normal reception.

[0128] Through the layered verification and comparison mechanism of the above technical solution, the receiver 103 can clearly identify whether the error occurs at the physical link transmission layer, at the logical layer of user data, or even if the data frame is complete and error-free. This layered verification strategy allows the receiver 103 to decouple more specific error causes from a single error indication, providing a precise basis for subsequent error recovery, retransmission strategy selection, or link quality assessment. It avoids generalizing all errors, thereby improving the accuracy of error diagnosis and processing efficiency.

[0129] Based on the above embodiments, in an exemplary embodiment, the frame header includes a preset preamble and frame length, further refining the process of receiving the target data frame in step S401. For example... Figure 6 As shown, it includes: S601 continuously moves the received target data frames into the sliding window buffer.

[0130] The sliding window buffer is a data structure used to continuously receive and temporarily store consecutive data bits from a communication link. This sliding window buffer can be a circular buffer or a first-in-first-out queue. Its characteristic is that it can slide a fixed-size window across the data stream, enabling the receiver 103 to perform real-time processing and pattern matching on the data within the window.

[0131] A sliding window buffer is used to continuously store the target data frame transmitted by the transmitter 102. As one possible implementation, the receiver 103 can convert the serial differential signal (i.e., the serialized differential form of the target data frame on the physical transmission medium) transmitted by the transmitter 102 into a serial bit stream using a low-voltage differential signal receiver. Driven by a double data rate sampling clock, the receiver shifts the two bits of data received in each clock cycle sequentially into a 64-bit sliding window buffer. This sliding window buffer is shifted left or right as soon as a new data bit is received, always maintaining the most recently received 64 bits of data. Since the serial data stream is continuous, the sliding window buffer is also continuously updated, providing a real-time sliding window for subsequent preamble matching.

[0132] S602, when the continuous data bit segments of the target data frame in the sliding window buffer match the preset truncation preamble feature sequence, the starting position of the detected target data frame is determined.

[0133] The truncated preamble sequence refers to a portion of the preset preamble in the frame header. The truncated preamble sequence is used for fast pattern matching within a sliding window buffer to detect the start of a frame. For example, if the preset preamble is 32 bits, the truncated preamble sequence could be its last 16 or 24 bits. When selecting the truncated preamble sequence, its uniqueness and matching efficiency must be considered to reduce the computational resources required for matching while ensuring synchronization accuracy.

[0134] The starting position refers to the starting point of the target data frame, which is the position of the first valid data bit or byte of the target data frame identified by matching the truncated leading feature sequence in the sliding window buffer.

[0135] The receiver 103 continuously monitors the continuous data bit segments (e.g., the middle 24 bits) at a specific position in the sliding window buffer and compares them with a preset truncated preamble feature sequence (e.g., 0xD55555, which can be the lower 24 bits of the preset preamble in the complete frame header). If the match is successful, the receiver 103 confirms that the specific position in the current sliding window corresponds to the starting boundary of the target data frame, that is, the starting position of the target data frame.

[0136] As an alternative implementation, since the transmitter 102 sends the same preset preamble at the beginning of each frame, and the truncation matching strategy allows the high 8 bits of the preset preamble to be ignored, a maximum of 1 byte of beat alignment deviation can be tolerated during the receiving and deserializing process.

[0137] S603, at the same moment the starting position is detected, extracts the frame length from the sliding window buffer and determines the total number of clock cycles required to receive the target data frame based on the frame length.

[0138] At the same clock cycle when the frame start position is detected (i.e., at the same moment), receiver 103 can directly read the frame length (in 32-bit words, assumed to be N_DW) in parallel from the corresponding bit segment of the sliding window buffer (e.g., bits 16 to 31 in the frame header). If the frame length represents the number of bytes in the data payload area, the total number of clock cycles can be calculated based on the total number of bytes in the frame header, data payload area, and frame trailer, as well as the number of clock cycles required for each byte transmission. Alternatively, the total number of clock cycles required to receive the complete target data frame can be calculated using the formula: Total Clock Cycles = N_DW × 16 + 16. Here, each 32-bit word corresponds to 16 clock cycles (since 2 bits are received per clock cycle, 32 bits require 16 cycles), and the additional 16 cycles are used to receive the frame header.

[0139] S604, start clock cycle counting, increment the clock cycle count by one every clock cycle until the clock cycle count reaches the total number of clock cycles, then close the sliding window buffer and trigger the step of determining the error transmission type of the target data frame based on the link transport layer verification information and the user application layer verification information.

[0140] Once the start of the target data frame is detected, a clock cycle count begins and stops when a predetermined total number of clock cycles is reached. This ensures that only the current complete target data frame is received, and the sliding window closes at this point to prevent the reception of data that does not belong to the current frame. Subsequent checksum and error transmission type determination processes are triggered by issuing a signal, setting a flag, or calling a specific processing function. Based on link transport layer checksum information and user application layer checksum information, the error transmission type of the target data frame is determined, ensuring that data integrity checks are performed immediately after the data frame is fully received.

[0141] As an optional implementation, receiver 103 starts an internal clock cycle counter (initially 0). Starting from the first clock cycle after the beginning of the target data frame, the clock cycle counter increments by one every clock cycle. During the counting period, the sliding window remains open, the serial differential signal continues to be shifted into the sliding window buffer, and the link layer verification circuit accumulates the calculations for the frame header and data payload area. When the value of the clock cycle counter reaches the total number of clock cycles minus 1 (or equals the total number of clock cycles), the state machine of receiver 103 immediately closes the sliding window buffer, indicating that the current target data frame has been completely received. At this time, the sliding window buffer exactly stores the data of a complete frame (including the frame header, data payload area, and frame trailer), which then triggers the comparison of link layer verification and application layer verification. Based on the combination of the two verification results, the error transmission type (normal reception, physical transmission error, or user data logic error) is determined. Throughout the process, the closing of the sliding window buffer and the verification trigger are strictly aligned, requiring no additional timeout wait or frame trailer search.

[0142] As another optional implementation, after the receiver 103 obtains the differential clock from the differential clock buffer, it performs a fixed phase shift (the phase shift amount is determined based on the board-level trace delay analysis to align the sampling clock with the center of the data eye diagram) through the on-chip phase-locked loop, and outputs a stable sampling clock to drive ISERDES (Input Serial-to-Parallel Logic Resources), without the need for training sequences or dynamic bit sliding operations.

[0143] The ISERDES primitive operates in DDR 1:2 mode, outputting 2 bits of parallel data per low-speed parallel clock cycle. The deserialized output is fed into a 64-bit sliding window shift register after passing through a one-cycle synchronization register (constrained to IOL). This register shifts in 2 bits of new data from the high end every cycle, always storing the most recently received 64-bit data segment, providing a real-time sliding window (i.e., a sliding window buffer) for preamble detection and frame information extraction.

[0144] The state machine of receiver 103 continuously monitors whether the middle 24 bits of the 64-bit sliding window buffer (i.e., the continuous data bit segment of the target data frame) match the preset preamble's lower 24-bit feature value (i.e., the truncated preamble feature sequence). The truncation strategy, which only matches 24 bits (ignoring the highest byte), can tolerate a maximum deviation of 1 byte in DDR deserialization clock alignment, improving the frame acquisition success rate. Once a match is found, the state machine immediately extracts the DWord length field (i.e., the frame length) from the sliding window buffer on the same clock edge, converts it into the total number of receive clock cycles (each DWord = 16 clock cycles, plus a fixed frame header offset), and precisely manages the receive window (i.e., the sliding window buffer) with a clock counter. When the clock counter reaches its end, the receive window is closed and a check comparison is triggered simultaneously, achieving zero additional delay between the end of reception and the check decision.

[0145] Through the above technical solution, a frame synchronization mechanism based on sliding window and feature sequence matching is introduced at the receiver 103. The receiver 103 can accurately and efficiently identify the start and end boundaries of the target data frame from the continuous communication data stream. This precise frame synchronization mechanism ensures that the frame header, data payload area, and frame trailer can be correctly parsed and extracted, thus providing a complete and error-free data foundation for subsequent link transport layer verification and user application layer verification. This significantly improves the reliability of data transmission, avoids verification failures and data misjudgments caused by frame boundary identification errors, and enables the receiver 103 to more accurately determine the erroneous transmission type of the target data frame, thereby improving the robustness of the entire data transmission system and the accuracy of data processing.

[0146] Based on the above embodiments, in an exemplary embodiment, the frame header further includes the current frame sequence number corresponding to the original data; when it is determined that the error transmission type is normal reception or user data logic error, the method further includes: determining the frame-level loss status of the original data based on the current frame sequence number and the frame sequence number of the historical received frames; when it is determined that the frame-level loss status is that the original data has been lost at the frame level, updating the packet loss count.

[0147] Among them, historical received frames refer to all data frames that the receiver 103 has successfully received and processed. The sequence numbers of historical received frames can be stored in a buffer, a list, or a bitmap for comparison with the sequence numbers of currently received frames. For example, a sliding window can be maintained to record the sequence numbers of the N most recently received frames, or a bitmap can be maintained to mark the range of received frame sequence numbers.

[0148] Frame loss refers to determining whether any data frames have been completely lost during transmission by analyzing the relationship between the current frame sequence number and the sequence numbers of historically received frames.

[0149] Packet loss count refers to the number of data frames lost when frame-level loss is detected.

[0150] After the link layer verification of the target data frame passes (i.e., normal reception or user data logic error), the receiver 103 extracts the current frame sequence number from the frame header of the target data frame and compares it with the frame sequence number of the correctly received and verified historical received frames. As one possible approach, if there is a jump between the current frame sequence number and the previous historical received frame sequence number (for example, if the previous frame sequence number is N and the current frame sequence number is N+2, then frame N+1 may be lost), a frame-level loss can be determined. If the current frame sequence number is exactly equal to the historical frame sequence number plus one (or incremented modulo 256), it is determined to be continuous reception with no packet loss. Alternatively, if the received current frame sequence number is discontinuous with the set of historical received frame sequence numbers, a frame-level loss can be determined. When a frame-level loss occurs, the receiver 103 automatically updates the packet loss count and updates the current frame sequence number to the new historical frame sequence number to continue detecting subsequent frames. Packet loss counting can be implemented using a packet loss counter. This counter can be a simple integer variable that increments by 1 each time a lost frame is detected; or it can be a more complex statistical structure that records packet loss of different types or over different time periods. For example, a total packet loss counter can be maintained, or an independent packet loss counter can be maintained for each port or each data stream. The entire process requires no feedback channel or software intervention and is entirely completed in real-time by the receiver's 103 hardware.

[0151] Through the above technical solution, the receiver 103 can not only identify physical layer errors or user data logic errors that may occur in a single data frame during transmission, but also effectively detect frame-level loss caused by network congestion, equipment failure, etc., throughout the entire data stream. When determining whether the erroneous transmission type is normal reception or a user data logic error, the receiver compares the current frame sequence number contained in the frame header with the frame sequence numbers of historically received frames to accurately determine whether frame-level loss exists in the original data. Once frame-level loss is detected, the packet loss count is updated promptly, enabling the receiver 103 to perform more comprehensive monitoring and evaluation of data transmission integrity. This provides more accurate data stream quality feedback for upper-layer applications, helping to adjust transmission strategies or perform data retransmission in a timely manner, thereby significantly improving the reliability of data transmission.

[0152] Based on the above embodiments, in an exemplary embodiment, after updating the packet loss statistics, the method further includes: mapping the packet loss count, the first count representing a physical transmission error of the link, and the second count representing a normal reception of the link to statistical values ​​of a preset bit width; concatenating the statistical values ​​into a status value; and outputting the status value in response to a single read operation of the processor 101, so that the processor 101 can evaluate the link quality based on the status value.

[0153] The first count refers to the number of link layer verification failures counted by the receiver 103, which is used to characterize the bit errors introduced during physical transmission.

[0154] The second count refers to the number of frames that passed the link layer verification and were received normally, as counted by the receiving end 103.

[0155] The preset bit width refers to the number of binary bits occupied by each counter in the status value, such as 8 bits.

[0156] A statistical value is a numerical value obtained by truncating or limiting each count according to a preset bit width.

[0157] A status value is a binary number (e.g., 32 bits) formed by concatenating multiple statistical values ​​in a fixed order.

[0158] The receiver 103 internally maintains three independent hardware counters, which respectively record the packet loss count (incrementing when the link layer verification passes but the sequence number is not consecutive), the link physical transmission error count (the number of times the link layer verification fails, i.e., the first count), and the normal reception count (the number of successful frames when the link layer verification passes and the frame sequence number is consecutive or packet loss is not detected, i.e., the second count). After each count update, the lower 8 bits of the hardware counter are taken as the statistical value according to a preset bit width (e.g., 8 bits each). If the count exceeds 255, only the lower 8 bits are retained (natural overflow), thus mapping the three counts to three 8-bit statistical values ​​respectively.

[0159] The receiver 103 concatenates three 8-bit statistical values ​​in a fixed order (e.g., packet loss count, first count, second count) into a 32-bit status value, where the high 8 bits can be retained or filled with zeros. This concatenation operation is performed in parallel by hardware without consuming additional clock cycles; the concatenated status value is written into a dedicated status register (e.g., a 32-bit register) for the processor 101 to read.

[0160] The processor 101 initiates a single read operation via the bus to access the address corresponding to the status register. Upon detecting the read request, the receiver 103 directly pushes the current status value onto the data bus and returns it to the processor. After obtaining this 32-bit status value, the processor parses the packet loss count, bit error count, and normal reception count from it, and then calculates the packet loss rate (packet loss count / normal reception count) and bit error rate (bit error count / normal reception count), thereby evaluating the link's transmission quality in real time. The entire process requires only one status register read operation, without interruption, handshake, or additional message exchange, achieving extremely low-overhead link quality quantification.

[0161] Through the above technical solution, the receiver 103 can integrate various link quality-related counting information into a unified status value and provide it to the processor 101 in a single read operation. This significantly simplifies the process of the processor 101 acquiring and evaluating link quality, reduces the number of reads and data processing burden on the processor 101, and improves the efficiency and real-time performance of link quality evaluation. Based on this comprehensive and easily accessible status value, the processor 101 can more timely and accurately determine the link status, thereby enabling more effective fault diagnosis, performance optimization, or resource scheduling.

[0162] Based on the above embodiments, in an exemplary embodiment, after the state machine of the transmitting end 102 detects that the descriptor FIFO is not empty in the IDLE state, it reads the descriptor and waits for several cycles to ensure data stability (TX_RD_STATUS state, which is the state of reading the descriptor and stabilizing the data). Then it enters the TX_DATA state. The TX_DATA state uses the lower 5 bits of the state hold time counter as the periodic index (each 32 cycles corresponds to a 64-bit word). At each 64-bit word boundary, a new data word is loaded into the 64-bit shift register (the first 64-bit word is the frame header, which contains a preset preamble and frame information). At the same time, the high and low 32 bits of the word are accumulated into the check register. The RAM read address is issued in advance by the RD_RAM_PRE_TICK state to mask the read pipeline delay. After all user data words have been sent, `{32'd0, check_num}` is loaded as the link layer frame end checksum word and the last round of shifting is completed. The system then enters the LVDS_TX_DONE (LVDS transmission complete) state, increments the frame counter, and returns to IDLE. Throughout this process, the accumulation and calculation are completely parallel to data transmission, and there is no additional waiting time for the frame end checksum to be appended.

[0163] While waiting for the preset preamble, receiver 103 continuously shifts serial data (i.e., serial differential signal) into its 64-bit sliding window shift register. When the truncated preamble (lower 24 bits 0xD55555) is matched, the frame sequence number, port number, and DWord length are immediately extracted from the same sliding window. rx_bitnum = N_DW×16 + 16 is calculated as the total number of ticks in the receiving window, and the link layer check register is initialized. The receiving flag is set to start the tick counter. During reception, whenever the lower 5 bits of the tick counter are all 1s (64-bit word boundary) and the data payload area is in the data area, the current 64-bit sliding window is written to the receiving RAM, and the link layer sum is updated synchronously. Simultaneously, the application layer check circuit independently detects the frame header flag (0xAAAA5555), frame tail flag (0xCCCC3333), and the accumulated sum of the user data, without interfering with the link layer check process. When the tick counter reaches rx_bitnum - 1, the receive window closes, and the final comparison of the link layer check is completed: if the comparison is successful, the RAM start address is advanced, written to the receive descriptor FIFO, and the frame sequence number continuity is compared (if not continuous, the packet loss counter is incremented); if the comparison fails, the RAM address remains unchanged (the current frame is discarded), and the bit error counter is incremented. After the two decision results are collected in the status register, the receive status is cleared, and the system enters the next frame waiting state.

[0164] It should be understood that the sequence number of each step in the above embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0165] Corresponding to the data transmission method in the above embodiment, Figure 7 A schematic diagram of a data transmission apparatus according to an embodiment of this application is shown. For ease of explanation, only the parts related to the embodiment of this application are shown. (Refer to...) Figure 7 The data transmission device of this embodiment is configured at the transmitting end 102, which is connected to the receiving end 103 via a unidirectional communication link; the data transmission device includes: The acquisition module 701 is used to acquire the raw data to be sent; the raw data includes user data and user application layer verification information. The sending module 702 is used to construct a target data frame and send the target data frame to the receiving end 103. The target data frame includes a frame header, a data payload area containing the original data, and a frame trailer containing link transport layer verification information. The link transport layer verification information is used to verify the frame header and the data payload area, and the user application layer verification information is used to verify the user data. The link transport layer verification information is generated by accumulating the data words in the frame header and the data payload area during the transmission of the frame header and the data payload area, and the link transport layer verification information is sent to the receiving end when the data payload area is completely transmitted.

[0166] As an optional implementation, the transmitting module 702 is specifically used to: sequentially transmit the data words corresponding to the frame header and data payload area to the receiving end 103 according to the preset data bit width; for each data word in the frame header and data payload area, when the data word begins to be transmitted, divide the data word into a first part and a second part, and add the first part and the second part to the total check value; when the last data word in the data payload area begins to be transmitted and the accumulation is completed, determine the total check value as the link transport layer check information, and at the moment when the last data word in the data payload area is transmitted, transmit the link transport layer check information to the receiving end 103 according to the preset data bit width.

[0167] As an optional implementation, when the data word begins to be transmitted, the device further includes: a differential signal output module, used to convert at least two data bits in the data word into serial differential signals for each clock cycle, and output them to the receiver 103 through a first channel in the unidirectional communication link; and a clock output module, used to generate a differential clock along with the local clock, and output it to the receiver 103 through a second channel in the unidirectional communication link so that the receiver 103 can recover the sampling clock.

[0168] As an optional implementation, the device further includes: an extraction module for obtaining the port number and frame length from the control metadata associated with the original data; and an assembly module for assembling the port number, frame length, preset preamble, and the current frame sequence number corresponding to the original data to form a frame header.

[0169] Corresponding to the data transmission method in the above embodiment, Figure 8 A schematic diagram of a data transmission apparatus according to an embodiment of this application is shown. For ease of explanation, only the parts related to the embodiment of this application are shown. (Refer to...) Figure 8 The data transmission device of this embodiment is configured at the receiving end 103, which is connected to the sending end 102 via a unidirectional communication link; the data transmission device includes: The receiving module 801 is used to receive the target data frame sent by the sending end 102. The target data frame includes a frame header, a data payload area containing the original data, and a frame trailer containing link transport layer verification information. The original data includes user data and user application layer verification information. The link transport layer verification information is used to verify the frame header and the data payload area, and the user application layer verification information is used to verify the user data. The link transport layer verification information is generated by accumulating the data words in the frame header and the data payload area during the transmission of the frame header and the data payload area, and the link transport layer verification information is sent to the receiving end when the data payload area is completely transmitted. The identification module 802 is used to determine the error transmission type of the target data frame based on the link transport layer verification information and the user application layer verification information.

[0170] As an optional implementation, the identification module 802 includes: a first determining unit, configured to determine a local link checksum based on the frame header and data payload area; a second determining unit, configured to determine a local user checksum based on user data; a first comparison unit, configured to compare the local link checksum with the link transport layer checksum to determine the link checksum result; a second comparison unit, configured to compare the local user checksum with the user data checksum to determine the user data checksum result; and an identification unit, configured to determine the error transmission type of the target data frame based on the link checksum result and the user data checksum result.

[0171] As an optional implementation, the identification unit is specifically used to: determine the error transmission type as normal reception when the link verification result indicates that the local link check code and the link transport layer check information are successfully compared, and the user data verification result indicates that the local user check code and the user application layer check information are successfully compared; determine the error transmission type as a link physical transmission error when the link verification result indicates that the local link check code and the link transport layer check information are not successfully compared; and determine the error transmission type as a user data logical error when the link verification result indicates that the local link check code and the link transport layer check information are successfully compared, and the user data verification result indicates that the local user check code and the user application layer check information are not successfully compared.

[0172] As an optional implementation, the frame header includes a preset preamble and a frame length; the receiving module 801 is specifically used to: continuously move the received target data frame into the sliding window buffer; when the continuous data bit segments of the target data frame in the sliding window buffer match the preset truncated preamble feature sequence, determine the starting position of the detected target data frame; the truncated preamble feature sequence refers to a portion of the bit segments of the preset preamble in the frame header; at the same moment the starting position is detected, extract the frame length from the sliding window buffer, and determine the total number of clock cycles required to receive the target data frame based on the frame length; start clock cycle counting, increment the clock cycle count by one every clock cycle, until the value of the clock cycle count reaches the total number of clock cycles, then close the sliding window buffer and trigger the identification module 802.

[0173] As an optional implementation, the frame header also includes the current frame sequence number corresponding to the original data; when it is determined that the error transmission type is normal reception or user data logic error, the device further includes: a loss determination module, used to determine the frame-level loss status of the original data based on the current frame sequence number and the frame sequence number of the historical received frames; and an update module, used to update the packet loss count when it is determined that the frame-level loss status is that the original data has been lost at the frame level.

[0174] As an optional implementation, the device further includes: a mapping module for mapping packet loss count, a first count representing physical transmission errors of the link, and a second count representing normal reception of the link to statistical values ​​of a preset bit width; a status splicing module for splicing the statistical values ​​into a status value; and an output module for outputting the status value in response to a single read operation of the processor 101, so that the processor 101 can evaluate the link quality based on the status value.

[0175] It should be noted that the information interaction and execution process between the modules in the above-mentioned data transmission device are based on the same concept as the method embodiment of this application. For details on their specific functions and technical effects, please refer to the method embodiment section, which will not be repeated here.

[0176] In one exemplary embodiment, a computer device is provided, which may be a server, and its internal structure diagram may be as follows: Figure 9 As shown, this computer device includes a processor, memory, input / output interfaces (I / O), and a communication interface. The processor, memory, and I / O interfaces are connected via a system bus, and the communication interface is also connected to the system bus via the I / O interfaces. The processor provides computational and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system, computer programs, and a database. The internal memory provides the environment for the operation of the operating system and computer programs stored in the non-volatile storage media. The database stores data required for data transmission methods. The I / O interfaces are used for exchanging information between the processor and external devices. The communication interface is used for communication with external terminals via a network connection. When the computer program is executed by the processor, it implements a data transmission method.

[0177] Those skilled in the art will understand that Figure 9 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0178] This application also provides a computer-readable storage medium storing a computer program, which, when executed by a processor, can implement the steps in the above-described method embodiments.

[0179] This application provides a computer program product that, when run on a mobile terminal, enables the mobile terminal to implement the steps described in the various method embodiments.

[0180] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, all or part of the processes in the methods of the above embodiments of this application can be implemented by a computer program instructing related hardware. The computer program can be stored in a computer-readable storage medium, and when executed by a processor, it can implement the steps of the various method embodiments described above. The computer program includes computer program code, which can be in the form of source code, object code, executable files, or certain intermediate forms. The computer-readable medium can include at least: any entity or device capable of carrying the computer program code to a photographic device / terminal device, a recording medium, a computer memory, a read-only memory (ROM), a random access memory (RAM), an electrical carrier signal, a telecommunication signal, and a software distribution medium. Examples include USB flash drives, portable hard drives, magnetic disks, or optical disks.

[0181] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0182] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0183] In the embodiments provided in this application, it should be understood that the disclosed apparatus / network devices and methods can be implemented in other ways. For example, the apparatus / network device embodiments described above are merely illustrative. For instance, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0184] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0185] The above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A data transmission method, characterized in that, Applied to the sending end; The transmitting end is connected to the receiving end via a one-way communication link; the data transmission method includes: Obtain the raw data to be sent; the raw data includes user data and user application layer verification information; Construct a target data frame and send the target data frame to the receiving end; The target data frame includes a frame header, a data payload area containing the original data, and a frame trailer containing link transport layer verification information. The link transport layer verification information is used to verify the frame header and the data payload area, and the user application layer verification information is used to verify the user data. The link transport layer verification information is generated by accumulating the data words in the frame header and the data payload area during the transmission of the frame header and the data payload area, and is sent to the receiving end at the moment the data payload area is completely transmitted. The receiving end is used to determine the error transmission type of the target data frame based on the link verification result and the user data verification result. The error transmission type includes normal reception, link physical transmission error, and user data logical error. The frame header includes the current frame sequence number of the original data. If the error transmission type is determined to be normal reception or user data logical error, the receiving end is also used to determine the frame-level loss status of the original data based on the current frame sequence number and the frame sequence numbers of historically received frames. When the frame-level loss status is determined to be frame-level loss of the original data, the packet loss count is updated.

2. The data transmission method according to claim 1, characterized in that, The process of constructing the target data frame and sending the target data frame to the receiving end includes: According to the preset data bit width, the data words corresponding to the frame header and the data payload area are sent to the receiving end in sequence. For each data word in the frame header and the data payload area, when the data word begins to be transmitted, the data word is divided into a first part and a second part, and the first part and the second part are added to the total check value; When the last data word in the data payload area begins to be transmitted and the accumulation is completed, the total check value is determined as the link transport layer check information, and at the moment when the last data word in the data payload area is transmitted, the link transport layer check information is sent to the receiving end according to the preset data bit width.

3. The data transmission method according to claim 2, characterized in that, When the data word begins to be transmitted, the method further includes: For each clock cycle, at least two data bits in the data word are converted into serial differential signals and output to the receiving end through the first channel in the unidirectional communication link; A differential clock is generated based on the local clock and output to the receiving end through the second channel in the unidirectional communication link so that the receiving end can restore the sampling clock.

4. The data transmission method according to claim 2, characterized in that, Before sequentially sending the data words corresponding to the frame header and the data payload area to the receiving end according to the preset data bit width, the method further includes: Obtain the port number and frame length from the control metadata associated with the original data; The port number, the frame length, the preset preamble, and the current frame sequence number corresponding to the original data are assembled to form the frame header.

5. A data transmission method, characterized in that, The method is applied at the receiving end; the receiving end is connected to the sending end via a unidirectional communication link; the data transmission method includes: The receiver receives a target data frame sent by the sending end. The target data frame includes a frame header, a data payload area containing raw data, and a frame trailer containing link transport layer verification information. The raw data includes user data and user application layer verification information. The link transport layer verification information is used to verify the frame header and the data payload area, and the user application layer verification information is used to verify the user data. The link transport layer verification information is generated by accumulating the data words in the frame header and the data payload area during the transmission of the frame header and the data payload area, and the link transport layer verification information is sent to the receiving end when the data payload area is completely transmitted. The error transmission type of the target data frame is determined based on the link transport layer verification information and the user application layer verification information; the error transmission type includes normal reception, link physical transmission error, and user data logical error. The frame header also includes the current frame sequence number corresponding to the original data; when the error transmission type is determined to be normal reception or user data logic error, the data transmission method further includes: Based on the current frame sequence number and the frame sequence numbers of historical received frames, determine the frame-level loss status of the original data; When it is determined that the frame-level loss situation is that the original data has been lost at the frame level, the packet loss count is updated.

6. The data transmission method according to claim 5, characterized in that, Determining the error transmission type of the target data frame based on the link transport layer verification information and the user application layer verification information includes: The local link checksum is determined based on the frame header and the data payload area; Determine the local user verification code based on the user data; The local link checksum is compared with the link transport layer checksum to determine the link checksum result; The local user verification code is compared with the user application layer verification information to determine the user data verification result; Based on the link verification result and the user data verification result, the error transmission type of the target data frame is determined.

7. The data transmission method according to claim 6, characterized in that, Determining the error transmission type of the target data frame based on the link verification result and the user data verification result includes: If the link verification result indicates that the local link verification code and the link transport layer verification information are successfully compared, and the user data verification result indicates that the local user verification code and the user application layer verification information are successfully compared, then the error transmission type is determined to be normal reception. If the link verification result indicates that the local link check code and the link transport layer check information are not successfully matched, the error transmission type is determined to be a link physical transmission error. If the link verification result indicates that the local link checksum is successfully compared with the link transport layer checksum, and the user data verification result indicates that the local user checksum is unsuccessfully compared with the user application layer checksum, then the error transmission type is determined to be a user data logical error.

8. The data transmission method according to claim 5, characterized in that, The frame header includes a preset preamble and frame length; The target data frame sent by the receiving and sending end includes: The received target data frames are continuously moved into the sliding window buffer; When a continuous data segment of the target data frame in the sliding window buffer matches a preset truncated preamble feature sequence, the starting position of the detected target data frame is determined; the truncated preamble feature sequence refers to a portion of the preset preamble code in the frame header; At the same moment the starting position is detected, the frame length is extracted from the sliding window buffer, and the total number of clock cycles required to receive the target data frame is determined based on the frame length; Start clock cycle counting, increment the clock cycle count by one every clock cycle, until the value of the clock cycle count reaches the total number of clock cycles, then close the sliding window buffer and trigger the step of determining the error transmission type of the target data frame based on the link transport layer verification information and the user application layer verification information.

9. The data transmission method according to claim 5, characterized in that, After updating the packet loss count, the method further includes: The packet loss count, the first count representing the link physical transmission error type, and the second count representing the normal reception type are respectively mapped to statistical values ​​of a preset bit width; The statistical values ​​are concatenated to form a state value; In response to a single read operation at the processor, the status value is output so that the processor can evaluate the link quality based on the status value.

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