An IBC cell and a method of manufacturing the same

Abstract

The application discloses an IBC battery and a preparation method thereof. The method comprises the following steps: providing an N-type silicon substrate, wherein the N-type silicon substrate comprises a front surface and a back surface which are opposite to each other; the back surface comprises a first region and a second region which are arranged in an interdigital manner; a first tunneling oxide layer and a first doped layer are prepared on the first region; a second tunneling oxide layer and a second doped layer are prepared on the second region; a texturing process is performed on the front surface and the interval region by using a preset texturing process to form a textured structure; a first passivation layer is prepared on the surface of the back surface which is away from the N-type silicon substrate, and a second passivation layer is prepared on the surface of the front surface which is away from the N-type silicon substrate; screen printing and high-temperature sintering are performed on the first region and the second region to form a first electrode which is in contact with the first doped layer on the first region and a second electrode which is in contact with the second doped layer on the second region, thereby obtaining the IBC battery. By using the method, the reflectivity of the textured structure is reduced, and the conversion efficiency of the battery is improved.

Description

Technical Field

[0001] This invention relates to the technical field of photovoltaic cells, and more particularly to an IBC cell and its preparation method. Background Technology

[0002] The core technology of interdigitated back contact (IBC) solar cells lies in fabricating high-quality, interdigitated p-regions and n-regions on the back of the solar cell. Without the obstruction of metal electrodes on the front, they exhibit higher short-circuit current. Furthermore, the back side allows for wider metal grid lines to reduce series resistance, thereby improving the fill factor. Combined with the open-circuit voltage gain resulting from the excellent passivation of the front side, this type of unobstructed solar cell not only boasts high conversion efficiency but also a more aesthetically pleasing appearance. Additionally, the fully back-electrode design makes the assembly of the module easier.

[0003] When fabricating IBC cells, texturing is required on the front side. Existing texturing methods typically involve pre-cleaning the silicon wafer surface to remove dirt and organic matter, followed by a low-temperature, low-alkaline texturing process. However, before texturing the front side, a doped polycrystalline silicon layer usually exists. Pre-cleaning alone cannot remove this polycrystalline silicon layer. Applying a low-temperature, low-alkaline texturing process directly to the front side not only fails to completely remove the polycrystalline silicon layer but also negatively impacts the texturing effect, resulting in poor texturing quality, higher reflectivity of the textured surface, and consequently, reduced conversion efficiency of the IBC cell. Summary of the Invention

[0004] This invention provides an IBC battery and its preparation method, which uses a pre-defined texturing process to form a textured surface structure on the front side and the spacer area, effectively reducing the reflectivity of the textured surface structure and improving the short-circuit current and conversion efficiency of the IBC battery.

[0005] In a first aspect, the present invention provides a method for preparing an IBC battery, comprising:

[0006] An N-type silicon substrate is provided; the N-type silicon substrate includes a front side and a back side facing away from each other, the back side including a first region and a second region arranged in an interdigitated space;

[0007] A first tunneling oxide layer and a first doped layer are prepared in the first region;

[0008] A second tunneling oxide layer and a second doped layer are prepared in the second region;

[0009] Using a pre-set flocking process, flocking is performed on the front side and in the interval between the first and second areas to form a flocked surface structure.

[0010] A first passivation layer is prepared on the back side surface facing away from the N-type silicon substrate, and a second passivation layer is prepared on the front side surface facing away from the N-type silicon substrate.

[0011] The first region and the second region are screen printed and sintered at high temperature to form a first electrode in the first region that contacts the first doped layer, and a second electrode in the second region that contacts the second doped layer, thereby obtaining an IBC cell.

[0012] Optionally, a first tunneling oxide layer and a first doped layer are prepared in the first region, including:

[0013] Using a deposition process, a first tunneling oxide layer and a first intrinsic silicon layer are fabricated on the front and back sides, respectively.

[0014] Boron diffusion process is used to dope the first intrinsic silicon layer with boron to form the first doped layer and the first mask layer;

[0015] Remove the first mask layer, the first doped layer, and the first tunneling oxide layer in the second region, as well as the first mask layer on the front side.

[0016] Optionally, removing the first mask layer, the first doped layer, and the first tunneling oxide layer in the second region, as well as the first mask layer on the front side, includes:

[0017] The first mask layer in the second region is removed using a laser process.

[0018] An etching process is used to remove the first mask layer on the front side, as well as the first doped layer and the first tunneling oxide layer in the second region.

[0019] Optionally, a second tunneling oxide layer and a second doped layer are prepared in the second region, including:

[0020] A second tunneling oxide layer and a second intrinsic silicon layer are fabricated on the front and back sides respectively using a deposition process.

[0021] A phosphorus diffusion process is used to dope the second intrinsic silicon layer with phosphorus to form a second doped layer and a second mask layer.

[0022] Remove the second mask layer from the first region and the interval region, as well as the second mask layer on the front side.

[0023] Optionally, using a preset flocking process, flocking is performed on the front side and in the interval between the first and second regions to form a flocked structure, including:

[0024] The second doped layer and the second tunneling oxide layer in the first region, as well as the second doped layer, the second tunneling oxide layer, the first doped layer, and the first tunneling oxide layer on the front side, are removed by using a coarse grooving process and an alkaline etching process.

[0025] A pile-making process is used to pile the spacers and the front side to create a pile surface structure.

[0026] Optionally, a pile forming process is used to pile the spacer area and the front side to form a pile structure, including:

[0027] An acid etching process is used to remove the first mask layer in the first region and the second mask layer in the second region.

[0028] Optionally, the rough polishing process includes a mixture of an alkaline solution and an additive, wherein the additive is a polishing additive that has the function of protecting the first mask layer and / or the second mask layer.

[0029] Optionally, the mass ratio of alkaline solution to additives ranges from 1% to 5%, and the concentration of the mixed solution ranges from 15% to 20%.

[0030] Optionally, the etching time range for the rough grooving process is 3-5 minutes, and the etching temperature range is 70℃-80℃.

[0031] Secondly, the present invention provides an IBC battery, which is prepared by the above-described method for preparing an IBC battery.

[0032] The technical solution of this invention involves providing an N-type silicon substrate; the N-type silicon substrate includes a front side and a back side that are opposite to each other, and the back side includes a first region and a second region arranged in an interdigitated pattern; a first tunneling oxide layer and a first doped layer are prepared in the first region; a second tunneling oxide layer and a second doped layer are prepared in the second region; a texturing process is used to texturize the front side and the spacer region between the first and second regions to form a textured structure; a first passivation layer is prepared on the back side surface opposite to the N-type silicon substrate, and a second passivation layer is prepared on the front side surface opposite to the N-type silicon substrate; the first and second regions are screen-printed and sintered at high temperature to form a first electrode in the first region that contacts the first doped layer, and a second electrode in the second region that contacts the second doped layer, thereby obtaining an IBC cell. Using the above method, the texturing process is employed to form a textured structure on the front side and the spacer region, effectively reducing the reflectivity of the textured structure and improving the short-circuit current and conversion efficiency of the IBC cell.

[0033] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0034] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0035] Figure 1 A flowchart illustrating a method for preparing an IBC battery according to an embodiment of the present invention;

[0036] Figure 2 This is a schematic diagram of the structure of an IBC battery provided in an embodiment of the present invention;

[0037] Figure 3 A flowchart illustrating a second method for preparing an IBC battery according to an embodiment of the present invention;

[0038] Figure 4 This is a schematic diagram of a flocking structure formed without the coarse polishing process, provided in an embodiment of the present invention.

[0039] Figure 5 This is a schematic diagram of a flocking structure formed after a rough polishing process, as provided in an embodiment of the present invention. Detailed Implementation

[0040] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0041] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, preparation method, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0042] In one embodiment, Figure 1This is a flowchart illustrating a method for preparing an IBC battery according to an embodiment of the present invention. Figure 2 This is a schematic diagram of an IBC battery structure provided by an embodiment of the present invention. This embodiment can be applied to situations where the reflectivity of the textured surface structure on the front of the IBC battery is reduced and the conversion efficiency of the IBC battery is improved. Figure 1 As shown, the method includes:

[0043] S110 provides an N-type silicon substrate.

[0044] The N-type silicon substrate 1 includes a front side and a back side facing away from each other. The back side includes a first region and a second region arranged in an interdigitated pattern. Typically, the first region can be an n-region or a p-region, and correspondingly, the second region can be a p-region or an n-region. In this embodiment, the first region can be a p-region, the second region can be an n-region, and the region separating the first region and the second region is a spacer region. The width of the first region ranges from 500um to 600um, and the width of the second region ranges from 400um to 500um.

[0045] Specifically, after providing the N-type silicon substrate 1, the substrate 1 first needs to be double-sided polished using a tank cleaning device. The main process includes pre-cleaning, alkaline solution, and acid solution. The pre-cleaning tank is a mixed solution of NaOH or KOH and H₂O₂, with a mass ratio of 0.3-5%. The alkaline solution tank is a NaOH or KOH solution, with a mass ratio of 4-20%. The acid solution tank is an HF or HCl solution with a mass ratio of 1-15%. The overall polishing time is 4-6 minutes. This effectively improves the surface smoothness of the battery, increases the reflection of long-wavelength light, promotes secondary light absorption, increases short-circuit current, and reduces leakage current.

[0046] S120, Prepare a first tunneling oxide layer and a first doped layer in the first region.

[0047] The first tunneling oxide layer 21 allows majority carriers (electrons) to pass smoothly through the tunneling effect while preventing the recombination of minority carriers (holes), thereby achieving selective carrier collection, reducing surface recombination, increasing the open-circuit voltage and fill factor of the battery, and ultimately improving the photoelectric conversion efficiency of the IBC battery. In this embodiment, the first tunneling oxide layer 21 is an ultrathin silicon dioxide layer. The first doped layer 22 is a boron-doped polycrystalline silicon layer, a special semiconductor layer with a high doping concentration formed by doping with boron.

[0048] Specifically, using a deposition process, under deposition conditions of 560℃-600℃, a first tunneling oxide layer 21 and a first intrinsic silicon layer are sequentially deposited in the first region. After the formation of the first intrinsic silicon layer, it needs to be elementally doped to form a first doped layer 22. The deposition of the first tunneling oxide layer 21 and the first intrinsic silicon layer includes, but is not limited to, low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), or physical vapor deposition (PVD), etc., which can be determined according to the actual situation and are not limited here. In this embodiment, the thickness of the first tunneling oxide layer 21 is 1nm-3nm, and the thickness of the first doped layer 22 is 300nm-350nm.

[0049] S130, Prepare a second tunneling oxide layer and a second doped layer in the second region.

[0050] The second tunneling oxide layer 31 allows majority carriers (electrons) to pass smoothly through the tunneling effect while preventing the recombination of minority carriers (holes), thereby achieving selective carrier collection, reducing surface recombination, improving the open-circuit voltage and fill factor of the battery, and ultimately enhancing the photoelectric conversion efficiency of the IBC battery. In this embodiment, the second tunneling oxide layer 31 is an ultrathin silicon dioxide layer. The second doped layer 32 is a phosphorus-doped polycrystalline silicon layer, a special semiconductor layer with a high doping concentration formed by doping with phosphorus.

[0051] Specifically, using a deposition process, under deposition conditions of 560℃-600℃, a second tunneling oxide layer 31 and a second intrinsic silicon layer are sequentially deposited in the second region. After the formation of the second intrinsic silicon layer, it needs to be elementally doped to form a second doped layer 32. The deposition of the second tunneling oxide layer 31 and the second intrinsic silicon layer includes, but is not limited to, low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), or physical vapor deposition (PVD), etc., and the specific method can be determined according to the actual situation, without limitation. In this embodiment, the thickness of the second tunneling oxide layer 31 is 1nm-3nm, and the thickness of the second doped layer 32 is 200nm-250nm.

[0052] S140. Using a preset flocking process, flocking is performed on the front side and in the interval between the first and second regions to form a flocked structure.

[0053] The texturing process refers to the special treatment of the front surface and spacer area of ​​the N-type silicon substrate 1 of the IBC cell during the production process, forming a rough, textured structure.

[0054] Specifically, a pre-defined texturing process is used to texturize the front and interstitial areas, thereby forming a uniformly arranged "pyramid" structure, i.e., a textured surface structure, in the front and interstitial areas. In this embodiment, the pre-defined texturing process includes, but is not limited to, rough polishing, pre-cleaning, and alkaline etching processes, to reduce the reflectivity of the textured surface structure, improve the light-trapping effect of the IBC cell, and effectively increase the short-circuit current of the IBC cell.

[0055] S150. A first passivation layer is prepared on the back side surface facing away from the N-type silicon substrate, and a second passivation layer is prepared on the front side surface facing away from the N-type silicon substrate.

[0056] The first passivation layer 4 and the second passivation layer 5 are used to reduce the reflection of sunlight, increase the absorption of sunlight, improve the conversion efficiency of IBC cells, reduce surface recombination, increase the mobility of charge carriers, and improve the overall performance of IBC cells.

[0057] Specifically, a first passivation layer 4 of a certain thickness is deposited on the back side of the N-type silicon substrate 1 using a deposition process. After forming the first passivation layer 4, a second passivation layer 5 of a certain thickness is deposited on the front side of the N-type silicon substrate 1. In this embodiment, the first passivation layer 4 includes a first alumina layer and a first silicon nitride layer, and the second passivation layer 5 includes a second alumina layer and a second silicon nitride layer. The deposition process used to deposit the first alumina layer on the back side may include, but is not limited to, atomic layer deposition (ALD), and the deposition conditions include a deposition temperature of 200℃-300℃ and a deposition time of 7min-12min. Under these conditions, the thickness of the first alumina layer is 4nm-6nm. After forming the first alumina layer on the back side, a first silicon nitride layer is deposited on the side of the first alumina layer facing away from the N-type silicon substrate 1. The deposition process for forming the first silicon nitride layer may include, but is not limited to, plasma-enhanced chemical vapor deposition (PECVD). The deposition conditions include a deposition temperature of 480℃-600℃ and a deposition time of 5 min-8 min. Under these conditions, the thickness of the first silicon nitride layer is 70 nm-80 nm. Similarly, the deposition conditions and processes for forming the second alumina layer and the second silicon nitride layer on the front side are the same as those for forming the first alumina layer and the first silicon nitride layer on the back side, and will not be described again here.

[0058] S160. Screen printing and high-temperature sintering are performed on the first region and the second region to form a first electrode in contact with the first doped layer in the first region and a second electrode in contact with the second doped layer in the second region, thereby obtaining an IBC cell.

[0059] Screen printing is one of the core processes in the manufacturing of IBC solar cells, primarily used for electrode forming. This process utilizes the basic principle that metal paste passes through the mesh openings of the screen in the patterned areas, while the non-patterned areas do not. During printing, the metal paste is precisely extruded through the mesh openings of the screen onto the N-type silicon substrate 1, forming the desired electrode pattern. Typically, the metal paste used for screen printing can include, but is not limited to, silver paste, aluminum paste, and / or copper paste. The pattern formed by screen printing includes metal grid lines. High-temperature sintering is used to process the electrode material screen-printed onto the surface of the solar cell at high temperatures, ensuring good ohmic contact between the metal grid lines and the N-type silicon substrate 1.

[0060] Specifically, after forming the first passivation layer 4 on the back side, electrodes need to be formed on the back side to convert photogenerated carriers generated by solar energy into current that flows to the external circuit. In this embodiment, screen printing is performed on the first and second regions on the back side to form metal grid lines on the surfaces of the first and second regions. After forming the metal grid lines, the formed metal grid lines need to be sintered and annealed at high temperature. The high-temperature sintering temperature is 780℃-900℃. The metal grid lines after high-temperature sintering can contact the first doped layer 22 and the second doped layer 32 to form an ohmic contact, thereby improving the fill factor of the IBC cell. Specifically, after high-temperature sintering and annealing, a first electrode 6 in contact with the first doped layer 22 is formed in the first region, and a second electrode 7 in contact with the second doped layer 32 is formed in the second region, thereby fabricating an IBC cell. In addition, the polarities of the first electrode 6 and the second electrode 7 are opposite. When the first electrode 6 is a positive electrode, the corresponding second electrode 7 is a negative electrode; when the first electrode 6 is a negative electrode, the corresponding second electrode 7 is a positive electrode. In this embodiment, the first region is the p region and the second region is the n region. The first electrode 6 formed in the p region is the positive electrode, and the second electrode 7 formed in the n region is the negative electrode.

[0061] The technical solution of this invention involves providing an N-type silicon substrate; the N-type silicon substrate includes a front side and a back side that are opposite to each other, and the back side includes a first region and a second region arranged in an interdigitated pattern; a first tunneling oxide layer and a first doped layer are prepared in the first region; a second tunneling oxide layer and a second doped layer are prepared in the second region; a texturing process is used to texturize the front side and the spacer region between the first and second regions to form a textured structure; a first passivation layer is prepared on the back side surface opposite to the N-type silicon substrate, and a second passivation layer is prepared on the front side surface opposite to the N-type silicon substrate; the first and second regions are screen-printed and sintered at high temperature to form a first electrode in the first region that contacts the first doped layer, and a second electrode in the second region that contacts the second doped layer, thereby obtaining an IBC cell. Using the above method, the texturing process is used to form a textured structure on the front side and the spacer region, effectively reducing the reflectivity of the textured structure and improving the short-circuit current and conversion efficiency of the IBC cell.

[0062] Figure 3 This is a flowchart illustrating a second method for preparing an IBC battery according to an embodiment of the present invention. Figure 4 This is a schematic diagram of a flocking structure formed without the coarse polishing process, provided in an embodiment of the present invention. Figure 5 This is a schematic diagram of a texturing structure formed after a rough grooving process, provided by an embodiment of the present invention. This embodiment refines the preparation method of the IBC battery described in the above embodiment. For details not covered in this embodiment, please refer to the above embodiment, which will not be repeated here. Figures 2 to 5 As shown, the method includes:

[0063] S210 provides an N-type silicon substrate.

[0064] S220. Using a deposition process, a first tunneling oxide layer and a first intrinsic silicon layer are prepared on the front and back sides, respectively.

[0065] Specifically, using deposition processes such as LPCVD, PECVD, or ALD, at a deposition temperature of 560℃-600℃, an N-type silicon substrate 1 is placed in the reaction chamber of the deposition process. By introducing silane at a certain flow rate and concentration into the reaction chamber, and after a certain deposition time, a first tunneling oxide layer 21 and a first intrinsic silicon layer of a certain thickness are deposited on the front and back sides, respectively. In this embodiment, the thickness of the first tunneling oxide layer 21 is 1nm-3nm, and the thickness of the first intrinsic silicon layer is 300nm-350nm.

[0066] S230. Boron diffusion process is used to dope the first intrinsic silicon layer with boron to form the first doped layer and the first mask layer.

[0067] Specifically, after forming the first intrinsic silicon layer, it needs to be doped to form the first doped layer. This is done using a boron diffusion process. A certain flow rate of boron tribromide or boron trichloride is introduced into the reaction chamber of the boron diffusion process. Under diffusion conditions of 900℃-1000℃ and a boron diffusion time of 5-7 minutes, the first intrinsic silicon layer can be doped with boron, thus forming the first doped layer 22. Since the boron in the doping process usually does not completely react into the first intrinsic silicon layer, but produces some residual organic matter, to prevent this residual organic matter from affecting the first doped layer 22, it can be post-oxidized. A certain flow rate of oxygen is introduced into the post-oxidation reaction chamber, allowing the residual organic matter to react with oxygen to form a first mask layer. Typically, the first mask layer is a borosilicate glass (BSG) layer.

[0068] It is understandable that the equipment for boron diffusion process includes, but is not limited to, a boron diffusion furnace. When boron diffusion is carried out in this equipment, it is usually double-sided diffusion, or boron diffusion is carried out on the N-type silicon substrate 1 in a double-insertion manner. In this process, it cannot be guaranteed that the borosilicate glass layer generated by post-oxidation will only be formed on the back side of the N-type silicon substrate 1. In actual production, the borosilicate glass layer will also be generated on the front side at the same time.

[0069] S240, Remove the first mask layer, the first doped layer and the first tunneling oxide layer of the second region, as well as the first mask layer on the front side.

[0070] This step can be further broken down as follows: using a laser process to remove the first mask layer in the second region; using an etching process to remove the first mask layer on the front side, as well as the first doped layer and the first tunneling oxide layer in the second region.

[0071] The laser process involves using a laser to remove the first mask layer in the second region on the back side according to a preset pattern. The etching process includes alkaline etching and acid etching. Acid etching, also known as chain acid etching, is a wet etching technique widely used in solar cell manufacturing. It mainly involves using a prepared acidic solution to chemically treat the silicon wafer surface to remove specific material layers or form specific structures. Alkaline etching involves using a prepared alkaline solution to chemically react with the first doped layer 22 to remove it.

[0072] Specifically, after forming the first tunneling oxide layer 21, the first doped layer 22, and the first mask layer on both the front and back sides, in order to ensure the texturing effect on the front side and the contact effect of the two electrodes on the back side, the first tunneling oxide layer 21, the first doped layer 22, and the first mask layer formed on the front side, the spacer region, and the second region need to be removed. In this embodiment, a laser process is used to open the first mask layer of the second region and the spacer region under laser conditions of laser frequency of 150kHz-300kHz, laser speed of 15000mm / s-30000mm / s, laser power of 20W-35W, and spot overlap rate of 40%-70%, thereby removing the first mask layer of the second region and the spacer region and exposing the first doped layer 22 of the second region. Next, dust and dirt generated after the laser process are cleaned and removed in a pre-cleaning solution formed by mixing sodium hydroxide or potassium hydroxide with hydrogen peroxide at a mass ratio of 0.3%-0.5%. Then, the first mask layer on the front side is etched away using an acid etching process. The etching solution for the acid etching process can be hydrofluoric acid solution. After removing the first mask layer in the second region, the first doped layer and the first tunneling oxide layer in the second region also need to be removed. In this embodiment, an alkaline etching process is used. A mixed solution formed by sodium hydroxide or potassium hydroxide solution and additives at a mass ratio of 4%-12% is introduced into the reaction chamber of the alkaline etching process. The chemical reaction between the alkaline solution and the doped layer removes the first doped layer in the second region, exposing the first tunneling oxide layer in the second region. Then, using an acid etching process, a hydrofluoric acid solution with a mass ratio of 0.5%-1% or a hydrochloric acid solution with a mass ratio of 3%-12% is introduced into the reaction chamber of the acid etching process. The chemical reaction between the acidic solution and the first tunneling oxide layer 21 removes the first tunneling oxide layer 21 in the second region. In addition, the alkaline etching process can be combined with a polishing process to remove the mechanical damage layer and contaminants caused by pre-cleaning, optimize the surface morphology, reduce the surface recombination rate, and thus improve the minority carrier lifetime of the IBC cell.

[0073] S250. Using a deposition process, a second tunneling oxide layer and a second intrinsic silicon layer are prepared on the front and back sides, respectively.

[0074] Specifically, using deposition processes such as LPCVD, PECVD, or ALD, at a deposition temperature of 560℃-600℃, a certain flow rate and concentration of silane are introduced into the reaction chamber of the deposition process. After a certain deposition time, a second tunneling oxide layer 31 and a second intrinsic silicon layer of a certain thickness can be deposited on the front and back sides, respectively. In this embodiment, the thickness of the second tunneling oxide layer 31 is 1nm-3nm, and the thickness of the second intrinsic silicon layer is 200nm-250nm. It can be understood that the second tunneling oxide layer 31 and the second intrinsic silicon layer formed in the first region on the back side are essentially deposited on the surface of the first mask layer away from the N-type silicon substrate 1.

[0075] S260. A phosphorus diffusion process is used to dope the second intrinsic silicon layer with phosphorus to form a second doped layer and a second mask layer.

[0076] Specifically, after forming the second intrinsic silicon layer, it needs to be doped to form the first doped layer. This is achieved using a phosphorus diffusion process. A certain flow rate of phosphorus oxychloride is introduced into the reaction chamber of the phosphorus diffusion process, serving as the dopant source. Under diffusion conditions of 600℃-800℃ and a diffusion time of 5-7 minutes, phosphorus oxychloride is thermally decomposed in a high-temperature tubular manner to achieve phosphorus doping of the second intrinsic silicon layer, thus forming the second doped layer 32. Since phosphorus in the doping process usually does not completely react into the second intrinsic silicon layer, some residual organic matter is generated during the reaction. To prevent this residual organic matter from affecting the second doped layer 32, it can be post-oxidized. A certain flow rate of oxygen is introduced into the post-oxidation reaction chamber, allowing the residual organic matter to react with oxygen to form a second mask layer. Typically, the second mask layer is a phosphorus silicon glass (PSG) layer.

[0077] It is understandable that the equipment for phosphorus diffusion process includes, but is not limited to, phosphorus diffusion furnace. When phosphorus diffusion is carried out in the equipment, it is usually double-sided diffusion, or phosphorus diffusion is carried out on the N-type silicon substrate 1 in a double-insertion manner. In this process, it cannot be guaranteed that the phosphorus-silicon glass layer generated by post-oxidation will only be formed on the back side of the N-type silicon substrate 1. In actual production, the phosphorus-silicon glass layer will also be generated on the front side at the same time.

[0078] S270, Remove the second mask layer from the first region and the interval region, as well as the second mask layer on the front side.

[0079] Specifically, the second tunneling oxide layer 31, the second doped layer 32, and the second mask layer are all deposited across the entire surface, meaning that the above three-layer structure is also deposited in the first region. At this point, it is necessary to remove the second tunneling oxide layer 31, the second doped layer 32, the second mask layer formed in the first region and the spacer layer, as well as the second mask layer on the front side. Firstly, a laser process can be used to open the second mask layer under laser conditions of 150kHz-300kHz laser frequency, 15000mm / s-30000mm / s laser speed, 20W-35W laser power, and 40%-70% spot overlap. This removes the second mask layer in the first region and the spacer region, exposing the second doped layer 32 in the first region.

[0080] S280. Using a coarse grooving process and an alkaline etching process, the second doped layer and the second tunneling oxide layer in the first region, as well as the second doped layer, the second tunneling oxide layer, the first doped layer, and the first tunneling oxide layer on the front side are removed.

[0081] The rough polishing process is a crucial step in the IBC cell production process, typically occurring during the chemical polishing damage removal stage. Its purpose is to remove the mechanically damaged layer generated on the surface of the N-type silicon substrate 1 during earlier processing using chemical methods, while simultaneously performing preliminary planarization on the N-type silicon substrate 1 surface. Furthermore, the rough polishing process utilizes a high solution concentration; combining it with alkaline etching allows for the complete removal of the polycrystalline silicon layer and tunneling oxide layer in the designated area through a chemical reaction.

[0082] Specifically, when removing the second doped layer 32, the second tunneling oxide layer 31, the first doped layer 22, the first tunneling oxide layer 21 formed on the front side, and the second doped layer 32 and the second tunneling oxide layer 31 formed in the first region, a rough sintering process and an alkaline etching process are used. By introducing a mixed solution of an alkaline solution and additives with a preset solution mass ratio and a preset solubility range into the reaction chamber of the rough sintering process, and etching for 3 to 5 minutes under the etching conditions of 70℃-80℃, the second doped layer 32, the second tunneling oxide layer 31, the first doped layer 22, the first tunneling oxide layer 21 formed on the front side, and the second doped layer 32 and the second tunneling oxide layer 31 formed in the first region can be partially removed. Next, an alkaline solution with a mass ratio of 0.4%-1.3%, such as a mixture of sodium hydroxide or potassium hydroxide solution and additives, is introduced into the reaction chamber of the alkaline etching process. The chemical reaction between the alkaline solution and the doped layer and tunneling oxide layer removes all residual second doped layer 32, second tunneling oxide layer 31, first doped layer 22, first tunneling oxide layer 21 on the front side, as well as all residual second doped layer 32 and second tunneling oxide layer 31 in the first region. Additionally, typically after the rough sizing process and before the alkaline etching process, organic matter and impurities generated after the rough sizing process are cleaned and removed. This is achieved through a pre-cleaning process, where the N-type silicon substrate 1 is cleaned in a mixture of an alkaline solution with a mass ratio of 0.3%-5% and hydrogen peroxide to ensure flatness and cleanliness.

[0083] It should be noted that the additive introduced in the rough polishing process is a polishing additive that protects the first mask layer and / or the second mask layer, ensuring that the first mask layer in the first region and the second mask layer in the second region are not etched away, thus affecting the first doped layer 22 in the first region and the second doped layer 32 in the second region. Furthermore, the mass ratio of the alkaline solution to the additive introduced in the rough polishing process ranges from 1% to 5%, such as 1%, 3%, or 5%, and the concentration of the mixed solution ranges from 15% to 20%, such as 15%, 18%, or 20%. The specific ratio can be determined based on actual conditions and is not limited here. Thus, adding a rough polishing process before pre-cleaning can effectively reduce the reflectivity of the front side, improving the light trapping effect and conversion efficiency of the IBC cell.

[0084] It is understandable that, for the spacer region, because the spacer region has been etched more times than the first region and the second region, the depth of the spacer region is greater than that of the first region and the second region, so as to play a role in isolating the two electrodes.

[0085] S290: A pile-making process is used to pile the spacer area and the front side to form a pile structure.

[0086] Specifically, after removing the second doped layer 32, the second tunneling oxide layer 31, the first doped layer 22, the first tunneling oxide layer 21 formed on the front side, and the second doped layer 32 and the second tunneling oxide layer 31 formed in the first region, texturing is required on the front side and the spacer region. This is done by introducing an alkaline solution of a certain flow rate and concentration into the reaction chamber of the texturing process, and adding texturing additives that protect the first and second mask layers. Under preset texturing conditions, texturing is performed on the spacer region and the front side to form a textured structure. Furthermore, the process time for both the alkaline etching process and the texturing process is 3-5 minutes.

[0087] Table 1 shows the influence of the presence or absence of a coarse grooving process on the structural parameters of the felt surface according to an embodiment of the present invention. (Refer to Table 1.) Figure 4 and Figure 5 It can be seen that the reflectivity of the pile structure formed after the coarse grooving process is significantly reduced, while the pile width and pile height are significantly increased, resulting in a larger specific surface area, a reduced pile yield of the pyramid, a higher height, and a more uniform size.

[0088]

[0089]

[0090] S300: Using acid etching process, the first mask layer of the first region and the second mask layer of the second region are removed.

[0091] Specifically, after the texturing structure is formed, it is necessary to remove the first region and the first mask layer and the second mask layer of the second region. This is done by using an acid etching process. A solution of hydrofluoric acid and hydrochloric acid with a mass ratio of 3%-10% is introduced into the reaction chamber of the acid etching process. The chemical reaction between the acid solution and the first and second mask layers removes the first mask layer of the first region and the second mask layer of the second region.

[0092] S310. Screen printing and high-temperature sintering are performed on the first region and the second region to form a first electrode in contact with the first doped layer in the first region and a second electrode in contact with the second doped layer in the second region, thereby obtaining an IBC cell.

[0093] Specifically, Table 2 shows the effect of the presence or absence of a coarse grooving process on the performance of IBC cells according to an embodiment of the present invention. Referring to Table 2, by conducting IV tests on two groups of samples under AM1.5 solar radiation intensity of 1000W / m2 and test temperature of 25℃-26℃, it can be seen that adding a coarse grooving process before texturing increases the short-circuit current and open-circuit voltage, thereby improving the fill factor of the IBC cell and thus improving the conversion efficiency of the IBC cell.

[0094]

[0095] The technical solution of this invention employs a coarse grooving process and an alkaline etching process to remove the second doped layer and the second tunneling oxide layer in the first region, as well as the second doped layer, the second tunneling oxide layer, the first doped layer, and the first tunneling oxide layer on the front side. A texturing process is then used to texturize the spacer region and the front side to form a textured surface structure. Through these methods, the reflectivity of the front side is significantly reduced, improving the light-trapping effect of the IBC cell and effectively increasing the short-circuit current and conversion efficiency of the IBC cell.

[0096] In another optional embodiment, this embodiment also provides a method flow for preparing an IBC battery, the specific flow of which includes:

[0097] S1. Double-sided polishing of N-type silicon substrate: The pre-cleaning tank is a mixed solution of NaOH and H2O2 with a mass ratio of 2%, and the pre-cleaning time is 4 min. The alkaline solution polishing tank is NaOH with a mass ratio of 4%, and the alkaline solution polishing time is 15 min. The acid solution polishing tank is a mixed solution of HF and HCl with a mass ratio of 9%, and the acid solution polishing time is 5 min.

[0098] S2. Deposition of poly-Si(p+) layer: Preparation of poly-layer passivated contact structure. The deposition technique is LPCVD, the reactant is silane (SiH4), the deposition temperature is 565℃, the thickness of the first tunneling oxide layer formed by deposition is 2nm, and the thickness of the first intrinsic silicon layer is 300nm.

[0099] S3. Boron diffusion: The first intrinsic silicon layer is boron-doped using high-temperature tubular thermal decomposition technology. The propagation temperature is set to 910℃ and the boron doping time is 7min. The boron source is boron trichloride (BCl3). After doping, a boron-doped polycrystalline silicon passivation contact structure, i.e. the first doped layer, is formed on the front and back sides, and a BSG layer is generated on the surface of the first doped layer.

[0100] S4. Laser 1 patterns the back side (PN regions are arranged in a cross pattern on the back side of the cell). The BSG film is opened in the n+ region with the p region size range of 500um and the n region size range of 500um. Under the opening conditions of laser frequency of 170kHz, laser speed of 17000mm / s, laser power of 36W and laser spot overlap rate of 50%, the BSG layer in the n region is removed.

[0101] S5. Acid etching: The acid etching tank is filled with HF solution to remove the BSG layer on the front side.

[0102] S6. Alkaline Etching and Polishing: The pre-cleaning tank is a mixed solution of NaOH and H₂O₂ with a mass ratio of 0.5%, and the pre-cleaning time is 4 min. The alkaline etching and polishing tank is a mixed solution of NaOH and polishing additives with a mass ratio of 4%, and the etching and polishing time is 4 min. The acid solution tank is an HF solution with a mass ratio of 1%, and the etching time is 1 min. Under the above conditions, the first doped layer and the first tunneling oxide layer in the n-region are removed.

[0103] S7. Deposition of poly-Si(n+): Preparation of poly-layer passivated contact structure. The deposition technique is LPCVD, the reactant is silane (SiH4), the deposition temperature is 600℃, and the thickness of the second tunneling oxide layer formed under this deposition condition is 2nm, and the thickness of the second intrinsic silicon layer is 200nm.

[0104] S8. Phosphorus diffusion: The battery is doped with phosphorus using high-temperature tubular thermal decomposition POCL3 technology. The propagation temperature is set to 900℃ and the phosphorus diffusion time is 7min. Phosphorus-doped polycrystalline silicon passivation contact structures, i.e., the second doped layer, are formed on the front and back sides, and a PSG layer is generated on the surface of the second doped layer.

[0105] S9. Laser 2 performs PSG delamination on parts of the p and n regions: The laser frequency of laser 2 is set to 170kHz, the laser speed to 17000mm / s, the laser power to 28W, and the laser spot overlap rate to 50%. Under these conditions, the PSG layer in the p region is removed, and the two laser regions in the n region (range 100-150um) are separated into gaps. The purpose of the gaps is to isolate the p and n regions to prevent short circuits caused by PN conduction.

[0106] S10, Acid Etching: The acid etching tank is filled with HF solution to remove the PSG layer on the front side.

[0107] S11. Texturing: The coarse polishing tank contains NaOH solution and a protective additive at a mass ratio of 5%, set at 75℃ for 3 minutes. The pre-cleaning tank contains a mixed solution of NaOH and H₂O₂ at a mass ratio of 0.5%, for 15 minutes. The alkaline solution texturing tank contains KOH solution at a mass ratio of 0.9%, for 10 minutes, removing the second doped layer, second tunneling oxide layer, first doped layer, and first tunneling oxide layer on the front side, as well as the second doped layer and second tunneling oxide layer in the p-region. The post-cleaning tank contains HF solution at a mass ratio of 0.3%, for 15 minutes, removing the BSG layer in the p-region and the PSG layer in the n-region.

[0108] S12. Preparation of passivation layer: An alumina layer with a thickness of 5.3 nm was deposited using atomic layer deposition (ALD) at a process temperature of 200℃ and a deposition time of 10 min. Then, a silicon oxynitride layer with a thickness of 80 nm was deposited on the side of the first alumina layer away from the N-type silicon substrate using physical vapor deposition (PECVD) at a process temperature of 600℃ and a deposition time of 8 min.

[0109] S13. Screen printing positive and negative electrode pastes, followed by sintering to prepare IBC cells: Using screen printing technology with metal paste as raw material, wherein the metal paste is silver paste, the back electrode and electric field of the battery are prepared. Then, the IBC cells are subjected to high-temperature sintering at 710℃ and low-temperature annealing treatment with light injection at 540℃ to form IBC cells.

[0110] Based on the same inventive concept, this invention also provides an IBC battery, which is prepared by the above-described method for preparing an IBC battery and has the corresponding functional modules and beneficial effects of the method.

[0111] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0112] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A method for preparing an IBC battery, characterized in that, include: Provides N-type silicon substrates; The N-type silicon substrate includes a front side and a back side that are opposite to each other, and the back side includes a first region and a second region arranged in an interdigitated space. A first tunneling oxide layer and a first doped layer are prepared in the first region; A second tunneling oxide layer and a second doped layer are prepared in the second region; Using a pre-defined flocking process, flocking is performed on the front surface and in the space between the first region and the second region to form a flocked structure. A first passivation layer is formed on the back surface opposite to the N-type silicon substrate, and a second passivation layer is formed on the front surface opposite to the N-type silicon substrate. The first region and the second region are screen printed and sintered at high temperature to form a first electrode in the first region that contacts the first doped layer, and a second electrode in the second region that contacts the second doped layer, thereby obtaining the IBC battery.

2. The preparation method according to claim 1, characterized in that, The preparation of a first tunneling oxide layer and a first doped layer in the first region includes: The first tunneling oxide layer and the first intrinsic silicon layer are respectively fabricated on the front side and the back side using a deposition process. The first intrinsic silicon layer is boron-doped using a boron diffusion process to form the first doped layer and the first mask layer. Remove the first mask layer, the first doped layer, and the first tunneling oxide layer from the second region, as well as the first mask layer on the front side.

3. The preparation method according to claim 2, characterized in that, Removing the first mask layer, the first doped layer, and the first tunneling oxide layer in the second region, as well as the first mask layer on the front side, includes: The first mask layer in the second region is removed using a laser process; An etching process is used to remove the first mask layer on the front side, as well as the first doped layer and the first tunneling oxide layer in the second region.

4. The preparation method according to claim 2, characterized in that, The fabrication of a second tunneling oxide layer and a second doped layer in the second region includes: The second tunneling oxide layer and the second intrinsic silicon layer are respectively prepared on the front side and the back side using a deposition process. The second intrinsic silicon layer is phosphorus-doped using a phosphorus diffusion process to form the second doped layer and the second mask layer. Remove the second mask layer from the first region and the interval region, as well as the second mask layer from the front side.

5. The preparation method according to claim 4, characterized in that, Using a pre-defined flocking process, flocking is performed on the front surface and in the space between the first and second regions to form a flocked structure, including: The second doped layer and the second tunneling oxide layer in the first region, as well as the second doped layer, the second tunneling oxide layer, the first doped layer, and the first tunneling oxide layer on the front side, are removed by using a coarse grooving process and an alkaline etching process. The pile fabrication process is used to pile the spaced areas and the front surface to form the pile structure.

6. The preparation method according to claim 5, characterized in that, After forming the pile structure by performing a pile forming process on the interval area and the front side, the process includes: An acid etching process is used to remove the first mask layer in the first region and the second mask layer in the second region.

7. The preparation method according to claim 5, characterized in that, The rough polishing process includes a mixed solution of an alkaline solution and an additive, wherein the additive is a polishing additive that has the function of protecting the first mask layer and / or the second mask layer.

8. The preparation method according to claim 7, characterized in that, The mass ratio of the alkaline solution to the additive is in the range of 1%-5%, and the concentration of the mixed solution is in the range of 15%-20%.

9. The preparation method according to claim 7, characterized in that, The etching time range of the rough grooving process is 3 min to 5 min, and the etching temperature range is 70℃ to 80℃.

10. An IBC battery, characterized in that, The IBC battery is prepared using the method described in any one of claims 1-9.

Images