A low-power approximate equalization circuit and method based on frequency domain error property mapping

Abstract

This invention relates to the fields of high-speed serial communication and digital signal processing, and discloses a low-power approximate equalization circuit and method based on frequency domain error attribute mapping. The circuit includes: a Fast Fourier Transform (FFT) module for converting the time-domain signal to be equalized into a frequency-domain signal; a frequency-domain equalization processing module for equalizing the frequency-domain signal; an Inverse Fast Fourier Transform (IFT) module for converting the equalized frequency-domain signal into a time-domain output signal; and a mapping control module for constructing a three-dimensional error attribute mapping relationship with frequency domain sub-bands as the first dimension, approximate calculation accuracy level as the second dimension, and the error polarity of the approximate arithmetic unit as the third dimension. This invention simultaneously considers frequency domain position, approximate accuracy, and error polarity characteristics in frequency-domain equalization, and achieves system-level error balance without introducing additional compensation circuits, thereby achieving low-power, high-reliability frequency-domain equalization.

Description

Technical Field

[0001] This invention relates to the fields of high-speed serial communication and digital signal processing, and more specifically, to a low-power approximate equalization circuit and method based on frequency domain error attribute mapping. Background Technology

[0002] In high-speed optical communication systems, high-speed serial interfaces, and inter-chip interconnect systems, as transmission rates continue to increase, problems such as limited channel bandwidth, dispersion effects, and inter-symbol interference become increasingly prominent. Receivers typically need to introduce equalization circuits to compensate for channel distortion. Among these, frequency domain equalization (FDE) is widely used in high-speed optical communication and high-speed interface systems due to its superior computational complexity under highly impaired channel conditions.

[0003] A typical frequency domain equalization architecture usually includes modules such as fast Fourier transform, frequency domain equalization processing, and inverse fast Fourier transform. Among them, the frequency domain equalization processing involves a large number of complex multiplication operations, which is the main source of power consumption and area of ​​the entire system.

[0004] To reduce hardware complexity, existing technologies have attempted to introduce approximate calculation techniques into frequency domain equalization circuits, sacrificing some computational accuracy in certain arithmetic units in exchange for reduced power consumption and area. However, existing approximate frequency domain equalization schemes typically suffer from the following shortcomings:

[0005] (1) The approximate calculation accuracy is mostly based on the frequency domain sub-bands, but the statistical characteristics of the approximation error in different sub-bands are not further distinguished. The low frequency sub-band usually contains the main energy and key information of the signal, such as the channel response and DC component. The high frequency sub-band usually has low signal energy and is not sensitive to accuracy. If the low frequency sub-band and the high frequency sub-band use the same or similar approximation intensity, it will lead to a significant increase in the bit error rate, a deterioration of the error vector amplitude, and a decrease in the system convergence. If the sub-band characteristics are not distinguished, the high frequency sub-band will also be forced to use high-precision arithmetic units, resulting in wasted power consumption, redundant hardware area, and insufficient optimization space. At the same time, if the approximation error is uniformly distributed in the frequency domain, it will produce unpredictable error peaks in the time domain after the inverse fast Fourier transform, which cannot be effectively compensated by subsequent processing.

[0006] (2) Most schemes only focus on the error magnitude and ignore the polarity distribution characteristics of the output error of the approximate arithmetic unit in the positive or negative direction, resulting in the statistical polarity of the error being too large in the positive direction or too small in the negative direction. If the polarity of all sub-band errors is consistent, after the inverse fast Fourier transform, a cumulative positive or negative offset will be formed in the time domain. This offset cannot be eliminated by the equalizer itself and requires an additional calibration circuit, which increases the hardware complexity and also offsets some of the power consumption and area benefits brought by the approximate calculation.

[0007] Therefore, how to simultaneously consider frequency domain position, approximation accuracy, and error polarity characteristics in frequency domain equalization, and achieve system-level error balance without introducing additional compensation circuits, has become a key technical problem in realizing low-power, high-reliability frequency domain equalization. Summary of the Invention

[0008] To address the problems existing in the prior art, this invention provides a low-power approximate equalization circuit and method based on frequency domain error attribute mapping. In frequency domain equalization, frequency domain position, approximation accuracy and error polarity characteristics are considered simultaneously, and system-level error balance is achieved without introducing additional compensation circuits, thereby achieving low-power and high-reliability frequency domain equalization.

[0009] To achieve the above technical objectives, the present invention adopts the following technical solution: A low-power approximate equalization circuit based on frequency domain error attribute mapping includes: a fast Fourier transform module, a frequency domain equalization processing module, an inverse fast Fourier transform module, and a mapping control module. The Fast Fourier Transform module is used to convert the time-domain signal to be equalized into a frequency-domain signal. The frequency domain equalization processing module is equipped with multiple frequency domain processing units, each of which corresponds to one or a group of frequency domain sub-bands. Different types of approximate arithmetic units are introduced through the frequency domain sub-bands to perform equalization processing on the frequency domain signal. The inverse fast Fourier transform module is used to convert the frequency domain signal processed by equalization into a time domain output signal; The mapping control module is used to construct a three-dimensional error attribute mapping relationship with frequency domain sub-band as the first dimension, approximate calculation accuracy level as the second dimension, and error polarity of approximate arithmetic unit as the third dimension, in order to determine the type of approximate arithmetic unit used in each frequency domain processing unit.

[0010] Furthermore, the frequency domain subband includes at least one or more of low-frequency subband, mid-frequency subband, and high-frequency subband.

[0011] Furthermore, the frequency domain processing unit corresponding to the low-frequency sub-band includes: a first complex data multiplier, an approximate arithmetic unit with high approximation calculation accuracy and negative error bias, a first carry-store adder, and a first row carry adder; The first complex data multiplier is used to perform complex multiplication on the frequency domain signal of the low-frequency subband to obtain the first multiplication result; The approximate arithmetic unit with high approximate calculation accuracy and negative error bias is used to introduce negative error bias and perform high-precision approximate summation on the result of the first multiplication operation to obtain the first approximate summation result; The carry-preserving adder is used to compress the first approximate summation result into two redundant sum vectors and a carry vector. The carry adder is used to sum the sum vector and the carry vector to obtain an accurate low-frequency equalization result. in: The approximate arithmetic unit with high approximate calculation accuracy and negative error bias includes: an accurate partial product generation array, an accurate 4-2 compressed tree, and a negative error bias logic block; The precise partial product generation array is used to generate a complete partial product array from the result of the first multiplication operation through Booth encoding. The precise 4-2 compression tree is used to precisely compress the partial products of high-weight bits and medium-weight bits in the partial product array without bit truncation, thus obtaining the precise compression results of high-weight bits and medium-weight bits. The negative error bias logic block is used to introduce fixed clear logic at the least significant bit position of the partial product array or to suppress the carry propagation of the least significant bit in the final addition stage, forming a negative error bias, and performing approximate compression processing on the partial product of the low-weight bits in the partial product array to obtain the approximate compression result of the low-weight bits. The precise compression results of the high-weight and medium-weight bits, together with the approximate compression results of the low-weight bits, constitute the first approximate summation result.

[0012] Furthermore, the frequency domain processing unit corresponding to the intermediate frequency sub-band includes: a second complex data multiplier, an approximate arithmetic unit with medium approximate calculation accuracy and dynamically configurable error, a second carry-store adder, and a second row carry adder; The second complex data multiplier is used to perform complex multiplication on the frequency domain signal of the intermediate frequency sub-band to obtain the second multiplication result; The approximate arithmetic unit with medium approximate calculation accuracy and dynamically configurable error polarity is used to dynamically select the error polarity of the approximate arithmetic unit, and to perform medium-precision approximate summation on the second multiplication result to obtain the second approximate summation result; The second carry-preserving adder is used to compress the second approximate summation result into two redundant sum vectors and a carry vector; The second row carry adder is used to sum the sum vector and the carry vector to obtain an accurate intermediate frequency equalization result; in: The approximate arithmetic unit with medium approximate calculation accuracy and dynamically configurable error polarity includes: an accurate compressor array, an approximate compressor array, a truncation processing unit, and a configurable polarity logic unit; The configurable polarity logic unit is used to generate a negative error bias or a positive error bias according to the configuration signal of the error polarity of the approximate arithmetic unit in the mapping control module, and control the approximate compressor array to enable negative compression logic or positive compression logic. The precise compressor array is used to precisely compress the partial product of the high-weight bits in the result of the second multiplication operation, so as to obtain the precise compression result of the high-weight bits. The approximate compressor array is used to perform approximate compression processing by combining the partial product of the middle weight bits in the second multiplication result with negative compression logic or positive compression logic to obtain the approximate compression result of the middle weight bits. The truncation processing unit is used to directly truncate the partial product of the low-weight bits in the result of the second multiplication operation. The precise compression result of the high-weight bits and the approximate compression result of the medium-weight bits are combined to form the second approximate summation result.

[0013] Furthermore, the frequency domain processing unit corresponding to the high-frequency sub-band includes: a third complex multiplier, an approximate arithmetic unit with low approximation calculation accuracy and positive error bias, and a simplified summation logic unit; The third complex multiplier is used to perform complex multiplication on the frequency domain signal of the high-frequency subband to obtain the result of the third multiplication operation. The approximate arithmetic unit with low approximate calculation accuracy and positive error bias is used to introduce positive error bias and perform low-precision approximate summation on the third multiplication result to obtain the third approximate summation result. The simplified summation logic unit is used to perform addition operations on the third approximate summation result without carry propagation or with a shortened carry chain, and outputs a high-frequency equalization result. in: The approximate arithmetic unit with low approximate calculation accuracy and positive error bias includes: a partial product truncation module and a positive approximate compressor array; The partial product truncation module is used to truncate the result of the third multiplication operation with low-weight bits. The forward approximation compressor array is used to introduce a forward error bias to approximate and compress the partial product retained in the third multiplication result, thereby obtaining the third approximate summation result.

[0014] Furthermore, the mapping control module includes: a precision configuration register, a polarity configuration register, a frequency point index generation unit, and a sub-band lookup table (LUT); The precision configuration register is used to store the approximate precision level corresponding to each frequency domain sub-band; The polarity configuration register is used to store the error polarity configuration corresponding to each frequency domain sub-band; The frequency index generation unit is used to generate the frequency index of the frequency domain signal; The subband lookup table (LUT) is used to determine the frequency domain subband based on the frequency point index, select the approximate calculation accuracy level and error polarity combination of the corresponding approximate arithmetic unit, and form a three-dimensional error attribute mapping relationship.

[0015] Furthermore, the mapping control module also includes: a performance monitoring interface and a dynamic configuration control state machine (FSM); The performance monitoring interface is used to receive performance metrics, including at least one of the following: bit error rate, error vector amplitude, or signal-to-noise ratio; The Dynamic Configuration Control State Machine (FSM) is used to dynamically update the three-dimensional error attribute mapping relationship based on performance indicators.

[0016] Furthermore, if frequency index The corresponding frequency domain signal is the low-frequency subband; if the frequency point index The corresponding frequency domain signal is the intermediate frequency sub-band; if the frequency point index The corresponding frequency domain signal is the high-frequency subband; in, The number of points representing the frequency domain signal. , This is the floor function. Indicates the first boundary parameter. Indicates the second boundary parameter. .

[0017] Furthermore, the present invention also provides a low-power approximate equalization method based on frequency domain error attribute mapping, comprising the following steps: Step S1: Perform a fast Fourier transform on the time-domain signal to be equalized to obtain the frequency-domain signal; Step S2: Construct a three-dimensional error attribute mapping relationship with frequency domain sub-band as the first dimension, approximate calculation accuracy level as the second dimension, and approximate calculation error polarity as the third dimension; Step S3: Determine the frequency index of the frequency domain signal, and determine the type of approximate arithmetic unit based on the constructed three-dimensional error attribute mapping relationship; Step S4: Perform equalization processing on the frequency domain signal using the determined approximate arithmetic unit; Step S5: Perform an inverse fast Fourier transform on the frequency domain signal after equalization to obtain the time domain output signal.

[0018] Compared with the prior art, the present invention has the following beneficial effects: (1) This invention constructs a three-dimensional error attribute mapping relationship with frequency domain sub-band as the first dimension, approximate calculation accuracy level as the second dimension, and error polarity of approximate arithmetic unit as the third dimension. The frequency domain sub-band to which the current frequency domain signal belongs is determined based on the frequency point index. Then, the approximate accuracy level and error polarity of the approximate arithmetic unit are determined according to the three-dimensional error attribute mapping relationship, and the type of matching approximate arithmetic unit is selected for each frequency domain processing unit. Through the three-dimensional error attribute mapping relationship, the approximate calculation intensity and error direction can be configured differently according to the importance of the frequency domain position, achieving refined and independent control of the calculation accuracy of different frequency domain sub-bands. (2) This invention utilizes the linear superposition property of the inverse fast Fourier transform to automatically balance the opposite polarity errors introduced by different frequency sub-bands in the time domain. Specifically, the approximate arithmetic unit corresponding to the low-frequency sub-band uses a negative error bias logic block to make the output lower than the accurate calculation result, forming a negative error bias; the approximate arithmetic unit corresponding to the high-frequency sub-band uses a positive approximate compressor array to make the output slightly higher than the accurate calculation result, forming a positive error bias. The frequency domain errors carrying opposite polarities are converted to the time domain by the inverse fast Fourier transform and cancel each other out in a statistical sense, avoiding the accumulation of errors in the same direction, thereby achieving system-level error balance without additional compensation circuitry.

[0019] (3) In the high-frequency subband, the present invention uses an approximate arithmetic unit with low approximate calculation accuracy and positive error bias. Compared with the exact multiplier, which needs to retain all partial products and perform complete carry propagation addition, the approximate arithmetic unit of the high-frequency subband greatly reduces the number of bits involved in the operation, the number of compressors and the number of adder stages, thereby significantly reducing dynamic switching power consumption, logic gate leakage power consumption and chip area. Attached Figure Description

[0020] Figure 1 This is a schematic diagram of the low-power approximate equalization circuit based on frequency domain error attribute mapping of the present invention. Figure 2 This is a schematic diagram illustrating the mapping relationship between frequency domain subbands and approximation accuracy and error polarity. Figure 3 This is a schematic diagram of the frequency domain processing unit corresponding to the low-frequency sub-band in this invention; Figure 4 This is a schematic diagram of the frequency domain processing unit corresponding to the intermediate frequency sub-band in this invention; Figure 5 This is a schematic diagram of the frequency domain processing unit corresponding to the high-frequency sub-band in this invention; Figure 6 This is a schematic diagram of the mapping control module in this invention; Figure 7 This is a schematic diagram illustrating the cancellation of frequency domain errors in the time domain after inverse fast Fourier transform. Figure 8This is a flowchart of the low-power approximate equalization method based on frequency domain error attribute mapping according to the present invention. Detailed Implementation

[0021] The technical solution of the present invention will be further explained and described below with reference to the accompanying drawings.

[0022] like Figure 1 This is a schematic diagram of the low-power approximate equalization circuit based on frequency domain error attribute mapping according to the present invention. The low-power approximate equalization circuit includes: an input interface module, a fast Fourier transform module, a frequency domain equalization processing module, an inverse fast Fourier transform module, and a mapping control module. The input interface module is used to receive the time-domain signal to be equalized; The Fast Fourier Transform module is used to convert the time-domain signal to be equalized into a frequency-domain signal; The frequency domain equalization processing module has multiple frequency domain processing units, each of which corresponds to one or a group of frequency domain sub-bands. Different types of approximate arithmetic units are introduced through the frequency domain sub-bands to perform equalization processing on the frequency domain signal. The inverse fast Fourier transform module is used to convert the frequency domain signal processed by equalization into a time domain output signal; The mapping control module is used to construct a three-dimensional error attribute mapping relationship with frequency domain sub-band as the first dimension, approximate calculation accuracy level as the second dimension, and error polarity of approximate arithmetic unit as the third dimension, in order to determine the type of approximate arithmetic unit used in each frequency domain processing unit.

[0023] This invention relates to a low-power approximate equalization circuit based on frequency domain error attribute mapping. By constructing a three-dimensional error attribute mapping relationship and coordinating the approximate arithmetic units in different frequency domain processing units based on the three-dimensional error attribute mapping relationship, the errors introduced by different frequency domain sub-bands can be statistically canceled in the time domain output after inverse fast Fourier transform. Thus, low-power and high-reliability frequency domain equalization processing can be achieved without introducing additional error compensation circuits.

[0024] In one technical solution of the present invention, the frequency domain sub-band includes at least one or more of low-frequency, mid-frequency, and high-frequency sub-bands. The approximate arithmetic units corresponding to different frequency domain sub-bands differ in at least one of the following: approximate calculation accuracy level and error polarity. This allows approximate errors with different polarities and amplitudes introduced by different frequency domain sub-bands to statistically cancel each other out and redistribute energy after being converted to the time domain by inverse fast Fourier transform, thereby suppressing time-domain error peaks and avoiding the introduction of additional system-level DC offset. The error polarity includes positive error bias and negative error bias, used to characterize the statistical error offset direction of the approximate arithmetic unit output result relative to the accurate calculation result. Figure 2The frequency domain processing unit corresponding to the low-frequency sub-band adopts an approximate arithmetic unit with high approximation calculation accuracy and negative error bias. It contains the main energy of the frequency domain signal. The high accuracy ensures basic performance, and the negative error bias can be canceled out by the positive error bias of other frequency domain sub-bands after inverse fast Fourier transform. The frequency domain processing unit corresponding to the mid-frequency sub-band adopts an approximate arithmetic unit with medium approximation calculation accuracy and dynamically configurable error. The corresponding frequency domain signal energy is moderate, and the accuracy requirement is between high and low frequencies. The error polarity can be dynamically configured according to the system performance indicators. The frequency domain processing unit corresponding to the high-frequency sub-band adopts an approximate arithmetic unit with low approximation calculation accuracy and positive error bias. The corresponding frequency domain signal energy is low and is not sensitive to accuracy. An aggressive approximation is used to maximize power saving.

[0025] like Figure 3 The frequency domain processing unit corresponding to the low-frequency sub-band includes: a first complex data multiplier, an approximate arithmetic unit with high approximation calculation accuracy and negative error bias, a first carry-store adder, and a first row carry adder. The first complex data multiplier is used to perform complex multiplication on the frequency domain signal of the low-frequency subband to obtain the first multiplication result; An approximate arithmetic unit with high approximate calculation accuracy and negative error bias is used to introduce negative error bias and perform high-precision approximate summation on the result of the first multiplication operation to obtain the first approximate summation result; The carry-preserving adder is used to compress the first approximate summation result into two redundant forms: a sum vector and a carry vector. The carry adder is used to sum the sum vector and the carry vector to obtain an accurate low-frequency equalization result.

[0026] The approximate arithmetic unit with high approximate calculation accuracy and negative error bias in this invention includes: an accurate partial product generation array, an accurate 4-2 compressed tree, and a negative error bias logic block; The precise partial product generation array is used to generate a complete partial product array from the result of the first multiplication operation through Booth encoding; The precise 4-2 compression tree is used to precisely compress the partial products of high-weight bits and medium-weight bits in a partial product array without bit truncation, resulting in precise compression of high-weight bits and medium-weight bits. The negative error bias logic block is used to introduce fixed clear logic at the least significant bit position of the partial product array or to suppress the carry propagation of the least significant bit in the final addition stage, forming a negative error bias. It performs approximate compression processing on the partial product of the low-weight bits in the partial product array, and obtains the approximate compression result of the low-weight bits, which is slightly lower than the accurate calculation result. The precise compression results of the high-weight and medium-weight bits, together with the approximate compression results of the low-weight bits, constitute the first approximate summation result.

[0027] like Figure 4 The frequency domain processing unit corresponding to the intermediate frequency sub-band includes: a second complex data multiplier, an approximate arithmetic unit with medium approximate calculation accuracy and error dynamically configurable, a second carry-store adder, and a second row carry adder. The second complex data multiplier is used to perform complex multiplication operations on the frequency domain signal of the intermediate frequency sub-band to obtain the second multiplication result; An approximate arithmetic unit with medium approximate calculation accuracy and dynamically configurable error polarity is used to dynamically select the error polarity of the approximate arithmetic unit, and to perform a medium-precision approximate summation operation on the second multiplication result to obtain the second approximate summation result; The second carry-preserving adder is used to compress the second approximate summation result into two redundant sum vectors and carry vectors; The second row of carry adders is used to sum the sum vector and the carry vector to obtain an accurate intermediate frequency equalization result.

[0028] The approximate arithmetic unit with medium approximate calculation accuracy and dynamically configurable error polarity in this invention includes: an accurate compressor array, an approximate compressor array, a truncation processing unit, and a configurable polarity logic unit; The configurable polarity logic unit is used to generate a negative error bias or a positive error bias based on the configuration signal of the error polarity of the approximate arithmetic unit in the mapping control module, and to control the approximate compressor array to enable negative compression logic or positive compression logic. The precise compressor array is used to precisely compress the partial product of the high-weight bits in the result of the second multiplication operation, so as to obtain the precise compressed result of the high-weight bits; The approximate compressor array is used to combine the partial product of the middle weight bits in the result of the second multiplication operation with negative or positive compression logic to perform approximate compression processing, so as to obtain the approximate compression result of the middle weight bits and reduce power consumption. The truncation processing unit is used to directly truncate the partial product of the low-weight bits in the result of the second multiplication operation, so that it does not participate in subsequent operations; The precise compression result of the high-weight bits and the approximate compression result of the medium-weight bits are combined to form the second approximate summation result.

[0029] like Figure 5 The frequency domain processing unit corresponding to the high-frequency sub-band includes: a third complex multiplier, an approximate arithmetic unit with low approximation calculation accuracy and positive error bias, and a simplified summation logic unit; The third complex multiplier is used to perform complex multiplication operations on the frequency domain signal of the high-frequency subband to obtain the result of the third multiplication operation; An approximate arithmetic unit with low approximate calculation accuracy and positive error bias is used to introduce positive error bias and perform low-precision approximate summation on the third multiplication result to obtain the third approximate summation result. The simplified summation logic unit is used to perform addition operations on the third approximate summation result without carry propagation or to shorten the carry chain, and outputs a high-frequency equalization result.

[0030] The approximate arithmetic unit with low approximate calculation accuracy and positive error bias in this invention includes: a partial product truncation module and a positive approximate compressor array; The partial product truncation module is used to truncate the result of the third multiplication operation with low weight bits; specifically, for the result of the third multiplication operation with 16 bits, the partial product of the lower 8 bits is directly truncated and does not participate in subsequent operations. The forward approximation compressor array is used to introduce a forward error bias to approximate and compress the partial product retained in the third multiplication result, resulting in a third approximate summation result, which is slightly higher than the accurate calculation result.

[0031] This invention employs an approximate arithmetic unit with low approximate calculation accuracy and positive error bias in the high-frequency subband. Compared to an exact multiplier that needs to retain all partial products and perform complete carry propagation addition, the approximate arithmetic unit in the high-frequency subband significantly reduces the number of bits involved in the operation, the number of compressors, and the number of adder stages, thereby significantly reducing dynamic switching power consumption and logic gate leakage power consumption and reducing chip area.

[0032] like Figure 6 The mapping control module in this invention includes: a precision configuration register, a polarity configuration register, a frequency point index generation unit, a subband lookup table (LUT), a performance monitoring interface, and a dynamic configuration control state machine (FSM). The precision configuration register is used to store the approximate precision level corresponding to each frequency domain sub-band; The polarity configuration register is used to store the error polarity configuration corresponding to each frequency domain sub-band; The frequency index generation unit is used to generate the frequency index of the frequency domain signal; The Subband Lookup Table (LUT) is used to determine the frequency domain subband based on the frequency index, select the approximate calculation accuracy level and error polarity combination of the corresponding approximate arithmetic unit, and construct a three-dimensional error attribute mapping relationship; specifically: if the frequency index The corresponding frequency domain signal is the low-frequency subband; if the frequency point index The corresponding frequency domain signal is the intermediate frequency sub-band; if the frequency point index The corresponding frequency domain signal is the high-frequency subband; in, The number of points representing the frequency domain signal. , This is the floor function. Indicates the first boundary parameter. Indicates the second boundary parameter. .

[0033] When the frequency domain data stream is input, the frequency domain equalization processing module synchronously reads the current frequency point index. The subband lookup table (LUT) is queried to instantly determine the subband to which the data belongs. Based on the three-dimensional error attribute mapping relationship, the approximate accuracy level and error polarity of the approximate arithmetic unit are determined, and a matching approximate arithmetic unit type is selected for each frequency domain processing unit. Through the three-dimensional error attribute mapping relationship, the approximate calculation intensity and error direction can be configured differently according to the importance of the frequency domain location, achieving fine-grained independent control over the calculation accuracy of different frequency domain subbands.

[0034] The performance monitoring interface is used to receive performance metrics, including at least one of the following: bit error rate, error vector magnitude, or signal-to-noise ratio; The Dynamic Configuration Control State Machine (FSM) is used to dynamically update the three-dimensional error attribute mapping relationship in the Subband Lookup Table (LUT) based on performance indicators. The LUT supports online reconfiguration and can be dynamically adjusted according to performance indicators such as bit error rate. and The values ​​and corresponding precision and polarity configurations.

[0035] like Figure 7 This diagram illustrates the cancellation of frequency domain errors in the time domain after inverse fast Fourier transform (IFFT). In the frequency domain equalization module, the low-frequency sub-band is configured with a negative error bias, and its approximate calculation result is slightly lower than the precise calculation result. The high-frequency sub-band is configured with a positive error bias, and its approximate calculation result is slightly higher than the precise calculation result. The mid-frequency sub-band can be dynamically configured with error polarity. After the frequency domain errors with different polarities are mapped to the time domain by IFFT, the positive and negative errors statistically cancel each other out, making the mean error of the time-domain output signal approach zero and avoiding the generation of systematic offset. Unlike existing technologies that require additional compensation circuits due to a single error polarity, this invention achieves natural error cancellation through a system-level coordinated distribution of error polarity.

[0036] like Figure 8 The present invention also provides a low-power approximate equalization method based on frequency domain error attribute mapping, comprising the following steps: Step S1: Perform a fast Fourier transform on the time-domain signal to be equalized to obtain the frequency-domain signal; Step S2: Construct a three-dimensional error attribute mapping relationship with frequency domain sub-band as the first dimension, approximate calculation accuracy level as the second dimension, and approximate calculation error polarity as the third dimension; Step S3: Determine the frequency index of the frequency domain signal, and determine the type of approximate arithmetic unit based on the constructed three-dimensional error attribute mapping relationship; Step S4: Perform equalization processing on the frequency domain signal using the approximate arithmetic unit; Step S5: Perform an inverse fast Fourier transform on the frequency domain signal after equalization to obtain the time domain output signal.

[0037] Example In a 128-point Fast Fourier Transform frequency domain equalizer, there are 128 frequency domain processing units. Using the low-power approximate equalization method based on frequency domain error attribute mapping, as described in this invention, the frequency domain signal is divided into three sub-band regions: low-frequency, mid-frequency, and high-frequency. The low-frequency sub-band is configured with approximate arithmetic units of high approximate calculation accuracy and negative error bias; the mid-frequency sub-band is configured with approximate arithmetic units of medium approximate calculation accuracy and dynamically configurable error; and the high-frequency sub-band is configured with approximate arithmetic units of low approximate calculation accuracy and positive error bias. This configuration significantly reduces the power consumption and area of ​​the equalization circuit while maintaining essentially unchanged bit error performance.

[0038] In the embodiments disclosed in this application, a computer storage medium may be a tangible medium that may contain or store programs for use by or in conjunction with an instruction execution system, apparatus, or device. The computer storage medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of computer storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, and portable compact disc read-only memory (CD). ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0039] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed in this application can be implemented in electronic hardware or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0040] The above are merely preferred embodiments of the present invention. The scope of protection of the present invention is not limited to the above embodiments. All technical solutions falling within the scope of the present invention's concept are within the scope of protection of the present invention. It should be noted that for those skilled in the art, any improvements and modifications made without departing from the principles of the present invention should be considered within the scope of protection of the present invention.

Claims

1. A low-power approximate equalization circuit based on frequency domain error attribute mapping, characterized in that, include: Fast Fourier Transform module, frequency domain equalization processing module, inverse Fast Fourier Transform module, and mapping control module; The Fast Fourier Transform module is used to convert the time-domain signal to be equalized into a frequency-domain signal. The frequency domain equalization processing module is equipped with multiple frequency domain processing units, each of which corresponds to one or a group of frequency domain sub-bands. Different types of approximate arithmetic units are introduced through the frequency domain sub-bands to perform equalization processing on the frequency domain signal. The inverse fast Fourier transform module is used to convert the frequency domain signal processed by equalization into a time domain output signal; The mapping control module is used to construct a three-dimensional error attribute mapping relationship with frequency domain sub-band as the first dimension, approximate calculation accuracy level as the second dimension, and error polarity of approximate arithmetic unit as the third dimension, in order to determine the type of approximate arithmetic unit used in each frequency domain processing unit.

2. The low-power approximate equalization circuit based on frequency domain error attribute mapping according to claim 1, characterized in that, The frequency domain subband includes at least one or more of low-frequency subband, mid-frequency subband, and high-frequency subband.

3. The low-power approximate equalization circuit based on frequency domain error attribute mapping according to claim 2, characterized in that, The frequency domain processing unit corresponding to the low-frequency sub-band includes: a first complex data multiplier, an approximate arithmetic unit with high approximation calculation accuracy and negative error bias, a first carry-store adder, and a first row carry adder. The first complex data multiplier is used to perform complex multiplication on the frequency domain signal of the low-frequency subband to obtain the first multiplication result; The approximate arithmetic unit with high approximate calculation accuracy and negative error bias is used to introduce negative error bias and perform high-precision approximate summation on the result of the first multiplication operation to obtain the first approximate summation result; The carry-preserving adder is used to compress the first approximate summation result into two redundant sum vectors and a carry vector. The carry adder is used to sum the sum vector and the carry vector to obtain an accurate low-frequency equalization result. in: The approximate arithmetic unit with high approximate calculation accuracy and negative error bias includes: an accurate partial product generation array, an accurate 4-2 compressed tree, and a negative error bias logic block; The precise partial product generation array is used to generate a complete partial product array from the result of the first multiplication operation through Booth encoding. The precise 4-2 compression tree is used to precisely compress the partial products of high-weight bits and medium-weight bits in the partial product array without bit truncation, thus obtaining the precise compression results of high-weight bits and medium-weight bits. The negative error bias logic block is used to introduce fixed clear logic at the least significant bit position of the partial product array or to suppress the carry propagation of the least significant bit in the final addition stage, forming a negative error bias, and performing approximate compression processing on the partial product of the low-weight bits in the partial product array to obtain the approximate compression result of the low-weight bits. The precise compression results of the high-weight and medium-weight bits, together with the approximate compression results of the low-weight bits, constitute the first approximate summation result.

4. A low-power approximate equalization circuit based on frequency domain error attribute mapping according to claim 2, characterized in that, The frequency domain processing unit corresponding to the intermediate frequency sub-band includes: a second complex data multiplier, an approximate arithmetic unit with medium approximate calculation accuracy and error dynamically configurable, a second carry-store adder, and a second row carry adder. The second complex data multiplier is used to perform complex multiplication on the frequency domain signal of the intermediate frequency sub-band to obtain the second multiplication result; The approximate arithmetic unit with medium approximate calculation accuracy and dynamically configurable error polarity is used to dynamically select the error polarity of the approximate arithmetic unit, and to perform medium-precision approximate summation on the second multiplication result to obtain the second approximate summation result; The second carry-preserving adder is used to compress the second approximate summation result into two redundant sum vectors and a carry vector; The second row carry adder is used to sum the sum vector and the carry vector to obtain an accurate intermediate frequency equalization result; in: The approximate arithmetic unit with medium approximate calculation accuracy and dynamically configurable error polarity includes: an accurate compressor array, an approximate compressor array, a truncation processing unit, and a configurable polarity logic unit; The configurable polarity logic unit is used to generate a negative error bias or a positive error bias according to the configuration signal of the error polarity of the approximate arithmetic unit in the mapping control module, and control the approximate compressor array to enable negative compression logic or positive compression logic. The precise compressor array is used to precisely compress the partial product of the high-weight bits in the result of the second multiplication operation, so as to obtain the precise compression result of the high-weight bits. The approximate compressor array is used to perform approximate compression processing by combining the partial product of the middle weight bits in the second multiplication result with negative compression logic or positive compression logic to obtain the approximate compression result of the middle weight bits. The truncation processing unit is used to directly truncate the partial product of the low-weight bits in the result of the second multiplication operation. The precise compression result of the high-weight bits and the approximate compression result of the medium-weight bits are combined to form the second approximate summation result.

5. A low-power approximate equalization circuit based on frequency domain error attribute mapping according to claim 2, characterized in that, The frequency domain processing unit corresponding to the high-frequency sub-band includes: a third complex multiplier, an approximate arithmetic unit with low approximation calculation accuracy and positive error bias, and a simplified summation logic unit; The third complex multiplier is used to perform complex multiplication on the frequency domain signal of the high-frequency subband to obtain the result of the third multiplication operation. The approximate arithmetic unit with low approximate calculation accuracy and positive error bias is used to introduce positive error bias and perform low-precision approximate summation on the third multiplication result to obtain the third approximate summation result. The simplified summation logic unit is used to perform addition operations on the third approximate summation result without carry propagation or with a shortened carry chain, and outputs a high-frequency equalization result. in: The approximate arithmetic unit with low approximate calculation accuracy and positive error bias includes: a partial product truncation module and a positive approximate compressor array; The partial product truncation module is used to truncate the result of the third multiplication operation with low-weight bits. The forward approximation compressor array is used to introduce a forward error bias to approximate and compress the partial product retained in the third multiplication result, thereby obtaining the third approximate summation result.

6. A low-power approximate equalization circuit based on frequency domain error attribute mapping according to claim 1, characterized in that, The mapping control module includes: a precision configuration register, a polarity configuration register, a frequency point index generation unit, and a sub-band lookup table (LUT); The precision configuration register is used to store the approximate precision level corresponding to each frequency domain sub-band; The polarity configuration register is used to store the error polarity configuration corresponding to each frequency domain sub-band; The frequency index generation unit is used to generate the frequency index of the frequency domain signal; The subband lookup table (LUT) is used to determine the frequency domain subband based on the frequency point index, select the approximate calculation accuracy level and error polarity combination of the corresponding approximate arithmetic unit, and form a three-dimensional error attribute mapping relationship.

7. A low-power approximate equalization circuit based on frequency domain error attribute mapping according to claim 6, characterized in that, The mapping control module also includes: a performance monitoring interface and a dynamic configuration control state machine (FSM); The performance monitoring interface is used to receive performance metrics, including at least one of the following: bit error rate, error vector amplitude, or signal-to-noise ratio; The Dynamic Configuration Control State Machine (FSM) is used to dynamically update the three-dimensional error attribute mapping relationship based on performance indicators.

8. A low-power approximate equalization circuit based on frequency domain error attribute mapping according to claim 6, characterized in that, If frequency point index The corresponding frequency domain signal is the low-frequency subband; if the frequency point index The corresponding frequency domain signal is the intermediate frequency sub-band; if the frequency point index The corresponding frequency domain signal is the high-frequency subband; in, The number of points representing the frequency domain signal. , This is the floor function. Indicates the first boundary parameter. Indicates the second boundary parameter. .

9. A low-power approximate equalization method based on frequency domain error attribute mapping, characterized in that, Includes the following steps: Step S1: Perform a fast Fourier transform on the time-domain signal to be equalized to obtain the frequency-domain signal; Step S2: Construct a three-dimensional error attribute mapping relationship with frequency domain sub-band as the first dimension, approximate calculation accuracy level as the second dimension, and approximate calculation error polarity as the third dimension; Step S3: Determine the frequency index of the frequency domain signal, and determine the type of approximate arithmetic unit based on the constructed three-dimensional error attribute mapping relationship; Step S4: Perform equalization processing on the frequency domain signal using the determined approximate arithmetic unit; Step S5: Perform an inverse fast Fourier transform on the frequency domain signal after equalization to obtain the time domain output signal.

Images