High bit rate FSKD jitter compensation circuit

Abstract

The present disclosure relates to high bit rate FSKD dither compensation circuit. According to embodiments, a wireless power receiving device includes a demodulator that generates carrier period data from a received frequency shift keying modulated signal having dither. A high pass filter circuit extracts offset values from the carrier period data. A polyphase filter circuit includes a plurality of smoothing filters and distributes the extracted offset values among the filters based on a dither pattern length. A compensation circuit stores smoothed offset values from the polyphase filter circuit in a dither table during an evaluation window and applies the stored values to compensate the carrier period data during a subsequent demodulation.

Description

Technical Field

[0001] This disclosure generally relates to electronic systems, and in certain embodiments, to jitter compensation techniques for high bit rate frequency shift keying demodulation. Background Technology

[0002] Wireless power transfer systems provide a convenient and wireless charging solution for a variety of electronic devices. These systems typically consist of a wireless power transmitter and a wireless power receiver, where the transmitter generates an electromagnetic field that is captured by the receiver and converted into electrical energy to charge the device's battery or directly power the device.

[0003] In many wireless power transmission systems, communication is established between the transmitter and receiver to facilitate efficient power transfer and ensure security. A common communication method in these systems is Frequency Shift Keying (FSK) modulation. FSK modulation is a technique for transmitting digital information by shifting the frequency of a carrier signal between two or more discrete values, each representing a specific data symbol.

[0004] When a wireless power transmitter establishes a connection with a compatible receiver, it can use FSK modulation to transmit data by modulating the operating frequency of the power signal. The receiver, in turn, uses an FSK demodulator to demodulate the received signal to extract the transmitted information. FSK modulation and demodulation create a communication channel that enables the transmission of parameters (such as device identification and other control data) from the power transmitter to the power receiver to operate the wireless power transmission system.

[0005] To minimize electromagnetic interference (EMI) with nearby electronic devices, wireless power delivery systems can incorporate techniques for reducing peak emission of the power signal. One such technique is jitter, which involves intentionally altering the frequency or phase of the power signal in a controlled manner. By distributing the signal's energy across a wider frequency range, jitter reduces peak emission at any single frequency, thereby improving EMC performance.

[0006] However, introducing jitter into the power signal can pose challenges to the FSK demodulation process at the receiver. Signal variations caused by jitter can affect the accuracy and reliability of the demodulated data, especially at high bit rates. With the increasing demand for faster communication and higher power transmission efficiency, there is a growing need for effective jitter compensation techniques to maintain the integrity of the demodulated data while benefiting from the EMI reduction provided by jitter. Summary of the Invention

[0007] The technical advantages are generally achieved by embodiments of this disclosure, which describe jitter compensation techniques for high bit rate frequency shift keying demodulation.

[0008] The first aspect relates to a wireless power receiving device configured to receive a frequency shift keying modulated signal with jitter, the wireless power receiving device comprising: a demodulator configured to generate carrier period data from the received modulated signal; a high-pass filter circuit configured to extract offset values ​​from the carrier period data; a polyphase filter circuit including a plurality of smoothing filters, the polyphase filter circuit being configured to receive the extracted offset values ​​and distribute the extracted offset values ​​among the plurality of smoothing filters based on a jitter mode length; and a compensation circuit configured to store the smoothed offset values ​​from the polyphase filter circuit in a jitter table during an evaluation window and apply the stored offset values ​​to compensate for the carrier period data during a subsequent demodulation period.

[0009] The second aspect relates to a jitter compensation circuit for a wireless power receiver, comprising: a high-pass filter configured to extract a carrier period offset; a polyphase filter including multiple smoothing filters and an allocation circuit configured to route the extracted carrier period offset to the corresponding smoothing filter based on its position within a jitter pattern length; a control circuit configured to track the completion of an evaluation window including multiple jitter pattern lengths; and a compensation circuit configured to store a smoothed offset value from the smoothing filters in a jitter table after the completion of the evaluation window, and to apply the stored offset value to compensate for the carrier period data during subsequent demodulation.

[0010] The third aspect relates to a method for compensating jitter in frequency shift keying demodulation, the method comprising: performing high-pass filtering on carrier period data to extract offset values; allocating the extracted offset values ​​among a plurality of smoothing filters based on jitter pattern lengths; smoothing the allocated offset values ​​over an evaluation window using the plurality of smoothing filters; storing the smoothed offset values ​​in a jitter table; and compensating subsequent carrier period data during demodulation using the stored offset values.

[0011] The embodiments can be implemented in hardware, software, or any combination thereof. Attached Figure Description

[0012] To fully understand this disclosure and its advantages, reference is now made to the following description taken in conjunction with the accompanying drawings, in which:

[0013] Figure 1 This is a block diagram of the wireless power system of an embodiment;

[0014] Figure 2 This is a block diagram of the receiving device in an embodiment;

[0015] Figure 3 It is possible to achieve this. Figure 2A block diagram of the embodiment circuit within the demodulator;

[0016] Figure 4 This is a block diagram of the jitter compensation circuit in an embodiment;

[0017] Figure 5 This is a block diagram of the control circuit of the embodiment;

[0018] Figure 6 This is a block diagram of the high-pass filter circuit in the embodiment;

[0019] Figure 7 This is a block diagram of the multiphase filter circuit in an embodiment;

[0020] Figure 8 This is a block diagram of the compensation circuit in the embodiment;

[0021] Figure 9 This is a flowchart of an embodiment of a method in a wireless power receiver;

[0022] Figure 10 This is a schematic diagram of an infinite impulse response (IIR) filter according to an embodiment; and

[0023] Figure 11 This is a schematic diagram of a recursive moving average circuit. Detailed Implementation

[0024] This disclosure provides numerous applicable inventive concepts that can be implemented in a wide range of specific contexts. Specific embodiments are merely illustrative of particular configurations and do not limit the scope of the claimed embodiments. Unless otherwise stated, features from different embodiments can be combined to form other embodiments. Various embodiments are illustrated in the accompanying drawings, wherein identical components and elements are identified by the same reference numerals, and repeated descriptions are omitted for brevity.

[0025] The variations or modifications described in one embodiment may also be applied to other embodiments. Furthermore, various modifications, substitutions, and alterations may be made to this document without departing from the spirit and scope of this disclosure as defined by the appended claims.

[0026] Although the inventive aspects have been described primarily in the context of wireless power transmission systems employing frequency shift keying demodulation, it should be understood that these inventive aspects can also be applied to other wireless communication systems that utilize FSK modulation and are affected by jitter. In particular, aspects of this disclosure can be similarly applied to wireless data communication systems, such as those present in radio frequency identification (RFID) tags, near field communication (NFC) devices, and short-range wireless communication protocols such as Bluetooth Low Energy (BLE).

[0027] In this embodiment, a jitter compensation technique for high bit rate frequency shift keying demodulation (FSKD) in wireless power transmission systems is proposed. This technique employs a combination of offset extraction, polyphase filtering, and table storage to mitigate the impact of jitter on the demodulated data.

[0028] In one embodiment, the wireless power receiver includes a counter-based FSKD demodulator that generates carrier period data from the received modulated signal. A high-pass filter circuit extracts an offset value from the carrier period data by determining the difference between each carrier period value and its corresponding mean. A polyphase filter circuit processes the extracted offset values ​​using multiple smoothing filters. A scheduling circuit distributes the offset values ​​among the smoothing filters based on their position within the jitter pattern length.

[0029] The polyphase filter circuit smooths the offset values ​​over an evaluation window spanning multiple jitter pattern lengths. After the evaluation window is complete, the smoothed offset values ​​can be stored in a jitter table. During subsequent modulation, the stored offset values ​​can be retrieved from the jitter table and applied to the incoming carrier period data to compensate for the effects of jitter.

[0030] Jitter compensation techniques offer several advantages over existing solutions. The proposed technique compensates for jitter by using an estimated jitter mode length at the receiver to extract and smooth offset values; this estimated jitter mode length is an integer multiple of the transmitter's jitter mode length. For example, if the transmitter has a jitter mode length of 8, the receiver can use a mode length of 16, but not 13, to ensure that offset values ​​are appropriately assigned to their corresponding smoothing filters. Furthermore, polyphase filtering allows for efficient processing of offset values, thereby reducing the computational burden on the receiver.

[0031] The disclosed technique is particularly well-suited for high-bit-rate FSKD applications, where jitter can have a more significant impact on demodulated data. By compensating for jitter in real time, this technique enables communication between the wireless power transmitter and receiver, even in the presence of high-bit-rate data transmission. These and additional details are discussed further below.

[0032] Figure 1 A block diagram of an embodiment of a wireless power system 100, also known as a wireless charging system, is shown. The system includes a transmitting device 110 and a receiving device 120, which may (or may not) be arranged as shown. The transmitting device 110 generates and transmits a power signal 130 to the receiving device 120.

[0033] Transmitting device 110 may be a base station, such as a charging pad, which provides inductive power to receiving device 120. Receiving device 120 may be, for example, a mobile device, tablet, cellular phone, wearable communication device (e.g., smartwatch), digital pen, wireless headphones, toothbrush, sensor, Internet of Things (IoT) device, etc. Receiving device 120 is the consumer of inductive power.

[0034] Transmitting device 110 includes transmitter coil 112 (L TX The receiving device 120 includes a receiver coil 122 (L). RX Each coil or winding can be a loop or a magnetic antenna. The coil can have a physical core (e.g., a ferrite core) or an air core. The coil can be implemented as an antenna strip or using Litz wire. The resonant frequency of each coil is based on the shape and size of the loop conductor or coil. In some embodiments, additional capacitance and inductance can be added to each coil to create a resonant structure at the desired resonant operating frequency.

[0035] In this embodiment, resonant inductive coupling between transmitter coil 112 and receiver coil 122 is used to transmit power signal 130 from transmitter 110 to receiver 120. Receiver 120 can use the power to charge a rechargeable battery or directly power its internal components.

[0036] In this embodiment, the wireless power system 100 employs amplitude shift keying (ASK) and frequency shift keying (FSK) modulation for communication between the transmitting device 110 and the receiving device 120. The transmitting device 110 can modulate the frequency of its power signal 130 to encode data, which is then demodulated by the receiving device 120. Conversely, the receiving device 120 can use an ASK modulated signal 140 to send back to the transmitting device 110. ASK / FSK communication allows the exchange of information such as power transfer protocols, device identification, and charging status.

[0037] The receiving device 120 may integrate glitch suppression circuitry within its FSK demodulator to ensure accurate demodulation and decoding of the power signal 130 even in the presence of noise and distortion that may arise from the power transmission process. Glitch suppression technology enables reliable high-bit-rate communication, which can be particularly beneficial for optimizing power transmission efficiency and supporting advanced features in compact electronic devices.

[0038] Figure 2A block diagram of an embodiment receiving device 120 is shown. The receiving device 120 includes a receiver coil 122, a voltage extractor circuit 220, a power charging circuit 200, a load 206, a comparator 208, a synchronization stage 210, and a demodulator 212, which may (or may not) be arranged as shown. The power charging circuit 200 includes a rectifier 202 and a regulator 204. The receiving device 120 may include... Figure 2 Additional components not shown include, for example, long-term storage devices (e.g., non-volatile memory), non-transitory computer-readable media, one or more antenna elements, drivers, demodulators, modulators, filter circuits, and impedance matching circuits.

[0039] Rectifier 202 converts the alternating current (AC) voltage at receiver coil 122 into a direct current (DC) voltage. It can be any type of rectifier, such as a low-impedance synchronous rectifier or an active rectifier with full-wave or half-wave rectification. In this embodiment, rectifier 202 can be a bridge rectifier; however, other types of rectifiers are also contemplated.

[0040] Regulator 204 receives voltage (V) from rectifier 202 RECT Then, the voltage is regulated to maintain a constant output voltage (V) at load 206. OUT Regulator 204 can be any type of voltage regulator, such as a linear regulator (e.g., a low dropout (LDO) linear regulator). In some embodiments, rectifier 202 and regulator 204 can be part of a switch-mode power supply (SMPS) circuit.

[0041] As shown, load 206 is the primary beneficiary of the wireless power transmitted from transmitting device 110 to receiving device 120. Load 206 can be a charge storage device, such as a battery. For example, load 206 could be a cellular phone battery or a smartwatch. For example, transmitting device 110 could be a charging pad, and the smartwatch could be placed on the charging pad. The charging pad transmits wireless power to the smartwatch's battery, and there is no connecting cable between the two devices.

[0042] Several interface standards have been developed to standardize wireless power transfer and related functions. One such interface standard is Qi, which is promoted by the Wireless Power Consortium (WPC). Qi and similar standardized protocols can be used to define the communication interface used to control power transfer in wireless power system 100. For example, receiving device 120 can request changes (e.g., increase, decrease, pause, etc.) related to the wireless energy transmitted from transmitting device 110.

[0043] The mechanism of inductive power transfer can also be used to communicate between transmitting device 110 and receiving device 120. For example, receiving device 120 can notify transmitting device 110 when the charging process is complete. This communication can be facilitated by a technique called backscatter modulation, as specified in the Qi standard for inductive wireless power transfer.

[0044] In practice, receiving device 120 can change its load impedance, for example, by changing the impedance of load 206. The change in impedance causes an observable change in the amplitude of the current or voltage in transmitter coil 112, thereby allowing information to be transmitted from receiving device 120 to transmitting device 110.

[0045] In one embodiment, voltage extractor circuit 220 receives an alternating current (AC) voltage from a rectifier. This AC voltage can be a signal generated during the rectification of a power signal or a voltage directly received across the terminals of receiver coil 122. The extracted voltage is provided to comparator 208, which maintains the same frequency variation as the incoming power signal. Voltage extractor circuit 220 may include a current sensing circuit comprising resistors and a differential amplifier to perform voltage extraction.

[0046] Comparator 208 is configured to compare the voltage associated with receiver coil 122 and extracted by voltage extractor circuit 220 with a reference voltage (V). REF The result of comparator 208 is sent to synchronization stage 210, while maintaining the same frequency variation as the incoming power signal from voltage extractor circuit 220.

[0047] Synchronization stage 210 is configured to synchronize the incoming signal from comparator 208 with the system clock (CLK). SYS Alignment is achieved to ensure proper timing of subsequent demodulation processes. Therefore, the output of synchronization stage 210 is the input signal to demodulator 212. Synchronization stage 210 may include circuitry for detecting and correcting the phase difference between the incoming signal and the system clock. This can facilitate accurate frequency measurement in counter-based FSK demodulation schemes.

[0048] Demodulator 212 may include glitch suppression circuitry, conditioning circuitry, demodulation circuitry, filtering stage, etc. In an embodiment, demodulator 212 is configured to filter out glitches from the binary input signal, thereby producing a clean output signal. In an embodiment, demodulator 212 may provide multiple operating modes to increase signal quality.

[0049] Demodulator 212 can implement counter-based FSK demodulation technology, as described below. Figure 3Further discussion follows. In this embodiment, it uses a synchronization signal from synchronization stage 210 and a system clock to measure the frequency of the incoming FSK signal. Demodulator 212 can count the number of system clock cycles within each cycle of the FSK signal, thereby converting the frequency variation into a digital value representing the transmitted data.

[0050] Figure 3 A block diagram of embodiment circuit 300 is shown, which can be implemented within demodulator 212. Circuit 300 includes a first counter 302, a filter 304, a second counter 306, a conditioning circuit 308, and a first-in-first-out (FIFO) logic circuit 310. These components may or may not be arranged as shown, and circuit 300 may include additional components not shown in the figure.

[0051] Circuit 300 is configured to operate based on a known frequency signal (e.g., SYS). CLK To measure unknown signals (e.g., FSK) IN The frequency of the FSK signal is determined by a counter. This scheme forms the basis of counter-based FSK demodulation, where the number of system clock ticks within one or more cycles of the incoming FSK signal determines the frequency of the FSK signal. This count is the ratio of the system clock frequency to the FSK signal frequency. They are approximately proportional.

[0052] The first counter 302 receives the system clock signal (SYS). CLK The filter 304 receives the incoming FSK signal (FSK signal) and increments its value at each rising edge of the known frequency signal. IN It also removes potential glitches, effectively functioning as a bandpass or low-pass filter in the embodiments. A second counter 306 coupled to the filter output increments its value at each rising edge of the filtered FSK signal.

[0053] The operation of these counters is synchronized so that the first counter 302 increments until the second counter 306 records a single increment. This event triggers a reset of both counters, preparing for the next evaluation cycle. This mechanism allows an unknown frequency signal to be converted into a digital sample, where the value in the first counter 302 corresponds to the frequency of the incoming FSK signal.

[0054] Typically, evaluation occurs over multiple carrier cycles to address the challenge of distinguishing between closely spaced FSK frequencies. This approach involves accumulating counts over several cycles (N increments of the second counter 306), thereby enhancing the system's ability to distinguish between small frequency differences, even in the presence of noise or signal distortion.

[0055] For example, consider a system with a system clock frequency of 48MHz and two FSK signal frequencies: 127.772kHz (FSK). IN1 ) and 126.984kHz (FSK) IN2 In this case, the first FSK signal (FSK) IN1 This will result in approximately 376 per cycle. One clock tick, and the second FSK signal (FSK) IN2 This will result in approximately 378 per cycle. One clock beat.

[0056] As shown in this example, the frequencies of the incoming FSK signals can be very close, resulting in small differences in the number of clock ticks counted. In extreme cases, two signals could produce a count of 377 ticks, making it impossible to distinguish between them within a single cycle. This small difference poses a challenge for reliable frequency change detection, especially in the presence of noise or signal distortion.

[0057] The proposed jitter compensation technique offers several advantages over existing solutions. A key advantage is that it does not require knowledge of the specific jitter mode or mode length used by the transmitting device 110. As long as the jitter mode length (DPL) set on the receiving device 120 is an integer multiple of the mode length used by the transmitting device 110, the technique can effectively compensate for the effects of jitter. For example, if the transmitted jitter mode length is 8, 16, or 32, then setting the jitter mode length on the receiving device 120 to 32 covers all possible cases, thus ensuring appropriate compensation.

[0058] The conditioning circuit 308 processes digital samples by, for example, averaging, extracting baseline measurement results (mean) and peak measurement results (peak), detecting the start of modulation, and can implement jitter compensation techniques. The FIFO logic circuit 310 stores the demodulated samples for subsequent processing or analysis.

[0059] In the embodiments, the proposed technique employs a combination of an IIR averaging filter for extracting the actual offset values ​​and a polyphase filter for smoothing the offset across multiple observation windows. The IIR averaging filter removes the DC component from the carrier period data, isolating the actual offset values ​​caused by the jitter process. The polyphase filter consists of a set of smoothing filters that smooth the offset values ​​across an extended evaluation window spanning multiple jitter pattern lengths. This multi-stage filtering scheme mitigates the effects of variations and noise in the extracted offsets, thereby providing an accurate estimate of the underlying jitter patterns.

[0060] While the FSK demodulation technique described above can extract transmitted data from a power signal, jitter in the signal can pose a challenge to the demodulation process. Jitter is commonly used in wireless power transmission systems to reduce electromagnetic interference (EMI) and improve electromagnetic compatibility (EMC) performance.

[0061] In a typical jitter scheme, the frequency or phase of a power signal is intentionally altered in a controlled manner. Distributing the signal's energy across a wider frequency range helps reduce peak emissions at any single frequency. Jitter can mitigate EMI issues and ensure regulatory compliance by attenuating power peaks at unwanted frequencies.

[0062] However, if jitter in the power signal is not adequately compensated, it can negatively impact the identification of transmitted data. Variations in the signal caused by jitter can lead to inaccuracies and errors in the demodulated data, especially at high bit rates.

[0063] To address this issue, jitter compensation techniques can be employed on the receiver side to mitigate the impact of jitter and ensure reliable data recovery. These techniques aim to reconstruct transmitted information by compensating for changes introduced by the jitter process.

[0064] Conventionally, on the receiving device 120, the demodulator 212 employs various smoothing techniques to attenuate the effects of jitter. These techniques may include, but are not limited to, moving averages over multiple carrier cycles (e.g., low-pass filters) or other signal processing methods. On the transmitting device 110, one scheme for jitter compensation can be implemented via an amplitude shift keying (ASK) demodulator that uses a jitter table shared between a pulse width modulator (PWM) timer and a local oscillator, thus following the same periodic evolution. However, various other methods and techniques can be implemented to achieve jitter compensation at the transmitter side.

[0065] However, these solutions may be impractical when, for example, the jitter pattern is unknown beforehand or when high bit-rate communication is desired. Due to the limited number of carrier cycle samples, conventional jitter compensation schemes using low-pass filters may be infeasible if the bit rate is very high. For example, at a carrier frequency of 360 kHz and a bit rate of 360 kbps, only one carrier cycle (corresponding to the bit itself) is available per bit, making averaging over multiple carrier cycles impossible.

[0066] Furthermore, the same jitter scheme used in ASK digital demodulation on transmitting device 110 (which depends on the known jitter pattern length) cannot be directly applied to receiving device 120. This is because the jitter pattern and its length are parameters that are generally known to the ASK demodulator on transmitting device 110 but not to receiving device 120.

[0067] This disclosure proposes a jitter compensation technique for high bit-rate FSKD applications to overcome these limitations. In embodiments, the proposed technique employs a combination of offset extraction, polyphase filtering, and table storage to mitigate the impact of jitter on demodulated data without prior knowledge of the specific jitter pattern used by the transmitting device 110.

[0068] Figure 4 A block diagram of an embodiment jitter compensation circuit 400 is shown, which can interface with a first counter 302 and a second counter 306 of an embodiment circuit 300 implemented within a demodulator 212. The jitter compensation circuit 400 is configured to extract, smooth, and compensate for the effects of jitter in incoming carrier periodic data. The jitter compensation circuit 400 includes a first counter 302, a second counter 306, a high-pass filter circuit 404, a polyphase filter circuit 406, a compensation circuit 408, and a control circuit 402, which may (or may not) be arranged as shown. The jitter compensation circuit 400 may include additional components not shown.

[0069] The first counter 302 receives the system clock signal (SYS_CNT) and generates a carrier period value. The second counter 306 is coupled to the first counter 302 and provides a data valid signal (DATA_VLD) to indicate the availability of new carrier period data. Different schemes can be implemented to ensure that a single sample corresponds to a single carrier. For example, the first counter 302 can be reset at each rising edge, where N evaluations are performed by subsequent accumulator circuitry. As another example, during calibration, the end-of-count (EoC) of the second counter 306 can be programmed to zero.

[0070] The high-pass filter circuit 404 is configured to extract offset values ​​from the carrier period data. This can be achieved by determining the difference between each carrier period value (i.e., the effective sample) and its corresponding DC component, which can be obtained using, for example, an infinite impulse response (IIR) exponential mean filter (also known as an IIR DC tracking filter).

[0071] In this embodiment, the IIR filter employs oversampling to ensure accurate offset extraction, even with only one sample per bit. The filter can extract the DC component from the carrier period value, and this DC component can be subtracted from the original value to obtain the actual offset. A programmable factor K can determine the time constant of the IIR filter, allowing the filter's response to be adjusted based on specific application requirements.

[0072] A polyphase filter circuit 406 is configured to process the extracted offset values. The polyphase filter smooths the offset across an evaluation window spanning multiple jitter pattern lengths (e.g., three times the jitter pattern length). This filtering process helps mitigate the effects of variations and noise in the extracted offset.

[0073] In this embodiment, the multiphase filter circuit 406 comprises a set of smoothing filters, each of which is implemented as a recursive moving average. The number of moving average filters in the set can be determined by the maximum jitter pattern length (DPL) supported by the system. For example, if the maximum jitter pattern length is 32, then the multiphase filter circuit 406 includes 32 moving average filters.

[0074] Control circuit 402 manages the data scheduled to polyphase filter circuit 406. In an embodiment, control circuit 402 is configured to count the number of valid data signals (DATA_VLD). The count of valid data signals (DPL_CNT) can be used to track each carrier cycle and schedule the corresponding offset value to the smoothing filter within polyphase filter circuit 406.

[0075] In one embodiment, the control circuit 402 is configured to distribute the extracted offset values ​​in a cyclic manner within the smoothing filters. For example, a first offset value is stored in a first smoothing filter, a second offset value is stored in a second smoothing filter, and so on, until the count of valid data signals (DPL_CNT) reaches the end of the jitter pattern length. This process is repeated, with subsequent offset values ​​being stored in the first smoothing filter.

[0076] The control circuit 402 is configured to determine an evaluation window valid signal (EVAL_WINDOW_VLD), which indicates when the expected number of jitter pattern length repetitions is reached, after which compensation by estimating the offset can be applied.

[0077] In this embodiment, the control circuit 402 is programmable. For example, the number of jitter pattern lengths included in each evaluation window can be programmed based on the application. For instance, if the number of times the valid data signal reaches the end of the jitter pattern length is set to N, the evaluation window will span N times the jitter pattern length. This allows for flexibility in the trade-off between smoothing effects and the responsiveness of the compensation process.

[0078] Once the evaluation window is reached, the compensation circuit 408 can store the final evaluated offset value in the jitter table. The stored offset value can compensate for the incoming carrier period data, thereby mitigating the effects of jitter. In this embodiment, the compensation process is performed before actual data modulation begins to ensure accurate data recovery.

[0079] In this embodiment, the compensation circuit 408 can select between incoming carrier periodic data and compensated data based on the state of the evaluation window valid signal (EVAL_WINDOW_VLD). When the evaluation window is reached, the compensation circuit 408 can switch to the compensated data, applying the offset value stored from the jitter table to the incoming data stream.

[0080] Advantageously, the proposed jitter compensation circuit provides a solution to the challenges posed by jitter in high bit-rate frequency shift keying demodulation (FSKD) applications. By extracting the offset, smoothing it across multiple jitter windows, and applying the compensation value to the incoming data, the circuit enables reliable communication between the wireless power transmitter and receiver, even when jitter is being applied to high bit-rate data transmission.

[0081] Figure 5 A block diagram of an embodiment control circuit 500 is shown, which can be implemented as follows: Figure 4 The control circuit 402 is located within the jitter compensation circuit. The control circuit 500 manages the flow of data and control signals within the jitter compensation circuit. The control circuit 500 includes an oversampling circuit 502, a jitter mode length (DPL) counter 504, and an evaluation window counter 506, which may (or may not) be arranged as shown. The control circuit 500 may include additional components, such as memory, not shown.

[0082] Control circuit 500 is configured to orchestrate the operation of the jitter compensation circuit. It ensures that offset values ​​are extracted, filtered, and applied to carrier period data in a synchronous and controlled manner based on a specified jitter pattern length and evaluation window duration. By providing the necessary control signals and counters, control circuit 500 enables seamless integration and coordination of the various components within the jitter compensation circuit.

[0083] Control circuit 500 receives a data valid signal (DATA_VLD) from second counter 306, which indicates the availability of new carrier cycle data. This signal is fed into oversampling circuit 502, which generates an oversampled version of the data valid signal (IR_VLD) and a flag associated with the end of the oversampling process (IIR_VLD_LAST). The oversampled version of the data valid signal (IR_VLD) is provided to high-pass filter circuit 404, thereby triggering the extraction of offset values ​​from the carrier cycle data.

[0084] In this embodiment, the jitter mode length (DPL) counter 504 is enabled by a jitter enable signal (DIT_EN) and configured to count incoming samples and wrap around each time it reaches the end of the count. The evaluation window counter 506 tracks how many times the jitter mode length (DPL) counter 504 wraps around, and once the evaluation window ends, generates an evaluation window valid signal (EVAL_WINDOW_VLD) to load the final offset evaluation into the jitter table of the compensation circuit 408.

[0085] The valid data signal (DATA_VLD) is also provided to the jitter mode length (DPL) counter 504. The DPL counter 504 is configured to increment on each valid data signal (DATA_VLD) pulse, thereby counting for each carrier cycle. The output (DP_CNT) of the DPL counter 504 controls the distribution of the extracted offset value within the smoothing filter in the polyphase filter circuit 406. When the DPL counter 504 reaches the end of the jitter mode length, it resets and restarts counting from the beginning.

[0086] Evaluation window counter 506 is configured to receive a jitter enable signal (DIT_EN) as input. The jitter enable signal (DIT_EN) determines whether the jitter compensation process is active or bypassed. When the jitter enable signal (DIT_EN) is asserted, evaluation window counter 506 begins counting the number of times the jitter mode length (DPL) counter 504 reaches the end of the jitter mode length. An evaluation window valid signal (EVAL_WINDOW_VLD) from evaluation window counter 506 indicates the completion of the evaluation window, which can span multiple jitter mode lengths.

[0087] The evaluation window validity signal (EVAL_WINDOW_VLD) is provided to the multiphase filter circuit 406 and the compensation circuit 408. In the multiphase filter circuit 406, the evaluation window count signal (EVAL_WINDOW_VLD) controls the accumulation and averaging of the offset values ​​within each smoothing filter. When the evaluation window is complete, the final average offset value can be used for further processing.

[0088] In the compensation circuit 408, the evaluation window valid signal (EVAL_WINDOW_VLD) triggers the storage of the final evaluated offset value in the jitter table. Once the evaluation window is reached, the stored offset value is applied to the incoming carrier period data to compensate for the effects of jitter.

[0089] Figure 6A block diagram of an embodiment of a high-pass filter circuit 600 is shown. This embodiment of the high-pass filter circuit 600 can be implemented as follows: Figure 4 The high-pass filter circuit 404 is shown in the figure. In this embodiment, the high-pass filter circuit 600 includes a filter 602, an adder 604, and a switch 606, which may (or may not) be arranged as shown. The high-pass filter circuit 600 may include additional components not shown. The high-pass filter circuit 600 is configured to extract the actual offset value from the carrier period data by removing the DC component or mean.

[0090] The high-pass filter circuit 600 receives three input signals: the system clock count (SYS_CNT) from the first counter 302, an oversampled version of the data valid signal (IR_VLD) provided by the oversampling circuit 502 in the control circuit 500, and a flag associated with the end of oversampling (IR_VLD_LAST).

[0091] In this embodiment, filter 602 is an Infinite Impulse Response (IIR) exponential mean filter, also known as an IIR DC tracking filter. It is configured to extract the DC component or mean from the system clock count (SYS_CNT) value. Filter 602 operates on oversampled data, processing multiple samples for each carrier cycle, as controlled by an oversampled version (IR_VLD) of the valid data signal.

[0092] In this embodiment, filter 602 has a programmable time constant determined by a factor K, which allows the filter's response to be adjusted based on specific application requirements. The time constant controls the rate at which filter 602 adapts to changes in the input signal to determine the cutoff frequency of the high-pass filter.

[0093] Adder 604 subtracts the output of filter 602, which represents the extracted DC component or mean, from the original system clock count (SYS_CNT) value. This subtraction operation produces the actual offset value, effectively removing the DC component from the carrier period data.

[0094] Switch 606 is controlled by a flag (IR_VLD_LAST) associated with the end of oversampling. When the oversampled version of the valid data signal (IR_VLD_LAST) is asserted indicating the availability of a new offset value (allowing for the stabilization of the output of filter 602), switch 606 closes, allowing the offset value to be passed to the output of high-pass filter circuit 600. In an embodiment, switch 606 may be implemented as a register enabled by the valid data signal (IR_VLD_LAST). The output of high-pass filter circuit 600 is provided to polyphase filter circuit 406 for further processing.

[0095] In this embodiment, the settling time of the asserted data valid signal (IR_VLD_LAST) to switch 606 is programmable. By employing oversampling and an IIR filter with a programmable time constant, the high-pass filter circuit 600 ensures accurate extraction of the actual offset value, even in scenarios where only one sample per bit is available. The extracted offset value forms the basis for smoothing and compensating for the effects of jitter in the carrier periodic data.

[0096] Figure 7 A block diagram of an embodiment of a multiphase filter circuit 700 is shown. This embodiment of the multiphase filter circuit 700 can be implemented as follows: Figure 4 The multiphase filter circuit 406 is shown in this embodiment. The multiphase filter circuit 700 includes scheduling logic 702, multiple smoothing filters 704, and multiple switches, which may (or may not) be arranged as shown. The multiphase filter circuit 700 may include additional components not shown. The multiphase filter circuit 700 is configured to smooth the extracted offset values ​​received from the high-pass filter circuit 404 over an evaluation window.

[0097] The multiphase filter circuit 700 receives an offset value from the high-pass filter circuit 404 and a jitter mode count signal (DP_CNT) from the control circuit 402. The number of smoothing filter circuits in the multiphase filter circuit 700 is determined by the maximum jitter mode length (DPL) supported by the system. In the example shown, there are N smoothing filter circuits and N switches, where N corresponds to the maximum jitter mode length.

[0098] Scheduling logic 702 is controlled by a jitter pattern count signal (DP_CNT), which acts as a selection signal. The jitter pattern count signal (DP_CNT) determines which output of scheduling logic 702 is valid, thereby effectively distributing the offset values ​​from high-pass filter circuit 404 into smoothing filter circuits. Scheduling logic 702 routes each offset value to the appropriate smoothing filter circuit based on its position within the jitter pattern. For example, the first offset value is directed to the first smoothing filter 704, the second offset value is directed to the next smoothing filter, and so on, until the jitter pattern count (DP_CNT) reaches the end of the jitter pattern length. This process is then repeated, with the next offset value being directed to the first smoothing filter 704.

[0099] Each smoothing filter 704 can be implemented as a recursive moving average filter. These filters accumulate and average the offset values ​​over a specific number of samples determined by the duration of the evaluation window. The recursive nature of the filters allows for the computation of moving averages without storing a large number of samples.

[0100] Switch 706 is controlled by an evaluation window valid signal (EVAL_WINDOW_VLD) from control circuit 402. When the evaluation window valid signal (EVAL_WINDOW_VLD) indicates the completion of the evaluation window, switch 706 closes, thereby allowing the output of each smoothing filter circuit to be passed to compensation circuit 408. The output of each smoothing filter 704 represents a smoothed offset value at a specific position within the jitter mode.

[0101] In this embodiment, the multiphase filter circuit 700 is configured to perform a two-dimensional filtering operation, in which the offset value is filtered both across the jitter pattern length (spatial filtering) and in time (temporal filtering). This approach allows for efficient smoothing of the offset value, thereby reducing the effects of noise and variation while preserving the underlying jitter pattern.

[0102] By employing a multiplexer to distribute the offset values ​​and using multiple moving average circuits to smooth them, the polyphase filter circuit 700 ensures that the smoothed offset values ​​accurately represent the characteristics of the jitter pattern. These smoothed offset values ​​are then used by the compensation circuit 408 to compensate for the effects of jitter in the carrier period data, thereby enabling reliable communication even in the presence of high bit rate data transmission.

[0103] For example, if the jitter pattern length is 8, the first offset is stored in the first smoothing filter 704, the second offset is stored in the subsequent smoothing filters 704, and so on, until the eighth offset, which is stored in the last smoothing filter 704. At this point, a wraparound operation occurs, and the next offset is stored in the first smoothing filter 704. At the end of the evaluation window, the offset values ​​are stored in the jitter table following the multiphase filter circuit 700.

[0104] Figure 8 A block diagram of an embodiment compensation circuit 800 is shown, which can be implemented as follows: Figure 4 The compensation circuit 408 is included in this embodiment. The compensation circuit 800 includes a jitter table 802, a first multiplexer 804, an adder 806, and a second multiplexer 808, which may (or may not) be arranged as shown. The compensation circuit 800 may include additional components not shown. The compensation circuit 800 is configured to store smoothed offset values ​​received from the polyphase filter circuit 406 and apply them to the incoming carrier period data to compensate for the effects of jitter.

[0105] The compensation circuit 800 receives a smoothed offset value from the multiphase filter circuit 406, a system clock count signal (SYS_CNT) from the first counter 302, and a jitter mode count signal (DP_CNT) and an evaluation window valid signal (EVAL_WINDOW_VLD) from the control circuit 402.

[0106] Jitter table 802 is a memory storage element that stores smoothed offset values ​​received from polyphase filter circuit 406. The size of jitter table 802 can be determined by the maximum jitter mode length (DPL) supported by the system. Each entry in jitter table 802 can correspond to a specific position within a jitter mode and retain a smoothed offset value for that position.

[0107] The jitter mode count signal (DP_CNT) can address the jitter table 802 through the first multiplexer 804, thereby selecting the appropriate entry based on the current position within the jitter mode. The jitter mode count signal (DP_CNT) and the first multiplexer 804 ensure that the stored offset value is aligned with the incoming carrier period data.

[0108] Adder 806 algebraically adds the selected offset value from jitter table 802 to the value of the incoming system clock count signal (SYS_CNT), which represents carrier period data. This addition operation compensates for jitter effects by removing the estimated offset from the carrier period data.

[0109] The second multiplexer 808 is controlled by the evaluation window valid signal (EVAL_WINDOW_VLD). When the evaluation window valid signal (EVAL_WINDOW_VLD) indicates the completion of the evaluation window, the second multiplexer 808 selects compensated carrier period data from the adder 806. Otherwise, it selects uncompensated carrier period data directly from the input system clock count signal (SYS_CNT).

[0110] The compensation circuit 800 operates in two phases: a calibration phase and a compensation phase. During the calibration phase, which occurs during the evaluation window, smoothed offset values ​​from the polyphase filter circuit 406 are stored in the jitter table 802. Once the evaluation window is complete, the compensation phase begins, and the stored offset values ​​are used to compensate for incoming carrier cycle data in real time.

[0111] By storing the smoothed offset values ​​in jitter table 802, algebraically adding them to carrier period data using adder 806, and selecting the appropriate output using second multiplexer 808 based on evaluation window count, compensation circuit 800 effectively mitigates the impact of jitter on demodulated data. This enables reliable communication between the wireless power transmitter and receiver, even in the presence of high bit rate data transmission and the effects of jitter.

[0112] Figure 9 A flowchart of an embodiment method 900 in a wireless power receiver is shown. Method 900 describes the steps involved in configuring FSK demodulation and performing jitter compensation to ensure reliable communication between the wireless power transmitter and receiver. Method 900 can use, for example... Figure 4 The jitter compensation circuit 400 described herein is used to achieve this.

[0113] It should be noted that not all steps outlined in the method are necessarily required and may be optional. Furthermore, changes to the arrangement of steps, the removal of one or more steps and path connections, and the addition of steps and path connections are also considered.

[0114] At step 902, the FSK demodulator is configured to work in conjunction with jitter compensation circuitry. This configuration may involve setting appropriate parameters such as the maximum jitter mode length (DPL), evaluation window duration, and IIR filter time constant. These parameters can be set based on specific application requirements and the characteristics of the wireless power system.

[0115] This method waits for the wireless power receiver to enter an active phase (ready to receive power and communicate with the transmitter). This waiting period ensures that the jitter compensation process is synchronized with the overall operation of the wireless power system. Once the active phase is detected, the FSK demodulator can operate on a single carrier cycle, allowing for accurate frequency measurement and demodulation.

[0116] At step 904, method 900 checks whether jitter compensation functionality is enabled. This can be controlled by a configuration register or a control signal such as the jitter enable signal (DIT_EN)).

[0117] If jitter compensation is not enabled, the method proceeds to step 914, where the FSK demodulator continues to operate without jitter compensation. In this case, the incoming carrier cycle data is processed directly without any offset extraction or compensation being applied. This bypass mode allows the FSK demodulator to operate in a standard manner without the additional processing overhead associated with jitter compensation.

[0118] At step 906, in response to jitter compensation being enabled, the offset extraction process begins. This may involve using a high-pass filter circuit 404 to remove the DC component from the incoming carrier period data and obtain the actual offset value.

[0119] Offset extraction can be performed continuously, with filters operating on oversampled data to ensure accurate offset estimation. The filter's programmable time constant can set the filter's response and its ability to track changes in offset values ​​over time. By operating on oversampled data, the filter can provide offset estimates even in the presence of noise or signal variations.

[0120] At step 908, it is checked whether an evaluation window that can span multiple jitter mode lengths has been completed. This can be determined by the evaluation window validity signal (EVAL_WINDOW_VLD) generated by control circuit 402.

[0121] The evaluation window represents the time period during which the offset value is accumulated and averaged by the multiphase filter circuit 406. The length of the evaluation window can be programmable and adjusted based on the specific requirements of the application, such as the expected jitter pattern length and the desired trade-off between compensation accuracy and latency.

[0122] If the evaluation window is not yet complete, the method returns to step 906 and continues the offset extraction process. This loop ensures that the offset values ​​are continuously updated and processed by the multiphase filter circuit 406 until the evaluation window is complete.

[0123] At step 910, once the evaluation window is complete, the smoothed offset values ​​from the polyphase filter circuit 406 are stored in the jitter table 802 of the compensation circuit 408. These stored offset values ​​represent the estimated jitter pattern and can be used for compensation in subsequent carrier cycles.

[0124] The calibration process involves transferring the contents of the smoothing filter in the multiphase filter circuit 406 to the corresponding entry in the jitter table 802. The jitter table 802 acts as a lookup table, allowing quick access to the appropriate offset value based on the current position within the jitter pattern.

[0125] At step 912, when the smoothed offset value is stored in jitter table 802, compensation circuit 408 applies compensation to the incoming carrier period data. This is done by using adder 806 to algebraically add the appropriate offset value selected based on the current position within the jitter pattern to the incoming data. The compensated data is selected as the output of the compensation circuit using second multiplexer 808.

[0126] At step 914, the FSK demodulator continues to operate with jitter compensation enabled, using the offset values ​​stored in jitter table 802 to compensate for jitter effects in real time. This ensures accurate demodulation and data recovery, even in high-bit-rate data transmissions with incoming signal variations caused by jitter.

[0127] Method 900 loops back to step 904 and continues to monitor the jitter compensation enable signal. If jitter compensation is disabled or an active phase is lost, the method adjusts accordingly and resumes from the appropriate step.

[0128] Figure 10 A schematic diagram of an embodiment of a finite impulse response (IIR) filter 1000 is shown, which can be implemented as part of a high-pass filter circuit 404 in a jitter compensation system. The IIR filter (also known as an IIR DC tracking filter) is configured to perform exponential averaging of the input values ​​to extract the DC component or mean from the carrier period data.

[0129] The IIR filter 1000 comprises several arithmetic and logic elements, including a sign extension circuit 1002, a first adder 1004, a second adder 1006, a multiplexer 1008, a register 1010, a shifter 1014, and a bit truncation circuit 1016, which may (or may not) be arranged as shown. The IIR filter 1000 may include additional components not shown.

[0130] The input value (x) represents the carrier period data from which the DC component needs to be extracted. In embodiments involving fixed-point arithmetic, this input is a sign-extended value before being provided to the first adder 1004 and the second adder 1006 to avoid overflow issues.

[0131] The IIR DC trace initial state signal (IIR_DC_TRACK_INITIAL_STATUS) initializes the internal state of the filter (corresponding to the value stored in register 1010). The initialization value of register 1010 is the output of multiplexer 1008, controlled by the load signal (LOAD). In this embodiment, the load signal can be programmed by firmware or hardwired.

[0132] The second adder 1006 adds the output of the first adder 1004 to the delayed output value stored in register 1010. The delayed output value stored in register 1010 represents the previous output value of the IIR filter 1000 (delayed by one sample). This delay is determined by the numerator of the transfer function. Item representation: .

[0133] The first adder 1004 subtracts the output of the shifter 1014 from the input value (x). The shifter multiplies by... The constant factor K. The programmable factor K determines the time constant of the IIR filter, which is an integer greater than or equal to zero. The time constant is given by the formula: By adjusting the value of K, the filter response can be tuned to effectively track the DC component and extract the DC component from the input signal.

[0134] The bit-truncation circuit 1016 can truncate the output of shifter 1014 by scaling the output dimension in embodiments involving fixed-point arithmetic, or it can directly propagate the output of shifter 1014.

[0135] The output of the second adder 1006 is stored in register 1010 as the updated output value. Register 1010 ensures that the delayed output value is available for subsequent calculation iterations. The output of register 1010 is also directly provided as the current state of the IIR filter 1000.

[0136] The output (y) of the IIR filter 1000 represents the extracted DC component or mean of the input signal (delayed by one sample). Its output is then provided to the adder 604 to perform an algebraic summation, thereby effectively removing the DC component of the input signal.

[0137] Figure 11 A schematic diagram of a recursive moving average circuit 1100 is shown, which can be implemented as follows: Figure 7 The smoothing filter 704. The moving average circuit 1100 is configured to calculate a moving average of a series of input values, such as offset values ​​extracted from carrier period data during jitter compensation.

[0138] The moving average circuit 1100 includes multiple registers 1102, a multiplexer 1104, a first adder 1106, a second adder 1108, and a register 1110, which may (or may not) be arranged as shown. The moving average circuit 1100 may include additional components not shown.

[0139] Register 1102 forms a delay line that stores the previous N input values, where N is the length of the moving average window. Each register 1102 is coupled in series, with the output of one register feeding into the input of the next register. The input to the first register 1102 is the current input value, denoted as x[n].

[0140] Multiplexer 1104 is configured to select older input values ​​x[nM], where M ranges from 1 to N, each stored in register 1102. This selection is controlled by a control signal (M) that determines the moving average length.

[0141] In this recursive architecture, multiplexer 1104 selects the output of an older sample x[nM] stored in register 1102 on the delay line, representing the oldest input value in the considered moving average window. First adder 1106 subtracts the output of multiplexer 1104 from the current input value x[n], thereby removing the oldest value and adding the latest value from the moving average calculation.

[0142] The second adder 1108 adds the output of register 1110, which holds the previous moving average, to the output of the first adder 1106. This operation updates the moving average by integrating the contribution of the latest value and removing the contribution of the oldest value.

[0143] The updated moving average is stored in register 1110 and provided as the output of moving average circuit 1100 (denoted as y[n]). Register 1110 ensures that the previous moving average is available for calculation in subsequent iterations.

[0144] The recursive structure of the moving average circuit 1100 allows for selective processing of input values, skipping unnecessary calculations for zero or irrelevant samples. This feature is particularly advantageous in jitter compensation, where offset values ​​are distributed across different smoothing filter circuits based on their position within the jitter pattern.

[0145] By implementing the moving average circuit 1100 as part of the multiphase filter circuit 406 in the jitter compensation system, the extracted offset values ​​can be smoothed and averaged, thereby reducing the effects of noise and variation while preserving the underlying jitter pattern.

[0146] The first aspect relates to a wireless power receiving device configured to receive a frequency shift keying modulated signal with jitter, the wireless power receiving device comprising: a demodulator configured to generate carrier period data from the received modulated signal; a high-pass filter circuit configured to extract offset values ​​from the carrier period data; a polyphase filter circuit including a plurality of smoothing filters configured to receive the extracted offset values ​​and distribute the extracted offset values ​​among the plurality of smoothing filters based on a jitter pattern length; and a compensation circuit configured to store the smoothed offset values ​​from the polyphase filter circuit in a jitter table during an evaluation window and apply the stored offset values ​​to compensate the carrier period data during a subsequent demodulation period.

[0147] According to the first aspect itself, in a first embodiment of the wireless power receiving device, the compensation circuit includes: a first multiplexer configured to select an offset value from a jitter table; an adder configured to algebraically sum the selected offset value with incoming carrier period data; and a second multiplexer configured to select between the output of the adder and the incoming carrier period data based on an evaluation window.

[0148] According to the first aspect itself or any of the foregoing embodiments of the first aspect, in a second embodiment of the wireless power receiving device, the high-pass filter circuit has a programmable time constant.

[0149] According to the first aspect itself or any of the foregoing embodiments of the first aspect, in a third embodiment of the wireless power receiving device, the multiphase filtering circuit is configured to smooth the extracted offset values ​​over an evaluation window that includes multiple jitter pattern lengths.

[0150] According to the first aspect itself or any of the foregoing embodiments of the first aspect, in a fourth embodiment of the wireless power receiving device, the number of smoothing filters is equal to the maximum supported jitter mode length.

[0151] According to the first aspect itself or any of the foregoing embodiments of the first aspect, in a fifth embodiment of the wireless power receiving device, the polyphase filtering circuit includes scheduling logic for distributing the extracted offset values ​​among the smoothing filters.

[0152] According to the first aspect itself or any of the foregoing embodiments of the first aspect, in a sixth embodiment of the wireless power receiving device, the wireless power receiving device further includes a control circuit configured to: count the number of carrier cycles; determine the current position within the jitter mode length based on the count; and control the distribution of the extracted offset value among a plurality of smoothing filters in a cyclic manner based on the current position.

[0153] According to the first aspect itself or any of the foregoing embodiments of the first aspect, in a seventh embodiment of the wireless power receiving device, the control circuit is further configured to: determine the number of completed jitter pattern lengths; and generate an evaluation window signal indicating the completion of the evaluation window when the number of completed jitter pattern lengths reaches a predetermined value.

[0154] According to the first aspect itself or any of the foregoing embodiments of the first aspect, in the eighth embodiment of the wireless power receiving device, the control circuitry is programmable to set a predetermined value.

[0155] According to the first aspect itself or any of the foregoing embodiments of the first aspect, in a ninth embodiment of the wireless power receiving device, the compensation circuit includes a multiplexer configured to select between compensated carrier period data and uncompensated carrier period data based on the state of an evaluation window.

[0156] The second aspect relates to a jitter compensation circuit for a wireless power receiver, comprising: a high-pass filter configured to extract a carrier period offset; a polyphase filter including multiple smoothing filters and an allocation circuit configured to route the extracted carrier period offset to the corresponding smoothing filter based on its position within a jitter pattern length; a control circuit configured to track the completion of an evaluation window including multiple jitter pattern lengths; and a compensation circuit configured to store a smoothed offset value from the smoothing filters in a jitter table after the completion of the evaluation window, and to apply the stored offset value to compensate for the carrier period data during subsequent demodulation.

[0157] According to the second aspect itself, in the first embodiment of the jitter compensation circuit, the high-pass filter circuit has a programmable time constant.

[0158] According to the second aspect itself or any of the foregoing embodiments of the second aspect, in a second embodiment of the jitter compensation circuit, the control circuit includes: a first counter configured to count carrier periods; a second counter configured to count the length of a completed jitter pattern; and a comparator configured to generate an evaluation window completion signal when the second counter reaches a predetermined value.

[0159] According to the second aspect itself or any of the foregoing embodiments of the second aspect, in a third embodiment of the jitter compensation circuit, the control circuit further includes a programmable register configured to store predetermined values.

[0160] According to the second aspect itself or any of the foregoing embodiments of the second aspect, in a fourth embodiment of the jitter compensation circuit, the allocation circuit includes scheduling logic configured to route the extracted carrier period offset to the corresponding smoothing filter based on the current position within the jitter mode length.

[0161] According to the second aspect itself or any of the foregoing embodiments of the second aspect, in a fifth embodiment of the jitter compensation circuit, the compensation circuit includes: an adder configured to perform an algebraic summation between a carrier period value and a smoothed offset value selected from a jitter table; and a multiplexer configured to select between the result of the algebraic summation and the corresponding carrier period value based on the state of the evaluation window.

[0162] According to the second aspect itself or any of the foregoing embodiments of the second aspect, in a sixth embodiment of the jitter compensation circuit, the jitter meter has a size determined by the length of the maximum jitter mode supported.

[0163] The third aspect relates to a method for compensating jitter in frequency shift keying demodulation, the method comprising: performing high-pass filtering on carrier period data to extract offset values; allocating the extracted offset values ​​among a plurality of smoothing filters based on jitter pattern length; smoothing the allocated offset values ​​over an evaluation window using the plurality of smoothing filters; storing the smoothed offset values ​​in a jitter table; and using the stored offset values ​​to compensate subsequent carrier period data during demodulation.

[0164] According to the third aspect itself, in a first embodiment of the method, smoothing the assigned offset value includes: accumulating the offset value over multiple jitter pattern lengths in each smoothing filter; tracking the completion of the evaluation window using a counter; and providing the smoothed offset value to the jitter table when the counter indicates the completion of the evaluation window.

[0165] According to the third aspect itself or any of the foregoing embodiments of the third aspect, in a second embodiment of the method, allocating the extracted offset values ​​includes: counting the number of carrier cycles; determining the current position within the jitter mode length based on the count; and routing each extracted offset value to a corresponding smoothing filter based on the current position.

[0166] Although this description has been described in detail, it should be understood that various changes, substitutions, and alterations can be made without departing from the spirit and scope of this disclosure as defined by the appended claims. Identical elements are designated by the same reference numerals in the various figures. Furthermore, the scope of this disclosure is not intended to be limited to the specific embodiments described herein, and as will be clearly understood by those skilled in the art from this disclosure, existing or future processes, machines, articles of manufacture, compositions of matter, apparatuses, methods, or steps can perform substantially the same functions or achieve substantially the same results as the corresponding embodiments described herein. Therefore, the appended claims are intended to include such processes, machines, articles of manufacture, compositions of matter, apparatuses, methods, or steps within their scope.

[0167] Therefore, the specification and drawings should be regarded merely as a description of this disclosure as defined by the appended claims, and are intended to cover any and all modifications, variations, combinations or equivalents falling within the scope of this disclosure.

Claims

1. A wireless power receiving device configured to receive a frequency shift keying modulation signal with jitter, the wireless power receiving device comprising: The demodulator is configured to generate carrier period data from the received modulated signal; A high-pass filter circuit is configured to extract offset values ​​from carrier periodic data; A multiphase filter circuit, comprising multiple smoothing filters, is configured as follows: Receive the extracted offset value, and The extracted offset value is assigned among the multiple smoothing filters based on the dithering mode length; The compensation circuit is configured as follows: During the evaluation window, smoothed offset values ​​from the multiphase filter circuit are stored in a jitter table, and The stored offset value is then applied during the subsequent demodulation to compensate for the carrier period data.

2. The wireless power receiving device according to claim 1, wherein, The compensation circuit includes: The first multiplexer is configured to select an offset value from the jitter table; The adder is configured to algebraically sum the selected offset value with the incoming carrier period data; and The second multiplexer is configured to select between the adder's output and the incoming carrier periodic data based on an evaluation window.

3. The wireless power receiving device according to claim 1, wherein, High-pass filter circuits have programmable time constants.

4. The wireless power receiving device according to claim 1, wherein, The multiphase filter circuit is configured to smooth the extracted offset values ​​over an evaluation window that includes multiple jitter pattern lengths.

5. The wireless power receiving device according to claim 1, wherein, The number of smoothing filters is equal to the maximum supported jitter pattern length.

6. The wireless power receiving device according to claim 1, wherein, The multiphase filter circuit includes scheduling logic for distributing the extracted offset values ​​among the smoothing filters.

7. The wireless power receiving device according to claim 1, further comprising a control circuit, the control circuit being configured to: Count the number of carrier cycles; The current position within the length of the jitter pattern is determined based on the count; and Based on the current position, the extracted offset value is cyclically distributed among the multiple smoothing filters.

8. The wireless power receiving device according to claim 7, wherein, The control circuit is also configured as follows: Determine the number of completed jitter patterns; and An evaluation window signal indicating the completion of the evaluation window is generated when the number of completed jitter patterns reaches a predetermined value.

9. The wireless power receiving device according to claim 8, wherein, The control circuit can be programmed to set the predetermined value.

10. The wireless power receiving device according to claim 1, wherein, The compensation circuit includes a multiplexer configured to select between compensated and uncompensated carrier period data based on the state of an evaluation window.

11. A jitter compensation circuit for a wireless power receiver, the jitter compensation circuit comprising: A high-pass filter is configured to extract the carrier period offset; Polyphase filters, including: Multiple smoothing filters, and The distribution circuit is configured to route the extracted carrier period offset to the corresponding smoothing filter based on the position within the jitter mode length; The control circuitry is configured to track the completion of an evaluation window comprising multiple jitter pattern lengths; and The compensation circuit is configured as follows: After the evaluation window is completed, the smoothed offset values ​​from the smoothing filter are stored in the jitter table, and The stored offset value is then applied during the subsequent demodulation to compensate for the carrier period data.

12. The jitter compensation circuit according to claim 11, wherein, The high-pass filter circuit has a programmable time constant.

13. The jitter compensation circuit according to claim 11, wherein, The control circuit includes: The first counter is configured to count the carrier period; The second counter is configured to count the length of the completed jitter pattern; and The comparator is configured to generate an evaluation window completion signal when the second counter reaches a predetermined value.

14. The jitter compensation circuit according to claim 13, wherein, The control circuitry also includes a programmable register configured to store the predetermined value.

15. The jitter compensation circuit according to claim 11, wherein, The allocation circuitry includes scheduling logic configured to route the extracted carrier period offset to the appropriate smoothing filter based on the current position within the jitter mode length.

16. The jitter compensation circuit according to claim 11, wherein, The compensation circuit includes: The adder is configured to perform an algebraic summation between the carrier period value and a smoothed offset value selected from the jitter table; and The multiplexer is configured to select between the result of the algebraic summation and the corresponding carrier period value based on the state of the evaluation window.

17. The jitter compensation circuit according to claim 11, wherein, The jitter table has a size determined by the maximum supported jitter pattern length.

18. A method for compensating jitter in frequency shift keying demodulation, the method comprising: High-pass filtering is performed on the carrier periodic data to extract the offset value; The extracted offset values ​​are allocated among multiple smoothing filters based on the dither pattern length; The assigned offset values ​​are smoothed over the evaluation window using the plurality of smoothing filters. Store the smoothed offset values ​​in the jitter table; and The stored offset value is used during demodulation to compensate for the data in the next carrier cycle.

19. The method according to claim 18, wherein, Smoothing the assigned offset values ​​includes: In each smoothing filter, the offset value is accumulated over multiple jitter pattern lengths; Use a counter to track the completion of the evaluation window; and When the counter indicates the completion of the evaluation window, the smoothed offset value is provided to the jitter table.

20. The method according to claim 18, wherein, The extracted offset values ​​are allocated as follows: Count the number of carrier cycles; The current position within the jitter pattern length is determined based on the count; and Each extracted offset value is routed to the corresponding smoothing filter based on the current position.

Images