Chip 3D stacking structure based on a photon field theory

Abstract

The application discloses a chip 3D stacking structure based on a glass field theory and a packaging method thereof, and belongs to the technical field of semiconductor packaging. The structure comprises a plurality of functional chips, an interlayer glass field coupling interface layer, gradient aperture TSVs and a global glass field confinement ring. The application utilizes the glass field coupling effect to direct conduct heat, suppress signal crosstalk and balance interface stress, and solves the problems of poor heat dissipation, high crosstalk and low yield of existing 3D stacking. The application can realize equivalent advanced process performance under a DUV process, and is suitable for high-performance SoC chip, AI acceleration chip and server Chiplet packaging scenarios.

Description

Technical Field

[0001] This invention relates to the field of semiconductor packaging technology, specifically to a chip 3D stacking structure based on glass field theory and its packaging method, which is applicable to high-performance SoC chips, AI acceleration chips and server chiplet packaging scenarios under DUV process. Background Technology

[0002] In the field of advanced semiconductor packaging, 3D stacking technology is widely used to improve chip computing density and integration. However, existing 3D stacking technologies suffer from the following key challenges: High interlayer thermal resistance leads to concentrated heat during operation of high-power chips, which can easily cause thermal runaway and performance degradation. As vertical interconnect (TSV) density increases, high-frequency signal crosstalk intensifies, leading to bandwidth limitations and reduced signal integrity. Mismatched thermal expansion coefficients between interlayer materials lead to stress concentration at the bonding interface, reducing packaging yield and long-term reliability.

[0003] Currently, there is no efficient solution that addresses heat dissipation, signal integrity, and interface stability from the perspective of underlying field effects. Summary of the Invention

[0004] Purpose of the invention This invention aims to overcome the shortcomings of existing 3D stacking technologies and provide a chip 3D stacking structure based on glass field theory. Through field coupling effect, it achieves directional heat dissipation, signal crosstalk suppression and interface stress balance, and effectively improves chip performance to the advanced process level under DUV process. Technical solution

[0005] A chip 3D stacking structure based on glass field theory, comprising: It has at least two functional chip layers, with a glass field coupling interface layer between the layers for directional conduction of the thermal field energy generated by the chip. Gradient aperture TSV vertical interconnects running through each chip layer have glass field shielding coatings deposited on their walls to suppress lateral crosstalk of high-frequency signals. A global glass field constraint ring surrounds the entire stacked structure to balance interlayer thermal stress and stabilize the field distribution.

[0006] The present invention also provides a chip 3D stacking packaging method, comprising: At least two functional chips are stacked and bonded through a glass field coupling interface layer; Etching forms gradient aperture TSVs that penetrate each chip layer, and a glass field shielding coating is deposited on the TSV hole walls; A global glass field constraint ring is formed around the stacked structure to complete the encapsulation. Beneficial effects

[0007] Heat dissipation efficiency is improved by more than 40%, supporting the operation of chips with higher power density; High-frequency signal crosstalk is reduced by more than 60%, and bandwidth is increased by 30%; Uniform distribution of interlayer interface stress improves encapsulation yield to 99.5%; Equivalent 3nm-level performance can be achieved using the DUV process without EUV equipment. Attached Figure Description

[0008] Figure 1 This is a schematic diagram of the overall 3D stacked structure of the chip of the present invention; Figure 2 This is a partially enlarged schematic diagram of the interlayer interface and TSV of the present invention; Figure 3 This is a schematic diagram of heat transfer and stress distribution in this invention.

[0009] Referring to the attached diagram, the component designations are defined as follows: 1-Top-level functional chip layer; 2-Middle-level functional chip layer; 3-Bottom-level functional chip layer; 4- Glass field coupling interface layer; 5- Gradient aperture TSV vertical interconnect; 6-Global glass field constraint ring; 7-Glass field shielding coating. Detailed Implementation

[0010] The present invention will now be described in further detail with reference to the accompanying drawings.

[0011] Example 1: Three-layer chip stacking structure (corresponding to) Figure 1 ) like Figure 1 As shown, the chip 3D stacking structure of this embodiment includes: Top functional chip layer 1, middle functional chip layer 2, bottom functional chip layer 3; A glass field coupling interface layer 4 is set between the layers. The material is a graphene-alumina composite layer with a thickness of 5μm. 5. Gradient aperture TSV vertical interconnection holes running through each layer; The entire surrounding area is a global glass field confinement ring 6, made of silicon carbide ceramic.

[0012] Example 2: Interlayer Interface and TSV Structure (corresponding) Figure 2 ) like Figure 2 As shown, this embodiment focuses on demonstrating a magnified local structure: A glass field coupling interface layer 4 is sandwiched between the upper chip 1 and the lower chip 2, and a wavy line is drawn inside the layer to indicate the thermal field coupling and conduction path. The gradient aperture TSV5 has a tapered structure that is narrower at the top and wider at the bottom, with a top aperture of 6μm and a bottom aperture of 12μm. TSV hole wall deposition glass field shielding coating 7, the material is silicon nitride, and the thickness is 1μm.

[0013] Example 3: Heat transfer and stress distribution (corresponding to) Figure 3 ) like Figure 3 As shown, this embodiment illustrates the field effect and mechanical distribution: A bidirectional arrow is drawn on the global glass field confinement ring 6 to indicate its role in balancing interlayer thermal stress and preventing structural deformation; Horizontal arrows are drawn inside each chip layer 1, 2, and 3 to indicate the directional diffusion of heat towards the glass field coupling interface layer 4, thus avoiding local overheating.

Claims

1. A chip 3D stacking structure based on glass field theory, characterized in that, include: It has at least two functional chip layers, with a glass field coupling interface layer between the layers for directional conduction of thermal energy; Gradient aperture TSV vertical interconnects penetrating each chip layer, with glass field shielding coating deposited on the walls of the TSV holes to suppress signal crosstalk; And a global glass field constraint ring surrounding the entire stacked structure, used to balance interlayer stress and stabilize field distribution.

2. The chip 3D stacking structure according to claim 1, characterized in that, The glass field coupling interface layer is a composite material with high thermal conductivity and low dielectric constant, and has a thickness of 3 μm to 8 μm.

3. The chip 3D stacking structure according to claim 1, characterized in that, The gradient aperture TSV is a tapered structure that is narrower at the top and wider at the bottom, with the ratio of the top aperture to the bottom aperture ranging from 1:1.2 to 1:

3.

4. The chip 3D stacking structure according to claim 1, characterized in that, The glass field shielding coating is an insulating dielectric material with a dielectric constant of less than 4.0 and a thickness of 0.5 μm to 2 μm.

5. The chip 3D stacking structure according to claim 1, characterized in that, The global glass field confinement ring is a ceramic material framework, and the deviation between its thermal expansion coefficient and the thermal expansion coefficient of the chip and interface layer does not exceed ±2×10⁻ 6 / ℃.

6. The chip 3D stacking structure according to any one of claims 1 to 5, characterized in that, The structure is used in high-performance SoC chips, AI acceleration chips, or server chiplet packaging scenarios using the DUV process.

7. A chip 3D stacking packaging method, characterized in that, include: At least two functional chips are stacked and bonded through a glass field coupling interface layer; A gradient aperture TSV is formed that runs through each chip layer, and a glass field shielding coating is deposited on the TSV hole wall; A global glass field constraint ring is formed around the stacked structure.

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