An overcurrent and short circuit protection system

Abstract

The application provides an overcurrent and short circuit protection system, and belongs to the technical field of power electronic protection. The system comprises a microcontroller, a logic gate, a drive circuit and a current sensor. The first output end of the microcontroller is used for sending an enabling switching signal for indicating whether software is enabled. The current sensor is used for detecting the current value of a first output signal output by the drive circuit and outputting a current state signal, and the current state signal is a current fault signal when the current value exceeds a current threshold. The first input end of the logic gate is connected with the first output end of the microcontroller, and the second input end of the logic gate is connected with the first output end of the current sensor, which is used for generating a disable control signal in response to the current fault signal when the enabling switching signal is at a high level. The drive circuit is used for receiving the disable control signal and shutting down the power device in the drive circuit. The application realizes the cooperation of hardware level fast shutdown and software level flexible control.

Description

Technical Field

[0001] This invention relates to the field of power electronic protection technology, and more specifically to an overcurrent and short-circuit protection system. Background Technology

[0002] In motor drive systems, overcurrent and short-circuit protection are key technologies for ensuring the safe operation of power devices. Current protection solutions include: integrated protection based on the driver chip (such as the EXB840 series), which uses a current transformer to detect the IGBT collector current, rectifies it, compares it with a reference voltage, and triggers the driver chip's internal gate voltage reduction or soft shutdown logic; software-dependent overcurrent detection solutions, where the MCU samples the current sensor signal in real time, and outputs a shutdown command after determining overcurrent through a software algorithm; MOSFET Rds(ON)-based detection solutions, which utilize the on-resistance voltage drop of the power MOSFET to detect overcurrent, such as the Infineon AUIR3200S driver; and tiered protection and fuse solutions, employing fuses or multi-level protection strategies, or combining current transformers and comparators to achieve segmented protection.

[0003] However, all of the above solutions have shortcomings in practical applications. Solutions based on integrated driver chips (such as the EXB840 series) have limited response speed, relying on internal comparators and RC delay circuits, resulting in a turn-off delay of approximately 5-10 μs, which is still higher than pure hardware logic gate solutions (such as 1-5 μs), failing to meet the μs-level instantaneous protection requirements of motor drive systems. Furthermore, they lack software coordination, requiring hardware reset or recovery under specific conditions after protection triggering, and cannot dynamically enable / disable protection functions via software signals (such as VEN), resulting in insufficient flexibility. In addition, the threshold of the internal comparator is susceptible to temperature drift, potentially leading to false triggering or protection failure. Software-dependent solutions require signal sampling, interrupt response, and program processing, accumulating delays of tens of μs, making it impossible to effectively protect power devices during short circuits (within a few μs). They are also susceptible to software crashes, interrupt blocking, or interference, leading to protection failure, and the MCU's processing priority may delay protection action under high loads. Additionally, they require high-performance MCUs and optimized code, increasing system complexity and cost. The MOSFET Rds(ON)-based solution lacks sufficient detection accuracy. Rds(ON) increases with temperature, causing the detection threshold to drift, potentially leading to false shutdown or protection delay under high-temperature conditions. Furthermore, being purely hardware-based, it cannot dynamically adjust the protection strategy via the enable switching signal (VEN). It also only applies to MOSFET overcurrent protection, providing incomplete short-circuit protection for the entire H-bridge. Tiered protection and fuse solutions are slow to respond, with fuses requiring tens of milliseconds to blow, failing to protect sensitive devices such as power MOSFETs. Additionally, fuses or hardware latching protection require manual reset, impacting continuous system operation efficiency. They also cannot flexibly adjust protection thresholds or enable states based on system status (such as startup mode).

[0004] In summary, the main core defects of the existing technology are: it is difficult to balance the speed and reliability of overcurrent and short-circuit protection for motor drive systems, and it is impossible to start / stop protection or quickly reset through software signals in real time. Summary of the Invention

[0005] In view of this, it is necessary to provide an overcurrent and short-circuit protection system to solve the technical problems in the prior art that make it difficult to balance speed and reliability, and that protection and reset cannot be started, stopped and reset in real time by software.

[0006] To solve the above-mentioned technical problems, the present invention provides an overcurrent and short-circuit protection system, comprising: a microcontroller, logic gates, a drive circuit, and a current sensor; The first output terminal of the microcontroller is used to send an enable switching signal indicating whether software enable is enabled; The current sensor is used to detect the current value of the first output signal output by the drive circuit and output a current status signal. When the current value exceeds the current threshold, the current status signal is a current fault signal. The first input terminal of the logic gate is connected to the first output terminal of the microcontroller, and the second input terminal of the logic gate is connected to the first output terminal of the current sensor. It is used to generate a disable control signal with a high level drive control signal in response to the current fault signal when the enable switching signal is high. The second input terminal of the driving circuit is connected to the output terminal of the logic gate, and is used to receive the disable control signal and turn off the power device in the driving circuit.

[0007] In one possible implementation, the current status signal is a normal current signal when the current value does not exceed the current threshold. The logic gate is used to generate a normal operation signal with a low drive control signal in response to the normal current signal when the enable switching signal is high.

[0008] In one possible implementation, when the enable switching signal is high, it indicates that the software is enabled, and a software enable signal is output; when the enable switching signal is low, it indicates that the software is disabled, and a software disable signal is output. When the enable switching signal is low, the logic gate directly generates a disable control signal in response to the software disable signal.

[0009] In one possible implementation, the first input terminal of the drive circuit is connected to the second output terminal of the microcontroller to receive the PWM drive signal output by the microcontroller.

[0010] In one possible implementation, the system also includes a load; The input terminal of the load is connected to the second output terminal of the current sensor, and is used to receive the second output signal output by the drive circuit through the current sensor.

[0011] In one possible implementation, the logic gate is a two-input NAND gate, expressed as follows:

[0012] Wherein, VDIS is the drive control signal, VEN is the enable switching signal, and VFLAG is the current state signal.

[0013] In one possible implementation, when the enable switching signal is low, the drive control signal is high; When the enable switching signal is high and the current state signal is high, the drive control signal is low; When the enable switching signal is high and the current state signal is low, the drive control signal is high.

[0014] In one possible implementation, when the enable switching signal is high and the power device in the drive circuit is turned off, the first output signal output by the drive circuit is in a disabled state, and the current of the first output signal is synchronously detected by the current sensor. When the current of the first output signal decreases to a preset current range, the current sensor changes the current status signal from low level to high level and outputs a normal current signal. The logic gate responds to the normal current signal by converting the drive control signal to a low level and outputs a normal operation signal to drive the system back to normal. The drive circuit receives the normal operation signal and outputs a first output signal.

[0015] In one possible implementation, the system achieves periodic and timely protection and reset by using an enable switching signal output in real time by the microcontroller and a current status signal output in real time by the current sensor monitoring the first output signal.

[0016] In one possible implementation, the driving circuit includes a driver and an H-bridge driving circuit; The driver is a gate driver chip with a disable control function. Its first input terminal is connected to the second output terminal of the microcontroller to receive the PWM drive signal output by the microcontroller. The second input terminal of the driver is connected to the output terminal of the logic gate to receive the drive control signal output by the logic gate. The first input terminal of the H-bridge driving circuit is connected to the first output terminal of the driver and is used to receive the first gate driving signal; the second input terminal of the H-bridge driving circuit is connected to the second output terminal of the driver and is used to receive the second gate driving signal. The driver is used to simultaneously turn off the first gate drive signal and the second gate drive signal through its internal disable control terminal when the drive control signal is high, thereby turning off the power devices in the H-bridge drive circuit.

[0017] The beneficial effects of this invention are as follows: The overcurrent and short-circuit protection system provided by this invention includes a microcontroller, logic gates, a drive circuit, and a current sensor. First, the microcontroller sends an enable switching signal indicating whether software is enabled, realizing dynamic software control of the protection function. Protection can be flexibly enabled or disabled according to various operating conditions such as startup and debugging. Second, the current sensor detects the current value of the first output signal from the drive circuit in real time and outputs a current status signal. When the current value exceeds the current threshold, the current status signal is a current fault signal. The fault is promptly judged and reflected based on the real-time detected current value. Finally, the logic gate receives the enable switching signal and the current fault signal output by the current sensor. When the enable switching signal is high, the logic gate directly outputs a disable control signal to the drive circuit, eliminating the need for microcontroller sampling or software interruption, thus eliminating software delay. The drive circuit responds to the disable control signal and immediately shuts down the power device, achieving microsecond-level rapid shutdown. This effectively avoids damage to the power device caused by overcurrent or short circuit, balancing hardware response speed and software dynamic reset capability. Furthermore, the hardware's self-looping mechanism also has cycle-by-cycle protection capability, achieving a combination of hardware-level response and flexible software control, improving system reliability. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 A schematic diagram of an embodiment of the overcurrent and short-circuit protection system provided by the present invention; Figure 2 This is a schematic diagram of another embodiment of the overcurrent and short-circuit protection system provided by the present invention. Detailed Implementation

[0020] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0021] In the description of the embodiments of the present invention, unless otherwise stated, "multiple" means two or more. "And / or" describes the relationship between related objects, indicating that there can be three relationships. For example, A and / or B can represent three situations: A exists alone, A and B exist simultaneously, and B exists alone.

[0022] The terms "first," "second," etc., used in the embodiments of this invention are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, a technical feature defined with "first" or "second" may explicitly or implicitly include at least one of that feature.

[0023] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of the invention. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0024] Before demonstrating the embodiments, the following terms will be explained.

[0025] Inductive loads are electrical devices that have current that lags behind voltage and have inductive parameters. Typical examples include motors, transformers, and compressors.

[0026] Pulse Width Modulation (PWM) is an effective technique for controlling analog circuits using digital signals. Its basic principle is to adjust the duty cycle (the ratio of high-level time to the entire cycle time) of a series of fixed-frequency pulses by changing their width, thereby simulating a continuous analog signal.

[0027] Enable signal: A binary signal used to control a specific function or operation. It is typically represented by a high level (logic 1) or a low level (logic 0) to indicate enabling or disabling.

[0028] This invention provides an overcurrent and short-circuit protection system, which will be described below.

[0029] Figure 1A schematic flowchart of an embodiment of the overcurrent and short-circuit protection system provided by the present invention is shown below. Figure 1 As shown, the overcurrent and short-circuit protection system includes: a microcontroller 100, a logic gate 200, a drive circuit 300, and a current sensor 400. The first output of the microcontroller 100 is used to send an enable switching signal indicating whether software enable is enabled; The current sensor 400 is used to detect the current value of the first output signal output by the drive circuit 300 and output a current status signal. When the current value exceeds the current threshold, the current status signal is a current fault signal. The first input terminal of logic gate 200 is connected to the first output terminal of microcontroller 100, and the second input terminal of logic gate 200 is connected to the first output terminal of current sensor 400. When the enable switching signal is high, it is used to generate a disable control signal with the drive control signal high in response to the current fault signal. The second input terminal of the drive circuit 300 is connected to the output terminal of the logic gate 200, and is used to receive a disable control signal and turn off the power device in the drive circuit.

[0030] It should be noted that the overcurrent and short-circuit protection system provided in this embodiment of the invention is a component of the motor drive system; the motor drive system includes, but is not limited to, general actuator control systems such as magnetic levitation controllers.

[0031] The overcurrent and short-circuit protection system provided in this invention includes a microcontroller, logic gates, a drive circuit, and a current sensor. First, the microcontroller sends an enable switching signal indicating whether software is enabled, achieving dynamic software control of the protection function. Protection can be flexibly enabled or disabled according to various operating conditions such as startup and debugging. Second, the current sensor detects the current value of the first output signal from the drive circuit in real time and outputs a current status signal. When the current value exceeds a current threshold, the current status signal is a current fault signal. The system promptly judges and reflects the occurrence of a fault based on the real-time detected current value. Finally, the logic gates receive the enable switching signal and the current fault signal output by the current sensor. When the enable switching signal is high, the logic gates directly output a disable control signal to the drive circuit, eliminating the need for microcontroller sampling or software interruption, thus eliminating software delay. The drive circuit responds to the disable control signal and immediately shuts down the power device, achieving microsecond-level rapid shutdown. This effectively avoids damage to the power device caused by overcurrent or short circuit, balancing hardware response speed and software dynamic reset capability. Furthermore, the hardware's self-looping mechanism also has cycle-by-cycle protection capability, achieving a combination of hardware-level response and flexible software-level control, improving system reliability.

[0032] In some embodiments of the present invention, the current status signal is a normal current signal when the current value does not exceed the current threshold. The logic gate is used to generate a normal operation signal with a low drive control signal when the enable switching signal is high, in response to the normal current signal.

[0033] In this embodiment, when the system is under normal operating conditions (current does not exceed the threshold) and the software allows it to be enabled, the logic gate can automatically output a normal operating signal, enabling the drive circuit to maintain normal output. This achieves stable operation in a fault-free state, avoids false triggering of protection functions, and ensures the continuity and stability of the motor drive system.

[0034] In some embodiments of the present invention, when the enable switching signal is high, it indicates that the software is enabled and a software enable signal is output; when the enable switching signal is low, it indicates that the software is disabled and a software disable signal is output. When the enable switching signal is low, the logic gate responds to the software disable signal and directly generates a disable control signal.

[0035] This embodiment clearly distinguishes between software-enabled and software-disabled states by using an enable switching signal. When the software is disabled, the logic gate directly generates a disable control signal, forcibly shutting down the drive circuit. This achieves a software-priority forced protection mechanism. Regardless of the state detected by the current sensor, the system can immediately enter a safe shutdown state according to the software instruction. This is suitable for scenarios requiring active output suppression during system debugging, standby, emergency shutdown, or specific operating conditions, improving the system's controllability and safety.

[0036] In some embodiments of the present invention, the first input terminal of the driving circuit is connected to the second output terminal of the microcontroller 100 to receive the PWM driving signal output by the microcontroller 100.

[0037] In this embodiment, the PWM drive signal precisely controls the average current output from the drive circuit to the load (e.g., a magnetic levitation coil) by changing the duty cycle, thereby adjusting the magnitude of the electromagnetic force and achieving dynamic adjustment of the motor drive system (e.g., dynamically adjusting the levitation height, stiffness, and other performance characteristics of a magnetic levitation system). During normal operation, the PWM drive signal determines the output power; in case of a fault, the disable control signal can forcibly shut down the drive circuit, overriding the PWM signal and ensuring safety. The PWM drive signal and the disable control signal form a collaborative relationship of "normal adjustment" and "fault shutdown."

[0038] In some embodiments of the present invention, such as Figure 1 As shown, the overcurrent and short-circuit protection system also includes a load of 500; The input terminal of load 500 is connected to the second output terminal of the current sensor to receive the second output signal output by the drive circuit through the current sensor.

[0039] Preferably, in the magnetic levitation controller, the load can be an electromagnet coil on a magnetic levitation bearing or a suspension frame. The electromagnet coil generates electromagnetic force under the second output signal to levitate the controlled object.

[0040] This embodiment limits the load to the electromagnet coil on the magnetic levitation bearing or suspension frame, clarifying that the specific application of this invention is a magnetic levitation control system. This distinguishes it from general motor drive protection schemes, demonstrating the targeted and practical nature of the technical solution. The electromagnet coil generates a controllable electromagnetic force under the second output signal, achieving contactless levitation of the controlled object. The ultimate goal of overcurrent and short-circuit protection is to ensure the safe operation of this key actuator, the electromagnet coil, preventing coil burnout or levitation failure, thereby maintaining the stability and reliability of the entire magnetic levitation system.

[0041] In some embodiments of the present invention, the logic gate is a two-input NAND gate, as shown in Equation 1: (1) Among them, VDIS is the drive control signal, VEN is the enable switching signal, and VFLAG is the current status signal.

[0042] In some embodiments of the present invention Figure 2 This is a schematic diagram of another embodiment of the overcurrent and short-circuit protection system provided by the present invention; as shown. Figure 2 As shown, VPWM is the PWM pulse width modulation drive signal issued by the microcontroller and sent to the drive circuit; VEN is the enable switching signal issued by the microcontroller and sent to the logic gate; VFLAG is the current status signal issued by the current sensor and sent to the logic gate; VDIS is the drive control signal issued by the logic gate and sent to the drive circuit; VOUT1 is the first output signal issued by the drive circuit and sent to the current sensor; VOUT2 is the second output signal issued by the current sensor and sent to the load.

[0043] It should be noted that the fast current fault signal from the current sensor (when the current status signal VFLAG is low) and the high-level enable switching signal (VEN), processed by a logic gate, produce a disable control signal (VDIS) that directly controls the DISABLE terminal of the driver chip. This achieves a μs-level fast shutdown of the power MOSFETs in the H-bridge, preventing device damage caused by overcurrent or short circuits. The core logic is shown in Equation 1. When there is an output overcurrent or short circuit, the current status signal VFLAG from the current sensor is low (current fault signal), and VEN is high (software enabled). In this case, VDIS is high, triggering the driver circuit to turn off its first output signal VOUT1. When VEN is low (software disabled), regardless of the state of the fast fault output signal VFLAG from the current sensor, VDIS is high, triggering the driver circuit to turn off its first output signal VOUT1. This approach balances hardware response speed and software dynamic reset capability.

[0044] In this embodiment, the logic gate is a two-input NAND gate, which achieves an ultra-fast turn-off response at the μs level, and differs from existing technologies in the following ways: (1) In the prior art, traditional solutions usually rely on software (such as MCU) to detect overcurrent signals and issue shutdown commands. This involves multiple stages such as signal sampling, interrupt response, program processing, and command output, and the cumulative delay is usually tens of microseconds (μs) or even longer. For power MOSFETs, overcurrent or short-circuit faults may cause irreversible thermal damage within a few microseconds, and software delay often becomes a key factor in protection failure.

[0045] (2) In this invention, the core protection logic (VDIS = NOT(VEN AND VFLAG)) is directly implemented by hardware logic gates. The response time of the logic gates is extremely short (usually in the nanosecond range). Combined with the response speed of the DISABLE terminal of the driver chip itself, the entire protection loop (from the occurrence of the fault to the turn-off of the MOSFET) can be controlled in the range of 1-5μs. This hardware-level speed far exceeds that of software solutions, and can cut off the power path before the current reaches a dangerous value, effectively preventing the MOSFET from burning out instantly due to overcurrent or short circuit, and greatly improving the system reliability.

[0046] In some embodiments of the present invention, when the enable switching signal is low, the drive control signal is high; When the enable switching signal is high and the current status signal is high, the drive control signal is low. When the enable switching signal is high and the current status signal is low, the drive control signal is high.

[0047] This embodiment takes into account the dynamic control capabilities of software and differs from the prior art in the following ways: (1) Existing technology: Although pure hardware protection schemes (such as using only comparators to trigger shutdown) are fast, once shutdown is triggered, they often require external reset operations or specific conditions to recover, which lacks flexibility. Pure software schemes are flexible, but slow.

[0048] (2) This invention cleverly introduces an enable switching signal VEN. By controlling the high and low levels of VEN through software, the hardware protection function can be dynamically enabled or disabled. For example: VEN is high: protection function is enabled. When VFLAG goes low (fault), VDIS immediately goes high to turn off the MOSFET.

[0049] VEN is low: The protection function is actively disabled by the software. At this time, regardless of the VFLAG state, VDIS remains high, and the MOSFET is turned off (software-controlled turn-off).

[0050] After fault handling, the software can quickly reset the protection state by setting VEN high, attempting to restore system operation without waiting for hardware reset or complex recovery logic. This design allows the system to possess high-speed hardware protection while retaining the flexibility of software in real-time management of protection functions and system recovery.

[0051] In some embodiments of the present invention, when the enable switching signal is high and the power device in the drive circuit is turned off, the first output signal output by the drive circuit is in a disabled state, and the current of the first output signal is synchronously detected by the current sensor. When the current of the first output signal drops to the preset current range, the current sensor will change the current status signal from low level to high level and output a normal current signal. The logic gate responds to the normal current signal, converts the drive control signal to a low level, and outputs a normal operation signal to drive the system to return to normal. After receiving the normal operation signal, the drive circuit outputs the first output signal.

[0052] In this embodiment, even after the first output signal is disabled, the current of the first output signal is continuously monitored by a current sensor. When the current drops to a preset safe range, the current status signal automatically changes from low to high, and the logic gate subsequently changes the drive control signal to low. The drive circuit can then resume normal output without software intervention. This mechanism forms a hardware self-loop of "shutdown-recovery-re-detection," possessing cycle-by-cycle protection (CBC) capability: if the fault is not eliminated, shutdown is triggered again; if the fault has disappeared, normal output is maintained. The entire process requires no software reset or manual intervention, ensuring rapid recovery after fault elimination while avoiding frequent system lock-ups.

[0053] In some embodiments of the present invention, the driving circuit includes a driver and an H-bridge driving circuit; The driver is a gate driver chip with a disable control function. Its first input terminal is connected to the second output terminal of the microcontroller to receive the PWM drive signal output by the microcontroller; the second input terminal of the driver is connected to the output terminal of the logic gate to receive the drive control signal output by the logic gate. The first input terminal of the H-bridge driver circuit is connected to the first output terminal of the driver and is used to receive the first gate drive signal; the second input terminal of the H-bridge driver circuit is connected to the second output terminal of the driver and is used to receive the second gate drive signal. The driver is used to simultaneously turn off the first gate drive signal and the second gate drive signal through its internal disable control terminal when the drive control signal is high, thereby turning off the power devices in the H-bridge drive circuit.

[0054] It should be noted that the internal disable control terminal of the driver is named "DISABLE" in the specific driver (such as the NSi6602 dual-channel isolated gate driver). The DISABLE pin is active high. When the DISABLE pin receives a high level, both output channels of the driver are forcibly turned off, thereby turning off all power devices in the H-bridge driver circuit at the same time.

[0055] In this embodiment, the driver is configured as a gate driver chip with a dedicated disable control function. The disable control signal output by the logic gate is directly connected to the disable control terminal of the driver (instead of controlling each power transistor separately). When the disable control signal is valid, the internal logic of the driver can simultaneously turn off its output first gate drive signal and second gate drive signal, thereby ensuring that all power devices in the H-bridge driver circuit enter the shutdown state synchronously and quickly. This design avoids the path inconsistency or delay difference that may occur when controlling the upper and lower bridge arms separately in traditional schemes, further shortening the protection response time and improving the reliability of short-circuit shutdown.

[0056] In some embodiments of the present invention, such as Figure 2The microcontroller shown can be any microcontroller chip, preferably the IMS320F28377D; the logic gate shown can be any logic gate chip, preferably the SN74LVC1G00DBVR; in the driving circuit shown, the driver should be any gate driver chip with enable or disable control function, preferably the NSi6602B-DSWR (high reliability isolated dual-channel gate driver IC), and the H-bridge driving circuit can be any H-bridge driving circuit, preferably the NCE0224D transistor; the current sensor shown should be any Hall current sensor with fast fault output function, preferably the SC844AFT-20F5 high-precision current sensor; the load shown can be any load, preferably an inductive load.

[0057] In this embodiment, each output channel of the driver (such as the NSi6602B-DSWR, a high-reliability isolated dual-channel gate driver IC) outputs two gate drive signals: a high-side drive signal (HO) and a low-side drive signal (LO), which are respectively connected to the gates of the high-side MOSFET and the low-side MOSFET in the same half-bridge of the H-bridge. For ease of description, HO1 and LO1, which control the left half-bridge, are collectively referred to as the first gate drive signal, and HO2 and LO2, which control the right half-bridge, are collectively referred to as the second gate drive signal. Therefore, the "first gate drive signal" and the "second gate drive signal" each contain two actual gate drive physical signals, which together control the four power MOSFETs of the H-bridge.

[0058] In some embodiments of the present invention, the overall process is as follows: (1) Under normal operating conditions of the driver, the microcontroller outputs the VPWM signal (PWM drive signal) normally and the VEN signal is set to a high potential; after hardware configuration, the current sensor preferably has its overcurrent point (current threshold) set to 15A.

[0059] (2) When the inductive load is normally loaded, the two ends of the load are suddenly short-circuited to short-circuit the output with the signal ground, thereby simulating the overcurrent or short circuit condition. At this time, the current sensor detects the current of the first output signal VOUT1 in real time. When the current exceeds the threshold (e.g., 15A), its VFLAG signal changes from high level to low level within 2us and is sent to the logic gate. Its core logic VDIS = NOT(VEN AND VFLAG) makes its VDIS change from low level to high level and is sent to the drive circuit 300, ultimately disabling the first output signal VOUT1, thus achieving the function of timely overcurrent or short circuit protection.

[0060] (3) During the process of automatically disabling the first output signal VOUT1, the current sensor is still detecting the current of the first output signal VOUT1 in real time. When its current drops to a certain range, the circuit sensor’s VFLAG signal will change from low level to high level and be sent into the logic gate, causing its VDIS to change from high level to low level. The drive circuit returns to normal state, and the first output signal VOUT1 is output normally.

[0061] (4) At this time, since the simulated overcurrent or short circuit condition still exists, when the current of the first output signal VOUT1 exceeds the set threshold (e.g., 15A) again, the VFLAG signal of the current sensor will still change from high level to low level within 2us and, after being processed by the logic gate and the drive circuit, will finally disable the first output signal VOUT1, thus achieving the function of timely overcurrent or short circuit protection. This process repeats, thus providing the function of CBC (cycle-by-cycle protection).

[0062] It should be noted that the CBC cycle-by-cycle protection function is enabled by the software when the software enable signal is high. In this state, when the current sensor detects an overcurrent, the current status signal VFLAG goes low, and the logic gate immediately outputs a high-level VDIS signal to turn off the power devices in the H-bridge drive circuit. Once the current drops to a safe range, VFLAG automatically returns to high, and VDIS goes low, resuming the drive circuit's output. If the overcurrent fault persists after recovery, the current will exceed the threshold again, triggering shutdown once more. This cycle repeats, forming the main cycle-by-cycle protection loop, where the fault signal itself recovers.

[0063] It should also be noted that the CBC cycle-by-cycle protection function of the present invention differs from the prior art in the following ways: (1) Different reset mechanisms: This invention does not rely on PWM clock synchronization, but is directly driven by the level change of the current state signal VFLAG output by the current sensor itself. When the short circuit drops to the safe range, VFLAG changes from low to high, the disable control signal VDIS is released, and the drive circuit immediately resumes output without waiting for the start of the PWM cycle. (2) Different implementation paths: This invention adopts a pure hardware combination (current sensor + logic gate + driver chip), without the need for the CBC module inside the MCU, which has a faster response speed and higher reliability; (3) Different protection continuity: When the overcurrent fault persists, the present invention will automatically form a hardware self-loop of "shutdown-recovery-re-detection-shutdown-recovery". Each loop performs overcurrent detection and protection independently without software intervention, realizing true hardware cycle-by-cycle protection.

[0064] Therefore, the CBC implemented in this invention is essentially a hardware self-recovering cycle-by-cycle protection, which differs substantially from existing clock-synchronization-dependent CBC schemes in both implementation mechanism and reset method.

[0065] The present invention also has the following advantages: (1) High reliability and anti-interference ability: Existing technologies are mostly software-based protection solutions, which are susceptible to software failures such as program crashes and interruptions, leading to protection failure. Complex software processing flows can also malfunction under interference. The core protection logic of this invention is implemented by simple hardware circuits (logic gates), unaffected by software runtime states (crashes, program crashes). As long as the hardware circuits are functioning normally, the protection function can be reliably executed. This deterministic hardware implementation greatly enhances the system's survivability under abnormal conditions.

[0066] (2) Simple structure and low cost: Existing technologies, when achieving the same speed with a purely hardware solution, may require more complex analog comparator circuits, delay circuits, latch circuits, etc.; high-speed software solutions require high-performance MCUs and carefully optimized code. This invention requires only a standard logic gate (such as a NAND gate) and a small number of external connections to achieve high-speed, controllable protection functions. The circuit structure is extremely simple, easy to implement and integrate into existing driver circuits, with negligible increase in hardware cost.

[0067] (3) The protection strategy is flexible and controllable: In existing technologies, the protection thresholds and behaviors of purely hardware-based solutions are typically fixed, making dynamic adjustment based on system status difficult. While the core shutdown logic of this invention is hardware-based, the software can provide macro-level control over protection via the VEN signal. For example, the software can temporarily disable protection under specific operating modes (such as startup or specific load) (VEN=Low), or enable protection only under specific conditions (VEN=High). The software can also combine other information (such as temperature and historical fault records) to dynamically manage the VEN state, achieving a more intelligent protection strategy.

[0068] This invention successfully solves the key challenge of power protection in high-dynamic, high-reliability systems such as magnetic levitation controllers through an extremely simple yet ingenious hardware logic (VDIS = NOT(VEN AND VFLAG)). (1) It achieves fast hardware shutdown at the μs level, effectively preventing instantaneous damage to power MOS devices caused by overcurrent / short circuit.

[0069] (2) While ensuring hardware-level speed and high reliability, it seamlessly integrates software control capabilities (enable / disable / reset), achieving perfect synergy between "hardware speed" and "software control".

[0070] (3) The solution has a simple structure, low cost and easy implementation, which significantly improves the overall reliability and safety of the system. It is especially suitable for application scenarios such as magnetic levitation drive with extremely high requirements for response speed and reliability.

[0071] These advantages and benefits are directly derived from the proposed core logic circuit structure (which uses VFLAG and VEN to directly control DISABLE through logic gates).

[0072] In another feasible implementation, the objective of the present invention can also be achieved in the following way: 1. Software-dependent dynamic protection scheme (1) Principle: By collecting signals such as current and speed in real time, the PID parameters are dynamically adjusted to achieve the overcurrent protection threshold that adapts to the operating conditions. For example, in a magnetic levitation bearing system, the control parameters are automatically adjusted according to the rotor speed and the ambient medium (air / liquid) to adapt to the current fluctuations caused by changes in fluid resistance.

[0073] (2) Advantages: High flexibility, can be combined with temperature compensation algorithm to reduce false triggering rate.

[0074] (3) Limitations: The response delay is relatively large (usually >10μs), which depends on the computing power of the MCU. It is difficult to avoid device damage in extreme short circuits.

[0075] 2. Hardware Topology Reconfiguration Scheme (1) Principle: The full-bridge series winding structure (e.g., A1-B1 to AN-BN) is adopted. By detecting the current of each branch and (e.g., ian+icn), the short-circuited bridge arm is located, and the current path is reconstructed to maintain electromagnetic force balance. For example, when a bridge arm is short-circuited, the current direction of other windings is adjusted to achieve fault-tolerant operation.

[0076] (2) Advantages: It supports continuous operation after a short circuit without the need for immediate shutdown.

[0077] (3) Limitations: The circuit is highly complex, increasing the cost by about 30%, and requires a high-precision current sensor.

[0078] 3. Novel Detection Technologies and Devices 3.1 Desaturation Detection (DESAT) (1) Principle: Monitor the on-state voltage drop (Vds) of the power transistor. When the current surges and causes Vds to exceed the threshold, it triggers the turn-off. Applicable to SiC MOSFETs, with a response time of approximately 1–2 μs.

[0079] (2) Advantages: No external shunt resistor required, low power consumption; (3) Limitations: A blanking time needs to be set to prevent false triggering, and threshold drift at high temperatures may affect accuracy.

[0080] 3.2 SenseFET Current Mirror (1) Principle: The proportional current output by the sensing FET connected in parallel with the main MOSFET is converted into a voltage signal through a small resistance for protection.

[0081] (2) Applicable scenarios: high power density modules (such as integrated SiC modules), with low parasitic inductance and low noise.

[0082] (3) Cost: The price of the module is 15-20% higher than that of the conventional solution.

[0083] 4. Material and Device Level Protection Scheme 4.1 PTC thermistor current limiting (1) Principle: The self-resetting PTC resistor is connected in series. When there is an overcurrent, the resistance increases sharply and it becomes a high-resistance state. For example, a PTC with a Curie temperature of 100°C is set in the secondary circuit of the power supply, and the operating current accuracy is ±10%.

[0084] (2) Applicability: For example, low-power magnetic levitation controllers (<1kW) are inexpensive but have slow response (milliseconds).

[0085] 4.2 SiC Dedicated Drive Protection For the 2–5μs short-circuit tolerance window of SiC MOSFETs, the following solutions are adopted: shunt resistor + fast ADC (response <1μs), or anti-interference gate drive combined with RC filtering.

[0086] The overcurrent and short-circuit protection system provided by this invention achieves rapid protection through a combination of hardware and software by using fast response of hardware logic gates, dynamic control of enable switching signals, and real-time signal coordinated control. (1) Fast response mechanism of hardware logic gates The core logic VDIS = NOT(VEN AND VFLAG) directly processes the current state signal (VFLAG) and enable switching signal (VEN) of the current sensor through hardware logic gates (such as NAND gates), achieving a μs-level shutdown response. This design avoids interruption delays and program queuing in software processing, and its response speed is more than 10 times faster than a pure software solution, effectively preventing power MOSFETs from burning out due to instantaneous overcurrent.

[0087] The logic gate circuit has a simple structure (requiring only one standard gate circuit), low cost, and strong anti-interference ability, and is not affected by software crashes or glitches.

[0088] (2) Enable dynamic control capability of switching signals The VEN signal is dynamically controlled by software, enabling flexible start and stop of protection functions: When VEN=High: Protection function is activated, VFLAG triggers immediate shutdown; When VEN=Low: Force shutdown of MOSFET (software-activated protection); After the fault is handled, the protection state can be quickly reset via VEN without the need for a hardware reset.

[0089] It supports adjusting protection policies based on operating conditions (such as startup mode), for example, temporarily disabling protection under specific loads.

[0090] (3) Signal coordination and fault diagnosis VFLAG, derived from the hardware-level fault output of the current sensor, ensures signal authenticity; combined with VEN, it provides dual verification to prevent false triggering.

[0091] The DISABLE terminal of the driver chip is directly controlled, shortening the protection path and reducing the risk of failure in intermediate links.

[0092] The overcurrent and short-circuit protection system provided by the present invention has been described in detail above. Specific examples have been used to illustrate the principle and implementation of the present invention. The description of the above embodiments is only for the purpose of helping to understand the system and its core ideas. At the same time, for those skilled in the art, there will be changes in the specific implementation and application scope based on the ideas of the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. An overcurrent and short-circuit protection system, characterized in that, include: Microcontrollers, logic gates, driver circuits, and current sensors; The first output terminal of the microcontroller is used to send an enable switching signal indicating whether software enable is enabled; The current sensor is used to detect the current value of the first output signal output by the drive circuit and output a current status signal. When the current value exceeds the current threshold, the current status signal is a current fault signal. The first input terminal of the logic gate is connected to the first output terminal of the microcontroller, and the second input terminal of the logic gate is connected to the first output terminal of the current sensor. It is used to generate a disable control signal with a high level drive control signal in response to the current fault signal when the enable switching signal is high. The second input terminal of the driving circuit is connected to the output terminal of the logic gate, and is used to receive the disable control signal and turn off the power device in the driving circuit.

2. The overcurrent and short-circuit protection system according to claim 1, characterized in that, When the current value does not exceed the current threshold, the current status signal is a normal current signal; The logic gate is used to generate a normal operation signal with a low drive control signal in response to the normal current signal when the enable switching signal is high.

3. The overcurrent and short-circuit protection system according to claim 1, characterized in that, When the enable switching signal is high, it indicates that the software is enabled, and a software enable signal is output; when the enable switching signal is low, it indicates that the software is disabled, and a software disable signal is output. When the enable switching signal is low, the logic gate directly generates a disable control signal in response to the software disable signal.

4. The overcurrent and short-circuit protection system according to claim 1, characterized in that, The first input terminal of the drive circuit is connected to the second output terminal of the microcontroller, and is used to receive the PWM drive signal output by the microcontroller.

5. The overcurrent and short-circuit protection system according to claim 1, characterized in that, The system also includes a load; The input terminal of the load is connected to the second output terminal of the current sensor, and is used to receive the second output signal output by the drive circuit through the current sensor.

6. The overcurrent and short-circuit protection system according to claim 1, characterized in that, The logic gate is a two-input NAND gate, and its expression is as follows: Wherein, VDIS is the drive control signal, VEN is the enable switching signal, and VFLAG is the current state signal.

7. The overcurrent and short-circuit protection system according to claim 6, characterized in that, When the enable switching signal is low, the drive control signal is high; When the enable switching signal is high and the current state signal is high, the drive control signal is low; When the enable switching signal is high and the current state signal is low, the drive control signal is high.

8. The overcurrent and short-circuit protection system according to claim 1, characterized in that, When the enable switching signal is high and the power device in the drive circuit is turned off, the first output signal output by the drive circuit is in a disabled state. At this time, the current of the first output signal is synchronously detected by the current sensor. When the current of the first output signal decreases to a preset current range, the current sensor changes the current status signal from low level to high level and outputs a normal current signal. The logic gate responds to the normal current signal by converting the drive control signal to a low level and outputs a normal operation signal to drive the system back to normal. The drive circuit receives the normal operation signal and outputs a first output signal.

9. The overcurrent and short-circuit protection system according to claim 1, characterized in that, The system achieves timely periodic protection and reset by using the enable switching signal output in real time by the microcontroller and the current status signal output in real time by the current sensor that monitors the first output signal.

10. The overcurrent and short-circuit protection system according to claim 1, characterized in that, The driving circuit includes a driver and an H-bridge driving circuit; The driver is a gate driver chip with a disable control function. Its first input terminal is connected to the second output terminal of the microcontroller and is used to receive the PWM drive signal output by the microcontroller. The second input terminal of the driver is connected to the output terminal of the logic gate, and is used to receive the drive control signal output by the logic gate; The first input terminal of the H-bridge driving circuit is connected to the first output terminal of the driver and is used to receive the first gate driving signal; the second input terminal of the H-bridge driving circuit is connected to the second output terminal of the driver and is used to receive the second gate driving signal. The driver is used to simultaneously turn off the first gate drive signal and the second gate drive signal through its internal disable control terminal when the drive control signal is high, thereby turning off the power devices in the H-bridge drive circuit.

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