A pure analog fixed pulse width detection latch circuit

Abstract

This invention discloses a pure analog fixed pulse width detection latch circuit. Given that traditional digital detection schemes are susceptible to single-event interference in aerospace scenarios and suffer from high power consumption and size, this invention employs a cascaded architecture consisting of an input stage, an active integrator, a window comparator, an AND unit, and a tri-state D flip-flop. When an external pulse is input, the integrator generates a linear voltage during its low-level period, which the comparator uses to perform dual-threshold discrimination from 1.5V to 3.5V. The AND unit only conducts and outputs a set signal when the voltage falls within a preset range, subsequently driving the flip-flop into the latch state. Because the circuit eliminates timing and program memory, it fundamentally avoids the state-flipping hazards caused by space particles. Simultaneously, thanks to the synergistic effect of the RC integrator network and the dual-threshold discrimination window, transient spike interference is effectively attenuated, thus achieving highly reliable, low-power, and accurate fixed pulse width discrimination.

Description

Technical Field

[0001] This invention relates to the field of electronic circuit technology, and in particular to a pure analog fixed pulse width detection latch circuit. Background Technology

[0002] In the operation of highly reliable electronic systems such as industrial automation control, aerospace electronics, and satellite payload control systems, pulse signals are the core carriers of information transmission, status triggering, and command execution. The width parameter of the pulse signal directly determines the system's control accuracy and operational reliability. In various complex electromagnetic environments, the pulse signals received by the circuit are often mixed with a large number of interference pulse noises of varying widths, which can easily lead to malfunctions such as false triggering, incorrect command execution, and misjudgment of status. Therefore, pulse width detection technology with high-precision window discrimination capabilities is urgently needed to accurately select effective pulse signals that conform to a preset fixed width, while thoroughly filtering out excessively narrow spike interference pulses and excessively wide clutter interference pulses, ensuring the stable and accurate operation of the electronic system.

[0003] Currently, the industry mainly employs two core technologies for the detection and identification of pulse signals with specific pulse widths: digital detection schemes and pure analog detection schemes. Both types of technologies have significant technical shortcomings in practical engineering applications, making them unsuitable for demanding application scenarios requiring radiation resistance, low power consumption, high integration, and high reliability, such as aerospace applications. The specific technical drawbacks are as follows: One approach is the digital detection method. This mainstream approach uses a microcontroller (MCU) or field-programmable gate array (FPGA) as the core control unit, coupled with a dedicated sampling clock module, to calculate and detect pulse width through clock counting. This digital detection architecture relies on software programming logic and an independent clock source. Firstly, it requires the development of a dedicated control program, configuration of a clock oscillation circuit, and peripheral auxiliary circuits, significantly increasing the complexity of hardware construction and the development and debugging costs of the software program. It also increases the size and integration difficulty of the entire detection system, hindering its adaptation to miniaturized electronic devices. Secondly, in the aerospace radiation environment, cosmic ray-induced single-event effects (including single-event upsets (SEUs) and single-event transients (SETs)) easily interfere with digital logic devices such as MCUs and FPGAs, leading to problems such as internal logic level flips, abnormal program execution, and false pulse detection triggering. Its resistance to radiation interference is extremely poor, failing to meet the high reliability requirements of aerospace electronic systems. Meanwhile, the entire digital detection system consumes several watts of power, which is relatively high. For platforms such as satellites and spacecraft where power supply, payload resources, and heat dissipation are limited, this will significantly consume system resources and reduce equipment endurance and operational stability. In addition, the clock circuit continuously generates electromagnetic radiation during system operation, which can easily interfere with the normal operation of sensitive core modules such as the onboard radio frequency receiving front-end and high-precision sensing acquisition, causing electromagnetic compatibility issues for the entire system.

[0004] Secondly, there is the traditional pure analog detection method, which mainly uses an RC integrator circuit combined with a single threshold comparator to achieve pulse detection. This circuit structure can only achieve unidirectional pulse width discrimination, and can only filter pulse signals with a width greater than or less than a set threshold. It cannot build a bidirectional window-type detection logic, and cannot accurately identify effective pulses with a preset fixed width. The pulse width detection accuracy and adaptability are extremely low. At the same time, the 555 timer monostable detection circuit disclosed in the prior art can initially achieve the detection function of fixed width pulses, but it has inherent structural defects: after the circuit is triggered, it cannot be automatically reset, and manual intervention is required to reset it before entering the next detection state. It cannot meet the continuous and automated pulse detection requirements of electronic systems. Moreover, this circuit lacks a targeted narrow pulse interference suppression mechanism, and cannot effectively filter out narrow spike interference pulses generated during circuit operation. Its anti-interference capability is weak, and the detection accuracy is difficult to guarantee.

[0005] In summary, current pulse width detection technologies generally suffer from numerous drawbacks, including complex system structures, poor resistance to space radiation, high power consumption, insufficient electromagnetic compatibility, inability to achieve accurate window-type pulse width discrimination, lack of automatic reset function, and weak resistance to narrow pulse interference. There is currently a lack of a dedicated fixed pulse width detection circuit on the market that features a simple structure, a fully analog architecture, accurate window width discrimination, support for latched output and manual reset, and adaptability to the harsh radiation-resistant working environment of aerospace. This makes it difficult to meet the core requirements of industrial control and aerospace electronic systems for high-precision, high-reliability, low-power, and highly integrated pulse detection. Summary of the Invention

[0006] This invention provides a pure analog fixed pulse width detection latch circuit that only recognizes low pulses of a set width (e.g., 160ms), and does not respond to narrow or wide pulses; it latches and outputs immediately after detection and supports manual reset; in aerospace applications, it has advantages such as resistance to single-event effects, extremely low power consumption, and no electromagnetic radiation.

[0007] This invention provides a purely analog fixed pulse width detection latch circuit, comprising: The input stage is used to receive external pulse signals and perform impedance matching and biasing; it normally outputs a high level. An active integrator, whose input is connected to the input stage, is used to integrate the signal during the period when the external pulse signal is low to generate a linearly rising integrated voltage. A window comparator, whose input is connected to the output of the active integrator, is used to perform dual threshold window discrimination on the integrated voltage. When the integrated voltage falls into a preset voltage range, a discrimination signal is output. The logic AND unit, whose input is connected to the output of the window comparator, is used to turn on and output a set signal when the discrimination signal is received; A tri-state D flip-flop, whose set terminal is connected to the output terminal of the AND logic unit, is used to enter the latch state in response to the set signal and output a high level at its output terminal; An indicator device, the input of which is connected to the output of the tri-state D flip-flop, is used to output an indicator state according to the high level.

[0008] In one embodiment of the present invention, the input stage includes a series resistor and a pull-down resistor; The first end of the series resistor receives the external pulse signal, the second end of the series resistor and the first end of the pull-down resistor are connected to the input of the active integrator, and the second end of the pull-down resistor is grounded.

[0009] In one embodiment of the present invention, the active integrator includes an operational amplifier, a feedback resistor, and a feedback capacitor; The inverting input terminal of the operational amplifier is connected to the input stage through the series resistor. The feedback resistor and the feedback capacitor are connected in parallel and then connected across the output terminal of the operational amplifier and the inverting input terminal. The non-inverting input terminal of the operational amplifier is connected to the reference voltage divider node.

[0010] In one embodiment of the present invention, the reference voltage divider node is obtained by dividing a 5V power supply voltage by a first voltage divider resistor and a second voltage divider resistor connected in series. The first voltage divider resistor has a resistance of 10kΩ and the second voltage divider resistor has a resistance of 10kΩ.

[0011] In one embodiment of the present invention, the window comparator includes a first comparator and a second comparator, wherein the non-inverting input of the first comparator is connected to the upper limit reference node, and the non-inverting input of the second comparator is connected to the lower limit reference node.

[0012] In one embodiment of the present invention, the upper limit reference node is obtained by dividing a 5V power supply voltage by a third voltage divider resistor and a fourth voltage divider resistor connected in series. The resistance of the third voltage divider resistor is 10kΩ and the resistance of the fourth voltage divider resistor is 23.3kΩ.

[0013] In one embodiment of the present invention, the lower limit reference node is obtained by dividing a 5V power supply voltage by a fifth voltage divider resistor and a sixth voltage divider resistor connected in series. The fifth voltage divider resistor has a resistance of 10kΩ and the sixth voltage divider resistor has a resistance of 4.28kΩ.

[0014] In one embodiment of the present invention, the logic AND unit is configured to be constructed based on the internal logic gates of the CD4001 chip, and its two input terminals respectively receive the pull-down signal from the output terminal of the first comparator and the pull-down signal from the output terminal of the second comparator, and the output terminal outputs a set level.

[0015] In one embodiment of the present invention, the reset terminal of the tri-state D flip-flop is connected to the output terminal of the inverter, the input terminal of the inverter receives the external pulse signal, and the reset terminal of the tri-state D flip-flop is also connected in parallel to a manual reset button, one end of which is grounded.

[0016] In one embodiment of the present invention, the indicating device includes a light-emitting diode and a current-limiting resistor. The anode of the light-emitting diode is connected to the Q output terminal of the tri-state D flip-flop, and the cathode of the light-emitting diode is grounded through the 470Ω current-limiting resistor.

[0017] The present invention has the following beneficial effects: (1) Since the circuit does not contain any sequential logic memory or program memory except for the latch unit, the bombardment of high-energy particles in space cannot cause unexpected state flips or program crashes, thus fundamentally eliminating the inherent SEU hidden danger in digital processor solutions.

[0018] (2) By leveraging the synergistic effect of the window comparator and the active integrator, this invention can efficiently suppress single-event transient interference. Given that the feedback resistor and the integrating capacitor are connected in parallel in the integration circuit to form a time constant of RC=1s, the SET pulse in the nanosecond to microsecond range is significantly attenuated before being transmitted to the comparator stage; at the same time, the lower limit comparator and the upper limit comparator lock the voltage discrimination window of 1.5V to 3.5V through the voltage divider network, so that any out-of-limit fluctuations caused by transient spikes cannot trigger the output of the dual comparators at the same time, thereby avoiding latch missetting.

[0019] (3) Based on specific device selection and single power supply design, this invention achieves controllable single-event lockout risk and extremely low system power consumption. Since the internal parasitic PNPN structure of the TL081 operational amplifier and LM393 comparator maintains a voltage higher than the power rail under a 5V operating voltage, the SEL risk in working propellant applications is effectively suppressed; in addition, the static power consumption of each logic chip and amplifier is less than 5mW, which can achieve a reduction in power consumption by orders of magnitude compared with traditional FPGA or microcontroller solutions, thus adapting to the stringent energy budget of satellite platforms. Attached Figure Description

[0020] Figure 1 A schematic diagram of a pure analog fixed pulse width detection latch circuit is shown in one embodiment of the present invention. Detailed Implementation

[0021] In the following description, the invention is described with reference to various embodiments. However, those skilled in the art will recognize that the embodiments may be practiced without one or more specific details or with other alternatives and / or additional methods, materials, or components. In other instances, well-known structures, materials, or operations are not shown or described in detail so as not to obscure the inventive points of the invention. Similarly, for illustrative purposes, specific quantities, materials, and configurations are set forth to provide a comprehensive understanding of embodiments of the invention. However, the invention is not limited to these specific details.

[0022] In this invention, the various embodiments are merely intended to illustrate the solutions of the invention and should not be construed as limiting.

[0023] In this specification, references to "an embodiment" or "this embodiment" mean that a particular feature, structure, or characteristic described in connection with that embodiment is included in at least one embodiment of the invention. The phrase "in one embodiment" appearing throughout this specification does not necessarily refer to the same embodiment in all instances.

[0024] Furthermore, the numbering of the steps in the methods of the present invention does not limit the execution order of the method steps. Unless otherwise specified, the method steps may be executed in different orders.

[0025] The present invention will be further described below with reference to the accompanying drawings and specific embodiments.

[0026] Figure 1 A schematic diagram of a pure analog fixed pulse width detection latch circuit is shown in one embodiment of the present invention.

[0027] like Figure 1 As shown, in this embodiment, the pure analog fixed pulse width detection latch circuit includes: Input stage 1 is used to receive external pulse signals and perform impedance matching and biasing. Normally, it outputs a high level. Input stage 1 includes a series resistor 11 and a pull-down resistor 12. The first end of the series resistor 11 receives the external pulse signal. The second end of the series resistor 11 and the first end of the pull-down resistor 12 are connected to the input terminal of the active integrator 2. The second end of the pull-down resistor 12 is grounded.

[0028] The input signal IN is connected in series with a 10kΩ resistor, and then connected to the inverting input of the TL081 and a 100kΩ pull-down resistor (to GND). The normal input level is high (5V).

[0029] The input terminal of the active integrator 2 is connected to the input stage 1 and is used to integrate the signal during the period when the external pulse signal is low to generate a linearly rising integrated voltage.

[0030] The active integrator 2 includes an operational amplifier 21, a feedback resistor 22, and a feedback capacitor 23. The inverting input terminal of the operational amplifier 21 is connected to the input stage 1 through the series resistor 11. The feedback resistor 22 and the feedback capacitor 23 are connected in parallel and then spanned between the output terminal and the inverting input terminal of the operational amplifier 21. The non-inverting input terminal of the operational amplifier 21 is connected to the reference voltage divider node.

[0031] The reference voltage divider node is obtained by dividing the 5V power supply voltage by a series connection of a first voltage divider resistor 24 and a second voltage divider resistor 25, with a voltage division value of 2.7V. The resistance of the first voltage divider resistor 24 is 10kΩ, and the resistance of the second voltage divider resistor 25 is 10kΩ.

[0032] In this embodiment, the active integrator 2 uses a TL081. The non-inverting input is connected to a 2.5V reference (obtained by dividing 5V by two 10kΩ resistors). The inverting input receives the input signal through a 10kΩ resistor. A 100kΩ resistor and a 10μF electrolytic capacitor are connected in parallel between the inverting input and the output. When the input is low (0V), the integrator output rises linearly from 2.5V; after the input returns to high, the integrator discharges through the feedback resistor, returning to 2.5V.

[0033] The input of the window comparator 3 is connected to the output of the active integrator 2, and is used to perform dual threshold window discrimination on the integrated voltage. When the integrated voltage falls into a preset voltage range, a discrimination signal is output.

[0034] The window comparator 3 includes a first comparator 31 and a second comparator 32. The non-inverting input of the first comparator 31 is connected to the upper limit reference node, and the non-inverting input of the second comparator 32 is connected to the lower limit reference node.

[0035] The upper limit reference node is obtained by dividing the 5V power supply voltage by the third voltage divider resistor 35 and the fourth voltage divider resistor 36 in series. The resistance of the third voltage divider resistor 35 is 10kΩ and the resistance of the fourth voltage divider resistor 36 is 23.3kΩ.

[0036] The lower limit reference node is obtained by dividing the 5V power supply voltage by the fifth voltage divider resistor 37 and the sixth voltage divider resistor 38 in series. The fifth voltage divider resistor 37 has a resistance of 10kΩ and the sixth voltage divider resistor 38 has a resistance of 4.28kΩ.

[0037] In this embodiment, window comparator 3 is selected as LM393. The first comparator (lower limit): the non-inverting input is connected to 1.5V (obtained by voltage divider), and the inverting input is connected to the integrator output. The second comparator (upper limit): the non-inverting input is connected to 3.5V (obtained by voltage divider), and the inverting input is connected to the integrator output. The outputs of the two comparators are connected to diodes via wired-AND or external NAND gates to implement the logic AND function (in this embodiment, an AND gate built with CD4001 is used).

[0038] The input of the AND unit 4 is connected to the output of the window comparator 3, and is used to turn on and output a set signal when the discrimination signal is received. The AND unit 4 is constructed using the internal logic gates of the CD4001 chip. Its two inputs receive the pull-down signal from the output of the first comparator 31 and the pull-down signal from the output of the second comparator 32, respectively, and its output outputs a valid set level.

[0039] The set terminal of the tri-state D flip-flop 5 is connected to the output terminal of the AND logic unit 4, and is used to enter the latch state in response to the set signal and output a high level at its output terminal. The reset terminal of the tri-state D flip-flop 5 is connected to the output terminal of the inverter 8, and the input terminal of the inverter 8 receives the external pulse signal. The reset terminal of the tri-state D flip-flop 5 is also connected in parallel to a manual reset button 7, one end of which is grounded.

[0040] The input terminal of the indicator device 6 is connected to the output terminal of the tri-state D flip-flop 5, and is used to output an indication state according to the high level. The indicator device 6 includes a light-emitting diode 61 and a current-limiting resistor 62. The anode of the light-emitting diode 61 is connected to the Q output terminal of the tri-state D flip-flop 5, and the cathode of the light-emitting diode 61 is grounded through the 470Ω current-limiting resistor 62.

[0041] In this embodiment, the component list is shown in the table below.

[0042] In terms of operational logic, an external low-level pulse, after being conditioned by input stage 1, enters the active integrator 2. When the pulse width strictly falls within the preset range, the integrated voltage will precisely cross the lower threshold without exceeding the upper threshold. Simultaneously, the window comparator 3 flips, the logic and unit 6 conducts, and outputs a set signal to drive the tri-state D flip-flop 7 for latching. Once flip-flop 7 is set, the Q terminal immediately outputs a high level to illuminate the indicator device 8, and the state is maintained until the manual reset button 9 is pressed. If the pulse is too narrow or too wide, the integrated voltage cannot simultaneously meet the dual threshold conditions, the window comparator 3 maintains its initial state, and the flip-flop 7 does not respond. Thanks to the all-analog signal processing path and the clockless sampling architecture, the circuit naturally avoids single-event transient interference, thereby achieving highly reliable pulse width discrimination, extremely low power consumption operation, and radiation-resistant latched output. In summary, the various components work together to complete the entire closed-loop control process of pulse window identification, state latching and maintenance, and manual reset clearing.

[0043] Although various embodiments of the invention have been described above, it should be understood that they are presented by way of example only and not as limitations. It will be apparent to those skilled in the art that various combinations, modifications, and alterations can be made without departing from the spirit and scope of the invention. Therefore, the breadth and scope of the invention disclosed herein should not be limited by the exemplary embodiments disclosed above, but should be defined solely by the appended claims and their equivalents.

Claims

1. A purely analog fixed pulse width detection latch circuit, characterized in that, include: The input stage is used to receive external pulse signals and perform impedance matching and biasing; it normally outputs a high level. An active integrator, whose input is connected to the input stage, is used to integrate the signal during the period when the external pulse signal is low to generate a linearly rising integrated voltage. A window comparator, whose input is connected to the output of the active integrator, is used to perform dual threshold window discrimination on the integrated voltage. When the integrated voltage falls into a preset voltage range, a discrimination signal is output. The logic AND unit, whose input is connected to the output of the window comparator, is used to turn on and output a set signal when the discrimination signal is received; A tri-state D flip-flop, whose set terminal is connected to the output terminal of the AND logic unit, is used to enter the latch state in response to the set signal and output a high level at its output terminal; An indicator device, the input of which is connected to the output of the tri-state D flip-flop, is used to output an indication state according to the high level.

2. The circuit according to claim 1, characterized in that, The input stage includes a series resistor and a pull-down resistor; The first end of the series resistor receives the external pulse signal, the second end of the series resistor and the first end of the pull-down resistor are connected to the input of the active integrator, and the second end of the pull-down resistor is grounded.

3. The circuit according to claim 1, characterized in that, The active integrator includes an operational amplifier, a feedback resistor, and a feedback capacitor; The inverting input terminal of the operational amplifier is connected to the input stage through the series resistor. The feedback resistor and the feedback capacitor are connected in parallel and then connected across the output terminal of the operational amplifier and the inverting input terminal. The non-inverting input terminal of the operational amplifier is connected to the reference voltage divider node.

4. The circuit according to claim 3, characterized in that, The reference voltage divider node is obtained by dividing the 5V power supply voltage by a first voltage divider resistor and a second voltage divider resistor connected in series. The resistance of the first voltage divider resistor is 10kΩ and the resistance of the second voltage divider resistor is 10kΩ.

5. The circuit according to claim 1, characterized in that, The window comparator includes a first comparator and a second comparator. The non-inverting input of the first comparator is connected to the upper limit reference node, and the non-inverting input of the second comparator is connected to the lower limit reference node.

6. The circuit according to claim 5, characterized in that, The upper limit reference node is obtained by dividing the 5V power supply voltage by a third voltage divider resistor and a fourth voltage divider resistor connected in series. The resistance of the third voltage divider resistor is 10kΩ and the resistance of the fourth voltage divider resistor is 23.3kΩ.

7. The circuit according to claim 5, characterized in that, The lower limit reference node is obtained by dividing the 5V power supply voltage by a fifth voltage divider resistor and a sixth voltage divider resistor connected in series. The fifth voltage divider resistor has a resistance of 10kΩ and the sixth voltage divider resistor has a resistance of 4.28kΩ.

8. The circuit according to claim 1, characterized in that, The logic unit is configured to be built based on the internal logic gates of the CD4001 chip. Its two input terminals receive the pull-down signals from the output terminals of the first comparator and the second comparator, respectively, and the output terminal outputs a set level.

9. The circuit according to claim 1, characterized in that, The reset terminal of the tri-state D flip-flop is connected to the output terminal of the inverter, and the input terminal of the inverter receives the external pulse signal. The reset terminal of the tri-state D flip-flop is also connected in parallel to a manual reset button, one end of which is grounded.

10. The circuit according to claim 1, characterized in that, The indicating device includes a light-emitting diode and a current-limiting resistor. The anode of the light-emitting diode is connected to the Q output terminal of the tri-state D flip-flop, and the cathode of the light-emitting diode is grounded through the 470Ω current-limiting resistor.

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