LDMOS nanosheet transistor including nanosheet drift region field plate

Abstract

A microelectronic device (100) includes a nanosheet lateral diffusion metal oxide semiconductor (LDMOS) transistor (101). The nanosheet transistor (101) includes source and drain regions (132, 133) of a first conductivity type extending into a semiconductor substrate (104). A nanosheet region (116) including semiconductor nanosheet layers (114) extends between the source and drain regions (132, 133). The nanosheet layers (114) alternate with gate conductor layers (142) extending between the source and drain regions (132, 132). The nanosheet layers (114) also alternate with field plate conductor layers (157) extending between the gate conductor layers (142) and the drain region (133).

Description

[0001] This specification relates to the field of microelectronic devices. More specifically, but not exclusively, this specification relates to gate-controlled devices, such as LDMOS transistors, and particularly nanosheet LDMOS transistors. Background Technology

[0002] Semiconductor components are constantly being improved to operate reliably with smaller feature sizes. Manufacturing semiconductor devices that offer increasingly higher performance while meeting performance and reliability specifications presents a variety of challenges. Summary of the Invention

[0003] The present invention is provided to provide a simplified overview of the concepts described, which will be further described below in specific embodiments, including the accompanying drawings. The present invention does not limit the scope of the specification or claims.

[0004] The described examples include microelectronic devices, such as integrated circuits, and methods of manufacturing such devices. One example includes a microelectronic device comprising a nanosheet laterally diffused metal-oxide-semiconductor (LDMOS) transistor. The transistor includes a source region and a drain region having a first conductivity type extending into a semiconductor substrate. A nanosheet region comprising semiconductor nanosheets extends between the source region and the drain region. The nanosheets alternate with a gate conductor layer extending between the source region and the drain region. The nanosheets also alternate with a field plate conductor layer extending between the gate conductor layer and the drain region. Attached Figure Description

[0005] Figure 1AA These are top views of example microelectronic devices at various stages of development, and Figures 1AB to 1BJ The image shows a cross-section of the example microelectronic device, which includes a nanosheet LDMOS transistor with a field plate.

[0006] Figure 2A This is a top view of an example microelectronic device after it has been formed, which includes a nanosheet LDMOS transistor containing multiple field plates.

[0007] Figure 2B The image shows a cross-section of an example microelectronic device after it has been formed, the example microelectronic device comprising a nanosheet LDMOS transistor, the nanosheet LDMOS transistor comprising multiple field plates.

[0008] Figure 3A This is a top view of an example microelectronic device after it has been formed, which includes a multi-finger nanosheet LDMOS transistor with a field plate.

[0009] Figure 3B and Figure 3C The image shows a cross-section of an example microelectronic device after it has been formed, the example microelectronic device comprising a multi-finger nanosheet LDMOS transistor with a field plate.

[0010] Figure 4A This is a top view of an example microelectronic device after it has been formed, which includes a nanosheet LDMOS transistor, the nanosheet LDMOS transistor including a field plate and a plurality of nanosheet dielectric spacers.

[0011] Figure 4B The image shows a cross-section of an example microelectronic device after it has been formed, the example microelectronic device comprising a nanosheet LDMOS transistor, the nanosheet LDMOS transistor comprising a field plate and a plurality of dielectric spacers. Detailed Implementation

[0012] This specification is described with reference to the accompanying drawings. The drawings are not to scale and are provided for illustrative purposes only. Several aspects of this specification are described below with reference to example applications used for illustration. Numerous specific details, relationships, and methods are set forth to provide an understanding of this specification. This specification is not limited to the order of the described actions or events, as some actions may occur in a different order and / or simultaneously with other actions or events unless otherwise stated. Furthermore, according to this specification, some of the described actions or events may be omitted in some examples.

[0013] Furthermore, although some examples illustrated herein are shown in two-dimensional views of various regions with depth and width, these regions are merely illustrative representations of a portion of a device that is actually a three-dimensional structure. Therefore, when manufactured in an actual device, these regions will have three dimensions, including length, width, and depth. Moreover, while this specification can be illustrated by examples of active devices, these illustrative representations are not intended to limit the scope or applicability of this specification. Furthermore, the active devices in this specification are not limited to the physical structures illustrated. These structures are included to demonstrate the utility and application of this specification to various examples.

[0014] It should be noted that terms such as top, bottom, above, upper, and lower are used in this specification. These terms do not limit the location or orientation of the structure or element, but are used to provide spatial relationships between structures or elements. The terms "lateral" and "laterally" refer to a direction parallel to a plane corresponding to the surface of a layer (e.g., the top surface of a semiconductor substrate). Furthermore, as used herein, the term "about" may in some cases refer to a variation of ±5% to ±10% of the value. In other cases, the term "about" may refer to a variation of ±10% to ±20% of the value.

[0015] Microelectronic devices are constantly being improved to operate reliably with higher performance and smaller feature sizes. Manufacturing such microelectronic devices that meet area scaling and reliability specifications presents an ongoing challenge. Some gate-controlled devices, such as metal-oxide-semiconductor (MOS) transistors, include features that support high-voltage operation, for example, voltages applied to their drain (or drain structure) of 20 V, 30 V, 40 V, or even higher. Such MOS transistors may include drain diffusion profiles (or drain junction profiles) designed to support high voltages applied to the drain, for example, having extended portions to distribute the voltage drop over a greater distance. Therefore, such MOS transistors may be referred to as extended-drain (ED) MOS transistors, such as extended-drain n-channel MOS (DENMOS) transistors, extended-drain p-channel MOS (DEPMOS) transistors, laterally diffused MOS (LDMOS) transistors, and groups of DENMOS and DEPMOS transistors (which may be referred to as complementary extended-drain MOS or DECMOS transistors). Other gate-controlled microelectronic devices may include gate-controlled bipolar semiconductor devices, gate-controlled unipolar semiconductor devices, insulated-gate bipolar transistors (IGBTs), metal-oxide-semiconductor triggered SCRs, MOS-controlled thyristors, and gate-controlled diodes. EDM transistors are miniaturized to smaller sizes to reduce microchip costs and improve circuit performance by reducing parasitic resistance and capacitance. Maintaining good reliability and yield can be challenging; therefore, improving transistor performance independently of lateral lithography scaling can be advantageous.

[0016] Stacking multiple transistor channels can be advantageous because it reduces on-resistance and increases on-current proportionally to the number of stacked layers. Figure 1AA to 1BJ The described example ED transistor may have a nanosheet doping distribution with a dose in the resurf (reduction of surface electric field) range of 10. 12 Up to 10 13 cm -2This sets the contribution of the drain drift region to the source-drain on-resistance (RDSON), which is typically the dominant contribution. Therefore, stacking multiple nanosheet ED transistors in parallel can reduce the RDSON in a given area, resulting in a lower cost-to-quality factor—the specific on-resistance (RSP), which is equal to RDSON multiplied by the area—and improved power scaling for a given lithography scaling capability. The physical geometry of the nanosheets used for ED transistors differs from that in nanosheet digital CMOS transistors. Typically, nanosheet digital CMOS transistors use nanosheet architectures containing nanosheet layers only a few nanometers thick. However, for high-voltage ED transistors, drain drift region mobility can be beneficial, and nanosheets thicker than 10 nm (e.g., in the range of 20 nm to 500 nm or greater) can be used to achieve the target RSP values ​​for efficient power circuit designs. In some examples, the nanosheet thickness can be 50 nm to 500 nm, or 100 nm to 300 nm, which keeps the drain drift region doping concentration sufficiently low to maintain high electron mobility and thus low RSP.

[0017] Some aspects of nanoribbon transistors are described in U.S. Patent Application No. 18 / 525,638, which is incorporated herein by reference in its entirety. The specification describes similar devices comprising one or more field plates. Adding such field plates to, for example... Figures 1AA to 1BJ The ED transistor in the example device described improves the uniformity of the electric field along the drain drift region. One or more field plates can better control the electrostatics of the drift region, thus avoiding localized high field regions. In other words, the field plates extend the equipotential lines through the drain drift region and reduce the inhomogeneity of the equipotential line spacing. One way to do this is to place one or more field plates along the drain drift region with a voltage that monotonically varies from the source and gate regions to the drain. External circuitry, such as resistor strings or breakdown diode strings, such as Zener diodes or avalanche diodes, can be used to force an increase in the monotonically varying field plate voltage from the source and gate regions (both grounded in the off state) to the drain region. In the on state, the field plates can be biased to accumulate drift region carriers, thereby reducing the drain-to-source resistance. In the on state, enhanced drift accumulation or a smaller drain-to-source resistance can be achieved through a larger field plate or a higher field plate potential. Optimization of field plate size, field plate spacing, number of field plates, and field plate potential can enhance the device's performance in both the off and on states.

[0018] This specification contains several examples of microelectronic devices comprising nanosheet LDMOS transistors incorporating one or more field plates. While such examples and variations are expected to provide lower RDSON than some baseline devices of similar size and other similar performance characteristics, no particular result is claimed in this specification unless expressly stated in the specific claims. As used herein, the term “superlattice” refers to a periodic structure of layers of at least two different materials. A superlattice may have many such layers, and in some cases may have as few as two layers, comprising a first material layer and a second material layer. As used herein, the term “nanosheet” means a layer within a superlattice having a thickness of no more than 500 nm (in a direction normal to the main surface of the substrate on which the superlattice is formed). A nanosheet may also be an active layer of a semiconductor device comprising said nanosheet. As used herein, the term “sacrificial layer” refers to a layer initially formed in a superlattice that is subsequently removed, in whole or in part, during the formation of the nanosheet transistor.

[0019] Figures 1AA to 1BJ The first type of microelectronic device is shown in a series of formation stages, which allows for the beneficial application of the principles of this specification. Figures 1AA to 1BJ A top view and a cross-sectional view of an example microelectronic device 100 are shown, including, for example, a nanosheet LDMOS transistor 101, referred to herein as nanosheet transistor 101. Nanosheet transistor 101 includes a gate conductor region 168 and a field plate region 161 electrically isolated from each other by a nanosheet dielectric spacer 158. (See example...) Figure 1AZ Unless otherwise implied, the nanosheet region 116 in this example comprises a semiconductor layer 114, sometimes referred to herein as nanosheet layer 114, and described below, implemented in an n-type laterally diffused metal-oxide-semiconductor (n-type LDMOS) nanosheet transistor 101. A p-type nanosheet LDMOS transistor comprising nanosheet region 116 is within the scope of this specification. In the example nanosheet transistor 101, the dopant of a first conductivity type is an n-type dopant, and the dopant of a second conductivity type is a p-type dopant. An example described herein is in which silicon is used as the semiconductor material for nanosheet layer 114, and SiGe is used as a sacrificial layer 115 initially present between nanosheet layers 114. Other examples within the scope of this specification may use other combinations of nanosheet layer 114 and sacrificial layer 115. For example, the roles of silicon and SiGe may be reversed, such that SiGe is used as the semiconductor material for nanosheet layer 114, and silicon is used as the sacrificial layer 115. Other combinations may also be used, in which materials can be formed in alternating layers, and one layer can be preferentially removed, leaving complete nanosheet layers 114.

[0020] Figure 1AAA top view of the microelectronic device 100 comprising nanosheet transistors 101 after its formation is shown. The top view shows a shallow trench isolation (STI) region 148 surrounding the nanosheet transistors 101. A nanosheet layer 114 is located between a source region 132 and a drain region 133. A p-type back gate region 160 is conductively connected to the source region 132. For clarity, during the successive formation stages for which the figures are provided, the figures may show a cross-section along the axis passing through the source region 132, or perpendicular to the axis between the source region 132 and the drain region 133, the axis of the first conductive layer 142 (hereinafter referred to as the gate conductor 142), the axis of the second conductive layer 157 (hereinafter referred to as the field conductor 157), and the axis of the nanosheet dielectric spacer 158.

[0021] refer to Figure 1AB and Figure 1AC A microelectronic device 100, including nanosheet transistors 101, is formed on and within a substrate wafer 102, such as a silicon wafer. The substrate wafer 102 may have a second conductivity type, which in this example may be p-type, such as... Figure 1AB and Figure 1AC As indicated. In an alternative version of this example, the substrate wafer 102 may contain a dielectric material, such as silicon dioxide or sapphire, to provide a silicon-on-insulator substrate. A semiconductor material 103 is formed on the substrate wafer 102. The semiconductor material 103 primarily comprises silicon and may consist essentially of silicon and dopants (e.g., boron), and may have a second conductivity type, i.e., p-type. The semiconductor material 103 may be formed by an epitaxial process, and as an example, may be 5 µm to 15 µm. The semiconductor material 103 extends to a top surface 107. The substrate wafer 102 and the semiconductor material 103 form a substrate 104.

[0022] A buried layer 105 may be formed in the substrate 104, extending into both the substrate wafer 102 and the semiconductor material 103. The buried layer 105 has a first conductivity type opposite to the second conductivity type. In this example, the first conductivity type is n-type. The buried layer 105 can be formed by implanting a dopant of the first conductivity type, such as phosphorus, arsenic, or antimony, into the substrate wafer 102 prior to the formation of the semiconductor material 103. The substrate wafer 102 may be annealed prior to the formation of the semiconductor material 103, and the semiconductor material 103 may subsequently be formed by an epitaxial process involving the thermal decomposition of silane, during which the dopant of the first conductivity type diffuses deeper into the substrate wafer 102 and into the semiconductor material 103, thereby forming the buried layer 105.

[0023] A deep well 106 may be formed in a semiconductor material 103, extending from the top surface 107 of the substrate 104 to the buried layer 105. The deep well 106 may have a first conductivity type, in this example n-type. The deep well 106 may be formed by implanting a dopant of the first conductivity type, such as phosphorus, into the semiconductor material 103, followed by thermal driving to diffuse the implanted dopant into the buried layer 105 and activate the implanted dopant. The deep well 106 may have an average concentration of the first conductivity type dopant that is at least 2 to 10 times greater than the average concentration of the second conductivity type dopant in the semiconductor material 103 outside the deep well 106. The deep well 106 provides isolation between the nanosheet transistor 101 and other components of the microelectronic device 100. The deep well 106 may preferably be degenerate-doped to achieve low leakage between the nanosheet transistor 101 and other components of the microelectronic device 100.

[0024] refer to Figure 1AD and Figure 1AE The image shows a cross-section after the formation of the nanosheet superlattice trench 112. After forming the buried layer 105 and the deep well 106, a first pad oxide layer 108 can be formed on the top surface 107 of the substrate 104. As an example, the first pad oxide layer 108 may primarily comprise silicon dioxide, can be formed by a thermal oxidation process or a thermochemical vapor deposition (CVD) process, and may have a thickness of 5 nm to 200 nm. A first hard mask layer 109 can be formed on the first pad oxide layer 108. The first hard mask layer 109 may comprise a material layer primarily composed of silicon nitride and a material layer primarily composed of silicon dioxide. The first hard mask layer 109 may have a thickness of 50 nm to 3 µm, depending on the depth of the nanosheet superlattice trench 112. The first pad oxide layer 108 can provide stress relief between the semiconductor material 103 and the first hard mask layer 109. The silicon nitride portion of the first hard mask layer 109 can provide a stop layer for subsequent etching and planarization processes. The silicon dioxide layer of the first hard mask layer 109 can provide a hard mask during superlattice trench etching 111 to form nanosheet superlattice trenches 112. A superlattice trench photomask (not specifically shown) can be formed on the first hard mask layer 109 having openings that expose the first hard mask layer 109 in the region for the nanosheet superlattice trenches 112.

[0025] Superlattice trench etching 111 forms nanosheet superlattice trenches 112 in substrate 104. Superlattice trench etching 111 may include multiple steps. After superlattice trench etching 111, the superlattice trench photomask is removed. After removing the superlattice trench photomask, superlattice trench dielectric sidewalls 113 are formed. Superlattice trench dielectric sidewalls 113 are formed by depositing a capping layer of dielectric material such as silicon dioxide or silicon nitride, followed by anisotropic etching (neither process is specifically shown). Anisotropic etching leaves superlattice trench dielectric sidewalls 113, which prevent the formation of processes (see process) in nanosheet region 116. Figure 1AF to 1AI Silicon or silicon-germanium is deposited during this period. After the formation of the superlattice trench dielectric sidewalls 113, there is no dielectric material on the horizontal surface of the nanosheet superlattice trench 112.

[0026] refer to Figure 1AF and Figure 1AG The image shows a cross-section after the formation of the first layer of nanosheet regions 116, consisting of sacrificial layer 115 and nanosheet layer 114. The first layer of nanosheet regions 116 can be formed by epitaxial deposition or atomic layer deposition (ALD) to produce a silicon-germanium alloy layer, referred to herein as sacrificial layer 115. Sacrificial layer 115 may have a thickness in the range of about 10 nm to about 200 nm, but other thicknesses are conceivable. Sacrificial layer 115 is etched away during subsequent processing.

[0027] After depositing the sacrificial layer 115, a nanosheet dielectric spacer 158 is formed in the sacrificial layer 115 between the source region 132 and the drain region 133. Figure 1AA (As shown in the top view of the reference). The formation of the nanosheet dielectric spacer 158 includes: a photolithography step to form a nanosheet dielectric spacer resist pattern; a nanosheet dielectric spacer etching process to remove the sacrificial layer 115 in the exposed areas of the nanosheet dielectric resist pattern, thereby forming a nanosheet dielectric spacer trench; deposition of a dielectric film filling the nanosheet dielectric spacer trench, followed by a planarization process, such as an etch-back process, to remove the dielectric material on the horizontal portion of the sacrificial layer 115 while leaving the nanosheet dielectric material in the nanosheet dielectric trench, thereby forming the nanosheet dielectric spacer 158 (the formation process of the nanosheet dielectric spacer 158 is not specifically shown). The nanosheet dielectric spacer 158 may be silicon dioxide, silicon nitride, silicon oxynitride, or other similar dielectric materials.

[0028] After the nanosheet dielectric spacer 158 is formed, a first nanosheet layer 114 can be formed on the sacrificial layer 115 by epitaxial deposition or ALD. The nanosheet layer 114 may have a thickness in the range of about 10 nm to about 200 nm, but other thicknesses are conceivable. After the sacrificial layer 115 is removed during subsequent processing, the nanosheet layer 114 is retained as the nanosheet layer 114 of the nanosheet transistor 101.

[0029] refer to Figure 1AH and Figure 1AI The processes of forming the sacrificial layer 115, the nanosheet dielectric spacer 158, and the nanosheet layer 114 are repeated twice to produce a stack consisting of three pairs of alternating sacrificial layers 115 and nanosheet layers 114, with one nanosheet dielectric spacer 158 within each sacrificial layer 115. Nanosheet regions 116 having more or fewer nanosheet layers than the example nanosheet transistor 101 are within the scope of this specification. After forming the nanosheet regions 116, the superlattice trench dielectric sidewalls 113 are removed.

[0030] Drain drift region 117 is formed in a portion of substrate 104 and nanosheet region 116, and subsequently surrounds Figure 1AT The drain region 133 mentioned above. One or more n-type implantations are performed to form a drain drift region 117 (which may be referred to as an n-drift region) in the substrate 104. The n-type dopant defining the n-drift region 117 may be implanted in one or more steps. For example, phosphorus may be implanted in a certain dose such that each nanosheet 114 receives approximately 1 × 10⁻⁶. 12 cm -2 From approximately 1 × 10 13 cm -2 The dosage and energy are suitable for forming the drain drift region 117 with or without subsequent thermal cycling. Arsenic can also be implanted at a similar dosage, but with a relatively higher energy than phosphorus implantation. The drain drift region 117 has an average doping concentration that is less than that of the drain region 133.

[0031] p-type well region 118 is formed in a portion of substrate 104 and nanosheet region 116, and subsequently surrounds Figure 1AT The source region 132 mentioned above. One or more p-type implantations are performed to form a p-type well region 118 in the substrate 104. The p-type dopant defining the p-type well region 118 can be implanted in one or more steps. For example, boron can be 1 × 10⁻⁶. 12 cm -2 With 1 × 10 13 cm -2 The total dose injected is sufficient to form a p-type well region 118 with or without subsequent thermal cycling. The p-type well region 118 can also receive a higher injection dose that is not depleted under reverse bias and is high enough to suppress source / drain leakage in the off state. Furthermore, the p-type well region 118 may be overdoped and unsuitable for p-type nanosheet LDMOS transistors (not specifically shown); if so, p-type drift injection may be required.

[0032] refer to Figure 1AJ and Figure 1AKThe image shows a cross-section after the deposition of dielectric layer 119. Dielectric layer 119 forms a dielectric gap fill between nanosheet region 116 and substrate 104.

[0033] refer to Figure 1AL and Figure 1AM The image shows a cross-section after the dielectric layer 119 outside the superlattice sidewall trenches has been removed by the chemical mechanical polishing (CMP) process 120. The dielectric layer 119 serves as a gap filler between the nanosheet region 116 and the substrate 104. After the CMP process 120, the first hard mask layer 109 is removed.

[0034] refer to Figure 1AN and Figure 1AO This diagram shows a cross-section after source / drain trench etch 163 forms source trench 123 and drain trench 124. First, a second pad oxide layer 121 and a second hard mask layer 122 are formed, followed by the formation of a source / drain photolithography pattern 162. After forming the source / drain photolithography pattern 162, a multi-step etching process is used to etch the second hard mask layer 122, the second pad oxide layer 121, and the nanosheet region 116 in the open regions of the source / drain photolithography pattern 162. After forming source trench 123 and drain trench 124, a p-type body photolithography pattern (not specifically shown) is formed, and p-type dopant is implanted in the regions below the sides and bottom of the source trench 123 using angled implantation (not specifically shown) to surround the source trench 123 and form a p-type body region 125. After forming the p-type body region 125, the p-type body region photolithographic pattern is removed, and an n-type buffer photolithographic pattern (not specifically shown) is formed. Then, n-type dopant is implanted at an angle (not specifically shown) along the sides and bottom of the drain trench 124 in the region surrounding the drain trench 124 to form the n-type buffer 126. After forming the n-type buffer 126, the n-type buffer photolithographic pattern is removed. Alternatively, in some cases, plasma doping can be used to implant dopant and form the p-type body region 125 and the n-type buffer 126.

[0035] refer to Figure 1 AP and Figure 1AQ The image shows a cross-section after the inner spacer dielectric material 128 has been deposited via an inner spacer plasma deposition process 129. After forming the p-type body region 125 and the n-type buffer zone 126, a portion of the sacrificial layer 115 is removed using selective isotropic SiGe etching—plasma etching or wet etching (not specifically shown)—to form an inner spacer recess 127 near the sidewalls of the p-type body region 125 and the n-type buffer zone 126. Following the formation of the inner spacer recess 127, a conformal layer of the inner spacer dielectric material 128 is formed. The inner spacer dielectric material 128 is a conformal dielectric layer filling the inner spacer recess 127.

[0036] refer to Figure 1AR and Figure 1AS The image shows a cross-section after the inner spacer dielectric material etching 130. The inner spacer dielectric material etching 130 is an anisotropic etching that removes the inner spacer dielectric material 128 from the top surface of the second hard mask layer 122 and from regions inside the source trench 123 and drain trench 124. The inner spacer dielectric material 128 remains in the inner spacer recess 127 region, where a portion of the sacrificial layer 115 of the source trench 123 and drain trench 124 has previously been removed.

[0037] refer to Figure 1AT and Figure 1AU This shows a cross-section after the formation of the source region 132 and drain region 133 in the polysilicon trench CMP process 131. Figure 1AR and 1AS Following the inner spacer dielectric material 128 mentioned above, n-type polysilicon deposition (not specifically shown) fills the source trench 123 and drain trench 124 with n-type polysilicon. The n-type silicon deposition filling the source trench 123 and drain trench 124 can also be epitaxial deposition. A polysilicon trench CMP process 131 is used to remove the polysilicon outside the source trench 123 and drain trench 124. After the polysilicon trench CMP process 131, the second hard mask layer 122 and the second pad oxide layer 121 are removed. After the polysilicon CMP process 131 is completed, p-type in-situ polysilicon deposition can be used to repeat the process. Figures 1AN to 1AU A process similar to that shown is used to form p-type regions, such as p-type back gate region 160 (in Figure 1AT and Figure 1AU Outside the plane, but Figure 1AA (As mentioned in the text). The p-type back gate region 160 is then electrically connected to the source region 132 via contacts and interconnects or via common silicide connections (neither of which are specifically shown).

[0038] refer to Figure 1AV This shows a cross-section after the formation of the gate trench 139. During the formation... Figures 1AN to 1AU After the source region 132 and drain region 133 mentioned above, a third pad oxide 135 and a third hard mask 136 are formed. A gate trench photomask 137 is patterned on the third hard mask 136. A multi-step gate trench etching 138 removes the third hard mask 136, the third pad oxide 135, and the nanosheet region 116 from the area exposed by the gate trench photomask 137, thereby forming a gate trench 139. After forming the gate trench 139, the gate trench photomask 137 is removed.

[0039] refer to Figure 1AWThe image shows a cross-section after the formation of the field trench 159. After forming the gate trench 139, a field trench photomask 165 is patterned on a third hard mask 136. A multi-step field trench etching 166 removes the third hard mask 136, the third pad oxide 135, and the nanosheet region 116 from the area exposed by the field trench photomask 165, thereby forming the field trench 159. After forming the field trench 159, the field trench photomask 165, the third hard mask 136, and the third pad oxide 135 are removed.

[0040] refer to Figure 1AX and Figure 1AY The image shows a cross-section after a plasma etching or wet etching process that selectively removes the sacrificial layer 115 of the nanosheet region 116 between the source region 132 and the drain region 133, leaving superlattice voids 140 with adjacent nanosheet layers 114. The superlattice voids 140 allow the nanosheet layers 114 to be suspended above the substrate 104 by attachment to the source region 132 and the drain region 133. After removal of the sacrificial layer 115, a cleanup process involving supercritical CO2 can be used to remove residues.

[0041] refer to Figure 1AZ , Figure 1BA and Figure 1BB The diagram shows a cross-section after the formation of a contact nanosheet layer 114 dielectric layer 141, referred to herein as nanosheet dielectric layer 141, a gate conductor 142 contacting the nanosheet dielectric layer 141, and a field conductor 157 also contacting the nanosheet dielectric layer 141, following an oxidation process and a polysilicon deposition process (sometimes not specifically shown). The nanosheet dielectric layer 141 can be based on silicon dioxide, silicon dioxide nitride, a metal gate, or other suitable dielectric materials used in semiconductor applications. Figure 1AZ , Figure 1BA and Figure 1BB In the example shown, a single polysilicon deposition is used to form the gate conductor 142 and the field conductor 157, but they are labeled as gate conductor 142 and field conductor 157 because they will become electrically isolated from each other during later processing. Nanosheet dielectric spacers 158 provide electrical isolation between the gate conductor 142 and the field conductor 157 between the nanosheet layers 114. The isolation of the polysilicon on the top surface 107 of the nanosheet transistor 101 between the gate conductor 142 and the field conductor 157 is achieved through… Figure 1BGThe process is achieved using the polysilicon etching technique mentioned above. The nanosheet dielectric layer 141 can be formed by the thermal oxidation of the nanosheet layer 114, thereby forming a continuous sheath around each nanosheet layer 114 between the source region 132 and the drain region 133. Polysilicon deposition fills the superlattice voids 140, the gate trench 139, and the field trench 159, and forms a continuous layer on the nanosheet region 116.

[0042] refer to Figure 1BC and Figure 1BD The image shows a cross-section after isolation trench 146 has been formed by isolation trench etching 145. To form isolation trench 146, a fourth hard mask 143 is formed on the gate conductor 142 and the field conductor 157. After forming the fourth hard mask 143, an isolation trench photomask 144 is formed. Isolation trench etching 145 forms isolation trench 146 in the open region of isolation trench photomask 144 by etching portions of the fourth hard mask 143, gate conductor 142, field conductor 157, nanosheet dielectric layer 141, source region 132, drain region 133, and nanosheet region 116. Isolation trench etching 145 also etches into the semiconductor material 103 and stops. After isolation trench etching 145, isolation trench photomask 144 is removed. The fourth hard mask 143 remains in place as a reference for... Figure 1BE and Figure 1BF The etching stop component mentioned in the subsequent STI CMP process 147.

[0043] refer to Figure 1BE and Figure 1BF This shows a cross-section after the shallow STI region 148 has been formed in the STI CMP process 147. This is achieved by first placing a fourth hard mask 143 in the isolation trench 146 and then the nanosheet transistor 101 (see [link]). Figure 1BC and Figure 1BD A layer of silicon dioxide or a similar dielectric material is formed on the isolation trench 146 to form the STI region 148. For example, high-density plasma (HDP) deposition or high aspect ratio plasma (HARP) technology can be used to fill the isolation trench 146. An STI CMP process 147 can be used to remove excess dielectric material outside the isolation trench 146, thereby leaving the STI region 148 in the isolation trench 146. The STI region 148 isolates the nanosheet layer 114, source region 132, and drain region 133 from the nanosheet region 116 retained between the STI region 148 and the dielectric layer 119. After the STI CMP process 147, a phosphoric acid chemical is used to remove the excess dielectric material. Figure 1BC and Figure 1BD The fourth hard mask 143 mentioned in the text Figure 1BE and Figure 1BF (Not specifically shown in the text), and HF-based chemicals were used to achieve the specified final profile of STI region 148.

[0044] refer to Figure 1BG and Figure 1BH The image shows a cross-section after plasmonic etching 150 of the gate and field conductors. A gate and field conductor photomask 149 is formed on the gate conductor 142 and field conductor 157. After forming the gate and field conductor photomask 149, plasmonic etching 150 removes the gate conductor 142, field conductor 157, and nanosheet dielectric layer 141 from the open regions of the photomask 149, thereby providing electrical isolation between the gate conductor 142 and the field conductor 157 at the top surface 107 of the nanosheet transistor 101. A nanosheet dielectric spacer 158 provides electrical isolation between the gate conductor 142 and the field conductor 157 in the region between the nanosheet layers 114. After plasmonic etching 150, the gate and field conductor photomask 149 is removed.

[0045] After removing the photomask 149 of the gate and field conductors, sidewall spacers (not specifically shown) can be formed on the vertical surfaces of the gate conductor 142 and the field conductor 157, and the sidewall spacers can extend from the lateral edges of the gate conductor 142 and the field conductor 157 by 50 nm to 200 nm. The sidewall spacers prevent the subsequent formation of silicide on the vertical surfaces of the silicon-containing region below the gate conductor 142, the field conductor 157, and the sidewall spacers.

[0046] Figure 1 BI and Figure 1BJ A cross-section of the nanosheet transistor 101 after the formation of the first-level interconnect 156 is shown. A metal silicide layer (not specifically shown) may be formed in the source region 132, drain region 133, and p-type back gate region 160 (in...). Figure 1 BI and Figure 1BJ Outside the plane of the cross-section shown, refer to Figure 1AA The metal silicide layer is located on the exposed portions of the gate conductor 142 and the field conductor 157. Compared to similar microelectronic devices without a metal silicide layer, the metal silicide layer can provide ohmic electrical connections with the source region 132, drain region 133, p-type back gate region 160, gate conductor 142, and field conductor 157 with lower resistance.

[0047] A metal-front dielectric (PMD) layer 151 is formed on the top surface 107 of the substrate 104. The PMD layer 151 may comprise one or more dielectric layers, such as silicon nitride, silicon oxynitride, and silicon dioxide. In some examples, the PMD layer 151 comprises a PMD liner and a main dielectric layer formed on the PMD liner. The PMD layer 151 may then be planarized using a CMP process (not specifically shown). Source contacts 152, gate contacts 154, field plate contacts 155, and drain contacts 153 may be formed in the PMD layer 151 using tungsten plugs or other suitable methods to form electrical connections to interconnects 156. Interconnects 156 are formed over the PMD layer 151 using any suitable metallization scheme and provide electrical contacts between the nanosheet transistor 101 and other components of the microelectronic device 100.

[0048] Figure 2A This is a top view representation of a microelectronic device 200 including a nanosheet transistor 201, which comprises multiple field plates, in this case a first field plate conductor 257A in a first field plate region 261A, a second field plate conductor 257B in a second field plate region 261B, and a gate conductor 242 in a gate region 268. More than one field plate can be used in the off-state to distribute the potential drop of the source region 232 into a smaller potential drop, which increases the more progressive monotonic voltage drop from the drain region 233 to the source region 232, and therefore, more ideally, enables a shorter drift region for a given breakdown voltage. The general fabrication process of the nanosheet transistor 201 is similar to... Figures 1AA to 1BJ The nanosheet transistor 101 mentioned above. The nanosheet transistor 201 includes a source region 232, a drain region 233, and a back gate region 260. (The last sentence appears to be incomplete and possibly refers to a different topic.) Figure 1AA Unlike the nanosheet transistor 101 mentioned earlier, the nanosheet transistor 201 includes a first nanosheet dielectric spacer 258A, a first field plate conductor 257A, a second nanosheet dielectric spacer 258B, and a second field plate conductor 257B. Although the example microelectronic device 200 includes the first nanosheet dielectric spacer 258A, the second nanosheet dielectric spacer 258B, the first field plate conductor 257A, and the second field plate conductor 257B, the nanosheet transistor 201 with additional dielectric spacers and field plates is also within the scope of this specification. Figure 2A The additional components include an STI isolation region 248 and a portion of a nanosheet layer 214 visible in the top view.

[0049] Figure 2B yes Figure 2AThe cross-section of the nanosheet transistor 201 shown is illustrated. The nanosheet transistor includes a first nanosheet dielectric spacer 258A, a second nanosheet dielectric spacer 258B, a first field plate region 261A, and a second field plate region 261B. The nanosheet transistor 201 includes a nanosheet region 216 of a nanosheet layer 214 between a source region 232 and a drain region 233. A nanosheet dielectric layer 241 surrounds the nanosheet layer 214 and provides electrical isolation between the gate conductor 242 and the nanosheet layer 214, as well as electrical isolation between the first field plate conductor 257A, the second field plate conductor 257B, and the nanosheet layer 214. The first nanosheet dielectric spacer 258A and the second nanosheet dielectric spacer 258B are located between the source region 232 and the drain region, and between vertically adjacent nanosheet layers 214. The gate conductor 242 between the source region 232 and the first nanosheet dielectric spacer 258A is situated within the gate region 268. The first field plate conductor 257A is located between the first nanosheet dielectric spacer 258A and the second nanosheet dielectric spacer 258B in the first field plate region 261A. The second field plate conductor 257B is located between the second nanosheet dielectric spacer 258B and the drain region 233 in the second field plate region 261B.

[0050] Other components of the nanosheet transistor 201 include a substrate wafer 202, a silicon layer 203, a substrate 204, an n-type buried layer 205, a deep well 206, a top surface 207 of the substrate 204, an n-type drift region 217, a p-type well region 218, a superlattice trench filler 219, a p-type body region 225, an n-type buffer 226, an inner spacer dielectric material 228, an isolation region 248, a metal front dielectric material 251, a source contact 252, a drain contact 253, a gate contact 254, a first field plate contact 255A, a second field plate contact 255B, and a metallide 256.

[0051] Figure 3A This is a top view of a microelectronic device 300 comprising a nanosheet transistor 301 having multiple nanosheet transistor fingers. While the example nanosheet transistor 301 has three nanosheet transistor fingers, namely, a first nanosheet transistor finger 369A, a second nanosheet transistor finger 369B, and a third nanosheet transistor finger 369C, nanosheet transistors 301 having fewer or more than three nanosheet transistor fingers are also within the scope of this specification. The general fabrication process of the nanosheet transistor 301 is similar to... Figures 1AA to 1BJ The nanosheet transistor 101 mentioned above includes a source region 332, a drain region 333, a back gate region 360, a gate region 368, a field plate region 361, and a nanosheet dielectric spacer 358 between the gate region 368 and the field plate region 361. Figure 1AAUnlike the nanosheet transistor 101 mentioned above, the nanosheet transistor 301 includes multiple gate trenches 339 and field plate trenches 359 between the source region 332 and the drain region 333, such that the nanosheet transistor fingers (369A, 369B or 369C) that contact the source region 332 and the drain region 333 are respectively located between a pair of gate trenches 339 in the gate region 368 and a pair of field plate trenches 359 in the field plate region 361. Figure 3A The additional components include an STI isolation region 348 and a portion of a nanosheet layer 314 visible in the top view.

[0052] Figure 3B yes Figure 3A A cross-section of a microelectronic device 300 containing nanosheet transistors 301 is shown, illustrating multiple gate trenches 339 and three nanosheet transistor fingers (369A, 369B, and 369C). The gate trenches 339 extend from the top surface 307 to a point beneath the nanosheet layer 314 in the p-type well region 318. The nanosheet layer 314 of each finger (369A, 369B, and 369C) is surrounded by a nanosheet dielectric layer 341 on the nanosheet layer 314, and a gate conductor 342 is located on the nanosheet dielectric layer 341. The gate conductor 342 fills the spaces between all the nanosheet layers 314 and the gate trenches 339 between the nanosheet layers 314. Nanosheet dielectric spacers 358 are present in... Figure 3B The cross-sectional view shown is outside the plane.

[0053] The additional components of the nanosheet transistor 301 include a substrate wafer 302, a silicon layer 303, a substrate 304, an n-type buried layer 305, a deep well 306, an unremoved region of the original silicon-germanium layer 315 outside the STI isolation region 348, a superlattice trench filler 319, a metal front dielectric material 351, a gate contact 354, and a metallization 356.

[0054] Figure 3C yes Figure 3A The cross-section of the microelectronic device 300 shown in the figure has nanosheet transistors 301 comprising nanosheet dielectric spacers 358 and a plurality of nanosheet transistor fingers. Figure 3CThe cross-section is along the plane between the source region 332, the drain region 333, and the second nanosheet transistor finger 369B. The nanosheet transistor 301 includes a nanosheet region 316 of the nanosheet layer 314 between the source region 332 and the drain region 333. A nanosheet dielectric layer 341 surrounds the nanosheet layer 314 and provides electrical isolation between the gate conductor 342 and the nanosheet layer 314, as well as electrical isolation between the field plate conductor 357 and the nanosheet layer 314. Nanosheet dielectric spacers 358 are located between the field plate region 361 and the gate region 368, between the nanosheet layers 314, and are vertically adjacent to each other. The gate conductor 342 is on the nanosheet dielectric layer 341, between the source region 332 and the nanosheet dielectric spacer 358, and fills the gaps between the nanosheet layers 314 and the region on the top surface 307 of the nanosheet transistor 301 located within the gate region 368. The field plate conductor 357 is on the nanosheet dielectric layer 341, between the nanosheet dielectric spacer 358 and the drain region 333, and fills the gaps between the nanosheet layers 314 and the area on the top surface 307 of the nanosheet transistor 301 located in the field plate region 361.

[0055] Other components of the nanosheet transistor 301 include a substrate wafer 302, a silicon layer 303, a substrate 304, an n-type buried layer 305, a deep well 306, a top surface 307 of the substrate 304, an n-type drift region 317, a p-type well region 318, a superlattice trench filler 319, a p-type body region 325, an n-type buffer zone 326, an inner spacer dielectric material 328, an STI isolation region 348, a metal front dielectric material 351, a source contact 352, a drain contact 353, a gate contact 354, a field plate contact 355, and a metallide 356.

[0056] Figure 4A This is a top view of a microelectronic device 400 comprising a nanosheet transistor 401, which includes a first nanosheet dielectric spacer 458A, a second nanosheet dielectric spacer 458B, and a third nanosheet dielectric spacer 458C between a source region 432 and a drain region 433. Multiple dielectric spacers or larger dielectric spacers allow for the use of a smaller field plate region 461 along the drain drift region 417 for a given field plate spacing. This reduces the electric field stress between the field plate conductor 457 and the surrounding nanosheet layer 414, because in the off state, the potential in the nanosheet layer 414 will monotonically decrease, while the field plate conductor 457, made of the same material as the gate conductor 442, is at a single potential. Therefore, a region with a higher field can appear between the corner of the field plate conductor 457 and the nanosheet layer 414 closest to it.

[0057] The general fabrication process of the nanosheet transistor 401 is similar to... Figures 1AA to 1BJThe nanosheet transistor 101 mentioned herein is formed. The nanosheet transistor 401 includes a source region 432, a drain region 433, and a back gate region 460. Although the example microelectronic device 400 includes three nanosheet dielectric spacers 458A, 458B, and 458C, nanosheet transistors 401 with fewer or additional nanosheet dielectric spacers are also within the scope of this specification. Figure 4A The additional components include STI isolation element 448, a portion of nanosheet layer 414, field conductor 457 in field region 461, and gate conductor 442 in gate region 468.

[0058] Figure 4B This is a cross-section of a nanosheet transistor 401 comprising three nanosheet dielectric spacers 458A, 458B, and 458C. The nanosheet transistor 401 includes a nanosheet region 416 of a nanosheet layer 414 between a source region 432 and a drain region 433. A nanosheet dielectric layer 441 surrounds the nanosheet layer 414 and provides electrical isolation between the gate conductor 442 and the nanosheet layer 414, as well as electrical isolation between the field plate conductor 457 and the nanosheet layer 414. Between the nanosheet layers 414, the first nanosheet dielectric spacer 458A and the second nanosheet dielectric spacer 458B are located between the gate region 468 and the field plate region 461, and the third nanosheet dielectric spacer 458C is located between the field plate region 461 and the drain region 433. The gate conductor 442 between the source region 432 and the first nanosheet dielectric spacer 458A is located on the nanosheet dielectric layer 441. The field conductor 457 is located between the second nanosheet dielectric spacer 458B and the third nanosheet dielectric spacer 458C, and on the nanosheet dielectric layer 441. The sacrificial layer 415 is retained between the third nanosheet dielectric spacer 458C and the inner spacer dielectric material 428, and between the first nanosheet dielectric spacer 458A and the second nanosheet dielectric spacer 458B, because these regions are not... Figure 1AV to Figure 1AY The field trench 159 or gate trench 139 mentioned above are in contact, therefore the sacrificial layer 415 is not removed. The gate region 468 and the field region 461 are electrically isolated from each other by the first nanosheet dielectric spacer 458A and the second nanosheet dielectric spacer 458B.

[0059] Other components of the nanosheet transistor 401 include a substrate wafer 402, a silicon layer 403, a substrate 404, an n-type buried layer 405, a deep well 406, a top surface of the substrate 407, a drain drift region 417, a p-type well region 418, a superlattice trench filler 419, a p-type body region 425, an n-type buffer 426, an inner spacer dielectric material 428, an STI isolation region 448, a metal front dielectric material 451, a source contact 452, a drain contact 453, a gate contact 454, a field plate contact 455, and a metallide 456.

[0060] While various examples of the specification have been described above, these examples are presented by way of illustration and not limitation. Therefore, although the foregoing examples are described as using various resist layers (e.g., photoresist or photomask layers) to perform various process steps (e.g., implantation or etching steps), this specification is not limited thereto. For example, one or more hard masks (comprising one or more layers) may be patterned to define various regions to which subsequent process steps are to be applied (e.g., regions for receiving dopant atoms, regions for blocking etchant). Furthermore, in some examples, the resist layer may comprise a multi-level resist rather than a single-level resist. Many changes may be made to the described examples based on the description herein without departing from the spirit or scope of this specification. Therefore, the breadth and scope of this specification are not limited by any of the foregoing examples. Rather, the scope of this specification is defined by the appended claims and their equivalents.

Claims

1. A microelectronic device comprising: A first doped semiconductor region and a second doped semiconductor region extend into a semiconductor substrate, the first doped semiconductor region and the second doped semiconductor region having a first conductivity type, and the semiconductor substrate having an opposite second conductivity type; A semiconductor layer that contacts the first doped semiconductor region and the second doped semiconductor region; A first conductive layer extends between the first doped semiconductor region and the second doped semiconductor region; A second conductive layer extends between the second doped semiconductor region and the first conductive layer; as well as A dielectric layer that contacts the semiconductor layer, the first conductive layer, and the second conductive layer.

2. The microelectronic device of claim 1, further comprising a dielectric spacer between and in contact with the first conductive layer and the second conductive layer.

3. The microelectronic device of claim 2, wherein the semiconductor layer is one of a first semiconductor layer and a second semiconductor layer connected between the first doped semiconductor region and the second doped semiconductor region, and the first conductive layer and the second conductive layer, the dielectric layer and the dielectric spacer are located between the first semiconductor layer and the second semiconductor layer.

4. The microelectronic device of claim 1, wherein the first doped semiconductor region is a source region and the second doped semiconductor region is a drain region, the source region and the drain region have a first average dopant concentration, and the microelectronic device further includes a drain drift region and a channel region, the drain drift region being in the semiconductor layer, having a first conductivity type and a lower second dopant concentration and extending from the drain region toward the source region, and the channel region being between the drain drift region and the source region, having the second conductivity type.

5. The microelectronic device of claim 4, further comprising a well region within the semiconductor layer and the semiconductor substrate, having the second conductivity type, surrounding the source region and extending from the source region toward the drain region.

6. The microelectronic device of claim 4, wherein the source region extends into a trench within the semiconductor substrate, and the microelectronic device further includes a body region having the second conductivity type along the sides and bottom of the trench.

7. The microelectronic device of claim 4, wherein the drain region extends into a trench within the semiconductor substrate, and the microelectronic device further includes a buffer having the first conductivity type along the sides and bottom of the trench.

8. The microelectronic device of claim 1, further comprising a gate trench extending into the semiconductor substrate, the gate trench being filled by the first conductive layer.

9. The microelectronic device of claim 1, further comprising a field plate trench extending into the semiconductor substrate, the field plate trench being filled by the second conductive layer.

10. The microelectronic device according to claim 3, further comprising: An inner spacer of dielectric material between the first semiconductor layer and the second semiconductor layer, the inner spacer electrically isolating the first conductive layer from the source region; And an inner spacer of dielectric material in the contact drain region between the first semiconductor layer and the second semiconductor layer, the inner spacer electrically isolating the second conductive layer from the drain region.

11. The microelectronic device of claim 1, wherein the semiconductor layer has a thickness greater than 10 nm.

12. A method of forming a microelectronic device, comprising: Trenches are formed in a semiconductor substrate having a first conductivity type; A semiconductor nanosheet stack is formed in the trench, the semiconductor nanosheet stack comprising a semiconductor layer and a sacrificial layer; Forming source and drain regions with opposite second conductivity types extending into the semiconductor nanosheet stack; Remove the sacrificial layer between the source region and the drain region; A dielectric spacer is formed between the source region and the drain region to contact the semiconductor layer; A dielectric layer is formed on the semiconductor layer; A first conductive layer is formed on the dielectric layer between the source region and the dielectric spacer; as well as A second conductive layer is formed on the dielectric layer between the drain region and the dielectric spacer.

13. The method of claim 12, wherein forming the semiconductor nanosheet stack comprises forming a first semiconductor layer and a second semiconductor layer, the sacrificial layer being located between the first semiconductor layer and the second semiconductor layer.

14. The method of claim 13, wherein forming the source region and the drain region comprises forming a source trench and a drain trench extending into the semiconductor nanosheet stack, and the method further comprises forming a recess in the sacrificial layer at the sidewalls of the source trench and the drain trench, and filling the recess with an inner spacer that electrically isolates the first conductive layer from the source region and the second conductive layer from the drain region.

15. The method of claim 13, wherein forming the drain region comprises forming a drain trench extending into the semiconductor nanosheet stack, and the method further comprises forming a buffer of the second conductivity type along the sidewall of the drain trench.

16. The method of claim 13, further comprising forming a drift region of the second conductivity type in the semiconductor nanosheet stack and the semiconductor substrate, the drift region extending from the drain region toward the source region.

17. The method of claim 13, further comprising forming a body region of the first conductivity type in the semiconductor nanosheet stack, the body region extending from the source region toward the drain region.

18. The method of claim 13, further comprising forming a well region of the first conductivity type in the semiconductor nanosheet stack and the semiconductor substrate, the well region surrounding the body region and the source region.

19. The method of claim 13, further comprising forming a first gate trench and a second gate trench extending through the semiconductor nanosheet stack, the first conductive layer extending from the first gate trench to the second gate trench.

20. The method of claim 13, further comprising forming a first field plate trench and a second field plate trench extending through the semiconductor nanosheet stack, the second conductive layer extending from the first field plate trench to the second field plate trench.

Images