LDMOS device and preparation method thereof

Abstract

The invention relates to the technical field of semiconductor devices, and discloses an LDMOS device and a preparation method thereof.The LDMOS device comprises a silicon substrate, a source region, a drain region, a gate region, a groove structure, an N-type drift region and a P-type well region, and the source region, the drain region, the gate region, the groove structure and the P-type well region are arranged in the N-type drift region on the silicon substrate; the trench structure is located between the source region and the drain region; the source region comprises a P-type heavily doped region and a first N-type heavily doped region and is arranged between the gate region and the drain region; the drain region comprises a second N-type heavily doped region; the gate region comprises a polycrystal structure and a first high dielectric constant insulating layer wrapping the polycrystal structure; the P-type well region is in contact with a source region arranged right above the P-type well region and is in contact with a gate region arranged right on the left side of the P-type well region, and a conducting channel is formed in the P-type well region under the condition that gate-source voltage is higher than starting voltage, so that the technical problem of how to improve the breakdown voltage of the device and reduce on resistance at the same time is solved.

Description

Technical Field

[0001] The present application relates to the technical field of semiconductor devices, and in particular to an LDMOS device and a method for preparing the same. Background Art

[0002] At present, with the continuous improvement of the integration of power integrated circuits, the requirements for various characteristics of circuits and devices are also getting higher and higher. Among RF power devices, LDMOS (laterally diffused metal oxide semiconductor field effect transistor) devices have shown excellent electrical characteristics such as high reliability and high linearity compared to other power devices, as well as the advantage of compatibility with traditional CMOS processes, which has become a research hotspot in the field of RF power devices. How to reduce the on-resistance of LDMOS devices and improve electrical characteristics such as breakdown voltage has become the focus of industry attention. The ability of the relevant power LDMOS to withstand high voltage when turned off is mainly determined by a certain length of lightly doped drift region. In order to increase the breakdown voltage of the device, it is necessary to increase the length of the drift region and reduce the doping concentration of the drift region, but this is somewhat contradictory to the design goal of reducing the on-resistance of the device. Summary of the invention

[0003] The present application provides an LDMOS device and a method for preparing the same, which solves the technical problem of how to increase the breakdown voltage of the device while reducing the on-resistance, thereby achieving the technical effect of increasing the integration of the device.

[0004] In order to achieve the above objectives, the main technical solutions adopted in this application include:

[0005] In a first aspect, an embodiment of the present application provides an LDMOS device, comprising a silicon substrate, a source region, a drain region, a gate region, a trench structure, an N-type drift region and a P-type well region, wherein: a source region, a drain region, a gate region, a trench structure and a P-type well region are provided in the N-type drift region on the silicon substrate; the trench structure is located between the source region and the drain region; the source region comprises a P-type heavily doped region and a first N-type heavily doped region, which are arranged between the gate region and the drain region; the drain region comprises a second N-type heavily doped region; the gate region comprises a polycrystalline structure and a first high dielectric constant insulating layer wrapping the polycrystalline structure; the P-type well region contacts the source region arranged directly above the P-type well region, and contacts the gate region arranged directly to the left of the P-type well region, and when the gate-source voltage is higher than the turn-on voltage, a conductive channel is formed in the P-type well region.

[0006] The LDMOS device provided in the embodiment of the present application includes a silicon substrate, a source region, a drain region, a gate region, a trench structure, an N-type drift region and a P-type well region, wherein: a source region, a drain region, a gate region, a trench structure and a P-type well region are provided in the N-type drift region on the silicon substrate; the trench structure is located between the source region and the drain region; the source region includes a P-type heavily doped region and a first N-type heavily doped region, which are provided between the gate region and the drain region; the drain region includes a second N-type heavily doped region; the gate region includes a polycrystalline structure and a first high dielectric constant insulating layer wrapping the polycrystalline structure; the P-type well region contacts the source region provided just above the P-type well region, and contacts the gate region provided just to the left of the P-type well region, and when the gate-source voltage is higher than the turn-on voltage, a conductive channel is formed in the P-type well region, thereby solving the technical problem of how to increase the breakdown voltage of the device while reducing the on-resistance, and achieving the technical effect of improving the integration of the device.

[0007] Optionally, the silicon substrate includes an SOI layer and a P-type epitaxial substrate, and the SOI layer is located between the N-type drift region and the P-type epitaxial substrate.

[0008] Optionally, the trench structure includes a low dielectric constant insulating layer and a silicon dioxide layer arranged sequentially from top to bottom.

[0009] Optionally, the outer side of the trench structure is wrapped with a second high dielectric constant insulating layer.

[0010] Optionally, the P-type well region extends along the sidewalls of the trench structure to the bottom of the trench structure.

[0011] Optionally, the LDMOS device further includes a plurality of P-type semiconductor blocks whose widths decrease successively along the source-drain direction, the plurality of P-type semiconductor blocks are arranged close to and directly below the P-type well region, and the bottoms of the P-type semiconductor blocks are in contact with the SOI layer.

[0012] Optionally, the LDMOS device further includes a third high dielectric constant insulating layer, which is disposed in the N-type drift region, electrically connected to the bottom of the drain region and extends toward the SOI layer.

[0013] Optionally, the electrode material in the source region, the drain region and the gate region is aluminum.

[0014] In a second aspect, an embodiment of the present application provides a method for preparing an LDMOS device, comprising the following steps: forming an N-type drift region on a silicon substrate; injecting ions into the N-type drift region to form a source region and a drain region, wherein the source region includes a P-type heavily doped region and a first N-type heavily doped region, the source region is arranged between the gate region and the drain region, and the drain region includes a second N-type heavily doped region; forming a trench structure in the N-type drift region, the trench structure being located between the source region and the drain region; forming a gate region in the N-type drift region, a polycrystalline structure being arranged on the gate region, and a first high dielectric constant insulating layer being wrapped around the polycrystalline structure; forming a P-type well region in the N-type drift region, the P-type well region being in contact with a source region arranged directly above the P-type well region, and in contact with a gate region arranged directly to the left of the P-type well region, and when the gate-source voltage is higher than the turn-on voltage, a conductive channel is formed in the P-type well region.

[0015] Optionally, the silicon substrate includes an SOI layer and a P-type epitaxial substrate, and an N-type drift region is formed on the SOI layer.

[0016] In a third aspect, an embodiment of the present application provides a computer device, comprising: a memory and a processor, wherein the memory and the processor are communicatively connected to each other, computer instructions are stored in the memory, and the processor executes the above-mentioned method for preparing the LDMOS device by executing the computer instructions.

[0017] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium, on which computer instructions are stored, and the computer instructions are used to enable a computer to execute the above-mentioned method for preparing the LDMOS device.

[0018] In a fifth aspect, an embodiment of the present application provides a computer program product, including computer instructions, wherein the computer instructions are used to enable a computer to execute the above-mentioned method for preparing the LDMOS device. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0020] Figure 1 A schematic diagram of the structure of an LDMOS device provided in an embodiment of the present application;

[0021] Figure 2 A flow chart of a method for preparing an LDMOS device provided in an embodiment of the present application;

[0022] Figure 3 A schematic diagram of the structure of a computer device provided in an embodiment of the present application.

[0023] Figure numerals: 1, source region; 1-1, P-type heavily doped region; 1-2, first N-type heavily doped region; 2, drain region; 2-1, second N-type heavily doped region; 3, gate region; 3-1, polycrystalline structure; 3-2, first high dielectric constant insulating layer; 4, trench structure; 4-1, low dielectric constant insulating layer; 4-2, silicon dioxide layer; 5, P-type well region; 5-1, P column; 6, N-type drift region; 7, SOI layer; 8, P-type epitaxial substrate; 9, P-type semiconductor block. DETAILED DESCRIPTION

[0024] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0025] At present, with the continuous improvement of the integration of power integrated circuits, the requirements for various characteristics of circuits and devices are also getting higher and higher. Among RF power devices, LDMOS (laterally diffused metal oxide semiconductor field effect transistor) devices have shown excellent electrical characteristics such as high reliability and high linearity compared to other power devices, as well as the advantage of compatibility with traditional CMOS processes, which has become a research hotspot in the field of RF power devices. How to reduce the on-resistance of LDMOS devices and improve electrical characteristics such as breakdown voltage has become the focus of industry attention. The ability of the relevant power LDMOS to withstand high voltage when turned off is mainly determined by a certain length of lightly doped drift region. In order to increase the breakdown voltage of the device, it is necessary to increase the length of the drift region and reduce the doping concentration of the drift region, but this is somewhat contradictory to the design goal of reducing the on-resistance of the device.

[0026] Trench LDMOS is an improved LDMOS device that improves device performance by introducing a trench structure in the drift region. The key point is to add a trench structure filled with low dielectric constant material in the drift region. This trench structure can deplete the drift region and optimize the body electric field distribution by vertically expanding the drift region, maintaining or even increasing the breakdown voltage without increasing the lateral area of ​​the device. The trench structure improves the current carrying capacity and does not require additional lateral space, effectively reducing the on-resistance per unit area of ​​the device, so that a smaller cell pitch can be achieved at the same voltage level, improving the device's integration and design flexibility.

[0027] Please refer to Figure 1 , Figure 1 This is a schematic diagram of the structure of the LDMOS device provided in the embodiment of the present application. Figure 1 As shown, an embodiment of the present application provides an LDMOS device, including a silicon substrate, a source region 1, a drain region 2, a gate region 3, a trench structure 4, an N-type drift region 6 and a P-type well region 5, wherein: a source region 1, a drain region 2, a gate region 3, a trench structure 4 and a P-type well region 5 are provided in the N-type drift region 6 on the silicon substrate; the trench structure 4 is located between the source region 1 and the drain region 2; the source region 1 includes a P-type heavily doped region 1-1 and a first N-type heavily doped region 1-2, which are provided between the gate region 3 and the drain region 2; the drain region 2 includes a second N-type heavily doped region 2-1; the gate region 3 includes a polycrystalline structure 3-1 and a first high dielectric constant insulating layer 3-2 wrapping the polycrystalline structure 3-1; the P-type well region 5 contacts the source region 1 provided directly above the P-type well region 5, and contacts the gate region 3 provided directly to the left of the P-type well region 5, and when the gate-source voltage is higher than the turn-on voltage, a conductive channel is formed in the P-type well region 5.

[0028] Specifically, the N-type drift region 6 is an N-doped region located between the source region 1 and the drain region 2, and is used to carry current and help disperse the electric field in high voltage applications. The trench structure 4 is located in the N-type drift region 6 between the source region 1 and the drain region 2. When the gate-source voltage is higher than the turn-on voltage, a conductive channel is formed in the P-type well region 5 directly to the right of the gate region 3, and electrons can be transported from the source region 1 to the drain region 2. The gate region 3 is located on the left side of the source region 1 and the P-type well region 5, and is used to control the process of the charge from the source region 1 to the drain region 2. The polycrystalline structure 3-1 in the gate region 3 is polycrystalline silicon, and the first high dielectric constant insulating layer 3-2 is wrapped outside the polycrystalline silicon. The polycrystalline silicon, the first high dielectric constant insulating layer 3-2 and the P-type well region 5 form a sandwich structure. The conductive channel formed in the P-type well region 5 is a vertical structure. When the gate region 3 is pressurized and the device is in the on state, the sandwich structure can be regarded as a capacitor, and a certain number of electrons are accumulated at the edge of the P-type well region 5 close to the first high dielectric constant insulating layer 3-2, thereby reducing the on-resistance of the conductive channel. At the same time, through the auxiliary depletion effect of the first high dielectric constant insulating layer 3-2, the doping concentration can be further increased, thereby reducing the on-resistance of the device.

[0029] The LDMOS device provided in the embodiment of the present application includes a silicon substrate, a source region 1, a drain region 2, a gate region 3, a trench structure 4, an N-type drift region 6 and a P-type well region 5, wherein: the N-type drift region 6 on the silicon substrate is provided with a source region 1, a drain region 2, a gate region 3, a trench structure 4 and a P-type well region 5; the trench structure 4 is located between the source region 1 and the drain region 2; the source region 1 includes a P-type heavily doped region 1-1 and a first N-type heavily doped region 1-2, which is located between the gate region 3 and the drain region 2; the drain region 2 includes a second N-type heavily doped region 1-2. Region 2-1; the gate region 3 includes a polycrystalline structure 3-1 and a first high dielectric constant insulating layer 3-2 wrapping the polycrystalline structure 3-1; the P-type well region 5 is in contact with the source region 1 located directly above the P-type well region 5, and is in contact with the gate region 3 located directly to the left of the P-type well region 5. When the gate-source voltage is higher than the turn-on voltage, a conductive channel is formed in the P-type well region 5, which solves the technical problem of how to increase the breakdown voltage of the device while reducing the on-resistance, and achieves the technical effect of improving the integration of the device.

[0030] In some embodiments, the silicon substrate includes an SOI layer 7 and a P-type epitaxial substrate 8 , and the SOI layer 7 is located between the N-type drift region 6 and the P-type epitaxial substrate 8 .

[0031] Among them, the P-type epitaxial substrate 8 refers to a semiconductor substrate doped with excess positive charge carriers (i.e., holes). Compared with the N-type substrate, the P-type substrate has different electron flow properties. In the P-type substrate, the main carriers are holes, not free electrons. SOI (Silicon on Insulator) is a semiconductor manufacturing technology, the core feature of which is to manufacture a single crystal silicon film on an insulating layer (usually silicon dioxide). In the embodiment of the present application, the SOI layer 7 is located between the N-type drift region 6 and the P-type epitaxial substrate 8. The ordinary SOI structure is composed of silicon dioxide. Due to the difference in dielectric constants, the electric field of the contact surface with silicon (N-type drift region 6) is changed, which can effectively deplete the bottom area of ​​the trench structure 4 of the device, thereby improving the lateral withstand voltage and doping concentration, and reducing the on-resistance. Due to the characteristics of the SOI material itself, its withstand voltage capability exceeds that of silicon (N-type drift region 6), so the longitudinal breakdown voltage of the device can be further improved.

[0032] In some embodiments, the trench structure 4 includes a low dielectric constant insulating layer 4 - 1 and a silicon dioxide layer 4 - 2 disposed sequentially from top to bottom.

[0033] Specifically, the trench structure 4 is composed of a low dielectric constant insulating layer 4-1 and a silicon dioxide layer 4-2, and the area occupied by the trench structure 4 is adjustable, thereby improving the withstand voltage and doping concentration on both sides of the trench structure 4, thereby reducing the on-resistance of the device.

[0034] In some embodiments, the outer side of the trench structure 4 is wrapped with a second high dielectric constant insulating layer.

[0035] Among them, at the junction of the low dielectric constant insulating layer 4-1 and the silicon dioxide layer 4-2 filled in the groove structure 4, due to the difference in dielectric constant, an electric field peak will be caused at the corresponding positions on both sides of the groove structure 4. A second high dielectric constant insulating layer is wrapped on the side wall and bottom wall of the groove structure 4. At this time, the source region 1, the conductive channel and the second high dielectric constant insulating layer can be regarded as a field plate structure, which is used to reduce the electric field concentration and optimize the electric field distribution. The second high dielectric constant insulating layer wrapping the groove structure 4 can effectively alleviate the electric field concentration phenomenon in the groove structure 4 due to its high dielectric constant, thereby further depleting the drift region. By wrapping the second high dielectric constant insulating layer on the outside of the groove structure 4, the withstand voltage of the N-type drift region 6 can be effectively improved, and the doping concentration of the N-type drift region 6 can be further increased, thereby reducing the on-resistance of the device.

[0036] In some embodiments, the P-type well region 5 extends along the sidewall of the trench structure 4 to the bottom of the trench structure 4 .

[0037] For example, the P-type well region 5 is attached to the outer side of the second high dielectric constant insulating layer wrapping the trench structure 4 and extends toward the bottom of the trench structure 4 to form a P column 5-1. The P column 5-1 located on the left side of the trench structure 4 can attract more electric flux near the P column 5-1 and absorb the electric flux flowing through the second high dielectric constant insulating layer, so that the electric field peak near the P column 5-1 is reduced, thereby preventing the electric field concentration in this area from causing avalanche breakdown.

[0038] In some embodiments, the LDMOS device further includes a plurality of P-type semiconductor blocks 9 whose widths decrease successively along the source-drain direction. The plurality of P-type semiconductor blocks 9 are arranged close to and directly below the P-type well region 5 , and the bottom of the P-type semiconductor block 9 contacts the SOI layer 7 .

[0039] Specifically, on the lower side of the trench structure 4 near the source region 1, a plurality of P-type semiconductor blocks 9, i.e., P-type doped blocks, are arranged in variable numbers and with decreasing widths from left to right on the SOI layer 7. Above the relevant SOI layer 7, the area on the side of the bottom of the trench structure 4 near the source region 1 is not completely depleted, and the electric field is easily concentrated at the bottom of the P-type well region 5, making the electric field distribution in this area extremely uneven and easy to break down. By arranging a plurality of P-type semiconductor blocks 9 with decreasing widths in the source-drain direction on the SOI layer 7, the depletion of this area is more uniform, and the electric field distribution in this area is more uniform. In addition, the P-type semiconductor blocks 9 prevent the source region 1 from extracting charges from the interface inversion layer, and the interface hole concentration increases, making the electric field distribution in this area more uniform, effectively increasing the breakdown voltage of this area, and at the same time, thereby increasing the doping concentration of this area, thereby reducing its on-resistance.

[0040] In some embodiments, the LDMOS device further includes a third high dielectric constant insulating layer, which is disposed in the N-type drift region 6 , electrically connected to the bottom of the drain region 2 and extends toward the SOI layer 7 .

[0041] The third high dielectric constant insulating layer is arranged at the bottom of the drain region 2, so that the depletion region below the drain region 2 is enlarged and its peak electric field is weakened, which can be used to adjust the electric field distribution and further improve the breakdown voltage of the device. The length and width of the third high dielectric constant insulating layer can be adjusted.

[0042] In some embodiments, the electrode material in the source region 1 , the drain region 2 and the gate region 3 is aluminum.

[0043] Specifically, the leads of the source region 1, the drain region 2 and the gate region 3 are set to "contact", that is, metal electrodes are used for conduction. The metal electrodes in the embodiment of the present application are made of aluminum, which is used for conducting voltage and controlling the function and use of the device.

[0044] Please refer to Figure 2 , Figure 2 A flow chart of a method for preparing an LDMOS device is provided in an embodiment of the present application. It should be noted that the steps shown in the flow chart of the accompanying drawings can be executed in a computer system such as a set of computer executable instructions, and although a logical order is shown in the flow chart, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0045] like Figure 2 As shown, the process includes the following steps:

[0046] Step S1, forming an N-type drift region 6 on a silicon substrate.

[0047] Step S3, injecting ions into the N-type drift region 6 to form a source region 1 and a drain region 2, wherein the source region 1 includes a P-type heavily doped region 1-1 and a first N-type heavily doped region 1-2, the source region 1 is arranged between the gate region 3 and the drain region 2, and the drain region 2 includes a second N-type heavily doped region 2-1.

[0048] Step S5 , forming a trench structure 4 in the N-type drift region 6 , wherein the trench structure 4 is located between the source region 1 and the drain region 2 .

[0049] Step S7, forming a gate region 3 in the N-type drift region 6, wherein a polycrystalline structure 3-1 is disposed on the gate region 3, and a first high dielectric constant insulating layer 3-2 is wrapped around the polycrystalline structure 3-1.

[0050] Step S9, forming a P-type well region 5 in the N-type drift region 6, wherein the P-type well region 5 contacts the source region 1 located directly above the P-type well region 5, and contacts the gate region 3 located directly to the left of the P-type well region 5, and when the gate-source voltage is higher than the turn-on voltage, a conductive channel is formed in the P-type well region 5.

[0051] Optionally, the silicon substrate includes an SOI layer 7 and a P-type epitaxial substrate 8 , and an N-type drift region 6 is formed on the SOI layer 7 .

[0052] The further functional description of each of the above modules and units is the same as that of the above corresponding embodiments and will not be repeated here.

[0053] See also Figure 3 , Figure 3 is a schematic diagram of the structure of a computer device provided in an embodiment of the present application, such as Figure 3 As shown, the computer device includes: one or more processors 10, a memory 20, and interfaces for connecting various components, including high-speed interfaces and low-speed interfaces. Various components are connected to each other using different buses for communication, and can be installed on a common mainboard or installed in other ways as needed. The processor can process the instructions executed in the computer device, including instructions stored in or on the memory to display the graphical information of the GUI on an external input / output device (such as, a display device coupled to the interface). In some optional embodiments, if necessary, multiple processors and / or multiple buses can be used together with multiple memories and multiple memories. Similarly, multiple computer devices can be connected, and each device provides some necessary operations (for example, as a server array, a group of blade servers, or a multi-processor system). Figure 3 A processor 10 is taken as an example.

[0054] The processor 10 may be a central processing unit, a network processor or a combination thereof. The processor 10 may further include a hardware chip. The hardware chip may be a dedicated integrated circuit, a programmable logic device or a combination thereof. The programmable logic device may be a complex programmable logic device, a field programmable gate array, a general purpose array logic or any combination thereof.

[0055] The memory 20 stores instructions executable by at least one processor 10, so that the at least one processor 10 executes the method shown in the above embodiment.

[0056] The memory 20 may include a program storage area and a data storage area, wherein the program storage area may store an operating system, an application required for at least one function; the data storage area may store data created according to the use of the computer device, etc. In addition, the memory 20 may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage device. In some optional embodiments, the memory 20 may optionally include a memory remotely arranged relative to the processor 10, and these remote memories may be connected to the computer device via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0057] The memory 20 may include a volatile memory, such as a random access memory; the memory may also include a non-volatile memory, such as a flash memory, a hard disk or a solid state drive; the memory 20 may also include a combination of the above types of memory.

[0058] The computer device further comprises a communication interface 30 for the computer device to communicate with other devices or a communication network.

[0059] The embodiment of the present application also provides a computer-readable storage medium. The above method according to the embodiment of the present application can be implemented in hardware, firmware, or can be implemented as a computer code that can be recorded in a storage medium, or can be implemented as a computer code that is originally stored in a remote storage medium or a non-temporary machine-readable storage medium and will be stored in a local storage medium through a network download, so that the method described herein can be stored in such software processing on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. Among them, the storage medium can be a magnetic disk, an optical disk, a read-only storage memory, a random access memory, a flash memory, a hard disk or a solid-state hard disk, etc.; further, the storage medium can also include a combination of the above types of memories. It can be understood that a computer, a processor, a microprocessor controller, or programmable hardware includes a storage component that can store or receive software or computer code. When the software or computer code is accessed and executed by a computer, a processor, or hardware, the method shown in the above embodiment is implemented.

[0060] The embodiment of the present application provides a computer program product, which includes computer instructions, which are stored in a computer-readable storage medium. A processor of a computer device reads the computer instructions from the computer-readable storage medium, and the processor executes the computer instructions, so that the computer device executes the method of any embodiment of the present application.

[0061] Although the embodiments of the present application are described in conjunction with the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present application, and such modifications and variations are all within the scope defined by the appended claims.

[0062] A typical implementation device is a computer. Specifically, the computer can be, for example, a personal computer, a laptop computer, a cellular phone, a camera phone, a smart phone, a personal digital assistant, a media player, a navigation device, an email device, a game console, a tablet computer, a wearable device, or a combination of any of these devices.

[0063] For the convenience of description, the above device is described in various units according to their functions. Of course, when implementing the present application, the functions of each unit can be implemented in the same or multiple software and / or hardware.

[0064] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the present application may adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) that contain computer-usable program code.

[0065] The present application is described with reference to the flowcharts and / or block diagrams of the methods and computer program products according to the embodiments of the present application. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of the processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0066] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture including an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0067] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0068] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of more restrictions, an element defined by the sentence "comprises a ..." does not exclude the presence of other identical elements in the process, method, commodity or device including the element.

[0069] The various embodiments in this specification are described in a progressive manner, and the same or similar parts between the various embodiments can be referenced to each other, and each embodiment focuses on the differences from other embodiments.

[0070] The above is only an embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various changes and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the scope of the claims of the present application.

[0071] Although the embodiments of the present application have been described in conjunction with the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present application, and such modifications and variations are all within the scope defined by the appended claims.

Claims

1. An LDMOS device, characterized in that: It includes a silicon substrate, a source region, a drain region, a gate region, a trench structure, an N-type drift region and a P-type well region, wherein: a source region, a drain region, a gate region, a trench structure and a P-type well region are provided in the N-type drift region on the silicon substrate; the trench structure is located between the source region and the drain region; the source region includes a P-type heavily doped region and a first N-type heavily doped region, which are provided between the gate region and the drain region; the drain region includes a second N-type heavily doped region; the gate region includes a polycrystalline structure and a first high dielectric constant insulating layer wrapping the polycrystalline structure; the P-type well region contacts the source region provided just above the P-type well region, and contacts the gate region provided just to the left of the P-type well region, and when the gate-source voltage is higher than the turn-on voltage, a conductive channel is formed in the P-type well region.

2. The LDMOS device according to claim 1, characterized in that: The silicon substrate comprises an SOI layer and a P-type epitaxial substrate, wherein the SOI layer is located between the N-type drift region and the P-type epitaxial substrate.

3. The LDMOS device according to claim 2, characterized in that: The trench structure includes a low dielectric constant insulating layer and a silicon dioxide layer arranged in sequence from top to bottom.

4. The LDMOS device according to claim 2, characterized in that: The outer side of the groove structure is wrapped with a second high dielectric constant insulating layer.

5. The LDMOS device according to claim 2 or 4, characterized in that: The P-type well region extends along the sidewall of the trench structure to the bottom of the trench structure.

6. The LDMOS device according to claim 5, characterized in that: It also includes a plurality of P-type semiconductor blocks with decreasing widths in the source-drain direction. The plurality of P-type semiconductor blocks are arranged just below the P-type well region, and the bottoms of the P-type semiconductor blocks are in contact with the SOI layer.

7. The LDMOS device according to claim 1, characterized in that: It also includes a third high dielectric constant insulating layer, which is arranged in the N-type drift region, electrically connected to the bottom of the drain region and extends toward the SOI layer.

8. The LDMOS device according to claim 1, characterized in that: The electrode material in the source region, the drain region and the gate region is aluminum.

9. A method for preparing an LDMOS device, characterized in that: The following steps are involved: forming an N-type drift region on a silicon substrate; Implanting ions into the N-type drift region to form a source region and a drain region, wherein the source region includes a P-type heavily doped region and a first N-type heavily doped region, the source region is arranged between the gate region and the drain region, and the drain region includes a second N-type heavily doped region; forming a trench structure in the N-type drift region, wherein the trench structure is located between the source region and the drain region; A gate region is formed in the N-type drift region, wherein a polycrystalline structure is disposed on the gate region, and a first high dielectric constant insulating layer is wrapped around the polycrystalline structure; A P-type well region is formed in the N-type drift region, and the P-type well region contacts a source region located directly above the P-type well region, and contacts a gate region located directly to the left of the P-type well region. When the gate-source voltage is higher than the turn-on voltage, a conductive channel is formed in the P-type well region.

10. The method for preparing an LDMOS device according to claim 9, characterized in that: The silicon substrate comprises an SOI layer and a P-type epitaxial substrate, and an N-type drift region is formed on the SOI layer.

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