LDMOS with bias circuit for biasing field plate

Abstract

The invention relates to an LDMOS with a bias circuit for biasing a field plate. A semiconductor device (100) includes: a drain extension transistor (101) having: a semiconductor layer (104) including oppositely doped body and drain drift regions (104, 120); a gate dielectric layer (134) over the body region (104) and extending over a junction between the body region (104) and the drain drift region (120); a gate electrode (140) over the gate dielectric layer (134); a drain region (160) in the drain drift region (120) and having a dopant density greater than a dopant density of the drain drift region (120); and a field plate (142) between the gate electrode (140) and the drain region (160); and a bias circuit (190) including an output coupled to the field plate (142) and a bias input coupled to a gate drive circuit (192).

Description

[0001] Cross-reference to related applications

[0002] This application claims priority and benefit to U.S. Provisional Patent Application Serial No. 63 / 684,328, filed August 16, 2024, entitled "Drain Extended Transistor with Field Plates," and U.S. Provisional Patent Application Serial No. 63 / 685,424, filed August 21, 2024, entitled "Drain Extended Transistor with Field Plates," the contents of which are hereby incorporated in their entirety by reference. Technical Field

[0003] This disclosure generally relates to semiconductors, and more specifically, to LDMOS having bias circuitry for a bias field plate. Background Technology

[0004] Extended drain transistors are used in high-voltage applications requiring high breakdown voltage ratings and efficient operation, such as low-side switches in switching power supplies, to provide low drain-source resistance (RDSON) in the on-state and the ability to block or withstand high off-state voltages between the drain and source or gate. The extended drain architecture features a lightly doped drift region that allows for carrier depletion under reverse bias, enabling the drain to block current flow during high-voltage operation. The polysilicon gate can be extended onto a field-release oxide above the drift region to improve the charge balance of the drift region. However, this approach leaves a non-uniform electric field with peaks in the drift region during off-state operation, such as a peak below the end of the polysilicon field plate. These non-uniform electric fields deviate from the ideal breakdown voltage and can lead to suboptimal breakdown voltage performance, which can only be addressed by increasing the lateral drift region length to accommodate the required drain blocking voltage in the off-state within semiconductor breakdown strength limitations. Increasing the drift region length to help improve voltage breakdown performance will suppress the effect of reducing circuit area and increase the on-state drain-source resistance (RDSON) of the transistor because there is more material for charge carriers to pass through. Summary of the Invention

[0005] In one aspect, a semiconductor device includes: a drain extension transistor comprising: a semiconductor layer having a body region having a first conductivity type and a drain drift region having an opposite second conductivity type; a gate dielectric layer situated over the body region and extending over a junction between the body region and the drain drift region; a gate electrode over the gate dielectric layer; a drain region having the second conductivity type in the drain drift region, the dopant density of the drain region being greater than the dopant density of the drain drift region; a field plate between the gate electrode and the drain region; and a bias circuit including an output coupled to the field plate and a bias input coupled to a gate drive circuit.

[0006] In another aspect, a semiconductor device includes: a drain extension transistor comprising: a semiconductor layer having a body region having a first conductivity type and a drain drift region having an opposite second conductivity type; a gate dielectric layer situated over the body region and extending over a junction between the body region and the drain drift region; a gate electrode over the gate dielectric layer; a drain region having the second conductivity type in the drain drift region, the dopant density of the drain region being greater than the dopant density of the drain drift region; a field plate between the gate electrode and the drain region; and a bias circuit comprising a clamping circuit having a diode coupled to the field plate.

[0007] In another aspect, a semiconductor device includes: a drain extension transistor comprising: a semiconductor layer having a body region having a first conductivity type and a drain drift region having an opposite second conductivity type; a gate dielectric layer situated over the body region and extending over a junction between the body region and the drain drift region; a gate electrode over the gate dielectric layer; a drain region having the second conductivity type in the drain drift region, the dopant density of the drain region being greater than the dopant density of the drain drift region; a field plate between the gate electrode and the drain region; and a bias circuit coupled to the field plate, the bias circuit including a reset circuit.

[0008] In another aspect, a semiconductor device includes: a drain extension transistor comprising: a semiconductor layer having a body region having a first conductivity type and a drain drift region having an opposite second conductivity type; a gate dielectric layer situated over the body region and extending over a junction between the body region and the drain drift region; a gate electrode over the gate dielectric layer; a drain region having the second conductivity type in the drain drift region, the dopant density of the drain region being greater than the dopant density of the drain drift region; a field plate between the gate electrode and the drain region; and a bias circuit coupled to the field plate, the bias circuit including a second transistor.

[0009] In another aspect, a semiconductor device includes: a drain extension transistor comprising: a semiconductor layer having a body region having a first conductivity type and a drain drift region having an opposite second conductivity type; a gate dielectric layer situated over the body region and extending over a junction between the body region and the drain drift region; a gate electrode over the gate dielectric layer; a drain region having the second conductivity type in the drain drift region, the dopant density of the drain region being greater than the dopant density of the drain drift region; and at least one field plate between the gate electrode and the drain region; and a bias circuit having an output coupled to a respective field plate and an input coupled to a voltage input of the semiconductor device, an input to the drain region, and an input to a gate drive circuit.

[0010] In another aspect, a method includes: forming a drain extension transistor in a semiconductor device, the drain extension transistor comprising: a semiconductor layer having a body region having a first conductivity type and a drain drift region having an opposite second conductivity type; a gate dielectric layer situated over the body region and extending over a junction between the body region and the drain drift region; a gate electrode over the gate dielectric layer; a drain region having the second conductivity type in the drain drift region, the dopant density of the drain region being greater than the dopant density of the drain drift region; and a field plate between the gate electrode and the drain region; and forming a bias circuit in the semiconductor device, the bias circuit including an output coupled to the field plate and a bias input coupled to a gate drive circuit. Attached Figure Description

[0011] Figure 1 It is along Figure 1A The image shows a partial cross-sectional side view of a semiconductor device, taken from line 1-1, which includes a drain extension transistor with a bias field plate.

[0012] Figure 1A yes Figure 1 A partial top view of a semiconductor device.

[0013] Figure 2 This is a partial cross-sectional side view of another semiconductor device containing a drain extension transistor with three bias field plates.

[0014] Figure 3-16A An example bias circuit is shown for providing bias voltages for one or more field plates. Detailed Implementation

[0015] In the drawings, the same reference numerals always refer to the same elements, and various features are not necessarily drawn to scale. Furthermore, the terms "coupled" or "couples" encompass indirect or direct electrical connections or mechanical connections, or combinations thereof. For example, if a first device is coupled to or with a second device, then the connection may be via a direct electrical connection or an indirect electrical connection via one or more intervening devices and connections. The following describes one or more operating characteristics of various circuits, systems, and / or components in the context of function, which in some cases arise from the configuration and / or interconnection of various structures when the circuit system is energized and operated. In the following statements and claims, the terms "including," "includes," "having," "has," "with," or variations thereof are intended to be inclusive in a manner similar to the term "comprising," and therefore should be interpreted as meaning "including but not limited to." Unless otherwise stated, "about," "approximately," or "substantially" preceding a value means + / - 10% of the stated value.

[0016] The following describes one or more operational characteristics of various circuits, systems, and / or components in the context of functionality, which in some cases arise from the configuration and / or interconnection of various structures when the circuit system is energized and operated. For ease of description in conjunction with specific figures, one or more structures, features, aspects, components, etc., may be referred to herein as first, second, third, etc., e.g., first and second terminals, first, second, and third components, etc., which should not be construed as limiting the claims. The various disclosed structures and methods can be advantageously applied to manufactured electronic devices, such as integrated circuits. While various improvements may be expected from such examples, this disclosure does not require a particular outcome unless expressly stated in a specific claim.

[0017] Figure 1 and 1A A semiconductor device 100 is shown, comprising a drain extension transistor 101 with a bias field plate 142 having a lateral position and bias voltage determined by means of a simulated device model. The bias field plate 142 may also be referred to as a bias drain field plate. The described example enables improved uniformity of the electric field distribution in the off-state drift region while maintaining good breakdown voltage performance at a small half-pitch size without increasing the drift region length and keeping the on-resistance low. Although semiconductor breakdown strength may limit scaling along the half-pitch size of the drift region, and doping density and carrier mobility in the drift region may limit reductions in on-resistance, the field plate positioning and bias can be tailored for a given design specification through simulation and iterative modeling to provide benefits beyond gate voltage bias field plate performance.

[0018] Semiconductor device 100 is shown in an example three-dimensional space, having a first direction X ( Figure 1 and 1A ), the second direction Y (perpendicular (orthogonal) Figure 1A ) and a third direction Z perpendicular (or orthogonal) to the first direction X and the second direction Y. Figure 1 The structures or features along any two of these directions are orthogonal to each other. Example drain extension transistor 101 is an n-channel laterally diffused metal-oxide-semiconductor (LDMOS) transistor. Figure 1 A schematic diagram of a drain extension transistor 101, labeled "T," is shown, having indicated connections to the gate G, drain D, and source S, and a field plate FP laterally disposed between the gate G and drain D. In another embodiment, the p-channel LDMOS transistor may be formed when the n-doped region is replaced by a p-doped region, and in another embodiment, when the p-doped region is replaced by an n-doped region. In one example, other electronic components (not shown) may be provided in the semiconductor device 100, such as a second drain extension transistor interconnected with the illustrated transistor 101 in a half-bridge circuit of a packaged integrated circuit, wherein terminals or leads provide external connections to some or all of the transistor terminals. In some embodiments, other circuit systems, such as gate driver circuitry (not shown), switching control timing circuitry, etc., may be included in a single integrated circuit for high-voltage switching applications, such as power conversion systems, transceivers, etc.

[0019] like Figure 1 Further illustrated, the example semiconductor device 100 includes a semiconductor substrate 102, such as silicon or other semiconductor material doped with impurities of a first conductivity type (e.g., P-type) from a starting wafer, such as silicon (Si) or other semiconductor wafers (e.g., silicon carbide or SiC, gallium nitride or GaN, etc.), silicon-on-insulator (SOI) wafers, etc. In one example, the semiconductor device 100 includes a semiconductor layer 104 (e.g., p-type epitaxial silicon) extending over the semiconductor substrate 102, and includes a body region 104 having a first conductivity type (e.g., P-type), wherein the semiconductor layer 104 may be interchangeably referred to as the body region 104. An n-type buried layer (NBL) 106 extends beneath the semiconductor layer 104 and has the opposite second conductivity type (e.g., N-type). The device 100 includes a field-release dielectric layer 114, such as a localized silicon oxide (LOCOS) layer of silicon dioxide (SiO2). In one example, the isolation structure including shallow trench isolation 118 extends around the outer periphery of transistor 101 and extends along semiconductor layer 104 into its top side.

[0020] Semiconductor device 100 includes drain drift region 120 (e.g., in...) Figure 1The dielectric layer 114, labeled "N-DRIFT", has a second conductivity type and extends in the bulk region 104. The field-release dielectric layer 114 extends over the drain drift region 120. (As shown...) Figure 1A As shown, the example drain extension transistor has a finger or racetrack shape with a central drain finger (e.g., labeled as...). Figure 1 The "D" in Figure 1A The "DRAIN" in the text), and the polysilicon gate surrounding the drain (e.g., marked as "DRAIN"). Figure 1 The "G" in Figure 1A The “GATE” in the diagram and the source surrounding the gate (e.g., labeled as…) Figure 1 The "S" in Figure 1A (as indicated by "SOURCE" in the text). In this or other examples, the transistor may include other drain center fingers or raceway structures (not shown). In these or other embodiments, the transistor may include one or more source center fingers or raceway structures and / or one or more gate center fingers or raceway structures (not shown).

[0021] like Figure 1 Further shown, the example semiconductor device 100 may also include a p-type buried layer 126 (e.g., labeled "P", also known as a pRESURF layer for secure operating area (SOA) improvement) having a first conductivity type and a dopant concentration greater than that of the body region 104. In one example, the body region 104 of the semiconductor layer includes a shallow well 130 (e.g., in...). Figure 1 The shallow well 130 (labeled "SPWELL") is located below the source S and has a first conductivity type (e.g., p-type) and a dopant density higher than that of the body region 104. The shallow well 130 increases the base doping level of the body region 104, which helps suppress parasitic lateral NPN bipolar transistors formed by the N+ source-p-body-N+ drain D. These parasitic lateral NPN bipolar transistors limit high-current operation of the LDMOS transistor 101, thereby limiting the safe operating area (SOA) of the LDMOS transistor 101.

[0022] Transistor 101 also includes a body region 104 ( Figure 1 The shape of the runway extending above a portion of ) Figure 1A The gate dielectric layer 134 extends over the junction between the body region 104 and the drain drift region 120. In one example, the gate dielectric layer 134 extends to the outer beak-shaped portion of the field release dielectric layer 114 and over the interface or junction between the channel and the p-type body region 104 and the n-type drift region 120 below a portion of the gate fingers or raceway G. Figure 1 and 1AAs further shown, the polysilicon gate electrode 140 extends over the gate dielectric layer 134 and also over the portion of the field release dielectric layer 114 located above the drift region 120.

[0023] Transistor 101 has a bias field plate 142, which may also be referred to as a bias drain field plate, and is located above the field release dielectric layer 114. In another embodiment, the field release dielectric layer 114 may be omitted, and the bias field plate 142 is located above the gate dielectric layer 134. In this example, the bias field plate 142 also has a racetrack shape (e.g., in...). Figure 1 and 1A (Illustrated as "FP"). A bias field plate 142 is laterally spaced from the gate electrode 140 and positioned laterally between the gate electrode 140 and the transistor drain. The field plate 142 is conductively connected to a bias circuit (not shown) that provides a field plate bias voltage to the field plate 142 during power-on operation of the semiconductor device 100. The example shown includes a single bias field plate 142. In other embodiments (e.g., below)... Figure 11 It can provide two or more bias field plates spaced apart from each other and positioned laterally between the gate G and the drain D, wherein the corresponding field plate size and position and the field plate bias voltage are determined according to the adjusted device model, as further described below.

[0024] like Figure 1A As shown in the example, the bias field plate 142 follows a path with rounded corners, the radius R of which is greater than the thickness 143 of the field plate 142 (e.g., along...). Figure 1 (The third direction Z in the example). In one example, the field release dielectric layer 114 comprises a localized silicon oxide (LOCOS) layer of silicon dioxide, and the field plate 142 extends over the tapered edge of the field release dielectric layer 114. In the example shown, the field plate 142 is located above the end point of the LOCOS layer at the top surface of the semiconductor layer 104 (e.g., where the beak shape of the LOCOS field release dielectric layer 114 begins) (e.g., along the edge of the semiconductor layer 104). Figure 1 (The first direction X in the middle). In one example, the field plate 142 is or contains polysilicon and can be formed and patterned simultaneously with the gate electrode 140.

[0025] Example drain extension transistor 101 also includes a p-type deep well region 146 having a first conductivity type (e.g., in...). Figure 1The source region 100 (labeled "DPWELL") extends through and beneath the p-type shallow well 130. A p-type deep well region 146 extends to the top side of the body region 104 and connects to the p-type buried layer 126. An n-type well region 148 extends along the top side of the p-type deep well region 146 and has a second conductivity type. The example semiconductor device 100 also includes sidewall spacers 154 along the lateral sides of the gate electrode 140 and the field plate 142. In one example, the sidewall spacer 154 comprises an oxide layer 150 and a nitride layer 152, formed by deposition and anisotropic etching. The sidewall spacer 154 overlaps with the edge of the field release dielectric layer 114 adjacent to the drain region. In another example, the nitride layer 152 may be deposited across the surface of the wafer and etched to form a nitride-only sidewall spacer 154. Transistor 101 has a source region 158 of a second conductivity type (N-type) in a p-type deep well 146, wherein the source region 158 has a greater depth than the n-type well region 148.

[0026] The transistor drain includes a drain region 160 of a second conductivity type (N-type) that extends along and into the top side of a drain drift region 120 in the body region 104, and the drain region 160 is laterally surrounded by a field plate 142. The field plate 142 is spaced apart from the gate electrode 140 and the drain region 160, and extends laterally between them. The dopant density of the drain region 160 is greater than that of the drain drift region 120. A field release dielectric layer 114 extends from the gate dielectric layer 134 toward the drain region 160 and has a thickness greater than that of the gate dielectric layer 134. In one example, the field plate 142 is electrically biased relative to the substrate 102 or relative to the source at a non-zero field plate bias voltage. In one example, the field plate 142 laterally extends a field plate width dimension 161 between the drain region 160 and the gate. Figure 1 In one example, the dimension is at least twice the thickness of the field release dielectric layer 114 along the third direction Z. In the illustrated example, the field plate 142 extends over the thin beak of the field release dielectric layer 114, but this is not necessary for all possible implementations. As shown below Figure 11 As shown, for example, in other embodiments, one or more field plates may extend partially or completely over portions of the field release dielectric layer.

[0027] In one example, semiconductor device 100 has a silicide barrier layer 162 ( Figure 1The field plate 140 is a sublayer comprising or contains one or more sublayers of oxides, nitrides, oxynitrides, or combinations thereof. In one example, a silicide barrier layer 162 extends over a sidewall spacer 154 between the gate G and the bias field plate FP. In the illustrated example, the gate electrode 140 extends over a field release dielectric layer 114, and the gate electrode 140 is laterally spaced from the field plate 142 by a portion of the silicide barrier layer 162 extending over the sidewall spacer 154. Sidewall spacers on the sidewalls of the field plate 142 extend to the drain region 160.

[0028] Semiconductor device 100 further includes a metal silicide layer 165 extending along the upper sides of a deep well region 146 of the source and a drain region 160 to facilitate low-resistance electrical connections to the source and drain terminals of transistor 101. Additionally, the metal silicide layer 165 may be provided with conductive metal (e.g., tungsten) contacts for low-resistance electrical connections to a bias field plate 142 and a gate electrode 140, said contacts being contained within a finger structure ( Figure 1A The gate contact is located in the gate contact region at the lateral end of the semiconductor device 100. The semiconductor device 100 also includes a nitride etch-stop layer 166 extending over portions of the metal silicide layer 165, the sidewall spacer 154, and the silicide barrier layer 162.

[0029] Semiconductor device 100 may include a single-layer or multi-layer metallization structure having a metal front dielectric 168 (PMD), conductive metal (e.g., tungsten) contacts 172 and 174 for the source and drain electrodes. Figure 1 and 1A ), gate contact 176 ( Figure 1A ) and field plate contact 181 ( Figure 1 and 1A ). Figure 1 The portion of the metallized structure shown also illustrates metal interconnects 178 and 180 conductively coupled to source contacts 172 and drain contacts 174, and metal interconnects 182 and 184 coupled to field plate contacts 181. Similar metal interconnects (not shown) are coupled to gate contacts 176 for electrical connections to the various terminals of transistor 101 in the metallized structure. Metal interconnects 182 and 184 allow bias voltage circuitry (not shown) to be electrically connected to bias field plate 142, and a non-zero field plate bias voltage can be applied during operation of the semiconductor device 100.

[0030] The extended drain of transistor 101 provides a relatively lightly doped drift region, allowing the high-voltage drain to extend away from the edge of the channel region. In certain processes, the planar drift region can be used to increase the reverse blocking voltage above the rated voltage of the gate dielectric layer 134. For even higher drain voltage ratings, the drain side of the gate polysilicon is spaced from the drift region 120 by a field-release dielectric layer 114 to promote more complete depletion of the drift region. Reducing the surface field (RESURF) profile doping can be used to achieve complete reverse bias depletion of the drift region. In some examples, the drift region doping level or dopant concentration can be higher near the transistor channel region junction to mitigate the effects of hot channel carrier injection into the gate and enhance transistor reliability. In addition, the bias field plate 142 helps to enhance the uniformity of the electric field in the drift region 120 below the field release dielectric layer 114 when the transistor 101 is off, thereby helping the transistor 101 to have good breakdown voltage performance without adversely affecting the drain-source resistance in the on state, and without having to increase the lateral length of the drift region along the first direction X.

[0031] In one example, semiconductor device 100 includes field plate voltage biasing circuit 190. Figure 1 This is configured when the semiconductor device 100 is powered and used to provide a non-zero field plate bias voltage VFP to the field plate 142, which is different from the voltage of the gate electrode 140. Other embodiments may include more than one bias field plate location between the gate and drain, each biased with a different field plate bias voltage for different gate voltages. In one example, the bias circuit provides a corresponding field plate bias voltage to maintain a monotonic voltage increase in the field plate segment in the direction from the source to the drain, such that the field plate can shape the potential in the drift region 120 to drop approximately uniformly from the drain to the source, but this is not necessary in all possible embodiments.

[0032] Any suitable bias circuit 190 can be used in single-biased or multi-biased field plate implementations, such as a string of diodes connected in series, such as Zener diodes, source / drain-well diodes, lateral avalanche diodes, diode-connected bipolar transistors, etc. (not shown). In other implementations, passive circuitry (e.g., resistor-based circuitry) and / or active circuitry (e.g., diode-connected transistors) can be used to bias the field plate 142, and / or a string of such circuitry can be used to bias multiple field plates 142, for example, to achieve temperature coefficient matching. In some implementations (not shown), the bias circuit 190 may include a bias source of the diode applied up to the first field plate 142 (closest to the gate), and a back-to-back diode may be added between the last field plate 142 and the drain, thereby allowing the entire string of field plates to be biased during the transistor's on-state, thereby reducing RDSON.

[0033] In this or another example, if increasing the field plate bias in the on-state is not required, for simplicity, the diode preceding the first field plate 142 closest to the gate can be connected to the gate or source or other suitable voltage supply node. In various embodiments, the drain voltage rating of the device can be selected by varying the number of field plates, and the field plate bias can facilitate achieving a high breakdown voltage rating without increasing the half-pitch of transistor 101. Furthermore, in multi-field plate embodiments, the field plate width and spacing can be identical, but this is not necessary in all possible embodiments. Additionally, the voltage drop between field plates can be approximately equal, but this is not necessary in all possible embodiments.

[0034] In operation, the extended drain of transistor 101 provides a relatively lightly doped drift region, allowing the high-voltage drain to extend away from the edge of the channel region, and the planar drift region can be used to increase the reverse blocking voltage. For higher drain voltage ratings, the drain side of the gate polysilicon is spaced from the drift region 120 by the gate dielectric layer 134 to promote more complete depletion of the drift region. Reducing the surface field profile doping can be used to achieve complete reverse bias depletion of the drift region. In some examples, the drift region doping level or dopant concentration can be higher near the junction of the transistor channel region to mitigate the effects of hot carrier injection into the gate and enhance transistor reliability. Additionally, the bias field plate 142 helps to enhance the uniformity of the electric field within the drift region 120 below the gate dielectric layer 134 in the off-state of transistor 101, thereby contributing to good breakdown voltage performance of transistor 101 without adversely affecting the drain-source resistance in the on-state or increasing the lateral length of the drift region along the first direction X.

[0035] In power switching circuits, such as those of DC-DC converters, high-side and low-side switches can be fabricated as drain-extended transistors, and the source / back gate terminals of the high-side device can be isolated from circuit ground to facilitate high-voltage operation. Furthermore, the shrinking geometry and alignment tolerances of advanced semiconductor manufacturing processes increase the impact of non-uniformities such as center-edge differences in device structure location on performance. Scaling drain-extended transistors to reduce the half-pitch size along the first direction X and / or designing transistors with a fixed half-pitch size to promote higher breakdown voltage ratings suppresses the ability to balance off-state breakdown voltage performance and low on-state drain-source resistance.

[0036] Figure 2 Another example semiconductor device 200 is shown, which includes a drain extension transistor 201, wherein three bias field plates 242 (e.g., labeled FP1, FP2 and FP3) are spaced apart from each other between the gate electrode 240 and the transistor drain D. Figure 2The device 200 includes a p-substrate 202, a body region 204 having p-type epitaxial silicon, a p-type implantation body region 246, an n-type drift region 220, a drain 260, and a source S258 having the implantation region, which in some respects may be similar to the combination described above. Figure 1 and 1A The corresponding structures 142, 140, 102, 104, 146, 120, 160, and 158 are shown and described. In other embodiments, any integer number of bias field plates can be used, with corresponding field plate bias voltages used to enhance the uniformity of the electric field effect during the off-state operation of the drain extended transistor, without significantly adversely affecting the desired low on-state resistance (RDSON) or increasing the half-pitch or other dimensions of the drain extended transistor to facilitate high power density and small form factor electronics. In the illustrated example, field plate 242 is situated above field release dielectric layer 214. In another embodiment, field release dielectric layer 214 may be omitted, with a thin gate dielectric layer extending below the gate electrode 240 and field plate 242, wherein bias field plate 142 is situated above the gate dielectric layer.

[0037] In one example, the semiconductor device 200 includes a field plate voltage biasing circuit 290. Figure 2 This configuration is used when the semiconductor device 200 is powered and used to provide non-zero field plate bias voltages VFP1, VFP2, and VFP3, which are different from the voltage of the gate electrode 240, to the respective field plates 242 (FP1, FP2, and FP3). Other embodiments may include more than one bias field plate location between the gate and drain, each biased with a different field plate bias voltage for different gate voltages. In one example, the bias circuit provides a corresponding field plate bias voltage to maintain a monotonic voltage increase in the field plate segment in the direction from the source to the drain, such that the field plates can shape the potential in the drift region 220 to drop approximately uniformly from the drain to the source, but this is not necessary in all possible embodiments.

[0038] Example semiconductor devices 100 and 200 provide corresponding field plate voltage bias circuits 190 and 290, which are configured when semiconductor devices 100 and 200 are powered and used to provide a non-zero field plate bias voltage VFP to field plate 142 or field plate 242 for a voltage different from that of gate electrodes 140 and 240. Additionally, in one example, in... Figure 2 In the multi-field plate example, the field plate voltage bias circuit 290 provides a monotonically increasing voltage to the corresponding field plate 242 in the direction from the gate electrode 240 to the drain, so that the field plate can form the potential in the drift region to decrease approximately uniformly in the direction from the drain to the source, but this is not necessary for all possible implementations.

[0039] Figure 3-16AExamples of suitable biasing circuits that can be used in example semiconductor devices 100 and 200 or other single-biased or multi-biased field-plate drain-extended transistors are shown. In some examples (e.g., Figure 3 , 3H In (e.g., 3J, 3L, 6E, 6F, 7B, 7D, 9-9B), the bias circuitry includes an output coupled to the field plate and a bias input coupled to the gate drive circuitry (e.g., gate driver 192 above). In some examples (e.g., Figure 3-3M In (4-4G, 5 and 6, 6H, 6I, 7D, 7F, 9-9B and 10-15), the diode-based biasing circuit includes a clamping circuit having a diode coupled to the field plate. Specific examples (e.g., Figure 6-6K Figures 7-7H, 8, 8A, 11, 12, and 14 show bias circuits with reset circuitry, some of which may include one or more capacitors, pull-up or pull-down circuits with resistors or current sources. In some embodiments (e.g., Figure 3 , 3G In (-3N, 9, 9A, 14, 16, 16A), the field plate bias circuit may include one or more additional transistors. In some examples (e.g., Figure 4F , 4G In (6J, ​​6K, 7G, 7H, 10-12, 15, 16, 16A), the bias circuit may include a resistor coupled to the gate of the clamping circuit transistor.

[0040] Some examples employ bias circuitry systems that shunt the field plate to the transistor source voltage level, also known as source shunt bias circuits. Other examples use bias circuitry systems that shunt the field plate to the transistor drain voltage level (e.g., also known as drain shunt bias circuits). Other implementations may provide shunts to both the source and drain voltages. Generally, the inherent capacitance of the drain-extended transistor affects the inherent field plate voltage (e.g., VFP) of a given design without voltage bias. A given design can be characterized empirically or based on simulation, for example, by ramping the drain-source voltage VDS from zero to the design breakdown voltage level VB and then back down to zero, and monitoring the voltage of the unbiased field plate, to determine the field plate voltage at which the drain-source voltage reaches the breakdown voltage level VB. This measured or simulated value can be compared to the target bias voltage required for the field plate. The breakdown voltage level VB is a non-monotonic function of the field plate voltage VFP because if VFP is much greater than VB / 2, the electric field peak will be closer to the source terminal of the drift region; while if VFP is much lower than VB / 2, the electric field peak will be closer to the drain terminal of the drift region. Therefore, there exists a target VFP voltage that makes the electric field peaks on the source and drain sides of the drift region approximately equal, thus improving (e.g., maximizing) the VB condition. If the measured or simulated field plate voltage exceeds the target value, the bias circuit can be designed to shunt current to the source; conversely, if the measured or simulated field plate voltage is lower than the target value, it may indicate that a bias circuit system needs to shunt current to the drain. When the measured or simulated field plate voltage is close to the target voltage and / or the process variation is large enough to affect the inherent capacitance of the field plate, a bias circuit system that shunts current to both the source and drain can be used.

[0041] First refer to Figure 3-3G , Figure 3 The diagram shows a source S, a gate G, and a single field plate 301 (e.g., as described above). Figure 1 The field plate 142 and the drain voltage V D An example of a drain-extended transistor T with drain D is a source-source shunt resistive pull-up bias circuit 300. Gate driver 302 (e.g., gate driver 192 above) provides a gate drive voltage signal V to the gate G. G The output 303 (e.g., gate voltage) and through the gate drive supply voltage V DRV The gate drive supply is powered. The bias circuit 300 includes a clamping circuit 304 (e.g., also in...). Figure 3B The general clamping element shown has a first terminal A (e.g., the anode of the clamping circuit) and a second terminal C (e.g., the cathode of the clamping circuit 304). The first terminal A is configured to provide a field plate bias voltage signal V to a circuit node 305 coupled to the field plate 301. FFurthermore, pull-up resistor 306 is coupled between circuit node 305 and input node 307 having a circuit input having a voltage V relative to the source S. S and relative to the gate drive supply voltage V DRV A positive voltage V IN (For example, the input voltage of semiconductor device 100, such as the input signal of a DC-DC converter). During power-on operation, clamping circuit 304 controls the clamping voltage V between first terminal A and second terminal C. CLAMP And the field plate bias voltage signal V F It is the clamping voltage plus the gate drive supply voltage (e.g., V). F =V CLAMP +V DRV ).

[0042] Figure 3A The curve shown in the figure represents the gate voltage V at the gate driver 302. G Switching to a low drain voltage V D At its maximum value, during the operation of bias circuit 300, the transistor drain-source voltage (V DS During a drift period from zero to its maximum value (e.g., the rated breakdown voltage of transistor T) and then back to zero, the drain voltage V... D Field plate bias voltage signal V F and gate drive voltage signal V G Voltage V relative to source S S The change in the field plate bias voltage signal V. In this example, the field plate bias voltage signal V. F Starts slightly below the gate drive supply voltage V DRV The value, and the drain voltage V D During the upward drift, it rises to a steady-state value V. F =V CLAMP +V DRV .

[0043] Figure 3B Show Figure 3 The general clamping circuit 304 of the bias circuit 300 is used to illustrate one or more possible clamping circuit implementations in the figures below. For example... Figure 3B As shown, the universal clamping circuit 304 includes a first terminal A serving as the anode of the clamping circuit 304 and a second terminal C serving as the cathode of the clamping circuit 304. The clamping circuit current I... A Based on the clamping circuit voltage V on the first terminal A and the second terminal C AC (For example, Figure 3 V in the implementation plan CLAMP It flows into the first terminal A.

[0044] Figure 3CCurve 309 in Figure 308 illustrates the use of dual diode clamping (e.g., Figure 3E In the implementation scheme of the bias circuit 300, and in the implementation scheme of the general clamping circuit 304, the clamping circuit current I... A With the clamping circuit voltage V on the first terminal A and the second terminal C AC The change. In this example, the clamping circuit 304 extends to the clamping circuit voltage bias circuit V at the first terminal A and the second terminal C. AC Reaching V CLAMP Conduction current I A And then the current I A Increase, so that at a slope of 1 / R RB Further increase the clamping circuit voltage V AC .

[0045] Figure 3D The clamping circuit voltage V is shown. AC With the clamping circuit current I entering the first terminal A A The variation is shown in Figure 310. Figure 310 includes clamping using avalanche / Zener diodes (e.g., Figure 3F and 3G Curve 311 of the general clamping circuit 304 in the implementation of the bias circuit 300. In this example, the clamping circuit voltage V AC For the positive clamping circuit current I A Following the slope R RB And for negative currents, it follows a similar slope R RB and from negative voltage V DIO Transition to clamping voltage V CLAMP The negative voltage V DIO yes Figure 3F and 3G The forward diode voltage drop of the junction diode 313 in the clamping circuit 312.

[0046] Figure 3E-3G A corresponding non-limiting embodiment is shown that can be used in a general clamping circuit or a general clamping element 304. Figure 3E An example of a general-purpose clamping element embodiment 312 with a junction diode 313 and a Zener diode 314 is shown. In this example, the anode of the junction diode 313 is connected to a first terminal A, the cathode of the junction diode 313 is connected to the cathode of the Zener diode 314, and the anode of the Zener diode 314 is connected to a second terminal C of the general-purpose clamping element embodiment 312.

[0047] Figure 3F An example of a general-purpose clamping element 315 with a Zener diode is shown. In this example, the cathode of the Zener diode is connected to the first terminal A, and the anode of the Zener diode is connected to the second terminal C. (Above) Figure 3A and 3D The diagram representation uses the corresponding Figure 3F The clamping circuit 304 of the single Zener universal clamping element 315. Figure 3 One embodiment of the bias circuit 300. In this example, Figure 3D V in CLAMP This represents the clamping voltage of the Zener diode, and when V... DS When close to 0V, Figure 3 The field plate bias voltage V in the corresponding embodiment of the bias circuit 300 F Roughly V DRV -V DIO When V DS When the voltage is close to the breakdown voltage VB, the bias voltage V of the field plate is... F Roughly V DRV +V ZENER V DRV It is the driver supply voltage, V DIO It is the forward diode voltage drop of the Zener diode, V ZENER It is a Zener voltage.

[0048] Refer again Figure 3 Example bias circuit 300, configured in alternative or variant forms, may include connecting the first terminal A of the clamping element to the source voltage V. S Gate voltage V G Or has a clamping voltage V CLAMP The corresponding change is made to another supply voltage node (not shown, e.g., referred to as VS). In these or other alternative implementations, active clamping can be implemented in many ways, as further described below. In these or other examples, a DC bias resistor, for example... Figure 3 The pull-up resistor 306 or pull-down resistor in the circuit can actually be implemented in many ways (e.g., current source, from V...). D To V S (such as resistor dividers).

[0049] Figure 3G Another example embodiment 316 of a general clamping element 304 having a first terminal A and a second terminal C is shown. Figure 3G The clamping element 316 includes a hybrid circuit having a Zener diode 317, a resistor 318, and an n-channel metal-oxide-semiconductor (e.g., NMOS) transistor 319. In this example, the cathode of the Zener diode 317 and the drain of the transistor 319 are connected to a first terminal A, the source of the transistor 319 is connected to a second terminal C, the anode of the Zener diode 317 is connected to the gate of the transistor 319, and the resistor 318 is connected between the gate and the source of the transistor 319.

[0050] Figure 3H-3J Three example alternative cathode connection variations of an active source shunt bias circuit for a single bias field plate of a drain-extended transistor are shown, the drain-extended transistor being illustrated using the general clamping element described above. In various embodiments, Figure 3H-3J The example shown can be a general clamping element Figure 3E-3G The example shown is just one example; however, different clamping circuits may be used in other implementations.

[0051] Figure 3H The diagram shows a source S, a gate G, and a field plate 321 (e.g., as described above). Figure 1 The field plate 142 and the drain voltage V D The drain extension transistor T of the drain D has a source shunt bias circuit 320. The gate driver 322 provides a gate drive voltage signal V to the gate G. G The output 323, and the gate driver 322 via having a gate drive supply voltage V DRV The gate drive supply is powered. Clamping circuit 324 (e.g., Figure 3E-3G (Each example shown or others) has a first terminal A coupled to a circuit node 325 coupled to a field plate 321, and a second terminal C coupled to a gate drive supply. The first terminal A is configured to provide a field plate bias voltage signal V to the field plate 321. F The gate drive supply voltage (e.g., V) is applied to the clamping voltage. F =V CLAMP +V DRV ). In use Figure 3E In an embodiment of the clamping element of 3F, the anode of the Zener diode of the source shunt bias circuit 320 is coupled to the gate drive supply voltage V. DRV When using Figure 3G In the implementation of the clamping element, the anode of the Zener diode in the source shunt bias circuit 320 is through Figure 3G Resistor 318 is coupled to the gate drive supply voltage V. DRV Furthermore, the source of transistor 319 is connected to the gate drive supply voltage V at the second terminal C. DRV .

[0052] Figure 3I The diagram shows a source S, a gate G, and a field plate 331 (e.g., as described above). Figure 1 The field plate 142 and the drain voltage V D The drain extension transistor T of the drain D has a source shunt bias circuit 330. The gate driver 332 provides a gate drive voltage signal V to the gate G. G The output is 333. Clamping circuit 334 (e.g., Figure 3E-3G(Either the example shown or others) has a first terminal A coupled to a circuit node 335 coupled to the field plate 331, and a second terminal C coupled to the source S. The first terminal A is configured to provide a field plate bias voltage signal V to the field plate 331. F Relative to the source voltage V S Clamping voltage V CLAMP When using Figure 3E In an embodiment of the clamping element of 3F, the anode of the Zener diode in the source shunt bias circuit 330 is coupled to the source SV. DRV When using Figure 3G In the implementation of the clamping element, the anode of the Zener diode in the shunt bias circuit 330 is through Figure 3G Resistor 318 is coupled to the source S of transistor 319, and the source of transistor 319 is connected to the source S of transistor T.

[0053] Figure 3J The diagram shows a source S, a gate G, and a field plate 341 (e.g., as described above). Figure 1 The field plate 142 and the drain voltage V D The drain extension transistor T of the drain D has a source shunt bias circuit 340. The gate driver 342 provides a gate drive voltage signal V to the gate G. G The output is 343. Clamping circuit 344 (e.g., Figure 3E-3G (Each example shown or others) has a first terminal A coupled to a circuit node 345 coupled to a field plate 341, and a second terminal C coupled to a gate driver output 343. The first terminal A is configured to provide a field plate bias voltage signal V to the field plate 341. F Apply a gate voltage (e.g., V) to the clamping voltage. F =V CLAMP +V G ). In use Figure 3E In an embodiment of the clamping element or 3F, the anode of the Zener diode in the source shunt bias circuit 340 is coupled to the gate driver output 343. When using... Figure 3G In the implementation of the clamping element, the anode of the Zener diode in the source shunt bias circuit 340 is through Figure 3G Resistor 318 is coupled to gate driver output 343, and source of transistor 319 is connected to gate driver output 343 at second terminal C.

[0054] Figure 3K The diagram shows a source S, a gate G, and a field plate 351 (e.g., as described above). Figure 1 The field plate 142 and the drain voltage V D The active source shunt bias circuit 350 of the drain extension transistor T of the drain D, wherein the shunt current source is pulled up to the device input voltage V INThe gate driver 352 provides a gate drive voltage signal V to the gate G. G The output is 353. Clamping circuit 354 (e.g., Figure 3E-3G (Either the example shown or others) has a first terminal A coupled to a circuit node 355 coupled to a field plate 351, and a second terminal C coupled to a gate drive supply. A current source 356 is coupled to the circuit node 355 and has a voltage V. IN (For example, the input voltage of the semiconductor device 100, such as the input signal of a DC-DC converter) between the input nodes 357 of the circuit input. IN Voltage V relative to source S S It is positive, and V IN Relative to the gate drive supply voltage V DRV Positive. The first terminal A is configured to provide a field plate bias voltage signal V to the field plate 351. F , is the clamping voltage V CLAMP Apply gate drive supply voltage V DRV (For example, V) F =V CLAMP +V DRV ). In use Figure 3E In an embodiment of the clamping element or 3F, the anode of the Zener diode of the source shunt bias circuit 350 is coupled to the gate drive supply (e.g., having a gate drive supply voltage V). DRV ). In use Figure 3G In the implementation of the clamping element, the anode of the Zener diode in the source shunt bias circuit 350 is through Figure 3G Resistor 318 is coupled to the gate drive supply, and the source of transistor 319 is connected to the gate drive supply at the second terminal C.

[0055] Figure 3L The diagram shows a source S, a gate G, and a field plate 351 (e.g., as described above). Figure 1 The field plate 142 and the drain voltage V D The drain extension transistor T of the drain D has an active source shunt bias circuit 360, wherein a reference resistor voltage divider is provided between the source S and the drain D. The gate driver 362 provides a gate drive voltage signal V to the gate G. G The output is 363, and it is supplied with a gate drive voltage V. DRV The gate drive supplies power to the node. Clamping circuit 364 (e.g., Figure 3E-3G(Each example shown or others) has a first terminal A coupled to a circuit node 365 coupled to a field plate 361, and a second terminal C coupled to a gate drive supply. The resistor divider circuit includes a first resistor 366 having a first terminal coupled to the transistor drain D and a second terminal coupled to the circuit node 365 (e.g., the first terminal A of the clamping circuit 364). The resistor divider circuit also includes a second resistor 367 having a first terminal coupled to the circuit node 365 and a second terminal coupled to the transistor source S.

[0056] The first terminal A of the clamping circuit is configured to provide a field plate bias voltage signal V to the field plate 361. F , is the clamping voltage V CLAMP Apply gate drive supply voltage V DRV (For example, V) F =V CLAMP +V DRV In one example, when the maximum rated drain-source voltage is approximately equal to the rated breakdown voltage of transistor T, the values ​​of the first resistor 366 and the second resistor 367 are designed to correspond to approximately V. CLAMP +V DRV Field plate bias voltage signal V F When using Figure 3E In an embodiment of the clamping element or 3F, the anode of the Zener diode of the source shunt bias circuit 360 is coupled to the gate drive supply (e.g., having a gate drive supply voltage V). DRV ). In use Figure 3G In the implementation of the clamping element, the anode of the Zener diode in the source shunt bias circuit 360 is through Figure 3G Resistor 318 is coupled to the gate drive supply, and the source of clamping circuit transistor 319 is connected to the gate drive supply at the second terminal C. In other embodiments, the second terminal of the second resistor 367 may be coupled to a circuit node other than the source S of transistor T, and / or the first terminal of the first resistor 366 may be coupled to another circuit node other than the drain D of transistor T.

[0057] Figure 3M and 3N This illustrates the biasing of the drain extension transistor T (e.g., the one above). Figure 2 Bias circuits 370 and 380 are provided for corresponding series and parallel clamping circuit implementations of multiple field plates. These examples illustrate individual clamping circuits (e.g., Figure 3M 374 and Figure 3N In various implementation schemes, 384) can be... Figure 3E-3G Any example shown or other clamping circuits or combinations thereof. Figure 3M and 3NA corresponding transistor T with three field plates is shown, each at a different field plate bias voltage; however, other embodiments may have any suitable integer number "n" field plates and associated bias voltages, where n is greater than 1. In other embodiments, a hybrid stacked / parallel clamping structure may be used to generate monotonically increasing field plate bias voltages for two or more field plates of a drain extension transistor.

[0058] Figure 3M The diagram illustrates a bias circuit 370 for clamping clamping of clamping circuits 374 in series or stacked configurations for use in active source shunt plate stack clamping. The bias circuit 370 comprises a series arrangement (e.g., stacked) of clamping circuits 374. Each clamping circuit 374 may be... Figure 3E-3G The example shown is an example or other clamping circuit or combination thereof. The first clamping circuit 374 has a first terminal A connected to a first instance of an output node 375 coupled to a first field plate 371, and coupled to a reference voltage V. A1 The second terminal C of the reference node 376, wherein the reference voltage is relative to the voltage V of the source S. S It can be positive, or it can be the source voltage. For example, reference node 376 can be connected to the source S, the gate driver supply node (e.g., at the gate driver supply voltage V). DRV (As discussed above), a gate drive voltage signal V is provided to the gate G. G The gate driver output node 373, or other suitable reference node of the semiconductor device. The first clamping circuit 374 provides a controlled voltage at the first output node instance 375 to control the first field plate bias voltage signal V at the first field plate 371. F1 Its clamping is at the reference voltage V A1 Apply the first clamping voltage V CLAMP1 (For example, V) F1 =V CLAMP1 +V A1 ).

[0059] In this example, the second clamping circuit 374 has a connection to a signal having a second field plate bias voltage V. F2 The second terminal A of the output node 375, coupled to the second field plate 371, corresponds to the first terminal A of the second instance. The second terminal C of the second clamping circuit 374 is coupled to the first field plate bias voltage signal V. F1 The first terminal A of the first clamping circuit 374. The second clamping circuit 374 provides a controlled voltage at the second output node instance 375 to control the second field plate bias voltage signal V at the second field plate 371. F2 Its clamping is based on the bias voltage signal V of the first field plate. F1 Apply the second clamping voltage V CLAMP2 (For example, V) F2 =VF1 +V CLAMP2 ).

[0060] Any other clamping circuits 374 included are connected in a similar manner to the "nth" or final clamping circuit 374, which provides a controlled voltage at the corresponding output node instance 375 to control the corresponding field plate bias voltage signal V at the corresponding final field plate 371. Fn Finally, the field plate 371 is clamped at the previous field plate bias voltage signal V. Fn-1 The voltage plus the corresponding nth clamping voltage V CLAMPn (For example, V) Fn =V Fn-1 +V CLAMPn In other embodiments, the stacked or series-connected bias circuitry 370 may further include a pull-up circuitry system (e.g., a resistor or current source), a pull-down circuitry system (e.g., a resistor or current source), one or more resistive voltage divider circuits referenced by suitable nodes (e.g., drain D and source S), or a combination thereof (not shown).

[0061] Figure 3N The diagram shows a biased drain extension transistor T (e.g., above). Figure 2 The example includes a bias circuit 380 with parallel clamping circuit implementation for multiple field plates. This example contains n instances of clamping circuits 384 for clamping bias of an active source shunt field plate. Each clamping circuit 384 can be... Figure 3E-3G The example shown or other clamping circuits or combinations thereof. Figure 3N The first clamping circuit 384 has a first terminal A connected to a first instance of an output node 385 coupled to the first field plate 381. The first clamping circuit 384 also has a connection to a first reference voltage V. A1 The second terminal C of the first reference node 386, wherein the reference voltage is relative to the voltage V of the source S. S It can be positive, or it can be the source voltage. For example, reference node 386 can be connected to the source S, the gate driver supply node (e.g., at the gate driver supply voltage V). DRV (As discussed above), a gate drive voltage signal V is provided to the gate G. G The gate driver output node 383, or other suitable reference node of the semiconductor device. The first clamping circuit 384 provides a controlled voltage at the first output node instance 385 to control the first field plate bias voltage signal V at the first field plate 381. F1 Its clamping is at the reference voltage V A1 Apply the first clamping voltage V CLAMP1 (For example, V) F1 =V CLAMP1 +V A1 ).

[0062] Figure 3N The second clamping circuit 384 in the middle has a connection to a second field plate bias voltage signal V. F2 The second terminal A of the output node 385, coupled to the second field plate 381, corresponds to the first terminal A of the second instance. The second terminal C of the second clamping circuit 384 is coupled to a circuit having a second reference voltage V. A2 The second reference node 386, the second reference voltage can be relative to the voltage V of the source S. S It can be positive, or it can be the source voltage. For example, reference node 386 can be connected to the source S, the gate driver supply node (e.g., at the gate driver supply voltage V). DRV (As discussed above), a gate drive voltage signal V is provided to the gate G. G The gate driver output node 383, or other suitable reference node of the semiconductor device. The second clamping circuit 384 provides a controlled voltage at the second output node instance 385 to control the second field plate bias voltage signal V at the second field plate 381. F2 Its clamping is at the second reference voltage V A2 Apply the second clamping voltage V CLAMP2 (For example, V) F2 =V A2 +V CLAMP2 V F2 >V F1 Any other clamping circuits 384 included are connected in a similar manner to the "nth" or final clamping circuit 384, which provides a controlled voltage at the corresponding output node instance 385 to control the corresponding field plate bias voltage signal V at the corresponding final field plate 381. Fn Finally, the field plate 381 is clamped at the nth reference voltage V. An Apply the corresponding nth clamping voltage V CLAMPn voltage (e.g., V) Fn =V Fn-1 +V CLAMPn In other embodiments, the parallel bias circuit 380 may further include a pull-up circuit system (e.g., a resistor or current source), a pull-down circuit system (e.g., a resistor or current source), one or more resistive voltage divider circuits referenced by suitable nodes (e.g., drain D and source S), or a combination thereof (not shown).

[0063] Figure 3-3M Some of the above-described bias circuit examples have an output coupled to the field plate and a gate drive circuit (e.g., Figure 3 , 3HThe bias circuit examples have bias inputs (e.g., 3J, 3L) and some bias circuit examples have an output coupled to the field plate and a bias input coupled to the gate drive circuitry (e.g., the gate driver 192 above). In some example embodiments, the diode-based bias circuit includes a clamping circuit having a diode coupled to the field plate. Specific examples (e.g., Figure 3 , 3G -3N) may have a field plate bias circuit with one or more additional transistors.

[0064] refer to Figure 4-4G Other example bias circuits have drain shunt characteristics and arrangements. Examples in these figures illustrate implementations with dual-diode clamping circuits (e.g., those described above). Figure 3D In other implementation schemes, Figure 4-4G The various clamping circuits in it can be Figure 3E-3G The example shown or other clamping circuits or combinations thereof.

[0065] Figure 4 The diagram shows a source S, a gate G, and a single field plate 401 (e.g., as described above). Figure 1 The field plate 142 and the drain voltage V D An example of an active drain shunt resistive pull-down bias circuit 400 is shown for the drain extension transistor T with drain D. The bias circuit 400 has a clamping voltage V. CLAMP The clamping circuit 404 includes a first terminal A and a second terminal C connected to the drain D. The clamping circuit 404 includes a junction diode 407 having an anode coupled to the first terminal A of the clamping circuit 404. A pull-down resistor 406 is coupled between the field plate 401 and the source S of the transistor T. The pull-down resistor 406 can be implemented in many ways (e.g., a current source, from V...). D To V S (e.g., a resistor divider). The cathode of the junction diode 407 is connected to the cathode of the Zener diode 408 in the clamping circuit 404, and the anode of the Zener diode 408 is connected to the second terminal C. In other embodiments, the clamping circuit 404 may be as described above. Figure 3E-3G Any example shown or other clamping circuits or combinations thereof. Gate driver 402 has the function of providing a gate drive voltage signal V to the gate G. G Output 403 (e.g., gate voltage). The second terminal C of clamping circuit 404 is configured to provide a field plate bias voltage signal V to the circuit node coupled to field plate 401. F During power supply operation, the clamping circuit 404 controls the clamping voltage V between the first terminal A and the second terminal C. CLAMP And the field plate bias voltage signal V F It is a drain voltage reduction clamp (e.g., V). F =V D-V CLAMP ).

[0066] Figure 4A The curve in the figure shows Figure 4 The drain voltage V of transistor T in D Field plate bias voltage signal V F and gate drive voltage signal V G Voltage V relative to source S S The figure illustrates the change in gate voltage V at gate driver 402. G Switching to a low drain voltage V D At its maximum value, the transistor drain-source voltage (V) during the operation of bias circuit 400 DS The field plate bias voltage signal V drifts from zero to its maximum value (e.g., the rated breakdown voltage of transistor T) and then back to zero. In this example, the field plate bias voltage signal V... F Starts slightly below V D -V CLAMP The value, and the drain voltage V D During the upward drift, it rises to a steady-state value V. F =V D -V CLAMP .

[0067] Figure 4B The diagram shows a source S, a gate G, and a single field plate 411 (e.g., as described above). Figure 1 The field plate 142 and the drain voltage V D Another example of a drain extension transistor T with drain D is an active drain shunt resistive pull-down bias circuit 410. Bias circuit 410 has a clamping voltage V. CLAMP The clamping circuit 414 includes a first terminal A and a second terminal C connected to the drain D. The clamping circuit 414 includes a first terminal A coupled to the clamping circuit 414 and a terminal C having an input voltage V. IN The junction diode 418 is the anode of the input 417 of the semiconductor device. A pull-down resistor 416 is coupled between the field plate 411 and the source S of the transistor T. The pull-down resistor 416 can be implemented in many ways (e.g., a current source, from V...). D To V S (e.g., a resistor divider). The cathode of the junction diode 418 is connected to the cathode of the Zener diode 419 in the clamping circuit 414, and the anode of the Zener diode 419 is connected to the second terminal C. In other embodiments, the clamping circuit 414 may be as described above. Figure 3E-3G Any example shown or other clamping circuits or combinations thereof. Gate driver 412 has the function of providing a gate drive voltage signal V to the gate G. GOutput 413 (e.g., gate voltage). The second terminal C of clamping circuit 414 is configured to provide a field plate bias voltage signal V to the circuit node coupled to field plate 411. F During power supply operation, the clamping circuit 414 controls the clamping voltage V between the first terminal A and the second terminal C. CLAMP And the field plate bias voltage signal V F It is the input voltage minus the clamping voltage (e.g., V). F =V IN- V CLAMP ).

[0068] Figure 4C The diagram shows a source S, a gate G, and a single field plate 421 (e.g., above). Figure 1 The field plate 142 and the drain voltage V D Another example of a drain extension transistor T with drain D is an active drain shunt resistive pull-down bias circuit 420. Bias circuit 420 has a clamping voltage V. CLAMP The clamping circuit 424 includes a first terminal A and a second terminal C connected to an input 427. The clamping circuit 424 includes a first terminal A coupled to the clamping circuit 424 and a second terminal C having an input voltage V. IN The Zener diode 429 is the cathode of the input 427 of the semiconductor device. A pull-down resistor 426 is coupled between the field plate 421 and the source S of the transistor T. The pull-down resistor 426 can be implemented in many ways (e.g., a current source, from V...). D To V S (e.g., a resistor divider). The anode of the Zener diode 429 is connected to the second terminal C of the clamping circuit 424. In other embodiments, the clamping circuit 424 may be as described above. Figure 3E-3G Any example shown or other clamping circuits or combinations thereof. Gate driver 422 has the function of providing a gate drive voltage signal V to the gate G. G Output 423 (e.g., gate voltage). The second terminal C of clamping circuit 424 is configured to provide a field plate bias voltage signal V to the circuit node coupled to field plate 421. F During power supply operation, the clamping circuit 424 controls the clamping voltage V between the first terminal A and the second terminal C. CLAMP And the field plate bias voltage signal V F It is the input voltage minus the clamping voltage (e.g., V). F =V IN- V CLAMP ).

[0069] Figure 4D The diagram shows a source S, a gate G, and a single field plate 431 (e.g., above). Figure 1 The field plate 142 and the drain voltage VD An example of an active drain shunt current source pull-down bias circuit 430 for a drain-extended transistor T with drain D. Bias circuit 430 has a clamping voltage V. CLAMP The clamping circuit 434 includes a first terminal A and a second terminal C connected to the drain D. The clamping circuit 434 includes a junction diode 437 having an anode coupled to the first terminal A of the clamping circuit 434. A current source 436 is coupled between the field plate 431 and the source S of the transistor T. The current source 436 can be implemented in many ways (e.g., Figure 4 The resistor shown in the figure, from V D To V S (e.g., a resistor divider). The cathode of the junction diode 437 is connected to the cathode of the Zener diode 438 in the clamping circuit 434, and the anode of the Zener diode 438 is connected to the second terminal C. In other embodiments, the clamping circuit 434 may be as described above. Figure 3E-3G Any example shown or other clamping circuits or combinations thereof. Gate driver 432 has the capability to provide a gate drive voltage signal V to the gate G. G Output 433 (e.g., gate voltage). The second terminal C of clamping circuit 434 is configured to provide a field plate bias voltage signal V to the circuit node coupled to field plate 431. F During power supply operation, the clamping circuit 434 controls the clamping voltage V between the first terminal A and the second terminal C. CLAMP And the field plate bias voltage signal V F It is the drain voltage minus the clamping voltage (e.g., V). F =V D -V CLAMP ).

[0070] Figure 4E The diagram shows a source S, a gate G, and a single field plate 441 (e.g., above). Figure 1 The field plate 142 and the drain voltage V D An example of an active shunt drain-source voltage (V) of a drain-extended transistor T with drain D as the drain terminal. DS Reference resistor voltage divider bias circuit 440. Bias circuit 440 has a clamped voltage V. CLAMP The clamping circuit 444 includes a first terminal A and a second terminal C connected to the drain D. The clamping circuit 444 includes a junction diode 447 having an anode coupled to the first terminal A of the clamping circuit 444. The cathode of the junction diode 447 is connected to the cathode of a Zener diode 448 of the clamping circuit 444, and the anode of the Zener diode 448 is connected to the second terminal C. In other embodiments, the clamping circuit 444 may be as described above. Figure 3E-3GAny example shown, or other clamping circuits or combinations thereof. The resistor divider includes a first resistor 445 and a second resistor 446. The first resistor 445 has a first terminal coupled to the drain D and a second terminal coupled to the field plate 441 of the transistor T. The second resistor 446 has a first terminal coupled to the field plate 441 and a second terminal coupled to the source S of the transistor T. The gate driver 442 provides a gate drive voltage signal V to the gate G. G Output 443 (e.g., gate voltage). The second terminal C of clamping circuit 444 is configured to provide a field plate bias voltage signal V to the circuit node coupled to field plate 441. F During power supply operation, the clamping circuit 444 controls the clamping voltage V between the first terminal A and the second terminal C. CLAMP And the field plate bias voltage signal V F It is the drain voltage minus the clamping voltage (e.g., V). F =V D -V CLAMP ).

[0071] Figure 4F and 4G The diagram shows a biased drain extension transistor T (e.g., above). Figure 2 Bias circuits 450 and 460 for multiple field plates having corresponding series (e.g., stacked) and parallel clamping circuit implementations. These examples illustrate individual clamping circuits (e.g., Figure 4F 458 and Figure 4G In 468), in various implementation schemes, it can be Figure 3E-3G Any example shown or other clamping circuits or combinations thereof. Figure 4F and 4G A corresponding transistor T with three field plates is shown, each at a different field plate bias voltage; however, other embodiments may have any suitable integer number "n" field plates and associated bias voltages, where n is greater than 1. In other embodiments, a hybrid stacked / parallel clamping structure may be used to generate monotonically increasing field plate bias voltages for two or more field plates of a drain extension transistor.

[0072] Figure 4F The clamping circuit 454 is shown in series or stacked arrangement for use with a source S, a gate G (e.g., also labeled 453), a field plate 451, and a drain voltage V. DThe bias circuit 450 clamps the active drain shunt field plate of the drain extension transistor T, which is connected to the drain of the drain D. The bias circuit 450 includes clamping circuits 454. Each clamping circuit 454 has a junction diode 457 and stacked or series-connected Zener diodes 458. The stacked clamping circuit 454 has a first terminal coupled to the anode of the junction diode 457 and connected to the drain D of the transistor T. The clamping circuit 454 has an integer number "n" second terminals coupled to corresponding instances of circuit nodes 455 connected to corresponding field plates 451. The first (e.g., top) Zener diode 458 has a cathode coupled to the cathode of the junction diode 457 and an anode coupled to the top field plate 451. The remaining series-connected Zener diodes 458 have an anode connected to the corresponding field plate 451 and a cathode coupled to the upper Zener diode. Each Zener diode has a corresponding clamping voltage (e.g., V). CLAMP1 ... V CLAMPn And a series of field plates 451 are at the corresponding field plate bias voltage V. F1 ... V Fn Lower bias. The uppermost field plate 455 (e.g., closest to the drain D) has a field plate bias voltage V. Fn , is the drain voltage V D Subtract the voltage drop across the junction diode 457 and the uppermost Zener voltage V. CLAMPn Furthermore, each individual field plate 451 is biased at a corresponding field plate bias voltage that is lower than the clamping voltage of the next higher field plate 451 corresponding to the clamping voltage of the Zener diode.

[0073] Figure 4G This diagram illustrates a biasing configuration having a source S, a gate G (e.g., also labeled 463), a field plate 461, and a drain voltage V. D The drain extension transistor T of the drain D (e.g., the one mentioned above) Figure 2 A bias circuit 460 with parallel clamping circuit implementation for multiple field plates 461. The bias circuit 460 includes a clamping circuit 464 having a junction diode 467 and a Zener diode 468 respectively coupled between the junction diode 467 and a corresponding one in the field plate 461. The clamping circuit 464 has a first terminal coupled to the anode of the junction diode 467 and connected to the drain D of the transistor T. The clamping circuit 464 has an integer number "n" second terminals 465 coupled to the anodes of the corresponding field plate 461 and the corresponding Zener diode 468. Each Zener diode 468 has a cathode coupled to the cathode of the junction diode 467. In one embodiment, each Zener diode 468 has a different monotonically increasing Zener voltage and associated clamping voltage (e.g., V). CLAMP1 ... V CLAMPn ), where the Zener voltage and clamping voltage decrease monotonically (e.g., V). CLAMP1 >VCLAMP2 >……、V CLAMPn This causes the bias voltage of the field plate 461 to have a monotonically increasing voltage value (e.g., V) in the direction from the source S to the drain D. F1 <V F2 <……、V Fn ).

[0074] Figure 5 The diagram shows a source S, a gate G, and a single field plate 501 (e.g., as described above). Figure 1 The field plate 142 and the drain voltage V D Example of a mixed source and drain shunt current source pull-down bias circuit 500 for a drain-extended transistor T with drain D. Bias circuit 500 has a first clamping voltage V. CLAMP-DRN Second clamping voltage V CLAMP-SRC The clamping circuit 504 includes a junction diode 507 having an anode coupled to the drain D, a first Zener diode 508 coupled between the junction diode 507 and a field plate 501 of the transistor T, and a second Zener diode 509 coupled between the field plate 501 and the source S. The cathode of the junction diode 507 is connected to the cathode of the first Zener diode 508 of the clamping circuit 504. The anode of the first Zener diode 508 is connected to the field plate 501. The cathode of the second Zener diode 509 is connected to the field plate 501, and the anode of the second Zener diode 509 is connected to the source S. The gate driver 502 provides a gate drive voltage signal V to the gate G. G Output 503 (e.g., gate voltage). Clamping circuit 504 is configured to provide field plate bias voltage signal V to field plate 501. F .

[0075] Also refer to Figure 6-6K Other examples provide methods for biasing a source S, a gate G, and one or more field plates (e.g., as described above). Figure 1 The field plate 142 and the drain voltage V D A capacitive shunt bias circuit for one or more field plates of the drain extension transistor T, with drain D as the base. In one or more examples, the bias circuit is coupled to one or more field plates and includes a reset circuit operated by a suitable control circuitry (not shown) to coordinate the timing of actuation relative to the transistor gate G. In these or other examples, the bias circuit includes one or more capacitors. In these or other examples, the bias circuit may include a pull-up circuit with a resistor or current source coupled to the drain D. In these or other examples, the bias circuit may include a pull-down circuit with a resistor or current source coupled to the source S of the drain extension transistor T or a resistor divider circuit.

[0076] Figure 6The diagram shows a source S, a gate G, and a single field plate 601 (e.g., as described above). Figure 1 The field plate 142 and the drain voltage V D An example of a drain-extended transistor T with drain D is an active-source shunt bias circuit 600. Gate driver 602 (e.g., gate driver 192 above) provides a gate drive voltage signal V to the gate G. G Output 603 (e.g., gate voltage). Bias circuit 600 includes an output 603 configured to provide a field plate bias voltage signal V to field plate 601. F The clamping circuit in this example includes a capacitor 604 coupled between the field plate 601 and the source S of the transistor T, and a reset circuit 605 (e.g., a switch) connected in parallel with the capacitor 604. The bias circuit 600 also includes a resistor divider connected in parallel with the reset circuit 605 and the capacitor 604, having: a first resistor 607 having a first terminal coupled to the drain D and a second terminal coupled to the field plate 601; and a second resistor 608 having a first terminal coupled to the field plate 601 and a second terminal coupled to the source S of the transistor T. In one example, the reset circuit 605 is controlled in a manner synchronized with the gate driver 602, for example, closing with a fixed timing relationship relative to a gate driver signal turning on the transistor T (e.g., connecting the field plate 601 to the source S), and then opening the reset circuit 605 to allow the capacitor 604 to charge with a fixed timing relationship relative to a gate drive signal turning off the transistor T.

[0077] Figure 6A The curve shown in the figure represents the gate voltage V at the gate driver 602. G Switching to a low drain voltage V D At its maximum value, during the operation of bias circuit 600, the transistor drain-source voltage (V DS During a drift period from zero to its maximum value (e.g., the rated breakdown voltage of transistor T) and then back to zero, the drain voltage V... D Field plate bias voltage signal V F and gate drive voltage signal V G Voltage V relative to source S S The change in the field plate bias voltage signal V. In this example, the field plate bias voltage signal V. F It starts at approximately zero and at the drain voltage V D During the upward drift, it rises to a steady-state value V. F In one example, when V D Approaching 0V (e.g., by monitoring V) DS or V G When ), the reset circuit 605 will reset the field plate bias voltage signal V. FInitialized to 0V. Capacitor C of capacitor 604. SHUNT It can be selected to make V DS From 0V to rated breakdown voltage V BV The transition will change the voltage of the field plate 601 from 0V to the target field plate bias voltage V. F The capacitor 604 can be formed using a metal system of a semiconductor device or any suitable technique. In other embodiments, the field plate 601 can alternatively be reset to another voltage, such as V. S V G Or has a capacitance C SHUNT Another supply (e.g., called V) that corresponds to any suitable change S In these or other embodiments, the reset circuit 605 may be omitted, for example, if the resistive voltage divider (e.g., resistors 607 and 608) is well matched such that when V DS = Rated breakdown voltage V BV At that time, V FS =V FS(TARGET) Alternative topologies are possible, for example, hybrid active and capacitive circuits, where the reset circuit closes after the gate G is turned on and the reset circuit 605 opens before the gate G is turned off.

[0078] Figure 6B The diagram shows a source S, a gate G, and a single field plate 611 (e.g., as described above). Figure 1 The field plate 142 and the drain voltage V D An example of a drain-extended transistor T with drain D is an active-source shunt bias circuit 610. Gate driver 612 (e.g., gate driver 192 above) provides a gate drive voltage signal V to gate G. G The output 613 (e.g., gate voltage) and via a gate drive supply voltage V DRV The gate drive supply is powered. Bias circuit 610 includes components configured to provide a field plate bias voltage signal V to field plate 611. F The clamping circuit. In this example, the clamping circuit includes a capacitor 614 coupled between the field plate 611 and the source S of the transistor T, and a connection between the capacitor 614 and the gate drive supply to reset the field plate 611 to the gate drive voltage V. DRV A reset circuit 615 (e.g., a switch), wherein the reset circuit is configured to close after the gate G is turned on, and the reset circuit 615 is configured to open before the gate G is turned off.

[0079] Figure 6C The diagram shows a source S, a gate G, and a single field plate 621 (e.g., as described above). Figure 1 The field plate 142 and the drain voltage V DAn example of a drain-extended transistor T with drain D is an active-source shunt bias circuit 620. Gate driver 622 (e.g., gate driver 192 above) provides a gate drive voltage signal V to the gate G. G The output 623 (e.g., gate voltage) and via a gate drive supply voltage V DRV The gate drive supply is powered. Bias circuit 620 includes components configured to provide a field plate bias voltage signal V to field plate 621. F The clamping circuit. In this example, the clamping circuit includes a capacitor 624 coupled between the field plate 621 and the gate drive supply, and a circuit connected in parallel with the capacitor 624 to reset the field plate 621 to the gate drive voltage V. DRV A reset circuit 625 (e.g., a switch), wherein the reset circuit is configured to close after the gate G is turned on, and the reset circuit 625 is configured to open before the gate G is turned off.

[0080] Figure 6D The diagram shows a source S, a gate G, and a single field plate 631 (e.g., above). Figure 1 The field plate 142 and the drain voltage V D An example of a drain-extended transistor T with drain D is an active-source shunt bias circuit 630. Gate driver 632 (e.g., gate driver 192 above) provides a gate drive voltage signal V to gate G. G The output 633 (e.g., gate voltage) is provided by a gate drive supply voltage V. DRV The gate drive supply is powered. Bias circuit 630 includes components configured to provide a field plate bias voltage signal V to field plate 631. F The clamping circuit. In this example, the clamping circuit includes a capacitor 634 coupled between the field plate 631 and the source S of the transistor T, and a circuit connected in parallel with the capacitor 634 to reset the field plate 631 to the source voltage V. S A reset circuit 635 (e.g., a switch), wherein the reset circuit is configured to close after the gate G is turned on, and the reset circuit 635 is configured to open before the gate G is turned off.

[0081] Figure 6E The diagram shows a source S, a gate G, and a single field plate 641 (e.g., above). Figure 1 The field plate 142 and the drain voltage V D An example of a drain-extended transistor T with drain D is an active-source shunt bias circuit 640. Gate driver 642 (e.g., gate driver 192 above) provides a gate drive voltage signal V to gate G. G The output 643 (e.g., gate voltage) and via a gate drive supply voltage V DRVThe gate drive supply is powered. Bias circuit 640 includes components configured to provide a field plate bias voltage signal V to field plate 641. F The clamping circuit. In this example, the clamping circuit includes a capacitor 644 coupled between the field plate 641 and the gate G of the transistor T, and a circuit connected in parallel with the capacitor 644 to reset the field plate 641 to the gate voltage V. G A reset circuit 645 (e.g., a switch), wherein the reset circuit is configured to close after the gate G is turned on, and the reset circuit 645 is configured to open before the gate G is turned off.

[0082] Now for reference Figure 6F and 6G , Figure 6F The diagram shows a source S, a gate G, and a single field plate 651 (e.g., above). Figure 1 The field plate 142 and the drain voltage V D An example of a drain-extended transistor T with drain D is an active-source shunt bias circuit 650. Gate driver 652 (e.g., gate driver 192 above) provides a gate drive voltage signal V to the gate G. G The output 653 (e.g., gate voltage) and via a gate drive supply voltage V DRV The gate drive supply is powered. Bias circuit 650 includes components configured to provide a field plate bias voltage signal V to field plate 651. F The clamping circuit. In this example, the clamping circuit includes a capacitor C coupled between the field plate 651 and the source S of the transistor T. SHUNT The capacitor 654. The clamping circuit includes a reset circuit 655 (e.g., a switch) connected in parallel with the capacitor 654, having a first reset switch RESET1 connected between the field plate 651 and the gate drive supply, and a second reset switch RESET2 connected between the field plate 651 and the source S of the transistor T.

[0083] Figure 6G The curve in Figure 657 shows the drain voltage V. D Field plate bias voltage signal V F and gate drive voltage signal V G Compared to Figure 6F The source voltage V of transistor T in the middle S The change. Figure 657 shows the gate voltage V being changed in the gate driver 652. G Switching to a low drain voltage V D At its maximum value, the transistor drain-source voltage (V) during the operation of bias circuit 650 DS This is an example of a drift from zero to a maximum value (e.g., the rated breakdown voltage of transistor T) and then back to zero. In this example, the field plate bias voltage signal V...F It starts at approximately zero and at the drain voltage V D During the upward drift, it rises to a steady-state value V. F In one example, the reset circuit 655 is controlled to operate at V. D Approaching 0V (e.g., by monitoring V) DS or V G When the first reset switch RESET1 is closed, the field plate bias voltage signal V is reset. F Initialized to gate drive supply voltage V DRV Then disconnect the first reset switch RESET1 (in Figure 6G In Figure 657, curve 658 becomes lower, so that capacitor 654 is connected to the gate drive supply voltage V. DRV Disconnect. In this example, the reset control circuitry (not shown) then closes the second reset switch RESET2. Figure 6G Curve 659 in the diagram is used to discharge the capacitor and bias the field plate voltage signal V relative to the source S of transistor T. F The voltage is reset to 0V, after which the second reset switch RESET2 is turned off again. This example allows the field plate bias voltage signal V to be applied. F When transistor T is in the ON state, it is approximately at the gate drive supply voltage V. DRV Simultaneously, use the ratio to reset to V DRV The method uses a smaller capacitor, 654, whose capacitance C SHUNT It is also relatively small, in which the first reset switch RESET1 will V F Drive to V DRV The second reset switch RESET2 only operates when the gate voltage V G Before descending, V F Reset to 0V. When V G When V is low, both reset switches are open. F Guided by capacitor 654.

[0084] Figure 6H The diagram shows a source S, a gate G, and a single field plate 661 (e.g., as described above). Figure 1 The field plate 142 and the drain voltage V D An example capacitive shunt current source bias circuit 660 with drain clamping is shown for the drain extension transistor T of the drain D. The gate driver 662 provides a gate drive voltage signal V to the gate G. GOutput 663 (e.g., gate voltage). Bias circuit 660 includes clamping circuit 665 coupled to drain D and field plate 661. Clamping circuit 665 includes junction diode 667 having an anode and cathode coupled to drain D, and Zener diode 668. The cathode of junction diode 667 is connected to the cathode of Zener diode 668, and the anode of Zener diode 668 is connected to field plate 661. Bias circuit 660 also includes a capacitor C. SHUNT A capacitor 664 is coupled between the field plate 661 and the source S of the transistor. A pull-down circuit 669 is coupled between the field plate 661 and the source S, and may include a reset circuit system (e.g., a switch) coupled between the field plate 661 and the source S. In another embodiment, the reset switch may be omitted. In one embodiment, the pull-down circuit 669 has a pull-down resistor having a first terminal coupled to the field plate 661 and a second terminal coupled to the source S. In another embodiment, the pull-down circuit 669 includes a current source coupled between the field plate 661 and the source S. A clamping circuit 665 is configured to provide a field plate bias voltage signal V to the field plate 661. F In one example, the capacitance C of capacitor 664 SHUNT The target capacitance of the field plate 661 is greater than or equal to 0V, so that at C SHUNT When approaching infinity, the bias voltage V of the field plate F Maintain stability.

[0085] Figure 6I The diagram shows a source S, a gate G, and a single field plate 671 (e.g., as described above). Figure 1 The field plate 142 and the drain voltage V D An example capacitive source shunt current pull-up bias circuit 670 with source clamping is shown for the drain extended transistor T of the drain D. The gate driver 672 provides a gate drive voltage signal V to the gate G. G Output 673 (e.g., gate voltage). Bias circuit 670 also includes a capacitor C. SHUNT A capacitor 674 is provided, and capacitor 674 is coupled between field plate 671 and the source S of transistor. Bias circuit 670 has clamping circuit 678, which has a Zener diode having an anode coupled to the source S and a cathode coupled to field plate 671. In one example, clamping circuit 678 has a coupling between field plate 671 and an input voltage V. IN A pull-up resistor is used between the inputs of the semiconductor device. In one example, the bias circuit 670 includes a reset circuit 679 having a reset switch coupled between the field plate 671 and the source S. In another example, the reset switch may be omitted. In one embodiment, the pull-up resistor may be omitted, and the reset circuit 679 includes a switch coupled between the field plate 671 and the source S having an input voltage V.IN The current source between the semiconductor device inputs. Clamping circuit 678 is configured to provide a field plate bias voltage signal V to field plate 671. F In one example, the capacitance C of capacitor 674 SHUNT The target capacitance of the field plate 671 is greater than or equal to 0V, so that at C SHUNT When approaching infinity, the bias voltage V of the field plate F Maintain stability.

[0086] Figure 6J A bias circuit 680 is shown, in which clamping capacitors 684 with reset circuit 685 are arranged in series or stacked, for having a source S, a gate G (e.g., also labeled 683), multiple field plates 681, and a drain voltage V. D The drain extension transistor T of the drain D is clamped by a stacked active drain shunt field plate. The first clamping capacitor 684 is coupled to a voltage V. BOT The first (e.g., lower) terminal of the bottom reference node and coupled to a first field plate bias voltage V F1 The second terminal of the first field plate 681. In one example, the bottom reference node can be the source S of transistor T. In other embodiments, the bottom reference node can be coupled to different circuit nodes, such as gate 683, gate driver supply node (not shown), input node of semiconductor device, etc., with the remaining clamping capacitors 684 coupled between the corresponding field plate 681 and the previous field plate 681 to control the bias voltage V of the corresponding field plate. F1 V F2 ... V Fn The reset circuit 685 includes reset switches that are jointly activated according to the reset signal RESET, wherein each reset switch is coupled to a corresponding field plate 681 and has a corresponding reference voltage V. R1 V R2 ... V Rn Between the associated row reference voltage nodes.

[0087] Figure 6K This diagram illustrates a biasing configuration having a source S, a gate G (e.g., also labeled 693), a field plate 691, and a drain voltage V. D The drain extension transistor T of the drain D (e.g., the one mentioned above) Figure 2 A capacitive source shunt bias circuit 690 with parallel clamping capacitors 694 is provided for multiple field plates 691. The bias circuit 690 includes clamping capacitors 694 coupled to respective field plates 691 and respective bottom reference nodes 696, and a reset circuit having a reset switch coupled between each respective field plate 691 and an associated reset reference node. A first capacitor 694 is coupled to a field plate having a first field plate voltage V. F1The first field plate 691 and having a first bottom reference voltage V BOT1 Between the first bottom reference node 696. The first reset switch is coupled to the first field plate 691 and has a first reference voltage V. R1 Between the first reset reference node 697. The second capacitor 694 is coupled between the second field plate voltage V. F2 The second field plate 691 and having a second bottom reference voltage V BOT2 Between the second bottom reference node 696. The second reset switch is coupled to the second field plate 692 and has a second reference voltage V. R2 Between the second reset reference node 697. Any other field plate 691 is connected in a similar manner to the reset switch of the corresponding capacitor 694 and the bias circuit 690, wherein the final or nth capacitor 694 is coupled to the field plate with the nth field plate voltage V. Fn The nth field plate 691 and the nth bottom reference voltage V BOTn Between the nth bottom reference node 696. The nth reset switch is coupled to the nth field plate 692 and has a reset reference voltage V. Rn Between the nth reset reference node 697.

[0088] In one embodiment, the bottom reference node 696 is coupled together at the source S of transistor T. In another embodiment, the bottom reference node 696 is coupled together at another suitable circuit node, such as gate 693, gate driver supply node (not shown), input node of semiconductor device, etc. In yet another embodiment, the bottom reference node 696 is coupled to respective reference nodes with different reference node voltages, for example, where V BOT1 <V BOT2 ... <V BOTn In some implementations, the reset reference node 697 may be coupled together at a suitable circuit node, such as a gate driver circuit (not shown), or coupled thereto to reset the reference voltage V. R1 =V R2 ... = V Rn Another suitable circuit node. In other embodiments, the reset reference node 697 may have a different reference node voltage, for example, where V R1 <V R2 ... <V Rn For example, any suitable combination of the connections of the bottom node 696 and the reset reference node 697 can be used such that the bias voltage of the field plate 691 has a voltage value that monotonically increases in the direction from the source S to the drain D (e.g., V). F1 <V F2 <……、V Fn ).

[0089] Also refer to Figure 7-7H Other examples provide methods for biasing a source S, a gate G, and one or more field plates (e.g., as described above). Figure 1 The field plate 142 and the drain voltage V D The drain extension transistor T has a capacitive drain shunt configuration with one or more field plates for its drain D. In one or more examples, a bias circuit is coupled to one or more field plates and includes a reset circuit operated by a suitable control circuitry (not shown) to coordinate the timing of actuation relative to the transistor gate G. In these or other examples, the bias circuit includes one or more capacitors. In these or other examples, the bias circuit may include a pull-up circuit with a resistor or current source coupled to the drain D. In these or other examples, the bias circuit may include a pull-down circuit with a resistor or current source coupled to the source S of the drain extension transistor T or a resistor divider circuit.

[0090] Figure 7 The diagram shows a source S, a gate G, and a single field plate 701 (e.g., as described above). Figure 1 The field plate 142 and the drain voltage V D An example of an active drain shunt bias circuit 700 is provided for the drain extension transistor T of the drain D. The gate driver 702 (e.g., gate driver 192 above) provides a gate drive voltage signal V to the gate G. G Output 703 (e.g., gate voltage). Bias circuit 700 includes an output 703 configured to provide a field plate bias voltage signal V to field plate 701. F The drain shunt circuit is described in this example. In this example, the drain shunt circuit includes a capacitor 704 coupled between the field plate 701 and the drain D of the transistor T, and a reset circuit 705 (e.g., a switch) connected between the field plate 701 and the source S of the transistor T. The bias circuit 700 also includes a resistor divider connected in parallel with the reset circuit 705, having: a first resistor 707 having a first terminal coupled to the drain D and a second terminal coupled to the field plate 701; and a second resistor 708 having a first terminal coupled to the field plate 701 and a second terminal coupled to the source S of the transistor T. In one example, the reset circuit 705 is controlled in a manner synchronized with the gate driver 702, for example, closing with a fixed timing relationship relative to a gate driver signal turning on the transistor T (e.g., connecting the field plate 701 to the source S), and then opening the reset circuit 705 to allow the capacitor 704 to charge with a fixed timing relationship relative to a gate drive signal turning off the transistor T.

[0091] Figure 7A The curve shown in the figure represents the gate voltage V at the gate driver 702. G Switching to a low drain voltage V DAt its maximum value, during the operation of bias circuit 700, the transistor drain-source voltage (V) DS During a drift period from zero to its maximum value (e.g., the rated breakdown voltage of transistor T) and then back to zero, the drain voltage V... D Field plate bias voltage signal V F and gate drive voltage signal V G Voltage V relative to source S S The change in the field plate bias voltage signal V. In this example, the field plate bias voltage signal V. F It starts at approximately zero and at the drain voltage V D Rise to target value V during upward drift F .

[0092] In one example Figure 7 The reset circuit 705 in the middle is controlled to be in V D Approaching 0V (e.g., by monitoring V) DS or V G When the bias voltage signal V of the field plate is applied... F Initialized to 0V. The capacitance C of capacitor 704. SHUNT It can be selected to make V DS From 0V to rated breakdown voltage V BV The transition will change the voltage of the field plate 701 from 0V to the target field plate bias voltage V. F The capacitor 704 can be formed using a metal system of a semiconductor device or any suitable technique. In other embodiments, the field plate 701 can alternatively be reset to another voltage, such as V. S V G Or has a capacitance C SHUNT Another supply (e.g., called V) that corresponds to any suitable change S In these or other implementations, the reset circuit 705 may be omitted, for example, if the resistive voltage divider (e.g., resistors 707 and 708) is well matched such that when V DS = Rated breakdown voltage V BV At that time, V FS =V FS(TARGET) Alternative topologies are possible, for example, hybrid active and capacitive circuits, where the reset circuit closes after gate G is turned on and the reset circuit 705 opens before gate G is turned off.

[0093] Figure 7B The diagram shows a source S, a gate G, and a single field plate 711 (e.g., as described above). Figure 1 The field plate 142 and the drain voltage V DAn example capacitive drain shunt bias circuit 710 is provided for the drain extension transistor T with drain D. The gate driver 712 (e.g., gate driver 192 above) provides a gate drive voltage signal V to the gate G. G The output 713 (e.g., gate voltage) and via a gate drive supply voltage V DRV The gate drive supply is powered. Bias circuit 710 includes components configured to provide a field plate bias voltage signal V to field plate 711. F The drain shunt capacitor 714. In this example, the drain shunt capacitor 714 is coupled between the field plate 711 and the drain D of the transistor T. A reset circuit 715 (e.g., a switch) is connected between the field plate 711 and the gate drive supply to reset the field plate 711 to the gate drive voltage V. DRV The reset circuit is configured to close after the gate G is turned on, and the reset circuit 715 is configured to open before the gate G is turned off.

[0094] Figure 7C The diagram shows a source S, a gate G, and a single field plate 721 (e.g., as described above). Figure 1 The field plate 142 and the drain voltage V D An example capacitive drain shunt bias circuit 720 is provided for the drain extension transistor T with drain D. Gate driver 722 (e.g., gate driver 192 above) provides a gate drive voltage signal V to the gate G. G Output 723 (e.g., gate voltage). Bias circuit 720 includes an output 723 configured to provide a field plate bias voltage signal V to field plate 721. F A drain shunt capacitor 724 is provided. In this example, the drain shunt capacitor 724 is coupled between the field plate 721 and the drain D of the transistor T. A reset circuit 725 (e.g., a switch) is connected between the field plate 721 and the source S to reset the field plate 721 to 0V, wherein the reset circuit 725 is configured to close after the gate G is turned on and to open before the gate G is turned off.

[0095] Figure 7D The diagram shows a source S, a gate G, and a single field plate 721 (e.g., as described above). Figure 1 The field plate 142 and the drain voltage V D Another example implementation of the capacitive drain shunt bias circuit 720 for the drain extension transistor T of the drain D is shown. The gate driver 722 (e.g., gate driver 192 above) provides a gate drive voltage signal V to the gate G. G Output 723 (e.g., gate voltage). In this example, bias circuitry 720 includes a field plate bias voltage signal V configured to provide field plate bias voltage signal V to field plate 721. FThe drain shunt capacitor 724 is coupled between the field plate 721 and the drain D of the transistor T. In this example, a reset circuit 725 (e.g., a switch) is connected between the field plate 721 and the gate G to reset the field plate 721 to the gate voltage V. G The reset circuit is configured to close after the gate G is turned on, and the reset circuit 725 is configured to open before the gate G is turned off.

[0096] Figure 7E The diagram shows a source S, a gate G, and a single field plate 731 (e.g., above). Figure 1 The field plate 142 and the drain voltage V D An example capacitive drain shunt pull-down bias circuit 730 with drain shunt capacitor 734 for the drain extension transistor T of drain D. Gate driver 732 provides a gate drive voltage signal V to gate G. G Output 733 (e.g., gate voltage). Bias circuit 730 has clamping circuit 736 coupled to drain D and field plate 731. Clamping circuit 736 includes junction diode 737 having an anode and cathode coupled to drain D, and Zener diode 738. The cathode of junction diode 737 is connected to the cathode of Zener diode 738, and the anode of Zener diode 738 is connected to field plate 731. Bias circuit 730 also includes a capacitor C. SHUNT A drain shunt capacitor 734 is provided, and capacitor 734 is coupled between the field plate 731 and the drain D of the transistor. A pull-down circuit 735 is coupled between the field plate 731 and the source S, and may include a reset circuit system (e.g., a reset switch) coupled between the field plate 731 and the source S. In another embodiment, the reset switch may be omitted. In one embodiment, the pull-down circuit 735 has a pull-down resistor having a first terminal coupled to the field plate 731 and a second terminal coupled to the source S. In another embodiment, the pull-down circuit 735 includes a current source coupled between the field plate 731 and the source S. A clamping circuit 736 is configured to provide a field plate bias voltage signal V to the field plate 731. F .

[0097] Figure 7F The diagram shows a source S, a gate G, and a single field plate 741 (e.g., above). Figure 1 The field plate 142 and the drain voltage V D An example capacitive drain and source shunt bias circuit 740 with a drain shunt capacitor 744 for the drain extended transistor T of drain D. The gate driver 742 provides a gate drive voltage signal V to the gate G. GOutput 743 (e.g., gate voltage). Bias circuit 740 has clamping circuit 746 coupled to drain D and field plate 741. Clamping circuit 746 includes a junction diode 747 having an anode and cathode coupled to drain D, and a Zener diode 748. The cathode of junction diode 747 is connected to the cathode of Zener diode 748, and the anode of Zener diode 748 is connected to field plate 741. Bias circuit 740 also includes a capacitor C. SHUNT A drain shunt capacitor 744 is provided, and capacitor 744 is coupled between the field plate 741 and the drain D of the transistor. A second Zener diode 745 has a cathode coupled to the field plate 741 and an anode coupled to the source S. Clamping circuit 746 is configured to provide a field plate bias voltage signal V to the field plate 741. F .

[0098] Figure 7G A bias circuit 750 is shown, in which shunt capacitors 754 with reset circuit 755 are arranged in series or stacked, for having a source S, a gate G (e.g., also labeled 753), multiple field plates 751 and a drain voltage V. D The drain extension transistor T of the drain D is clamped by a stacked active drain shunt field plate. The first drain shunt capacitor 754 is coupled to a voltage V. F1 The first (e.g., lower) terminal of the first field plate 751 is coupled to a second field plate bias voltage V. F2 The second terminal of the second field plate 751. The reset circuit 755 includes a reset switch coupled between each field plate 751 and the corresponding reset reference node 756, and a first reset switch connected between the first field plate 751 and the first reset reference node 756. The remaining drain shunt capacitors 754 are coupled between the corresponding field plate 751 and the subsequent field plate 751 to control the corresponding field plate bias voltage V. F1 V F2 ... V Fn And finally, the reset capacitor 754 is coupled to the final field plate 751 (with field plate bias voltage V). Fn Between the drain D and the reset circuit 755. The reset circuit 755 includes reset switches that are jointly activated according to the reset signal RESET, wherein each reset switch is coupled to a corresponding field plate 751 and has a corresponding reference voltage V. R1 V R2 ... V Rn The associated reference voltage nodes are connected between the reference voltage nodes. In one example, the reset reference node 756 is connected to the corresponding tap node of a resistor divider (not shown) coupled between the drain D and source S of transistor T. In this or another example, the corresponding reference voltage is set such that V R1 <V R2 <…… <V RnFurthermore, the bias circuit 750 provides the field plate bias voltage, making V F1 <V F2 <……V Fn .

[0099] Figure 7H This diagram illustrates a biasing configuration having a source S, a gate G (e.g., also labeled 763), a field plate 761, and a drain voltage V. D The drain extension transistor T of the drain D (e.g., the one mentioned above) Figure 2 Another example of a multi-biased field plate is a capacitive drain shunt bias circuit 760 with clamping capacitors 764, comprising multiple field plates 761. The bias circuit 760 includes a drain shunt capacitor 764 coupled between the drain D and the respective field plate 761, and a reset circuit, wherein a reset switch 765 is coupled between each respective field plate 761 and an associated reset reference node 766. A first drain shunt capacitor 764 is coupled between the drain D and a field plate having a first field plate voltage V. F1 Between the first field plate 761. A first reset switch 765 is coupled between the first field plate 761 and a first reference voltage V. R1 Between the first reset reference node 766 and the second drain shunt capacitor 764. The second drain shunt capacitor 764 is coupled between the drain and has a second field plate voltage V. F2 The second field plate 761 is between the second field plate 762 and the second reset switch 765 is coupled to the second field plate 762 and has a second reference voltage V. R2 Between the second reset reference node 766. Any other field plate 761 is connected in a similar manner to the reset switch 765 of the corresponding capacitor 764 and the bias circuit 760, wherein the final or nth capacitor 764 is coupled to the drain D and has the nth field plate voltage V. Fn Between the nth field plate 761. The nth reset switch 765 is coupled to the nth field plate 762 and has a reset reference voltage V. Rn Between the nth reset reference node 766. In one embodiment, the reset reference nodes 766 may be coupled together at a suitable circuit node, such as the source S of transistor T, or coupled to the reset reference voltage V. R1 =V R2 ... = V Rn Another suitable circuit node. In other embodiments, the reset reference node 766 may have a different reference node voltage, for example, where V R1 <V R2 …… <V Rn For example, by connecting to the corresponding tap node of a resistor divider (not shown). Any suitable combination of connections for resetting the reference node 766 can be used, for example, such that the bias voltage of the field plate 761 has a voltage value that monotonically increases in the direction from the source S to the drain D (e.g., V). F1 <VF2 <……、V Fn ).

[0100] Also refer to Figure 8 and 8A Other examples may provide a hybrid drain and source shunt bias circuit with a reset circuit system for a drain extension transistor T having one or more bias field plates. Figure 8 This diagram illustrates several generations of drain voltage V for biasing a source S, a gate G (e.g., also labeled 803), and a field plate 801. D An example of a single-biased field plate with a capacitive source and drain shunt bias circuit 800 having shunt capacitors 804 and 806 on the field plate 801 of the drain extended transistor T with drain D. The bias circuit 800 includes a shunt capacitor 804 coupled between the drain D and the field plate 801, and a second shunt capacitor 806 coupled between the field plate 801 and the source S. The bias circuit 800 also includes a shunt capacitor coupled between the field plate 801 and a reset reference voltage V. R A reset circuit 805 (e.g., a reset switch) is used between reset reference nodes 809. Shunt capacitors 804 and 806 generate a field plate voltage V. F When shunt capacitors 804 and 806 have approximately equal capacitance, the field plate voltage V... F Roughly V DS / 2, unequal capacitors can be used to provide different plate voltages V F The reset reference node 809 can be connected to any suitable circuit node, such as the source S, gate driver supply node (not shown), semiconductor device input node (not shown), etc. In one example, the reset circuit 805 may be omitted. In one embodiment, the reset circuit 805 is actuated in a coordinated manner to achieve the desired timing relationship between the field plate reset operation and the actuation of the transistor gate G.

[0101] Figure 8A A multi-field plate drain extended transistor T is shown with a capacitive source and drain shunt bias circuit 810 having a shunt capacitor 814. In this example, the bias circuit 810 includes a series or stacked arrangement of the shunt capacitors 814 with a reset circuit 815 for having a source S, a gate G (e.g., also labeled 813), multiple field plates 811, and a drain voltage V. D The drain extension transistor T of the drain D has an active drain and source field plate stack for current shunt. The first shunt capacitor 814 is coupled to a capacitor with a voltage V. F1 The first (e.g., lower) terminal of the first field plate 811 is coupled to a second field plate bias voltage V with a higher bias voltage V. F2The second terminal of the second field plate 811. The remaining shunt capacitors 814 are coupled between the corresponding field plate 811 and the subsequent field plate 811, used to control the bias voltage V of the corresponding field plate. F1 V F2 ... V Fn And finally, the reset capacitor 814 is coupled to the final field plate 811 (with field plate bias voltage V). Fn Between the bottom capacitor 816 and the drain D. The bottom capacitor 816 is coupled to the first field plate 811 and has a bottom reference voltage V. BOT Between the bottom reference nodes 818. The bottom reference node 818 can be connected to any suitable circuit node, such as the source S, gate driver supply node (not shown), semiconductor device input node (not shown), etc.

[0102] The reset circuit 815 includes a reset switch coupled between each field plate 811 and a corresponding reset reference node 819, and includes a first reset switch connected between the first field plate 811 and the first reset reference node 819. The reset circuit 815 includes reset switches that are jointly activated according to a reset signal RESET, wherein each reset switch is coupled to a corresponding field plate 811 and has a corresponding reference voltage V. R1 V R2 ... V Rn The associated reference voltage nodes are connected between the reference voltage nodes. In one example, the reset reference node 819 is connected to the corresponding tap node of a resistor divider (not shown) coupled between the drain D and source S of transistor T. In this or another example, the corresponding reference voltage is set such that V R1 <V R2 <…… <V Rn Furthermore, the bias circuit 810 provides the field plate bias voltage, making V F1 <V F2 <……V Fn .

[0103] Also refer to Figure 9-9B Other examples provide direct-drive field-biased circuit systems, for example, to facilitate improvements in the specific resistance of low-side switches in transistor applications. Figure 9 This diagram illustrates a device having a source S, a gate G (e.g., also labeled 903), a field plate 901, and a drain voltage V. D The active bias circuit 900 clamps the active drain and source shunt field plates of the drain extension transistor T of the drain D. The gate driver 902 (e.g., the gate driver 192 above) provides a gate drive voltage signal V to the gate G. G The output 903 (e.g., gate voltage) and through the gate drive supply voltage V DRVThe gate drive supply is powered. Bias circuit 900 includes a first Zener diode 904 and a second Zener diode 905, and a capacitor 906 connected in parallel with the second Zener diode 905. Bias circuit 900 is an active circuit, wherein the second transistor T2 has a source and gate coupled to the field plate 901 and a drain coupled to the input node 909 via diode 907. The first Zener diode 904 has an anode coupled to the field plate 901 and a cathode coupled to the gate of the second transistor T2. The second Zener diode 905 has an anode coupled to the gate drive supply and a cathode coupled to the gate of transistor T2. Capacitor 906 and the cathode of the second Zener diode 905 are coupled to the input node 909 via resistor 908. Low-side operation of the drain extension transistor T (e.g., in a half-bridge configuration) is facilitated by the second transistor T2 of bias circuit 900, which provides a source follower to pull up the field plate bias voltage V of the field plate 901 when the low-side transistor T is turned on. F The bias circuit 900 can advantageously reduce the on-state drain-source resistance (RDSON) of transistor T, for example, where in one example, compared to the 0V field plate bias voltage V... F 5V field plate bias voltage V F This can provide approximately a 10% reduction in RDSON, and an 18V field plate bias voltage V. F This can provide approximately a 20% reduction in RDSON. In one example, a Zener diode 905 can be used for field plate bias voltage V. F Any desired level setting size (e.g., Zener voltage).

[0104] Figure 9A This diagram illustrates a device having a source S, a gate G (e.g., also labeled 913), a field plate 911, and a drain voltage V. D Another example of an active bias circuit 910 is the active drain and source shunt field plate stack clamping of the drain extension transistor T of the drain D. The gate driver 912 (e.g., gate driver 192 above) provides a gate drive voltage signal V to the gate G. G The output 913 (e.g., gate voltage) and via a gate drive supply voltage V DRVThe gate drive supply is powered. The bias circuit 910 includes a first Zener diode 914 and a second Zener diode 915, and a capacitor 916 connected in parallel with the second Zener diode 915. The bias circuit 910 is an active circuit, wherein the second transistor T2 has a source and a gate coupled to the field plate 911, and a drain coupled to the input node 919 via a diode 917. The first Zener diode 914 has an anode coupled to the field plate 911 and a cathode coupled to the gate of the second transistor T2. The second Zener diode 915 has an anode coupled to the gate drive supply and a cathode coupled to the gate of the transistor T2. Figure 9A The bias circuit 910 further includes a third Zener diode Z3, which has an anode connected to the gate drive supply and a cathode connected to the field plate 911. The cathodes of capacitor 916 and the second Zener diode 915 are coupled to the input node 919 via resistor 918. Low-side operation of the drain extension transistor T (e.g., in a half-bridge configuration) is facilitated by a second transistor T2 in the bias circuit 910, which provides the source follower with a pull-up field plate bias voltage V on the field plate 911 when the low-side transistor T is on. F The bias circuit 910 can advantageously reduce the on-state drain-source resistance (RDSON) of transistor T to facilitate low-side operation of the half-bridge circuit (not shown), and the Zener diodes 915 and Z3 can be used for the field plate bias voltage V. F Any desired level setting size (e.g., Zener voltage). In one example, the third Zener diode Z3 can be sized for the desired drain current level of transistor T, and the first Zener diode 914 and the second Zener diode 915 can be smaller than Z3, but a close match between the sizes of Zener diodes 914, 915 and Z3 can help mitigate source follower leakage during operation.

[0105] Figure 9B This diagram illustrates an application with a source S, a gate G (e.g., also labeled 923), a field plate 921, and a drain voltage V. D Another example of a bias circuit 920 for high-side operation of the drain extension transistor T of the drain D. The gate driver 922 (e.g., the gate driver 192 above) provides a gate drive voltage signal V to the gate G. G The output 923 (e.g., gate voltage) and via a gate drive supply voltage V DRV The gate drive supply is powered. The bias circuit 920 includes a clamping circuit comprising: a Zener diode 925 having an anode connected to the gate drive supply and a cathode connected to the field plate 921; and a resistor 928 coupled between the field plate 921 and the drain D. In this example, the clamping circuit controls the field plate voltage V of the field plate 921. FFurthermore, the bias circuit 920 can help improve the specific resistance of transistor T, for example, for high-side operation.

[0106] Figure 10-16 Other example biasing circuits for biasing multiple field plates of a drain extension transistor are shown. Figure 10 It shows a source S, a gate G, multiple field plates 1001, and a drain voltage V. D An example bias circuit 1000 for a drain-extended transistor T with drain D. In this example, bias circuit 1000 includes a clamping circuit having a series or stacked arrangement of Zener diodes 1002 and clamping capacitors 1005. A first Zener diode 1002 has an anode coupled to the source S and a cathode coupled to a first field plate 1001, and is coupled in parallel with the first clamping capacitor 1005. Other Zener diodes 1002 and clamping capacitors 1005 are connected in parallel with each other in successive pairs in the field plate 1001. A junction diode 1004 has an anode and a cathode coupled to the transistor drain D, and another Zener diode 1003 has an anode coupled to the final field plate 1001 and a cathode coupled to the cathode of the junction diode 1004. Bias circuit 1000 facilitates low-loss, high-efficiency operation and operation during startup.

[0107] Figure 11 It shows a source S, a gate G, multiple field plates 1101, and a drain voltage V. D Another example bias circuit 1100 for the drain extension transistor T of the drain D. In this example, the bias circuit 1100 includes a clamping circuit having a series or stacked arrangement of Zener diodes 1102 and clamping capacitors 1105. A first Zener diode 1102 has an anode coupled to the source S and a cathode coupled to the first field plate 1101, and is coupled in parallel with the first clamping capacitor 1105. Other Zener diodes 1102 and clamping capacitors 1105 are connected in parallel with each other in succession in the field plate 1101. A junction diode 1104 has an anode and a cathode coupled to the transistor drain D, and another Zener diode 1103 has an anode coupled to the final field plate 1101 and a cathode coupled to the cathode of the junction diode 1104. The bias circuit 1100 also includes another capacitor 1006 connected in parallel with the other Zener diode 1103, and a reset circuit system comprising a first set of switches 1107 respectively coupled between the cathode of the junction diode 1104 and its counterpart in the field plate 1101, and a second set of switches respectively coupled between the counterpart in the field plate 1101 and the parallel combination of the associated Zener diode 1102 and capacitor 1105.

[0108] Figure 12 It shows a source S, a gate G, multiple field plates 1201, and a drain voltage V.D Another example bias circuit 1200 for the drain extension transistor T of the drain D. In this example, the bias circuit 1200 includes a clamping circuit having a series or stacked arrangement of Zener diodes 1202 and clamping capacitors 1205. A first Zener diode 1202 has an anode coupled to the source S and a cathode coupled to the first field plate 1201, and is coupled in parallel with the first clamping capacitor 1205. Other Zener diodes 1202 and clamping capacitors 1205 are connected in parallel with each other in succession in the field plate 1201. A junction diode 1204 has an anode and a cathode coupled to the transistor drain D, and another Zener diode 1203 has an anode coupled to the final field plate 1201 and a cathode coupled to the cathode of the junction diode 1204. The bias circuit 1200 also includes another capacitor 1006 connected in parallel with the other Zener diode 1203, and a reset circuit system comprising a first set of switches 1207 respectively coupled between adjacent field plates 1201, wherein the final one of the first set of reset switches 1207 is coupled between the final field plate 1201 and the cathode of the junction diode. In this case, the reset circuit system also includes a second set of switches respectively coupled between the corresponding one in the field plate 1201 and the parallel combination of the associated Zener diode 1202 and capacitor 1205.

[0109] Figure 13 It shows a source S, a gate G, multiple field plates 1301, and a drain voltage V. D An example active bias circuit 1300 for the drain extension transistor T with drain D is shown, which does not have a clamping capacitor. In this example, bias circuit 1300 includes a driver circuit system having a driver 1302 coupled to each of the field plates 1301 and a blocking diode 1305. For each of the field plates 1301, driver 1302 provides an associated output voltage (e.g., V1, V2, V3, and V4 in the four-field-plate example shown). The respective driver output is connected to the anode of the corresponding blocking diode 1305, and the cathode of diode 1305 is connected to the corresponding field plate 1301. In one example, driver 1302 is driven by other circuitry (not shown) through the drain D of transistor T.

[0110] Figure 14 It shows a source S, a gate G, multiple field plates 1401, and a drain voltage V. DAn example active biasing circuit 1400 for a drain extension transistor T of a drain D, which does not have a clamping capacitor. In this example, the biasing circuit 1400 includes driver circuitry having drivers 1402 and blocking diodes 1405 coupled to each of field plates 1401. For each of the field plates 1401, a driver 1402 provides an associated output voltage (e.g., V1, V2, V3, and V4 in the illustrated four-field plate example), where the driver output voltages are monotonically increasing (e.g., V1 < V2 < V3 < V4). The respective driver outputs are connected to the anodes of corresponding blocking diodes 1405, and the cathodes of the diodes 1405 are connected to corresponding field plates 1401. The biasing circuit 1400 further includes optional reset switches connected in parallel across each of the diodes 1405, and a reset switch 1407 connected between the drain of a second transistor T2 and the corresponding one of the field plates 1401, respectively. In this example, the biasing circuit 1400 further includes an inductor 1406 coupled between the source and the drain D of the second transistor T2. For example, the second transistor T2 may be a high-side transistor, where the drain extension transistor T serves as a low-side transistor, and a DC-DC power converter configuration uses a voltage input (e.g., represented as a voltage source 1408) to provide input power to the converter.

[0111] Figure 15 Another example biasing circuit 1500 without a clamping capacitor for providing field plate bias voltage signals to a plurality of field plates 1501 of a drain extension transistor T configured in a half-bridge configuration, where the drain D of an upper (e.g., high-side) transistor T is coupled to an input node having an input voltage VIN, the source S of the upper (e.g., high-side) transistor T is coupled to a switch node SW, the drain D of a lower (e.g., low-side) transistor T is coupled to the switch node SW, and the source S of the low-side transistor T is coupled to ground or a reference node. Each transistor T includes a source S, a gate G (also labeled 1503), a plurality of field plates 1501, and a drain voltage V DThe drain D. The bias circuitry for each transistor T includes a Zener diode 1505 and a resistor 1506 for each bias field plate 1501. In the four-field-plate example shown, the Zener diode 1505 is connected between each pair of adjacent field plates 1501, with the anode coupled to one field plate and the cathode coupled to the next higher field plate 1501, and the bottom Zener diode 1505 for the upper transistor T (e.g., a high-side device) has an anode coupled to the source S and a cathode coupled to the first field plate 1501. For the lower transistor T, the bottom Zener diode 1505 has an anode coupled to the transistor circuit 1508. The resistor 1506 of the upper transistor T has an upper first terminal coupled to the input node (VIN) via a first coupling diode and to the startup node (BOOT) via a second coupling diode, and a lower or second terminal of the resistor 1506 of the upper transistor T is coupled to a corresponding one in the field plate 1501. For the lower transistor T, resistor 1506 is coupled between the input node (VIN) and the corresponding one in the field plate 1501 of the lower transistor T.

[0112] Figure 16 and 16A Another example bias circuit without clamping capacitors is shown for providing field plate bias voltage signals to multiple field plates 1611 of a drain extension transistor T configured in a half-bridge configuration. The drain D of the upper (e.g., high-side) transistor T is coupled to an input node having an input voltage VIN, the source S of the upper (e.g., high-side) transistor T is coupled to a switching node SW, the drain D of the lower (e.g., low-side) transistor T is coupled to the switching node SW, and the source S of the low-side transistor T is coupled to ground or a reference node. Each transistor T includes a source S, a gate G (also labeled 1603), multiple field plates 1611, and a drain voltage VIN. D The drain electrode D. Figure 16 Details of the bias circuitry system for the low-side (e.g., lower) transistor T are shown, and the high-side (e.g., upper) transistor T may contain the same or a similar bias circuitry system. The bias circuitry includes an n-channel transistor 1605, a resistor divider circuit 1606, and a p-channel transistor 1607 coupled between adjacent field plates, and a pulse generator circuit 1608 having an n-channel transistor and a current source for providing a short-circuit pulse after the low-side transistor is turned on, thereby raising the gate voltage on the source follower transistor 1605 to drive FP1-FP4 close to V. IN The pulse generator 1608 briefly turns on after the low-side transistor is turned on to turn on the p-channel transistor 1607. After turning on, the p-channel transistor 1607 short-circuits the resistor in the resistor divider 1606 (at which point switch 1609 turns off), thereby charging the gate of the n-channel natural transistor 1605 to V0. INTherefore, the n-channel natural transistor 1605 will charge FP1 through FP4 to V. IN This results in the lowest possible RDSON for the low-side transistor T. Figure 16 The bias circuit also includes a pulse-width modulated n-channel transistor 1609 coupled between a resistor divider 1606 and a common reference node. Additionally, the bias circuit includes circuitry 1610, wherein the n-channel transistor includes a first transistor coupled between first field plates 1611 and a second transistor that is pulse-width modulated and coupled to a current source connected to the common reference. The source of the first transistor is connected to the drain of a third transistor in circuitry 1610, the third transistor being switched on between a high pulse-width modulated signal from the second transistor and a maximum value at the switching node SW. Figure 16 The example also includes a driver 1612 that provides a gate drive signal to the gate G of transistor T and via a gate drive supply voltage VDRV. IN The gate driver is powered by the power supply.

[0113] Figure 16A Curve 1622 in Figure 1620 shows the application to Figure 16 Figure 1620 shows an example pulse-width modulated signal for the gate of the third transistor in circuit 1610, and curve 1624 shows an example of the low-side gate drive signal at the output of driver 1612. Curve 1626 shows an example of the field plate bias voltage (e.g., low or approximately zero drain-source voltage) of one of the field plates 1611, which is high when the low-side transistor T is on and low when the low-side transistor T is off. Figure 1620 further shows curve 1628, an example of the switching node voltage (SW) in an example half-bridge circuit configuration. Curve 1626 indicates that the field plate bias voltage will be at V IN (For example, the low-side transistor T is in the linear region (low or zero drain-source voltage) to enhance RDSON) and the field plate bias voltage will be set to the desired value set by the resistor divider network 1606 for the time (e.g., the low-side transistor T is saturated or off (e.g., a larger drain-source voltage) to promote high BVDSS).

[0114] The examples provided provide bias circuitry systems for one or more bias field plates for drain-extended transistors to promote uniform electric field distribution in the drift region, thereby achieving optimal small drift lengths (limited by the semiconductor breakdown strength in the drift region) and thus optimal low on-resistance (limited by the doping density and carrier mobility in the drift region). While various examples of this disclosure have been described above, it should be understood that they are presented by way of example only and not as limiting. Many changes may be made to the disclosed examples in accordance with the disclosure herein without departing from the spirit or scope of this disclosure. Therefore, the breadth and scope of this specification should not be limited by any of the examples described above. In fact, the scope of this disclosure should be defined by the appended claims and their equivalents. Within the scope of the claims, modifications to the examples are possible and other embodiments are possible.

Claims

1. A semiconductor device, comprising: A drain-extended transistor, comprising: A semiconductor layer comprising a body region having a first conductivity type and a drain drift region having the opposite second conductivity type; A gate dielectric layer is located above the body region and extends over the junction between the body region and the drain drift region; A gate electrode, which is located on the gate dielectric layer; A drain region having the second conductivity type in the drain drift region, wherein the dopant density of the drain region is greater than the dopant density of the drain drift region; and A field plate is located between the gate electrode and the drain region; and The bias circuit includes an output coupled to the field plate and a bias input coupled to the gate drive circuit.

2. The semiconductor device of claim 1, further comprising a field release dielectric layer over the drain drift region, the field release dielectric layer extending from the gate dielectric layer toward the drain region and having a thickness greater than that of the gate dielectric layer, wherein the field plate is located over the field release dielectric layer.

3. A semiconductor device, comprising: A drain-extended transistor, comprising: A semiconductor layer comprising a body region having a first conductivity type and a drain drift region having the opposite second conductivity type; A gate dielectric layer is located above the body region and extends over the junction between the body region and the drain drift region; A gate electrode, which is located on the gate dielectric layer; A drain region having the second conductivity type in the drain drift region, wherein the dopant density of the drain region is greater than the dopant density of the drain drift region; and A field plate is located between the gate electrode and the drain region; and The bias circuit includes a clamping circuit with a diode coupled to the field plate.

4. The semiconductor device of claim 3, wherein the clamping circuit comprises: a first diode having an anode coupled to the field plate; and a Zener diode having a cathode coupled to the cathode of the first diode.

5. The semiconductor device of claim 3, wherein the clamping circuit comprises a Zener diode having a cathode coupled to the field plate.

6. The semiconductor device of claim 3, wherein the clamping circuit comprises: First terminal; Second terminal; A clamping circuit transistor having a drain coupled to the first terminal, a source coupled to the second terminal, and a gate; A Zener diode having an anode coupled to the gate of the clamping circuit transistor and a cathode coupled to the first terminal; as well as A resistor coupled between the gate of the clamping circuit transistor and the second terminal.

7. A semiconductor device, comprising: A drain-extended transistor, comprising: A semiconductor layer comprising a body region having a first conductivity type and a drain drift region having the opposite second conductivity type; A gate dielectric layer is located above the body region and extends over the junction between the body region and the drain drift region; A gate electrode, which is located on the gate dielectric layer; A drain region having the second conductivity type in the drain drift region, wherein the dopant density of the drain region is greater than the dopant density of the drain drift region; and A field plate is located between the gate electrode and the drain region; as well as A bias circuit coupled to the field plate, the bias circuit including a reset circuit.

8. The semiconductor device of claim 7, wherein the bias circuit comprises a capacitor.

9. The semiconductor device of claim 7, wherein the bias circuit includes a pull-up circuit having a resistor or current source coupled to the drain region.

10. The semiconductor device of claim 7, wherein the bias circuit includes a pull-down circuit having a resistor or current source coupled to the source of the drain extension transistor.

11. A semiconductor device, comprising: A drain-extended transistor, comprising: A semiconductor layer comprising a body region having a first conductivity type and a drain drift region having the opposite second conductivity type; A gate dielectric layer is located above the body region and extends over the junction between the body region and the drain drift region; A gate electrode, which is located on the gate dielectric layer; A drain region having the second conductivity type in the drain drift region, wherein the dopant density of the drain region is greater than the dopant density of the drain drift region; and A field plate is located between the gate electrode and the drain region; as well as A bias circuit coupled to the field plate, the bias circuit including a second transistor.

12. The semiconductor device according to claim 11, wherein: The bias circuit includes a first terminal and a second terminal, the first terminal being coupled to the field plate; The second transistor has a drain coupled to the first terminal, a source coupled to the second terminal, and a gate; The bias circuit includes a Zener diode having an anode coupled to the gate of the second transistor and a cathode coupled to the first terminal; and The bias circuit includes a resistor coupled between the gate of the second transistor and the second terminal.

13. A semiconductor device, comprising: A drain-extended transistor, comprising: A semiconductor layer comprising a body region having a first conductivity type and a drain drift region having the opposite second conductivity type; A gate dielectric layer is located above the body region and extends over the junction between the body region and the drain drift region; A gate electrode, which is located on the gate dielectric layer; A drain region having the second conductivity type in the drain drift region, wherein the dopant density of the drain region is greater than the dopant density of the drain drift region; and Field plates, which are spaced apart from each other between the gate electrode and the drain region; as well as A bias circuit having an output coupled to a corresponding field plate and an input coupled to a voltage input of the semiconductor device, the drain region, and the gate drive circuit.

14. The semiconductor device of claim 13, further comprising a field release dielectric layer over the drain drift region, the field release dielectric layer extending from the gate dielectric layer toward the drain region and having a thickness greater than that of the gate dielectric layer, wherein the field plate is located over the field release dielectric layer.

15. The semiconductor device of claim 13, wherein the input of the bias circuit is coupled to the voltage input of the semiconductor device.

16. The semiconductor device of claim 13, wherein the input of the bias circuit is coupled to the drain region.

17. The semiconductor device of claim 13, wherein the input of the bias circuit is coupled to the gate drive circuit.

18. The semiconductor device of claim 13, wherein the bias circuit is configured to achieve a monotonically increasing voltage of the field plate from the source of the drain extension transistor to the drain region.

19. A method comprising: A drain extension transistor is formed in a semiconductor device, the drain extension transistor comprising: A semiconductor layer comprising a body region having a first conductivity type and a drain drift region having the opposite second conductivity type; A gate dielectric layer is located above the body region and extends over the junction between the body region and the drain drift region; A gate electrode, which is located on the gate dielectric layer; A drain region having the second conductivity type in the drain drift region, wherein the dopant density of the drain region is greater than the dopant density of the drain drift region; and A field plate is located between the gate electrode and the drain region; as well as A bias circuit is formed in the semiconductor device, the bias circuit including an output coupled to the field plate and a bias input coupled to the gate drive circuit.

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