LDMOS structure and method of forming the same

Abstract

The application provides an LDMOS structure and a forming method thereof. The forming method comprises the following steps: providing a semiconductor substrate, a first well region is formed in the semiconductor substrate, the first well region is doped with boron ions, and an isolation trench is formed in the first well region; forming a diffusion barrier layer comprising carbon ions on the side wall and the bottom of the isolation trench, the interface between the diffusion barrier layer and the semiconductor substrate comprises a carbon boron cluster layer; forming an isolation structure in the isolation trench, the surface of the isolation structure is coplanar with the surface of the semiconductor substrate; and forming an LDMOS structure comprising a second well region, a gate structure, and a source and a drain. The LDMOS structure and the forming method thereof can effectively prevent the diffusion of doped ions in the well region to the isolation structure, and greatly improve the device performance.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor manufacturing, and in particular to an LDMOS structure and a forming method thereof. BACKGROUND

[0002] In a manufacturing process of a laterally-diffused metal-oxide semiconductor (LDMOS), a shallow trench isolation (STI) structure is usually used to improve the electric field and the device performance, such as improving the breakdown voltage (BV) and the electro-static discharge (ESD) problem.

[0003] However, the LDMOS with the STI structure still has many defects, such as the diffusion of the doping ions in the well region into the STI, which causes the loss of the doping ions in the well region and the reduction of the doping ion concentration. Especially in the thermal annealing process of the STI or in the annealing process of other processes, the diffusion and loss of the doping ions are more serious, which leads to the degradation of the device performance, such as the increase of the leakage current. Meanwhile, it also causes a large difference in the performance between devices. SUMMARY

[0004] The technical problem to be solved by the present application is the diffusion of the doping ions in the well region into the STI, which leads to poor device performance.

[0005] To solve the above technical problem, the present application provides a forming method of an LDMOS structure, comprising: providing a semiconductor substrate, wherein a first well region is formed in the semiconductor substrate, the first well region is doped with boron ions, and an isolation trench is formed in the first well region; forming a diffusion barrier layer including carbon ions on the side wall and the bottom of the isolation trench, wherein the interface between the diffusion barrier layer and the semiconductor substrate includes a carbon-boron cluster layer; forming an isolation structure in the isolation trench, wherein the surface of the isolation structure is coplanar with the surface of the semiconductor substrate; forming an LDMOS structure including a second well region, a gate structure, and a source and a drain, wherein the second well region is located in the first well region on one side of the isolation structure, the gate structure spans and covers part of the surface of the isolation structure, the first well region, and the second well region, the drain is located in the first well region on the side of the isolation structure away from the gate structure, and the source is located in the second well region on the side of the gate structure.

[0006] In the embodiment of the present application, the process of forming the diffusion barrier layer is in-situ epitaxial growth, chemical vapor deposition, or physical vapor deposition.

[0007] In the embodiment of the present application, the thickness of the diffusion barrier layer is 3-20 nm.

[0008] In the embodiment of the present application, before forming the isolation structure, boron ions are doped in the diffusion barrier layer, and the doped boron ions are enriched at the interface between the diffusion barrier layer and the semiconductor substrate, and the concentration of the boron ions is not more than 5*10 19 / cm 3 .

[0009] In the embodiment of the present application, the material of the diffusion barrier layer comprises at least one of silicon carbide and silicon carbide boron.

[0010] In the embodiment of the present application, before forming the isolation structure in the isolation trench, the diffusion barrier layer is subjected to oxidation treatment or nitridation treatment.

[0011] In the embodiment of the present application, the oxidation treatment is dry oxygen oxidation or wet oxygen oxidation, wherein the flow rate of oxygen is 1.2 SLM-0.9 SLM, and the treatment time is 15 s-30 s.

[0012] The present application also provides an LDMOS structure, comprising: a semiconductor substrate, wherein a first well region is formed in the semiconductor substrate, and the first well region is doped with boron ions; an isolation structure located in the first well region and coplanar with the surface of the semiconductor substrate, comprising a diffusion barrier layer and an isolation material layer on the surface of the diffusion barrier layer, wherein the diffusion barrier layer comprises carbon ions; a carbon boron cluster layer located at the interface between the diffusion barrier layer and the semiconductor substrate; a second well region located in the first well region on one side of the isolation structure; a gate structure spanning and covering the surfaces of part of the isolation structure, the first well region and the second well region; a drain located on the side of the isolation structure away from the gate structure; and a source located in the second well region on one side of the gate structure.

[0013] In the embodiment of the present application, the thickness of the diffusion barrier layer is 3-20 nm.

[0014] In the embodiment of the present application, the material of the diffusion barrier layer comprises at least one of silicon carbide and silicon carbide boron.

[0015] In the embodiment of the present application, the material of the diffusion barrier layer comprises silicon oxide or silicon carbon nitride.

[0016] In the embodiment of the present application, the interface between the diffusion barrier layer and the semiconductor substrate is also enriched with boron ions, and the concentration of the enriched boron ions is not more than 5*10 19 / cm 3 .

[0017] Compared with the prior art, the forming method of the LDMOS structure of the technical scheme of the present application can effectively prevent the boron ions in the well region from diffusing into the isolation structure, solve the problem of poor device performance caused by the loss of boron ions in the well region, and reduce the performance difference between devices.

[0018] The diffusion barrier layer is doped with boron ions, and the doped boron ions are enriched at the interface between the diffusion barrier layer and the semiconductor substrate, further reducing the loss of boron ions in the well region.

[0019] The formed diffusion barrier layer is subjected to oxidation treatment, which can improve the material performance of the diffusion barrier layer, reduce the stress of the isolation structure on the semiconductor substrate, reduce the leakage caused by the isolation structure process, and further improve the device performance.

[0020] The LDMOS structure of the technical scheme of the present application adopts an isolation structure including a diffusion barrier layer, which can effectively prevent the boron ions in the well region from diffusing into the isolation structure, solve the problem of poor device performance caused by the loss of boron ions in the well region, and reduce the performance difference between devices. BRIEF DESCRIPTION OF DRAWINGS

[0021] The following drawings describe the exemplary embodiments disclosed in the present application in detail. The same reference numerals in the several views of the drawings represent similar structures. Those skilled in the art will understand that these embodiments are non-limiting, exemplary embodiments, and the drawings are only for the purpose of illustration and description, and are not intended to limit the scope of the present application, and other embodiments can also achieve the same purpose. It should be understood that the drawings are not drawn to scale. Among them:

[0022] Figures 1 to 7 The structure schematic diagram of the forming method of the LDMOS structure of the embodiments of the present application. DETAILED DESCRIPTION

[0023] The following description provides specific application scenarios and requirements of the present application, which is to enable those skilled in the art to manufacture and use the content in the present application. Various local modifications of the disclosed embodiments are obvious to those skilled in the art, and the general principles defined herein can be applied to other embodiments and applications without departing from the spirit and scope of the present application. Therefore, the present application is not limited to the shown embodiments, but is consistent with the widest range of claims.

[0024] In view of the problem of serious loss of doping ions diffusion of the conventional STI structure LDMOS, the technical scheme of the present application improves the STI structure, forms a diffusion barrier layer on the bottom and sidewall of the STI isolation groove, the material of the diffusion barrier layer includes carbon ions, so that the boron ions of the well region diffuse to the interface between the diffusion barrier layer and the semiconductor substrate, forming a carbon-boron cluster layer, which effectively blocks the diffusion of boron ions into the STI, thereby improving the device performance.

[0025] The forming method of the LDMOS structure of the technical scheme of the present application is described in detail below in combination with the drawings and specific embodiments.

[0026] Reference Figure 1 , a semiconductor substrate 110 is provided. The semiconductor substrate 110 can be a silicon substrate, a germanium substrate, a silicon germanium substrate, a silicon-on-insulator or a germanium-on-insulator, etc., and can also be a substrate including other elemental semiconductors or compound semiconductors, such as silicon carbide, gallium arsenide, indium antimonide, gallium phosphide, gallium antimonide, aluminum gallium arsenide, indium gallium arsenide, gallium antimony arsenide, or indium phosphide, etc. In the embodiments of the present application, the material of the semiconductor substrate 110 is silicon. Doping ions are implanted into the semiconductor substrate 110 by an ion implantation process to form a first well region 120. In the embodiments of the present application, the first well region 120 includes boron ions, and the concentration of the boron ions is 3×10 18 / cm 3 ~ 6×10 18 / cm 3 . Since boron ions are prone to diffusion, the doping ions of the first well region 120 are seriously lost, affecting the device performance.

[0027] Reference Figure 2 , an isolation groove 140 is formed in the first well region. The forming method can include: forming a mask layer 130 on the surface of the semiconductor substrate 110 of the first well region 120; forming an isolation groove 140 in the semiconductor substrate 110 by an etching process.

[0028] The conventional process directly fills an isolation material in the isolation groove 140 after forming the isolation groove 140, thereby forming an isolation structure. However, the isolation structure formed in this way cannot resist the diffusion of the doping ions of the first well region 120, so the problem of serious loss of doping ions of the first well region due to the diffusion of the doping ions into the isolation structure often occurs, thereby affecting the device performance.

[0029] Reference Figure 3In order to solve the problem of diffusion of the doping ions, the diffusion barrier layer 150 is formed on the bottom and sidewall of the isolation trench 140 after the isolation trench 140 is formed. The diffusion barrier layer 150 includes carbon ions. When the boron ions in the first well region 120 diffuse to the interface between the semiconductor substrate 110 of the first well region 120 and the diffusion barrier layer 150, the boron ions form a carbon-boron cluster layer with the carbon ions in the diffusion barrier layer 150. The carbon-boron cluster layer can effectively prevent the boron ions from further diffusing into the STI. In the embodiment, the material of the diffusion barrier layer 150 includes silicon carbide. On one hand, the silicon carbide can effectively prevent the diffusion of the doping ions. On the other hand, the silicon carbide can improve the current characteristics and reduce the on-resistance (Ron). Considering the cost and the blocking effect, the thickness of the diffusion barrier layer 150 is 3 nm to 20 nm. The process of forming the diffusion barrier layer 150 can be in-situ epitaxial growth, chemical vapor deposition or physical vapor deposition.

[0030] In some embodiments, in order to further reduce the loss of the doping ions in the first well region 120, ion doping can also be performed in the diffusion barrier layer 150. For example, in order to reduce the loss of the boron ions, boron ion doping is performed in the diffusion barrier layer 150. The process of the boron ion doping is, for example, ion implantation process. The implanted boron ions are enriched at the interface between the diffusion barrier layer 150 and the semiconductor substrate 110 of the first well region 120, and the concentration of the enriched boron ions is not more than 5×1019 / cm3. 19 / cm 3 After the diffusion barrier layer 150 is doped with the boron ions, the material of the diffusion barrier layer 150 includes silicon boron carbide and can also include silicon carbide.

[0031] After the diffusion barrier layer 150 is formed, the diffusion barrier layer 150 can also be subjected to oxidation treatment or nitridation treatment to further improve the isolation effect. The diffusion barrier layer 150 subjected to the oxidation treatment can not only reduce the stress of the isolation structure on the semiconductor substrate, but also prevent the diffusion of the boron ions and reduce the leakage caused by the process of the isolation structure. Therefore, the oxidation treatment is beneficial to improving the performance of the device. In some embodiments, the process of the oxidation treatment can be dry oxygen oxidation or wet oxygen oxidation. The flow rate of the oxygen is 1.2 SLM to 0.9 SLM, and the processing time is 15 s to 30 s. It should be noted that in other embodiments, the diffusion barrier layer 150 can not be subjected to the oxidation treatment or the nitridation treatment. After the oxidation treatment, the material of the diffusion barrier layer 150 includes silicon oxide; after the nitridation treatment, the material of the diffusion barrier layer 150 includes silicon carbon nitride.

[0032] Reference Figure 4A isolation structure 170 is formed in the isolation groove, and a surface of the isolation structure 170 is coplanar with a surface of the semiconductor substrate 110. The process of forming the isolation structure 170 includes: depositing an isolation material layer on surfaces of the semiconductor substrate 110 and the diffusion barrier layer 150, and the deposition process can be chemical vapor deposition, physical vapor deposition, atomic layer deposition, etc.; and polishing the isolation material layer until a surface of the isolation material layer is coplanar with a surface of the semiconductor substrate 110. The isolation material layer includes silicon oxide.

[0033] Then, an LDMOS structure including a second well region, a gate structure, and a source and a drain is formed.

[0034] Reference is made to Figure 5 A second well region 180 is formed in the first well region 120 on one side of the isolation structure 170, and the forming process can include: forming a mask on surfaces of the semiconductor substrate 110 and the isolation structure 170 of the first well region 120, and the mask exposes a position of the second well region; implanting dopant ions into the first well region 120 by using an ion implantation process to form the second well region 180; and removing the mask. The second well region 180 is opposite to the first well region 120 in type of dopant ions, for example, the first well region 120 is P-type, and the second well region 180 is N-type. The second well region 180 has a depth smaller than that of the first well region 120.

[0035] Reference is made to Figure 6 A gate structure 190 is formed across and covering surfaces of part of the isolation structure 170, the first well region 120, and the second well region 180. The process of forming the gate structure 190 can include: sequentially depositing a gate oxide material layer and a gate material layer on surfaces of the semiconductor substrate 110 of the first well region 120 and the second well region 180, and on a surface of the isolation structure 170; etching the gate oxide layer and the gate material layer to form a gate oxide layer and a gate layer across and covering surfaces of part of the isolation structure 170, the first well region 120, and the second well region 180; and forming a side wall on a side wall of the gate oxide layer and the gate layer.

[0036] Reference is made to Figure 7 A drain 210 is formed in the first well region 120 on a side of the isolation structure 170 away from the gate structure 190 by using an ion implantation process, and a source 220 is formed in the second well region 180 on a side of the gate structure 170. The drain 210 and the source 220 are of the same type of dopant ions as the first well region 120. In the embodiment of the present application, the source and the drain are both P-type.

[0037] Reference is made to Figure 7The embodiment of the present application also provides an LDMOS structure, comprising: a semiconductor substrate 110, wherein a first well region 120 is formed, and the first well region 120 is doped with boron ions; an isolation structure 170 located in the first well region 120 and coplanar with the surface of the semiconductor substrate 110, comprising a diffusion barrier layer 150 and an isolation material layer located on the surface of the diffusion barrier layer 150, wherein the diffusion barrier layer 150 comprises carbon ions; a carbon-boron cluster layer located at the interface between the diffusion barrier layer 150 and the semiconductor substrate 110; a second well region 180 located in the first well region 120 on one side of the isolation structure 170; a gate structure 190 crossing and covering part of the surfaces of the isolation structure 170, the first well region 120 and the second well region 180; a drain 210 located on the side of the isolation structure 170 away from the gate structure 190; and a source 220 located in the second well region 180 on the side of the gate structure 190.

[0038] In some embodiments, the thickness of the diffusion barrier layer 150 is 3-20 nm.

[0039] In some embodiments, the material of the diffusion barrier layer 150 comprises at least one of silicon carbide and silicon boron carbide.

[0040] In some embodiments, the material of the diffusion barrier layer 150 comprises silicon oxycarbide or silicon carbonitride.

[0041] In some embodiments, the interface between the diffusion barrier layer 150 and the semiconductor substrate 110 is also enriched with boron ions, and the concentration of the enriched boron ions is not more than 5*1018 / cm2. 19 / cm 3 .

[0042] In some embodiments, the gate structure comprises: a gate oxide layer crossing and covering part of the surfaces of the isolation structure 110, the first well region 120 and the second well region 180; a gate layer located on the surface of the gate oxide layer; and a side wall located on the two side walls of the gate oxide layer and the gate layer.

[0043] The LDMOS structure and the forming method thereof according to the embodiment of the present application can form a cluster layer of carbon ions and doping ions at the interface between the isolation structure and the semiconductor substrate by forming a diffusion barrier layer comprising carbon ions at the bottom and the side wall of the isolation trench, thereby effectively blocking the diffusion of boron ions in the well region, and solving the problem of performance degradation of the device caused by the loss of boron ions in the well region due to the diffusion of boron ions in the well region into the isolation structure.

[0044] In view of the foregoing, after reading this disclosure, those skilled in the art will appreciate that the foregoing description of the application is intended to be illustrative only and that changes can be made to the application without departing from the spirit and scope thereof. Although not explicitly described, those skilled in the art will appreciate that the application is intended to encompass various reasonable changes, improvements and modifications of the embodiments described herein. Such changes, improvements and modifications are intended to be within the spirit and scope of the exemplary embodiments of the application.

[0045] It should be understood that the term "and / or" as used herein encompasses all possible combinations of one or more of the associated listed items. It should be understood that when an element such as a layer, region, or substrate is referred to as being "on" or "coupled" to another element, it can be directly on or coupled to the other element or intervening elements can also be present.

[0046] Similarly, it should be understood that, when an element or layer is referred to as being "on" another element or substrate, it can be directly on the other element or substrate, or intervening elements can also be present. In contrast, the term "directly on" means that there are no intervening elements present. It should also be understood that, as used herein, the term "comprises" and / or "comprising" and / or the like are intended to mean that the object include the recited elements, but not excluding other elements. "Excluding other elements" means that the other elements are not present, but do not preclude the addition of other elements.

[0047] It should also be understood that, although the terms first, second, third, etc. can be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Thus, a first element in some embodiments can be termed a second element in other embodiments without departing from the teachings of the present application. The same reference numerals or same reference designators denote the same elements throughout the specification.

[0048] In addition, the description of the application has been presented using idealized exemplary cross-sectional and / or plan and / or perspective views. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Thus, the exemplary embodiments should not be construed as limited to the precise shapes illustrated herein but are intended to include what is within the scope of such shapes, for example, due to manufacturing. For example, an etched region illustrated as a rectangle will typically have rounded or curved features. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the precise shape of a region of a device and are not intended to limit the scope of the exemplary embodiments.

Claims

1. A method for forming an LDMOS structure, characterized in that, include: A semiconductor substrate is provided, wherein a first well region is formed therein, the first well region is doped with boron ions, and an isolation trench is formed therein; A diffusion barrier layer comprising carbon ions is formed on the sidewalls and bottom of the isolation trench, and the interface between the diffusion barrier layer and the semiconductor substrate comprises a carbon boron cluster layer. An isolation structure is formed within the isolation trench, and the surface of the isolation structure is coplanar with the surface of the semiconductor substrate. An LDMOS structure is formed, comprising a second well region, a gate structure, and a source and a drain, wherein the second well region is located in a first well region on one side of the isolation structure, the gate structure spans and covers a portion of the surfaces of the isolation structure, the first well region, and the second well region, the drain is located in the first well region on the side of the isolation structure away from the gate structure, and the source is located in the second well region on one side of the gate structure.

2. The method for forming an LDMOS structure according to claim 1, characterized in that, The process for forming the diffusion barrier layer is in-situ epitaxial growth, chemical vapor deposition, or physical vapor deposition.

3. The method for forming an LDMOS structure according to claim 1, characterized in that, The thickness of the diffusion barrier layer is 3nm to 20nm.

4. The method for forming an LDMOS structure according to claim 1, characterized in that, Prior to forming the isolation structure, boron ion doping is performed on the diffusion barrier layer, and the doped boron ions are enriched at the interface between the diffusion barrier layer and the semiconductor substrate, with the concentration of the boron ions not exceeding 5 × 10⁻⁶. 19 / cm 3 .

5. The method for forming an LDMOS structure according to claim 1, characterized in that, The diffusion barrier layer is made of at least one of silicon carbide and silicon carbide boron.

6. The method for forming an LDMOS structure according to claim 1 or 4, characterized in that, Before forming the isolation structure within the isolation trench, the process further includes: oxidizing or nitriding the diffusion barrier layer.

7. The method for forming an LDMOS structure according to claim 6, characterized in that, The oxidation process is either dry oxygen oxidation or wet oxygen oxidation, wherein the oxygen flow rate is 1.2 SLM to 0.9 SLM and the treatment time is 15 s to 30 s.

8. An LDMOS structure, characterized in that, include: A semiconductor substrate, wherein a first well region is formed in the semiconductor substrate, and the first well region is doped with boron ions; An isolation structure, located in the first well region and coplanar with the surface of the semiconductor substrate, includes a diffusion barrier layer and an isolation material layer located on the surface of the diffusion barrier layer, wherein the diffusion barrier layer comprises carbon ions; A carbon boron cluster layer is located at the interface between the diffusion barrier layer and the semiconductor substrate; The second well region is located in the first well region on one side of the isolation structure; A gate structure that spans and covers a portion of the surfaces of the isolation structure, the first well region, and the second well region; The drain is located on the side of the isolation structure away from the gate structure; The source is located in the second well region on one side of the gate structure.

9. The LDMOS structure according to claim 8, characterized in that, The thickness of the diffusion barrier layer is 3nm to 20nm.

10. The LDMOS structure according to claim 8, characterized in that, The diffusion barrier layer is made of at least one of silicon carbide and silicon carbide boron.

11. The LDMOS structure according to claim 8, characterized in that, The diffusion barrier layer is made of silicon oxycarbonate or silicon carbonitride.

12. The LDMOS structure according to claim 8, characterized in that, The interface between the diffusion barrier layer and the semiconductor substrate is also enriched with boron ions, and the concentration of enriched boron ions does not exceed 5 × 10⁻⁶. 19 / cm 3 .

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