LDMOS device manufacturing method and LDMOS device

Abstract

The invention discloses a manufacturing method of an LDMOS (Laterally Diffused Metal Oxide Semiconductor) device and the LDMOS device, and belongs to the technical field of semiconductors. The polycrystalline silicon is deposited on the upper surface of the drift region, the polycrystalline silicon is doped to form the polycrystalline silicon doped structure on the upper surface of the drift region, and the polycrystalline silicon doped structure is directly contacted with the upper surface of the drift region, so that the area of the drift region can be increased, the voltage withstanding area can be increased, and the breakdown voltage of the LDMOS device can be improved; or the surface electric field intensity distribution can be adjusted; forming medium structures on the two sides of the polycrystalline silicon doped structure through dry etching; through the contact between the dielectric structure and the gate oxide layer, the dielectric structure can be used as the gate oxide layer of the gate, and the electric field intensity of the gate close to the drift region side lower part can be effectively reduced; according to the LDMOS device, the polycrystalline silicon doping structure and the dielectric structure are arranged, so that the electric field intensity of the LDMOS device is reduced, the voltage withstanding area is increased, and the breakdown voltage of the LDMOS device is improved.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor technology, and particularly relates to a method for manufacturing an LDMOS device and an LDMOS device. Background Technology

[0002] Laterally diffused metal-oxide-semiconductor (LDMOS) transistors are core high-voltage devices in modern intelligent power integrated circuits (BCD technology). LDMOS devices can be integrated on the same chip with low-voltage CMOS, bipolar, and other devices, fully leveraging the high-voltage power handling capabilities of LDMOS and the high-density, low-power control advantages of CMOS. The source, drain, and gate electrodes of LDMOS devices are all located on the chip surface, facilitating interconnection, and therefore they are widely used in power management, display drivers, automotive electronics, and other fields requiring high-voltage switching and power control. The core performance indicators for LDMOS devices are breakdown voltage (BV) and specific on-resistance (Ron, sp). LDMOS aims to achieve a higher breakdown voltage with the lowest possible specific on-resistance.

[0003] To optimize the trade-off between breakdown voltage and specific on-resistance—that is, to increase breakdown voltage without increasing specific on-resistance, or to decrease specific on-resistance without decreasing breakdown voltage—LDMOS devices commonly employ field plate structures in the drift region to alleviate surface electric field concentration. Mainstream technologies include shallow trench isolation (STI) field plates and localized silicon oxide (LOCOS) field plates. STI field plates are constructed by etching a silicon substrate to form trenches and filling them with oxide. This process is complex, and severe electric field concentration is prone to occur at the sharp corners of the STI trenches, leading to premature device breakdown and reliability issues such as hot carrier injection (HCI). While LOCOS field plate structures are highly compatible with CMOS processes, the structures formed during the oxidation process encroach on the source region area, and controlling the oxide layer thickness and morphology is difficult, limiting the efficiency and uniformity of the field plate's modulated electric field. Summary of the Invention

[0004] The present invention aims to provide a method for manufacturing an LDMOS device and an LDMOS device to solve the above-mentioned technical problems. By setting a polysilicon doped structure and a dielectric structure, the electric field strength of the LDMOS device is reduced, the voltage withstand area is increased, and thus the breakdown voltage of the LDMOS device is improved.

[0005] To address the aforementioned technical problems, embodiments of the present invention provide a method for manufacturing an LDMOS device, comprising: A substrate is defined, a channel region is formed on one side of the upper part of the substrate, and a drift region is formed on the other side of the upper part of the substrate; A drain is formed in the drift region, and a source is formed in the channel region; Polysilicon is deposited on the upper surface of the drift region and then doped to form a polysilicon doped structure on the upper surface of the drift region. A dielectric structure is formed on both sides of the polysilicon doped structure by dry etching. A gate oxide layer is formed on the upper surface of the polysilicon doped structure, the dielectric structure, the channel region, and the drift region, so that the gate oxide layer covers the upper surface of the polysilicon doped structure, the dielectric structure, the channel region, and the drift region; A gate is disposed on the upper surface of the gate oxide layer.

[0006] It is understood that this invention, by forming a channel region on one side of the upper part of the substrate and a drift region on the other side, then forming a drain in the drift region and a source in the channel region, can build a device foundation for the subsequent formation of polysilicon doped structures and dielectric structures. Subsequently, polysilicon is deposited on the upper surface of the drift region and doped to form a polysilicon doped structure on the upper surface of the drift region. By forming a polysilicon doped structure in direct contact with the upper surface of the drift region, the drift region area can be increased, thereby increasing the breakdown voltage area and improving the breakdown voltage of the LDMOS device; alternatively, the surface electric field intensity distribution can be adjusted. Finally, dry etching is performed. A dielectric structure is formed on both sides of a polysilicon doped structure. Then, a gate oxide layer is formed on the upper surfaces of the polysilicon doped structure, the dielectric structure, the channel region, and the drift region, covering these surfaces. Through the contact between the dielectric structure and the gate oxide layer, the dielectric structure acts as the gate oxide layer, effectively reducing the electric field strength below the gate near the drift region. By setting the polysilicon doped structure and the dielectric structure, the electric field strength of the LDMOS device is reduced, the breakdown area is increased, and thus the breakdown voltage of the LDMOS device is improved. Simultaneously, the entire manufacturing process avoids complex deep trench etching and difficult-to-control LOCOS field plate structures, employing only standard deposition, etching, implantation, and oxidation processes, simplifying the process flow and improving the efficiency and reliability of LDMOS device manufacturing.

[0007] As a preferred embodiment, the deposition of polycrystalline silicon on the upper surface of the drift region and the doping of the polycrystalline silicon to form a polycrystalline silicon doped structure on the upper surface of the drift region includes: Polycrystalline silicon is deposited on the upper surface of the drift region; Ions of the same or opposite type as those in the drift region are selected, and ion implantation is used to dope the polycrystalline silicon, thereby forming a polycrystalline silicon doped structure on the upper surface of the drift region; wherein the ion doping type of the polycrystalline silicon doped structure is the same or opposite to that of the drift region.

[0008] This preferred embodiment deposits polysilicon on the upper surface of the drift region; and selects ions of the same or opposite type as those in the drift region, using ion implantation to dope the polysilicon, thereby forming a polysilicon doped structure; when the ion doping type of the polysilicon doped structure is opposite to that of the drift region, the polysilicon doped structure forms a PN junction because it is in direct contact with the upper surface of the drift region, thus acting as a RESURF region, which can adjust the surface electric field intensity distribution; when the ion doping type of the polysilicon doped structure is the same as that of the drift region, the polysilicon doped structure is in contact with the upper surface of the drift region, thereby increasing the drift region area, improving the breakdown voltage area, and thus improving the breakdown voltage of the LDMOS device.

[0009] As a preferred embodiment, the method of forming a dielectric structure on both sides of the polysilicon doped structure using dry etching includes: An initial dielectric layer is deposited on the upper surface and both sides of the polycrystalline silicon doped structure; The initial dielectric layer is dry etched to form a first dielectric layer on one side of the polysilicon doped structure and a second dielectric layer on the other side of the polysilicon doped structure. The first dielectric layer and the second dielectric layer constitute a dielectric structure.

[0010] This preferred embodiment deposits an initial dielectric layer on the upper surface and both sides of a polysilicon doped structure, followed by dry etching to form a first dielectric layer and a second dielectric layer. This allows the dielectric structure to act as a sidewall of the polysilicon doped structure. The dielectric structure formed by dry etching makes the surface potential change smoother and more controllable, effectively alleviating the electric field concentration at the gate edge. At the same time, this process does not require a photomask, which simplifies the process. The dielectric structure can also act as the gate oxide layer of the gate, effectively reducing the electric field intensity below the gate near the drift region.

[0011] As a preferred embodiment, after the gate is formed on the upper surface of the gate oxide layer, the method further includes: A third dielectric layer is formed on one side of the gate using dry etching. A fourth dielectric layer is formed on the other side of the gate using dry etching. Both the third dielectric layer and the fourth dielectric layer are located on the upper surface of the gate oxide layer.

[0012] This preferred embodiment forms a third dielectric layer and a fourth dielectric layer on both sides of the gate through dry etching, and places the third dielectric layer and the fourth dielectric layer on the upper surface of the gate oxide layer, so that the third dielectric layer and the fourth dielectric layer can act as sidewalls of the gate, thereby modulating the edge electric field between the gate, the drift region, and the polysilicon doped structure; at the same time, it can increase the effective dielectric thickness between the gate and the substrate, further smoothing the surface electric field transition, thereby distributing the electric field more uniformly.

[0013] As a preferred embodiment, when the LDMOS device is an N-type LDMOS device, the ion type of the drift region is N-type, and the ion doping type of the polysilicon doped structure is P-type or N-type; when the LDMOS device is a P-type LDMOS device, the ion type of the drift region is P-type, and the ion doping type of the polysilicon doped structure is P-type or N-type.

[0014] This preferred embodiment ensures the applicability of the polysilicon doped structure and dielectric structure by setting the LDMOS device to either an N-type or P-type LDMOS device. When the ion doping type of the polysilicon doped structure is opposite to that of the drift region, the polysilicon doped structure forms a PN junction due to direct contact with the upper surface of the drift region, acting as a RESURF region, thereby adjusting the surface electric field intensity distribution. When the ion doping type of the polysilicon doped structure is the same as that of the drift region, the polysilicon doped structure contacts the upper surface of the drift region, thereby increasing the drift region area, improving the breakdown voltage area, and thus increasing the breakdown voltage of the LDMOS device.

[0015] Accordingly, this invention provides an LDMOS device, which is manufactured by the LDMOS device manufacturing method described above; The LDMOS device includes: a dielectric structure, a polysilicon doped structure, a substrate, a gate oxide layer, a gate, a drain, and a source. A channel region is formed on one side of the upper portion of the substrate; a drift region is formed on the other side of the upper portion of the substrate; The drain is disposed within the drift region; the source is disposed within the channel region; The polysilicon doped structure is disposed on the upper surface of the drift region, and the dielectric structure is disposed on both sides of the polysilicon doped structure; The gate oxide layer covers the upper surfaces of the polysilicon doped structure, the dielectric structure, the channel region, and the drift region; The gate is disposed on the upper surface of the gate oxide layer.

[0016] Understandably, compared to existing technologies, this invention utilizes an LDMOS device comprising a dielectric structure, a polysilicon doped structure, a substrate, a gate oxide layer, a gate, a drain, and a source. A channel region is formed on one side of the upper portion of the substrate, and a drift region is formed on the other side. A drain is then positioned within the drift region, and a source is positioned within the channel region. A polysilicon doped structure is then formed on the upper surface of the drift region. By directly contacting the polysilicon doped structure with the upper surface of the drift region, the drift region area can be increased, thereby increasing the breakdown voltage area and improving the breakdown voltage of the LDMOS device. Alternatively, it can... The surface electric field intensity distribution is adjusted; then, dielectric structures are set on both sides of the polysilicon doped structure, and a gate oxide layer covers the upper surface of the polysilicon doped structure, the dielectric structure, the channel region, and the drift region; through the contact between the dielectric structure and the gate oxide layer, the dielectric structure can act as the gate oxide layer of the gate, which can effectively reduce the electric field intensity below the gate near the drift region; by setting the polysilicon doped structure and the dielectric structure, the electric field intensity of the LDMOS device is reduced, the breakdown area is increased, and thus the breakdown voltage of the LDMOS device is improved.

[0017] As a preferred embodiment, the ion doping type of the polycrystalline silicon doped structure is the same as or opposite to the ion type of the drift region.

[0018] This preferred embodiment achieves this by having the polysilicon doping structure form a PN junction, acting as a RESURF region, when the ion doping type of the polysilicon doped structure is opposite to that of the drift region, as the polysilicon doped structure directly contacts the upper surface of the drift region, thereby adjusting the surface electric field intensity distribution. When the ion doping type of the polysilicon doped structure is the same as that of the drift region, the polysilicon doped structure contacts the upper surface of the drift region, thereby increasing the drift region area, improving the breakdown voltage area, and thus improving the breakdown voltage of the LDMOS device.

[0019] As a preferred embodiment, the dielectric structure includes: a first dielectric layer and a second dielectric layer; The first dielectric layer is disposed on one side of the polysilicon doped structure; The second dielectric layer is disposed on the other side of the polysilicon doped structure; The gate oxide layer covers the upper surfaces of the first dielectric layer and the second dielectric layer.

[0020] This preferred embodiment includes a dielectric structure comprising a first dielectric layer and a second dielectric layer, wherein the first dielectric layer is disposed on one side of the polysilicon doped structure and the second dielectric layer is disposed on the other side of the polysilicon doped structure; and the gate oxide layer is ensured to cover the upper surfaces of the first dielectric layer and the second dielectric layer; the dielectric structure can act as the gate oxide layer of the gate, and can effectively reduce the electric field strength below the gate near the drift region.

[0021] As a preferred embodiment, the LDMOS device further includes: a third dielectric layer and a fourth dielectric layer; The third dielectric layer is disposed on one side of the gate; the fourth dielectric layer is disposed on the other side of the gate; Both the third and fourth dielectric layers are located on the upper surface of the gate oxide layer.

[0022] This preferred embodiment provides a third dielectric layer and a fourth dielectric layer on both sides of the gate, with the third and fourth dielectric layers located on the upper surface of the gate oxide layer. This allows the third and fourth dielectric layers to act as sidewalls of the gate, thereby modulating the edge electric field between the gate, the drift region, and the polysilicon doped structure. Simultaneously, it increases the effective dielectric thickness between the gate and the substrate, further smoothing the surface electric field transition and resulting in a more uniform electric field distribution.

[0023] As a preferred embodiment, when the LDMOS device is an N-type LDMOS device, the ion type of the drift region is N-type, and the ion doping type of the polysilicon doped structure is P-type or N-type; when the LDMOS device is a P-type LDMOS device, the ion type of the drift region is P-type, and the ion doping type of the polysilicon doped structure is P-type or N-type.

[0024] This preferred embodiment ensures the applicability of the polysilicon doped structure and dielectric structure by setting the LDMOS device to either an N-type or P-type LDMOS device. When the ion doping type of the polysilicon doped structure is opposite to that of the drift region, the polysilicon doped structure forms a PN junction due to direct contact with the upper surface of the drift region, acting as a RESURF region, thereby adjusting the surface electric field intensity distribution. When the ion doping type of the polysilicon doped structure is the same as that of the drift region, the polysilicon doped structure contacts the upper surface of the drift region, thereby increasing the drift region area, improving the breakdown voltage area, and thus increasing the breakdown voltage of the LDMOS device. Attached Figure Description

[0025] Figure 1 A flowchart illustrating the steps of a method for manufacturing an LDMOS device according to an embodiment of the present invention; Figure 2This is a schematic diagram of the first LDMOS device structure provided in an embodiment of the present invention; Figure 3 This is a schematic diagram of a second LDMOS device structure provided in an embodiment of the present invention; Figure 4 This is a schematic diagram of a third LDMOS device structure provided in an embodiment of the present invention; Figure 5 This is a schematic diagram of the fourth LDMOS device structure provided in the embodiments of the present invention; Figure 6 This is a schematic diagram of the fifth LDMOS device structure provided in the embodiments of the present invention; Figure 7 This is a schematic diagram of the sixth LDMOS device structure provided in the embodiments of the present invention; Figure 8 This is a schematic diagram of the seventh LDMOS device structure provided in the embodiments of the present invention; Figure 9 This is a schematic diagram of the eighth LDMOS device structure provided in the embodiments of the present invention; Figure 10 This is a schematic diagram of the ninth LDMOS device structure provided in an embodiment of the present invention; Figure 11 This is a schematic diagram of the tenth LDMOS device structure provided in an embodiment of the present invention; Figure 12 This is a schematic diagram of the overall structure of an LDMOS device provided in an embodiment of the present invention; Figure 13 A detailed structural schematic diagram of an LDMOS device provided in an embodiment of the present invention; Figure 14 A schematic diagram of the doping distribution of a conventional LDMOS device provided in an embodiment of the present invention; Figure 15 A schematic diagram of the doping distribution of an LDMOS device with an inverse-type doped polysilicon doped structure provided in an embodiment of the present invention; Figure 16 A schematic diagram of the doping distribution of an LDMOS device with a similar doped polysilicon structure provided in an embodiment of the present invention; Figure 17 A schematic diagram of the electric field distribution in the breakdown state of a conventional LDMOS device provided in an embodiment of the present invention; Figure 18 A schematic diagram of the breakdown state electric field distribution of an LDMOS device with an inverse-type doped polysilicon doped structure provided in an embodiment of the present invention; Figure 19 A schematic diagram of the breakdown state electric field distribution of an LDMOS device with a similar doped polysilicon structure provided in an embodiment of the present invention; Figure 20 A comparison diagram of the surface electric field distribution of three LDMOS devices in the breakdown state provided in the embodiments of the present invention; Wherein, 1: substrate; 2: channel region; 3: drift region; 4: source; 5: drain; 6: polysilicon doped structure; 7: dielectric structure; 71: first dielectric layer; 72: second dielectric layer; 8: gate oxide layer; 9: gate; 101: third dielectric layer; 102: fourth dielectric layer; 11: metal wiring layer. Detailed Implementation

[0026] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0027] Example 1 Please refer to Figure 1 , Figure 1 The flowchart of a method for manufacturing an LDMOS device provided in an embodiment of the present invention includes steps S101 to S105.

[0028] Step S101: Determine substrate 1, form channel region 2 on one side of the upper part of the substrate, and form drift region 3 on the other side of the upper part of the substrate.

[0029] In one alternative embodiment, please refer to Figure 2 , Figure 2 This is a schematic diagram of the first LDMOS device structure provided in an embodiment of the present invention; Figure 3 This is a schematic diagram of a second LDMOS device structure provided in an embodiment of the present invention; as shown. Figure 2 First, substrate 1 is determined; in this embodiment, substrate 1 is selected as a silicon substrate; then as follows... Figure 3 As shown, an ion implantation process is then used to dope one side of the upper part of the substrate 1 to form the channel region 2; and the same ion implantation process is used on the other side of the substrate 1 to form the drift region 3. Wherein, if the LDMOS device is a PLDMOS device, then the channel region 2 is an N-type channel region with N-type ion doping, and the drift region 3 is a P-type drift region with P-type ion doping; if the LDMOS device is an NLDMOS device, then the channel region 2 is a P-type channel region with P-type ion doping, and the drift region 3 is an N-type drift region with N-type ion doping.

[0030] Step S102: A drain electrode 5 is formed in the drift region 3, and a source electrode 4 is formed in the channel region 2.

[0031] In one alternative embodiment, please refer to Figure 4 , Figure 4 This is a schematic diagram of a third LDMOS device structure provided in an embodiment of the present invention; wherein, a drain 5 is formed in the drift region 3 and a source 4 is formed in the channel region 2; the drain 5 can be formed by ion implantation or ion implantation with heating diffusion; the source 4 can be formed by ion implantation or ion implantation with heating diffusion.

[0032] Step S103: Deposit polysilicon on the upper surface of the drift region and dope the polysilicon to form a polysilicon doped structure 6 on the upper surface of the drift region.

[0033] In this embodiment, the deposition of polysilicon on the upper surface of the drift region and the doping of the polysilicon to form a polysilicon-doped structure on the upper surface of the drift region includes: Polycrystalline silicon is deposited on the upper surface of the drift region; Ions of the same or opposite type as those in the drift region are selected, and ion implantation is used to dope the polysilicon, thereby forming a polysilicon doped structure 6 on the upper surface of the drift region; wherein the ion doping type of the polysilicon doped structure 6 is the same or opposite to that of the drift region.

[0034] In one alternative embodiment, please refer to Figure 5 , Figure 5 This is a schematic diagram of the fourth LDMOS device structure provided in this embodiment of the invention. First, polysilicon is deposited on the upper surface of the drift region using low-pressure chemical vapor deposition (LPCVD) or plasma-enhanced chemical vapor deposition (PECVD). The deposition thickness can be specifically set according to actual design requirements. Then, based on the actual application requirements of the LDMOS device, ions of the same or opposite ion type (P-type or N-type) as those in drift region 3 are selected, and ion implantation is used to dope the polysilicon, thereby forming a structure on the upper surface of the drift region as shown in the diagram. Figure 5 The polycrystalline silicon doped structure 6 shown is illustrated. If the LDMOS device is a PLDMOS device, then drift region 3 is a P-type drift region, meaning the ion type in drift region 3 is P-type. In this case, the ions used for polysilicon doping can be either P-type or N-type. If N-type is selected, then the ion doping type of the formed polysilicon doped structure 6 is opposite to that of drift region 3. In this case, polysilicon doped structure 6 and drift region 3 form a PN junction, which acts as a RESURF region, thereby adjusting the surface electric field intensity distribution. If P-type ions are selected, then the ion doping type of the formed polysilicon doped structure 6 is the same as that of drift region 3. Polysilicon doped structure 6 contacts the upper surface of drift region 3, thereby increasing the drift region area, improving the breakdown voltage area, and thus improving the breakdown voltage of the LDMOS device. If the LDMOS device is an NLDMOS device, then drift region 3 is an N-type drift region, meaning the ion type in drift region 3 is N-type. In this case, the ions used for polysilicon doping can be either P-type or N-type. If P-type is selected, then the ion doping type of the formed polysilicon doped structure 6 is opposite to that of drift region 3. In this case, polysilicon doped structure 6 and drift region 3 form a PN junction, which acts as a RESURF region, thereby adjusting the surface electric field intensity distribution. If N-type ions are selected, then the ion doping type of the formed polysilicon doped structure 6 is the same as that of drift region 3. Polysilicon doped structure 6 contacts the upper surface of drift region 3, thereby increasing the drift region area, improving the breakdown voltage area, and thus increasing the breakdown voltage of the LDMOS device.

[0035] In this embodiment, polysilicon is deposited on the upper surface of the drift region. Ions of the same or opposite type as those in the drift region are selected and doped using ion implantation, thereby forming a polysilicon doped structure. When the ion doping type of the polysilicon doped structure is opposite to that of the drift region, the polysilicon doped structure forms a PN junction in direct contact with the upper surface of the drift region, acting as a RESURF region, thus adjusting the surface electric field intensity distribution. When the ion doping type of the polysilicon doped structure is the same as that of the drift region, the polysilicon doped structure contacts the upper surface of the drift region, thereby increasing the drift region area, improving the breakdown voltage area, and thus improving the breakdown voltage of the LDMOS device.

[0036] Step S104: A dielectric structure 7 is formed on both sides of the polysilicon doped structure 6 by dry etching.

[0037] In this embodiment, the formation of the dielectric structure 7 on both sides of the polysilicon doped structure 6 using dry etching includes: An initial dielectric layer is deposited on the upper surface and both sides of the polycrystalline silicon doped structure 6; The initial dielectric layer is dry etched to form a first dielectric layer 71 on one side of the polysilicon doped structure and a second dielectric layer 72 on the other side of the polysilicon doped structure. The first dielectric layer 71 and the second dielectric layer 72 constitute the dielectric structure 7.

[0038] In one alternative embodiment, please refer to Figure 6 and Figure 7 , Figure 6 This is a schematic diagram of the fifth LDMOS device structure provided in the embodiments of the present invention; Figure 7 This is a schematic diagram of the sixth LDMOS device structure provided in the embodiments of the present invention; as shown. Figure 6 As shown, in this embodiment, dielectric structures 7 are formed on both sides of the polysilicon doped structure 6. Further, a chemical vapor deposition (CVD) process is first used to deposit an initial dielectric layer on the upper surface and both sides of the polysilicon doped structure 6, so that the initial dielectric layer can cover the polysilicon doped structure 6. The material of the initial dielectric layer can be silicon dioxide (SiO2). Then, the initial dielectric layer is dry etched to form the structure shown. Figure 7 The first dielectric layer 71 is shown on one side of the polysilicon doped structure 6, and the second dielectric layer 72 is formed on the other side of the polysilicon doped structure 6.

[0039] In this embodiment, an initial dielectric layer is deposited on the upper surface and both sides of a polysilicon doped structure, followed by dry etching to form a first dielectric layer and a second dielectric layer. This allows the dielectric structure to act as a sidewall of the polysilicon doped structure. The dielectric structure formed by dry etching makes the surface potential change smoother and more controllable, effectively alleviating the electric field concentration at the gate edge. At the same time, this process does not require a photomask, which simplifies the process. The dielectric structure can also act as the gate oxide layer of the gate, effectively reducing the electric field intensity below the gate near the drift region.

[0040] Step S105: A gate oxide layer 8 is formed on the upper surface of the polysilicon doped structure 6, the dielectric structure 7, the channel region 2, and the drift region 3, so that the gate oxide layer 8 covers the upper surface of the polysilicon doped structure 6, the dielectric structure 7, the channel region 2, and the drift region 3.

[0041] In one alternative embodiment, please refer to Figure 8 , Figure 8 This is a schematic diagram of the seventh LDMOS device structure provided in the embodiments of the present invention; as shown. Figure 8As shown, the upper surfaces of the polysilicon doped structure 6, the dielectric structure 7, the channel region 2, and the drift region 3 are cleaned using a diluted hydrofluoric acid (DHF) solution; then, thermal oxidation is performed on the upper surfaces of the polysilicon doped structure 6, the dielectric structure 7, the channel region 2, and the drift region 3, thereby forming a structure as shown in the diagram. Figure 8 The gate oxide layer 8 is shown; and the gate oxide layer 8 is annealed; as shown Figure 8 As shown, the gate oxide layer 8 covers the upper surfaces of the polysilicon doped structure 6, the dielectric structure 7, the channel region 2, and the drift region 3.

[0042] Step S106: A gate 9 is disposed on the upper surface of the gate oxide layer 8.

[0043] In one alternative embodiment, please refer to Figure 9 , Figure 9 This is a schematic diagram of the eighth LDMOS device structure provided in this embodiment of the invention. The gate material is selected according to the requirements of the LDMOS device; in this embodiment, polysilicon is selected as the gate material. A layer of polysilicon is uniformly deposited on the upper surface of the gate oxide layer 8 as the gate material using low-pressure chemical vapor deposition (LPCVD), followed by ion implantation and rapid thermal annealing to heavily dope it and obtain low resistance. Then, photolithography and dry etching are performed on the gate material to form a structure on the upper surface of the gate oxide layer 8 as shown in the diagram. Figure 9 Gate 9 is shown; finally, the photoresist is removed and gate 9 is cleaned.

[0044] In this embodiment, please refer to Figure 10 , Figure 10 This is a schematic diagram of the ninth LDMOS device structure provided in an embodiment of the present invention; After the gate 9 is formed on the upper surface of the gate oxide layer 8, the method further includes: A third dielectric layer 101 is formed on one side of the gate 9 using dry etching. A fourth dielectric layer 102 is formed on the other side of the gate 9 using dry etching. The third dielectric layer 101 and the fourth dielectric layer 102 are both located on the upper surface of the gate oxide layer.

[0045] In an alternative embodiment, such as Figure 10 As shown, firstly, a fifth dielectric layer is deposited on the upper surface and both sides of the gate 9 using a chemical vapor deposition (CVD) process. The material of the fifth dielectric layer is silicon dioxide (SiO2). The fifth dielectric layer covers the gate 9. Then, the fifth dielectric layer is dry etched to form the desired shape. Figure 10The third dielectric layer 101 is shown on one side of the gate 9, and the fourth dielectric layer 102 is formed on the other side of the gate 9.

[0046] In this embodiment, a third dielectric layer and a fourth dielectric layer are formed on both sides of the gate by dry etching, and the third dielectric layer and the fourth dielectric layer are located on the upper surface of the gate oxide layer. This allows the third dielectric layer and the fourth dielectric layer to act as sidewalls of the gate, thereby modulating the edge electric field between the gate, the drift region, and the polysilicon doped structure. At the same time, it can increase the effective dielectric thickness between the gate and the substrate, further smoothing the surface electric field transition, thereby distributing the electric field more uniformly.

[0047] In one alternative embodiment, please refer to Figure 11 , Figure 11 This is a schematic diagram of the tenth LDMOS device structure provided in an embodiment of the present invention; as shown below. Figure 11 As shown, after completing the fabrication of the third dielectric layer 101 and the fourth dielectric layer 102 of the LDMOS device, a metal wiring layer 11 also needs to be formed; wherein, the metal wiring layer 11 is connected to the source 4; the metal wiring layer is connected to the drain 5; the metal wiring layer 11 is used to connect the source 4 and the drain 5; after completing the fabrication of the third dielectric layer 101 and the fourth dielectric layer 102 of the LDMOS device, a metal wiring layer 11 is also needed; wherein, the metal wiring layer 11 is connected to ...; the metal wiring layer 11 is connected to the drain 5; the metal wiring layer 11 is used to connect the source 4 and the drain 5; after completing Figure 11 After the LDMOS device shown is fabricated, the manufacturing of the LDMOS device is complete.

[0048] In this embodiment, when the LDMOS device is an N-type LDMOS device, the ion type of the drift region is N-type, and the ion doping type of the polysilicon doped structure is P-type or N-type; when the LDMOS device is a P-type LDMOS device, the ion type of the drift region is P-type, and the ion doping type of the polysilicon doped structure is P-type or N-type.

[0049] This embodiment ensures the applicability of the polysilicon doped structure and dielectric structure by setting the LDMOS device to either an N-type or P-type LDMOS device. When the ion doping type of the polysilicon doped structure is opposite to that of the drift region, the polysilicon doped structure forms a PN junction due to direct contact with the upper surface of the drift region, thus acting as a RESURF region and adjusting the surface electric field intensity distribution. When the ion doping type of the polysilicon doped structure is the same as that of the drift region, the polysilicon doped structure contacts the upper surface of the drift region, thereby increasing the drift region area, improving the breakdown voltage area, and thus increasing the breakdown voltage of the LDMOS device.

[0050] Example 2 Please refer to Figure 12 and Figure 13 , Figure 12This is a schematic diagram of the overall structure of an LDMOS device provided in an embodiment of the present invention; Figure 13 A detailed structural schematic diagram of an LDMOS device provided in an embodiment of the present invention; The LDMOS device is manufactured by a method for manufacturing an LDMOS device as described in Embodiment 1 above; The LDMOS device includes: a dielectric structure 7, a polysilicon doped structure 6, a substrate 1, a gate oxide layer 8, a gate 9, a drain 5, and a source 4. A channel region 2 is formed on one side of the upper part of the substrate 1; a drift region 3 is formed on the other side of the upper part of the substrate 1. The drain electrode 5 is disposed within the drift region 3; the source electrode 4 is disposed within the channel region 2; The polysilicon doped structure 6 is disposed on the upper surface of the drift region 3, and the dielectric structure 7 is disposed on both sides of the polysilicon doped structure 6. The gate oxide layer 8 covers the upper surfaces of the polysilicon doped structure 6, the dielectric structure 7, the channel region 2, and the drift region 3; The gate 9 is disposed on the upper surface of the gate oxide layer 8.

[0051] In this embodiment, the ion doping type of the polysilicon doped structure 6 is the same as or opposite to the ion type of the drift region 3.

[0052] In this embodiment, when the ion doping type of the polysilicon doped structure is opposite to that of the drift region, the polysilicon doped structure forms a PN junction by directly contacting the upper surface of the drift region, thus acting as a RESURF region and adjusting the surface electric field intensity distribution. When the ion doping type of the polysilicon doped structure is the same as that of the drift region, the polysilicon doped structure contacts the upper surface of the drift region, thereby increasing the drift region area, improving the breakdown voltage area, and thus improving the breakdown voltage of the LDMOS device.

[0053] In this embodiment, as Figure 13 As shown, the dielectric structure 7 includes: a first dielectric layer 71 and a second dielectric layer 72; The first dielectric layer 71 is disposed on one side of the polysilicon doped structure 6; The second dielectric layer 72 is disposed on the other side of the polysilicon doped structure 6; The gate oxide layer 8 covers the upper surfaces of the first dielectric layer 71 and the second dielectric layer 72.

[0054] This embodiment sets a dielectric structure including a first dielectric layer and a second dielectric layer. The first dielectric layer is disposed on one side of the polysilicon doped structure, and the second dielectric layer is disposed on the other side of the polysilicon doped structure. At the same time, it ensures that the gate oxide layer covers the upper surfaces of the first dielectric layer and the second dielectric layer. The dielectric structure can act as the gate oxide layer of the gate, which can effectively reduce the electric field strength below the gate near the drift region.

[0055] In this embodiment, the LDMOS device further includes: a third dielectric layer 101 and a fourth dielectric layer 102; The third dielectric layer 101 is disposed on one side of the gate 9; the fourth dielectric layer 102 is disposed on the other side of the gate 9; The third dielectric layer 101 and the fourth dielectric layer 102 are both located on the upper surface of the gate oxide layer 8.

[0056] In this embodiment, by setting a third dielectric layer and a fourth dielectric layer on both sides of the gate, and with the third dielectric layer and the fourth dielectric layer located on the upper surface of the gate oxide layer, the third dielectric layer and the fourth dielectric layer can act as sidewalls of the gate, thereby modulating the edge electric field between the gate, the drift region, and the polysilicon doped structure; at the same time, it can increase the effective dielectric thickness between the gate and the substrate, further smoothing the surface electric field transition, thereby distributing the electric field more uniformly.

[0057] In an alternative embodiment, such as Figure 12 and Figure 13 As shown, the LDMOS device further includes: a metal wiring layer 11; the metal wiring layer 11 and the upper surface of the drain 5; the metal wiring layer 11 is disposed on the upper surface of the source 4.

[0058] This embodiment, by setting a metal wiring layer, enables the drain and source to be connected, thereby electrically connecting the LDMOS device, ensuring the electrical stability of the LDMOS device, and ensuring that the LDMOS device can be used normally.

[0059] In this embodiment, when the LDMOS device is an N-type LDMOS device, the ion type of the drift region is N-type, and the ion doping type of the polysilicon doped structure is P-type or N-type; when the LDMOS device is a P-type LDMOS device, the ion type of the drift region is P-type, and the ion doping type of the polysilicon doped structure is P-type or N-type.

[0060] This embodiment ensures the applicability of the polysilicon doped structure and dielectric structure by setting the LDMOS device to either an N-type or P-type LDMOS device. When the ion doping type of the polysilicon doped structure is opposite to that of the drift region, the polysilicon doped structure forms a PN junction due to direct contact with the upper surface of the drift region, thus acting as a RESURF region and adjusting the surface electric field intensity distribution. When the ion doping type of the polysilicon doped structure is the same as that of the drift region, the polysilicon doped structure contacts the upper surface of the drift region, thereby increasing the drift region area, improving the breakdown voltage area, and thus increasing the breakdown voltage of the LDMOS device.

[0061] In an optional embodiment, to verify the performance of the LDMOS device provided in this embodiment of the invention in terms of breakdown voltage (BV) and specific on-resistance (Ron, sp), this embodiment conducts an experimental comparison between LDMOS devices with different doping types and conventional LDMOS devices; please refer to Table 1, which is a data table of different doping types of an LDMOS device provided in this embodiment of the invention; wherein, conventional LDMOS devices refer to LDMOS devices commonly used in the art; RESURF technology (REduced surface field) is a technology used to optimize the withstand voltage capability of high voltage semiconductor devices (such as LDMOS). "Inverse-type doped polysilicon structure" refers to a polysilicon doped structure 6 described in this embodiment where the ion doping type is opposite to that of the drift region 3; "Same-type doped polysilicon structure" refers to a polysilicon doped structure 6 described in this embodiment where the ion doping type is the same as that of the drift region 3; "VTG" is the threshold voltage of the gate, which is the minimum gate voltage required for the channel region of an LDMOS device to begin forming a conductive channel and for the device to transition from the off state to the on state. BV is the breakdown voltage, and Ron, sp is the specific on-resistance; in this field, the value used to evaluate the quality of an LDMOS device from the perspectives of breakdown voltage and conduction loss is called the FOM value. The larger the FOM value, the better the performance of the LDMOS device.

[0062] Table 1 first, Figure 14 A schematic diagram of the doping distribution of a conventional LDMOS device provided in an embodiment of the present invention; Figure 15 A schematic diagram of the doping distribution of an LDMOS device with an inverse-type doped polysilicon doped structure provided in an embodiment of the present invention; Figure 16This is a schematic diagram of the doping distribution of an LDMOS device with a similar doped polysilicon structure provided in an embodiment of the present invention; as shown below. Figure 14 As shown, traditional LDMOS devices do not use polysilicon doped structures; while... Figure 15 As shown, this embodiment uses an LDMOS device with an inverse-type doped polysilicon doped structure. Figure 15 The purple rectangle in the image represents the polycrystalline doped structure, and it can be seen that its doping differs from that of the orange region below (i.e., the drift region); while... Figure 16 As shown, this embodiment uses an LDMOS device with the same type of doped polysilicon structure. Figure 16 The orange rectangle in the image represents the polycrystalline doped structure, and it can be seen that it has the same doping as the orange region below (i.e., the drift region).

[0063] As shown in Table 1, the gate threshold voltage (VTG) of a conventional LDMOS device is 1.21V, while the LDMOS device used in this embodiment, which has an inverse-type doped polysilicon doped structure or a homo-type doped polysilicon doped structure, has a gate threshold voltage (VTG) of 1.18V, which is significantly lower than that of a conventional LDMOS device. This indicates that the LDMOS device provided in this embodiment has significantly lower operational requirements than that of a conventional LDMOS device.

[0064] Secondly Figure 17 A schematic diagram of the electric field distribution in the breakdown state of a conventional LDMOS device provided in an embodiment of the present invention; Figure 18 A schematic diagram of the breakdown state electric field distribution of an LDMOS device with an inverse-type doped polysilicon doped structure provided in an embodiment of the present invention; Figure 19 A schematic diagram of the breakdown state electric field distribution of an LDMOS device with a similar doped polysilicon structure provided in an embodiment of the present invention; Figure 20 This is a comparison diagram of the surface electric field distribution of three LDMOS devices in the breakdown state provided in the embodiments of the present invention; Figure 20 In the diagram, the red curve represents the surface electric field distribution of a conventional LDMOS device in the breakdown state; the green curve represents the surface electric field distribution of an LDMOS device with the same type of doped polysilicon structure in the breakdown state; and the blue curve represents the surface electric field distribution of an LDMOS device with the opposite type of doped polysilicon structure in the breakdown state. (Comparison) Figure 17 , Figure 18 , Figure 19 and Figure 20 Different colors represent different electric field strengths, with red indicating a stronger electric field; compared to Figure 17 The inverse-type doped polysilicon doped structure of this embodiment ( Figure 18 ) and similar doped polycrystalline silicon structures ( Figure 19A breakdown point was added to the lower right side of the polycrystalline silicon doped structure, and by Figure 20 As can be seen from this, both the inverse-type doped polysilicon doped structure and the same-type doped polysilicon doped structure in this embodiment have electric field peaks on the lower right side of the polysilicon doped structure, which optimizes the electric field distribution on the device surface and makes the electric field distribution more uniform. Therefore, regardless of whether an inverse-type doped polysilicon doped structure or a same-type doped polysilicon doped structure is used, the electric field distribution of the final LDMOS device in the breakdown state is better than that of the traditional LDMOS device. Furthermore, as shown in Figure 1, the breakdown voltage (BV) of a conventional LDMOS device is 19V, while the LDMOS device using the inverse doped polysilicon structure in this embodiment has a breakdown voltage (BV) of 22.9V; the LDMOS device using the same doped polysilicon structure has a breakdown voltage (VTG) of 22.3V. The breakdown voltages of the LDMOS devices provided in this embodiment are all higher than those of conventional LDMOS devices, indicating that the LDMOS devices provided in this embodiment have significantly higher breakdown voltage performance than conventional LDMOS devices. As shown in Table 1, the LDMOS device provided in this embodiment exhibits significantly higher breakdown voltage performance than traditional LDMOS devices. The specific on-resistance of the traditional LDMOS device is 3.45, while the specific on-resistance of the LDMOS device using an inverse-type doped polysilicon structure is 3.91; and the specific on-resistance of the LDMOS device using a homogeneous doped polysilicon structure is 3.75. Despite a substantial increase in breakdown voltage, the specific on-resistance of the LDMOS device in this embodiment only increases slightly, indicating that the LDMOS device in this embodiment has superior performance.

[0065] As shown in Table 1, the FOM value of a traditional LDMOS device is 104.6, while the FOM value of an LDMOS device using an inverse-type doped polysilicon doped structure in this embodiment is 134.1; and the FOM value of an LDMOS device using a homogeneous doped polysilicon doped structure is 132.6. The breakdown voltage of the LDMOS device provided in this embodiment is higher than that of the traditional LDMOS device, indicating that the LDMOS device provided in this embodiment has significantly better performance in terms of withstand voltage and conduction loss than the traditional LDMOS device.

[0066] In summary, this invention provides an LDMOS device comprising a dielectric structure, a polysilicon doped structure, a substrate, a gate oxide layer, a gate, a drain, and a source. A channel region is formed on one side of the upper portion of the substrate, and a drift region is formed on the other side of the upper portion of the substrate. A drain is then positioned within the drift region, and a source is positioned within the channel region. A polysilicon doped structure is then formed on the upper surface of the drift region. By forming the polysilicon doped structure in direct contact with the upper surface of the drift region, the drift region area can be increased, thereby increasing the breakdown voltage of the LDMOS device. Alternatively, the surface charge can be adjusted. The electric field intensity distribution is then determined. Dielectric structures are then formed on both sides of the polysilicon doped structure, and a gate oxide layer covers the upper surfaces of the polysilicon doped structure, the dielectric structure, the channel region, and the drift region. Through the contact between the dielectric structure and the gate oxide layer, the dielectric structure can act as the gate oxide layer, effectively reducing the electric field intensity below the gate near the drift region. By setting the polysilicon doped structure and the dielectric structure, the electric field intensity of the LDMOS device is reduced, the breakdown area is increased, and thus the breakdown voltage of the LDMOS device is improved.

[0067] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above descriptions are merely specific embodiments of the present invention and are not intended to limit the scope of protection of the present invention. In particular, it should be noted that any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention for those skilled in the art.

Claims

1. A method for manufacturing an LDMOS device, characterized in that, Includes the following steps: A substrate is defined, a channel region is formed on one side of the upper part of the substrate, and a drift region is formed on the other side of the upper part of the substrate; A drain is formed in the drift region, and a source is formed in the channel region; Polysilicon is deposited on the upper surface of the drift region and then doped to form a polysilicon doped structure on the upper surface of the drift region. A dielectric structure is formed on both sides of the polysilicon doped structure by dry etching. A gate oxide layer is formed on the upper surface of the polysilicon doped structure, the dielectric structure, the channel region, and the drift region, so that the gate oxide layer covers the upper surface of the polysilicon doped structure, the dielectric structure, the channel region, and the drift region; A gate is disposed on the upper surface of the gate oxide layer.

2. The method for manufacturing an LDMOS device as described in claim 1, characterized in that, The process of depositing polysilicon on the upper surface of the drift region and doping the polysilicon to form a polysilicon-doped structure on the upper surface of the drift region includes: Polycrystalline silicon is deposited on the upper surface of the drift region; Ions of the same or opposite type as those in the drift region are selected, and ion implantation is used to dope the polycrystalline silicon, thereby forming a polycrystalline silicon doped structure on the upper surface of the drift region; wherein the ion doping type of the polycrystalline silicon doped structure is the same or opposite as that of the drift region.

3. The method for manufacturing an LDMOS device as described in claim 1, characterized in that, The process of forming a dielectric structure on both sides of the polysilicon doped structure using dry etching includes: An initial dielectric layer is deposited on the upper surface and both sides of the polycrystalline silicon doped structure; The initial dielectric layer is dry etched to form a first dielectric layer on one side of the polysilicon doped structure and a second dielectric layer on the other side of the polysilicon doped structure. The first dielectric layer and the second dielectric layer constitute a dielectric structure.

4. The method for manufacturing an LDMOS device as described in claim 1, characterized in that, After the gate is formed on the upper surface of the gate oxide layer, the method further includes: A third dielectric layer is formed on one side of the gate using dry etching. A fourth dielectric layer is formed on the other side of the gate using dry etching. Both the third dielectric layer and the fourth dielectric layer are located on the upper surface of the gate oxide layer.

5. The method for manufacturing an LDMOS device as described in claim 2, characterized in that, When the LDMOS device is an N-type LDMOS device, the ion type of the drift region is N-type, and the ion doping type of the polysilicon doped structure is P-type or N-type; when the LDMOS device is a P-type LDMOS device, the ion type of the drift region is P-type, and the ion doping type of the polysilicon doped structure is P-type or N-type.

6. An LDMOS device, characterized in that, The LDMOS device is manufactured by the manufacturing method of an LDMOS device according to any one of claims 1 to 5; The LDMOS device includes: a dielectric structure, a polysilicon doped structure, a substrate, a gate oxide layer, a gate, a drain, and a source. A channel region is formed on one side of the upper portion of the substrate; a drift region is formed on the other side of the upper portion of the substrate; The drain is disposed within the drift region; the source is disposed within the channel region; The polysilicon doped structure is disposed on the upper surface of the drift region, and the dielectric structure is disposed on both sides of the polysilicon doped structure; The gate oxide layer covers the upper surfaces of the polysilicon doped structure, the dielectric structure, the channel region, and the drift region; The gate is disposed on the upper surface of the gate oxide layer.

7. An LDMOS device as described in claim 6, characterized in that, The ion doping type of the polycrystalline silicon doped structure is the same as or opposite to the ion type of the drift region.

8. An LDMOS device as described in claim 6, characterized in that, The dielectric structure includes: a first dielectric layer and a second dielectric layer; The first dielectric layer is disposed on one side of the polysilicon doped structure; The second dielectric layer is disposed on the other side of the polysilicon doped structure; The gate oxide layer covers the upper surfaces of the first dielectric layer and the second dielectric layer.

9. An LDMOS device as described in claim 6, characterized in that, Also includes: The third and fourth dielectric layers; The third dielectric layer is disposed on one side of the gate; The fourth dielectric layer is disposed on the other side of the gate; Both the third and fourth dielectric layers are located on the upper surface of the gate oxide layer.

10. An LDMOS device as described in claim 7, characterized in that, When the LDMOS device is an N-type LDMOS device, the ion type of the drift region is N-type, and the ion doping type of the polysilicon doped structure is P-type or N-type; when the LDMOS device is a P-type LDMOS device, the ion type of the drift region is P-type, and the ion doping type of the polysilicon doped structure is P-type or N-type.

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