LDMOS device and method of manufacturing the same
By introducing a low-doped or inverted first low-doped region and a second low-doped region into the LDMOS device, an electron cooling layer is formed, which solves the hot carrier injection effect in the high electric field region, improves device performance and reduces on-resistance.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SOUTHEAST UNIV
- Filing Date
- 2026-04-21
- Publication Date
- 2026-07-07
AI Technical Summary
In LDMOS devices, the hot carrier injection effect in the high electric field region leads to a decrease in the oxide layer interface quality, affecting device performance, especially in SiC materials.
In LDMOS devices, a first low-doped region or a second low-doped region with low doping or inversion is introduced to form an electron cooling layer, which adjusts the electric field distribution and reduces the electric field intensity in the electric field concentration region, thereby alleviating the hot carrier injection effect.
By using sparse potential line distribution, the electric field and collisional ionization rate are reduced, the hot carrier injection effect of the device is improved, the device performance is enhanced, and the on-resistance is reduced.
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Figure CN122349239A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor device technology, and in particular to an LDMOS device and a method for manufacturing an LDMOS device. Background Technology
[0002] As the semiconductor industry continues to develop, the component density of integrated circuits is constantly increasing with the miniaturization of device dimensions. Among them, the lateral diffused metal-oxide-semiconductor field-effect transistor (LDMOS), as an integrated power device, has also been developing towards higher gain and higher power density. With the reduction of gate oxide thickness, channel length, and the continuous increase of breakdown voltage, high electric field regions inevitably appear inside the device. Under the influence of these high electric fields, charge carriers gain significantly higher kinetic energy than the average kinetic energy of the thermal equilibrium state; these high-energy charge carriers are called "hot carriers." Hot carriers further collide with the crystal lattice, ionizing to generate electron-hole pairs. Some "lucky electrons" overcome the interface barrier and inject into the oxide layer, where they are captured by the oxide layer's trap charges or generate interface states. The deterioration of the oxide layer interface quality leads to threshold voltage drift and current capability degradation, seriously affecting device performance.
[0003] In recent years, to further improve the power density of devices, emerging wide-bandgap semiconductors, such as silicon carbide (SiC), have also been used to manufacture high-performance LDMOS. Compared with Si, SiC has a worse interface quality and is therefore more sensitive to hot carrier effects. Summary of the Invention
[0004] Therefore, it is necessary to provide an LDMOS device and its manufacturing method that can improve the hot carrier injection effect of the device.
[0005] An LDMOS device includes: a source region having a first conductivity type; a drain region having a first conductivity type; a drift region having a first conductivity type, at least a portion of which is located between the source region and the drain region; a field oxide layer on the drift region; a gate extending from a position near the edge of the source region onto the field oxide layer; a first lightly doped region located directly below the field oxide layer on the side near the source region; and a second lightly doped region located directly below the gate on the side near the drain region, wherein the region between the first and second lightly doped regions has a first conductivity type; wherein the first and second lightly doped regions have a first conductivity type and the doping concentration is lower than the doping concentration of the region between the first and second lightly doped regions; or the first and second lightly doped regions have a second conductivity type, the second conductivity type being the opposite of the first conductivity type.
[0006] In the aforementioned LDMOS device, low-doped or inverted regions (i.e., a first low-doped region and a second low-doped region) are introduced in two regions where the electric field was originally concentrated (directly below the source region of the field oxide layer, and directly below the drain region of the gate) to form an electron cooling layer. This makes the potential line distribution in these two regions, which were originally concentrated in electric field, sparse, thereby reducing the electric field in these two regions, decreasing the collisional ionization rate, and mitigating the hot carrier injection effect in these two regions.
[0007] In one embodiment, the LDMOS device further includes a first conductivity type region located between the first low-doped region and the second low-doped region, wherein the doping concentration of the first conductivity type region is greater than the doping concentration of the drift region.
[0008] In one embodiment, the LDMOS device further includes: a body region having a second conductivity type, wherein the source region is located in the body region; a first well region having a second conductivity type and located below the first low-doped region; and a second well region having a second conductivity type and located below the second low-doped region; wherein the first low-doped region and the second low-doped region have the second conductivity type, and the doping concentration of the first low-doped region and the second low-doped region is less than the doping concentration of the body region, the first well region, and the second well region.
[0009] In one embodiment, the first well region and the second well region are formed in the same ion implantation step after photolithography using the same photomask as the body region.
[0010] In one embodiment, the LDMOS device further includes a third well region, wherein the drain region is at least partially located in the third well region, and the doping concentration of the third well region is greater than the doping concentration of the drift region.
[0011] In one embodiment, the first conductivity type region is formed in the same ion implantation step after photolithography using the same photomask as the third well region.
[0012] In one embodiment, the drain region is at least partially formed in the third well region.
[0013] In one embodiment, the LDMOS device further includes a buffer located below the third well region and the drain region, the buffer having a first conductivity type and a doping concentration greater than that of the drift region.
[0014] In one embodiment, the doping concentration of the first low-doped region and the second low-doped region is lower than that of the drift region.
[0015] In one embodiment, the first conductivity type is N-type, the second conductivity type is P-type, and the LDMOS device is an N-channel LDMOS device.
[0016] In one embodiment, the LDMOS device is a silicon carbide device.
[0017] A method for manufacturing an LDMOS device includes: obtaining a wafer with a drift region formed thereon, the drift region having a first conductivity type; forming a first conductivity type well region and a second conductivity type well region in the drift region by photolithography, ion implantation of the first conductivity type, and ion implantation of the second conductivity type, respectively; the region where the second conductivity type well region overlaps with a first side of the first conductivity type well region is a first low-doped region, and the region where the second conductivity type well region overlaps with a second side of the first conductivity type well region is a second low-doped region; the second conductivity type is the opposite of the first conductivity type; the first low-doped region and the second... The low-doped region has a first conductivity type and the doping concentration is lower than that of the well region of the first conductivity type, or the first low-doped region and the second low-doped region have a second conductivity type; a field oxide layer is formed on the drift region, and the first low-doped region is located directly below a first side of the field oxide layer; a gate is formed on the drift region with one end extending to the field oxide layer, and the second low-doped region is located directly below a first side of the gate; a source region and a drain region are formed on both sides of the drift region below the field oxide layer; the first side of the gate is the side away from the source region, and the first side of the field oxide layer is the side away from the drain region.
[0018] The aforementioned LDMOS device fabrication method involves one N-type ion implantation and one P-type ion implantation, forming a first and a second lightly doped region at the overlapping location of the two implantations. These two lightly doped or inverted regions can serve as electron cooling layers. This sparses the potential line distribution in these two regions, which were originally characterized by concentrated electric fields, thereby reducing the electric field and decreasing the collisional ionization rate, thus mitigating the hot carrier injection effect. The portion of the first conductivity type well region located between the first and second lightly doped regions provides a current path, reducing the device's on-resistance.
[0019] In one embodiment, the step of forming a first conductivity type well region and a second conductivity type well region in the drift region by photolithography, ion implantation of a first conductivity type, and ion implantation of a second conductivity type includes: forming a second conductivity type body region in the drift region simultaneously with forming the second conductivity type well region by photolithography and ion implantation of the second conductivity type; the step of forming the source region is to form the source region in the body region.
[0020] In one embodiment, the step of forming the second conductivity type well region includes forming a first well region located below the first low-doped region and a second well region located directly below the second low-doped region, the first well region and the second well region having a second conductivity type.
[0021] In one embodiment, the step of forming a first conductivity type well region and a second conductivity type well region in the drift region by photolithography, ion implantation of a first conductivity type and ion implantation of a second conductivity type respectively includes: forming a third well region of the first conductivity type in the drift region simultaneously by photolithography and ion implantation of the first conductivity type to form the first conductivity type well region.
[0022] In one embodiment, the step of forming the first conductivity type well region includes forming a first conductivity type region located between the first low-doped region and the second low-doped region.
[0023] In one embodiment, the distance between the side of the second conductivity type well region near the source region and the source region is not greater than the distance between the side of the first conductivity type well region near the source region and the source region, and the distance between the side of the second conductivity type well region near the drain region and the drain region is not greater than the distance between the side of the first conductivity type well region near the drain region and the drain region. Attached Figure Description
[0024] To better describe and illustrate embodiments and / or examples of the inventions disclosed herein, reference may be made to one or more accompanying drawings. Additional details or examples used to describe the drawings should not be considered as limiting the scope of any of the disclosed inventions, the currently described embodiments and / or examples, or the best mode of these inventions as currently understood.
[0025] Figure 1 This is a schematic diagram of the structure of an LDMOS device in one embodiment of this application.
[0026] Figure 2 This is a schematic diagram of the structure of an LDMOS device in another embodiment of this application.
[0027] Figure 3 This is a schematic diagram of the structure of an LDMOS device in another embodiment of this application.
[0028] Figure 4 This is a schematic diagram of the structure of an LDMOS device in another embodiment of this application.
[0029] Figure 5 The potential line distribution is shown in the embodiments and comparative examples of this application.
[0030] Figure 6The electric field distribution is shown in the embodiments and comparative examples of this application.
[0031] Figure 7 The collision ionization rate distribution is shown in the embodiments and comparative examples of this application.
[0032] Figure 8 This is a flowchart of a method for manufacturing an LDMOS device according to an embodiment of this application. Detailed Implementation
[0033] To facilitate understanding of the present invention, a more complete description will be given below with reference to the accompanying drawings. Preferred embodiments of the invention are shown in the drawings. However, the invention can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
[0034] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.
[0035] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this invention, the first element, component, area, layer, or portion discussed below may be referred to as the second element, component, area, layer, or portion.
[0036] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “under” the other element or feature will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.
[0037] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.
[0038] Embodiments of the invention are described herein with reference to cross-sectional views that serve as schematic diagrams of ideal embodiments (and intermediate structures). Thus, variations in the shape shown can be anticipated due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the invention should not be limited to the specific shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing processes. For example, implantation regions shown as rectangular typically have rounded or curved features at their edges and / or implantation concentration gradients, rather than a binary change from implantation regions to non-implantation regions. Similarly, the buried regions formed by implantation can result in some implantation in the region between the buried region and the surface traversed during implantation. Therefore, the regions shown in the figures are substantially schematic, and their shapes are not intended to show the actual shapes of the regions of the device and are not intended to limit the scope of the invention.
[0039] The semiconductor terminology used in this article is the technical terminology commonly used by those skilled in the art. For example, for P-type and N-type impurities, in order to distinguish the doping concentration, P+ type represents heavily doped P-type, P type represents moderately doped P-type, P- type represents lightly doped P-type, N+ type represents heavily doped N-type, N type represents moderately doped N-type, and N- type represents lightly doped N-type.
[0040] Through experiments and research, the inventors discovered that when a SiC LDMOS operates in a high-voltage forward conduction state for a long time, electric field concentration occurs at the edge of the field oxide near the source and at the end of the polysilicon near the drain, which intensifies collisional ionization. Severe hot carrier injection is likely to occur in these two regions, forming interface traps or trap charges in the oxide layer, which leads to an increase in the on-resistance of the device. Moreover, the interface trap charges near the source have a greater impact on the on-resistance than the interface trap charges near the drain.
[0041] This application proposes an LDMOS device structure that improves the device's resistance to thermal carrier effects by optimizing the electric field distribution at the field oxygen edge and the end of the gate field plate. Figure 1 This is a schematic diagram of an LDMOS device according to an embodiment of this application, including a source region 142, a drain region 144, a drift region 112, a field oxide layer 160, a gate 170, a first low-doped region 132, and a second low-doped region 134. The source region 142, drain region 144, and drift region 112 have a first conductivity type. At least a portion of the drift region 112 is located between the source region 142 and the drain region 144. The field oxide layer 160 is located on the drift region 112. The gate 170 extends from a position near the edge of the source region 142 onto the field oxide layer 160 (actually, the portion of the gate 170 on the field oxide layer 160 is a gate field plate, which is uniformly referred to as the gate in this application). The first low-doped region 132 is located directly below the side of the field oxide layer 160 near the source region 142. The second low-doped region 134 is located directly below the side of the gate 170 near the drain region 144 (i.e., the side of the structure where the gate material extends onto the field oxide layer 160 near the drain region 144). The region between the first low-doped region 132 and the second low-doped region 134 has a first conductivity type. Figure 1 In the illustrated embodiment, the region between the first low-doped region 132 and the second low-doped region 134 is part of the drift region 112. The purpose of setting the first low-doped region 132 and the second low-doped region 134 is to adjust the electric field at the corresponding locations. The region from the first low-doped region 132 to the second low-doped region 134 needs to exhibit a first conductivity type doping with low doping concentrations (even inversion to the second conductivity type) on both sides and high doping concentrations in the middle. Therefore, the first low-doped region 132 and the second low-doped region 134 have the first conductivity type, and their doping concentrations are lower than the doping concentrations in the region between the first low-doped region 132 and the second low-doped region 134; or the first low-doped region 132 and the second low-doped region 134 have the second conductivity type. Figure 1 In the illustrated embodiment, the device is an N-channel LDMOS, and correspondingly, the first conductivity type is N-type and the second conductivity type is P-type; in other embodiments, the device may also be a P-channel LDMOS, and correspondingly, the first conductivity type is P-type and the second conductivity type is N-type. The doping concentration of the source region 142 and the drain region 144 is greater than the doping concentration of the drift region 112.
[0042] In the aforementioned LDMOS device, low-doped or inverted regions (i.e., the first low-doped region 132 and the second low-doped region 134) are introduced into two regions where the electric field was originally concentrated (directly below the side of the field oxide layer 160 near the source region 142, and directly below the side of the gate 170 near the drain region 144) to form an electron cooling layer. This makes the potential line distribution in these two regions, which were originally concentrated in electric field, sparse, thereby reducing the electric field at these two locations, decreasing the collisional ionization rate, and mitigating the hot carrier injection effect at these locations.
[0043] See Figure 2 In one embodiment of this application, the LDMOS device further includes a first conductivity type region 125 located between a first low-doped region 132 and a second low-doped region 134. The doping concentration of the first conductivity type region 125 is greater than the doping concentration of the drift region 112. The first conductivity type region 125 can provide a current path, reducing the impact of the first low-doped region 132 and the second low-doped region 134 on the on-resistance of the device.
[0044] See Figure 3 In one embodiment of this application, the LDMOS device further includes a body region 122, a first well region 121, and a second well region 123. The body region 122 has a second conductivity type, and a source region 142 is located within the body region 122. The first well region 121 has a second conductivity type and is located below a first low-doped region 132. The second well region 123 has a second conductivity type and is located below a second low-doped region 134. The first well region 121 and the second well region 123 are formed using the same photomask as the body region 122 and in the same ion implantation step. Therefore, the junction depth of the first well region 121 and the second well region 123 is the same as that of the body region 122. Since the first well region 121 and the second well region 123 share a photomask with the body region 122 and are formed in the same ion implantation step, the first well region 121 and the second well region 123 do not require additional photomasks and processes, which helps control manufacturing costs.
[0045] In embodiments where the first low-doped region 132 and the second low-doped region 134 have a second conductivity type, the doping concentration of the first low-doped region 132 and the second low-doped region 134 is less than the doping concentration of the body region 122, the first well region 121 and the second well region 123.
[0046] In one embodiment of this application, the first low-doped region 132 and the second low-doped region 134 have a first conductivity type and a doping concentration lower than that of the drift region 112.
[0047] In one embodiment of this application, the LDMOS device further includes a third well region 124. A drain region 144 is at least partially located within the third well region 124. The doping concentration of the third well region 124 is greater than the doping concentration of the drift region 112. In one embodiment of this application, a first conductivity type region 125 is formed using the same photomask as the third well region 124 and then formed in the same ion implantation step as the third well region 124.
[0048] In one embodiment of this application, the region formed in the drift region 112 by the implantation step to form the first conductivity type region 125 partially overlaps with the region formed in the drift region 112 by the implantation steps to form the first well region 121 and the second well region 123. This overlapping region constitutes the first low-doped region 132 and the second low-doped region 134. Since the two implanted conductivity types are opposite, they neutralize each other, resulting in lower doping concentrations in the first low-doped region 132 and the second low-doped region 134. The ion implantation to form the first conductivity type region 125 is intended to control the diffusion range of the first well region 121 and the second well region 123, optimizing charge matching and preventing excessively high concentrations and large areas of the second conductivity type region from introducing additional electric field peaks on the side of the second low-doped region 134 near the drain region 144, which could lead to premature breakdown. Simultaneously, the first conductivity type region 125 also provides a current path, reducing the impact of this improved structure on the device's on-resistance.
[0049] In one embodiment of this application, the LDMOS device further includes a body lead-out region 146 located in the body region 122. The body lead-out region 146 has a second conductivity type and a doping concentration greater than that of the body region 122. The source region 142 is located between the body lead-out region 146 and the first low-doped region 132.
[0050] In one embodiment of this application, the LDMOS device further includes a substrate 110, at least a portion of which is located below the drift region 112. The substrate 110 has a first conductivity type.
[0051] In one embodiment of this application, the gate 170 is made of polysilicon. In other embodiments, metals, metal nitrides, metal silicides, or similar compounds may also be used as the material of the gate 170.
[0052] Figure 4This is a schematic diagram of the structure of an LDMOS device in another embodiment of this application. It includes a substrate 210, a source region 242, a drain region 244, a body lead-out region 246, a drift region 212, a field oxide layer 260, a gate 270, a first low-doped region 232, a second low-doped region 234, a first conductivity type region 225, a body region 222, a first well region 221, a second well region 223, a third well region 224, and a buffer zone 226. The LDMOS device is an NLDMOS, where the source region 242 and drain region 244 are N+ regions, the drift region 212 is an N-type drift region, the substrate 210, the first conductivity type region 225, the third well region 224, and the buffer zone 226 are N-type regions, the body region 222, the first well region 221, and the second well region 223 are P-type regions, and the body lead-out region 246 is a P+ region.
[0053] At least a portion of drift region 212 is located between source region 242 and drain region 244. Field oxide layer 260 is located on drift region 212. Gate 270 extends from near the edge of source region 242 onto field oxide layer 260. First low-doped region 232 is located directly below the side of field oxide layer 260 near source region 242. Second low-doped region 234 is located directly below the side of gate 270 near drain region 244. The doping concentration of first conductivity type region 225 is greater than the doping concentration of drift region 212. First low-doped region 232 and second low-doped region 234 are low-doped N-type or P-type regions.
[0054] Source region 242 and body lead-out region 246 are located within body region 222. First well region 221 is located below first low-doped region 232, and second well region 223 is located below second low-doped region 234. First well region 221 and second well region 223 are P-wells formed using the same photomask as body region 222 and in the same ion implantation step (hereinafter referred to as P-well implantation). Therefore, the junction depth of first well region 221 and second well region 223 is the same as that of body region 222. Drain region 244 is at least partially located within third well region 224. First conductivity type region 225 is an N-well formed using the same photomask as third well region 224 and in the same ion implantation step (hereinafter referred to as N-well implantation). That is, the region formed by N-well implantation partially overlaps with the region formed by P-well implantation; the overlapping region is the first low-doped region 232 and the second low-doped region 234. Since the two types of implanted conductivity are opposite, the doping concentrations of the first low-doped region 232 and the second low-doped region 234 are low.
[0055] Buffer 226 is located below the third well region 224 and the drain region 244. The doping concentration of buffer 226 is greater than that of drift region 212.
[0056] Figure 4 The illustrated embodiment also shows contact holes and a metal layer above the silicon nitride layer.
[0057] Figure 5 The potential line distribution is shown in the embodiments and comparative examples of this application. Figure 5 (a) is a comparative example, and (b) is an embodiment of this application. Figure 5 As can be seen from the embodiments, by setting a first low-doped region 232 and a second low-doped region 234, the potential line distribution in these two regions, which originally had concentrated electric fields, becomes sparse, thereby reducing the electric field in these two locations. Figure 6 As shown. Figure 6 (a) is a comparative example, and (b) is an embodiment of this application. Figure 7 It can be seen that the collisional ionization rate of the regions where the first low-doped region 232 and the second low-doped region 234 are located decreases, which alleviates the hot carrier injection effect in these two regions. Figure 7 (a) is a comparative example, and (b) is an embodiment of this application.
[0058] The LDMOS device structure of this application embodiment is applicable not only to SiC LDMOS, but also to LDMOS devices based on other substrate materials, such as silicon-based LDMOS.
[0059] This application provides a method for manufacturing an LDMOS device. Figure 8 This is a flowchart of a method for manufacturing an LDMOS device according to one embodiment of this application, which can be used to manufacture the LDMOS device described in any of the above embodiments, and includes the following steps:
[0060] S810, acquires a wafer with a drift region formed.
[0061] In one embodiment of this application, the wafer includes a substrate 210 and an epitaxial layer on the substrate 210, a portion of the epitaxial layer serving as a drift region 212. In one embodiment of this application, the substrate 210 has a first conductivity type.
[0062] S820 forms first and second conductivity type well regions in the drift region through photolithography and ion implantation, respectively.
[0063] A first conductivity type well region is formed in the epitaxial layer by photolithography of a first conductivity type well region and ion implantation of a first conductivity type. A second conductivity type well region is formed in the epitaxial layer by photolithography of a second conductivity type well region and ion implantation of a second conductivity type. The step of forming the second conductivity type well region can be performed before or after the formation of the first conductivity type well region.
[0064] The region where the second conductivity type well region overlaps with the first side of the first conductivity type well region is designated as the first low-doped region 232, and the region where the second conductivity type well region overlaps with the second side of the first conductivity type well region is designated as the second low-doped region 234. In one embodiment of this application, the first low-doped region 232 and the second low-doped region 234 have a first conductivity type, and the doping concentration is lower than that of the first conductivity type well region. In another embodiment of this application, the first low-doped region 232 and the second low-doped region 234 have a second conductivity type.
[0065] In one embodiment of this application, the step of forming a second conductivity type well region in the epitaxial layer by second conductivity type well region photolithography and second conductivity type ion implantation includes: forming a second conductivity type body region 222 in the epitaxial layer simultaneously with forming the second conductivity type well region by second conductivity type well region photolithography and second conductivity type ion implantation. In one embodiment of this application, the second conductivity type well region includes a first well region 221 located directly below the first low-doped region 232 and a second well region 223 located directly below the second low-doped region 234. In one embodiment of this application, the first well region 221 and the second well region 223 are P-wells formed in the same ion implantation step (hereinafter referred to as P-well implantation) after photolithography using the same photomask as the body region 222. Therefore, the junction depth of the first well region 221 and the second well region 223 is the same as that of the body region 222.
[0066] In one embodiment of this application, the step of forming a first conductivity type well region in the epitaxial layer by photolithography of the first conductivity type well region and ion implantation of the first conductivity type includes: simultaneously forming a third well region 224 of the first conductivity type in the epitaxial layer by photolithography of the first conductivity type well region and ion implantation of the first conductivity type. In one embodiment of this application, the first conductivity type well region includes a first conductivity type region 225 located between the first low-doped region 232 and the second low-doped region 234. In one embodiment of this application, the first conductivity type region 225 is an N-well formed in the same ion implantation step (hereinafter referred to as N-well implantation) after photolithography using the same photomask as the third well region 224. That is, the region formed by N-well implantation partially overlaps with the region formed by P-well implantation, and the overlapping region is the first low-doped region 232 and the second low-doped region 234. Since the conductivity types of the two implantations are opposite, the doping concentrations of the first low-doped region 232 and the second low-doped region 234 are low.
[0067] In one embodiment of this application, the first conductivity type is N-type and the second conductivity type is P-type.
[0068] S830 forms a field oxygen layer in the drift region.
[0069] A field oxide layer 260 is formed on the epitaxial layer. The material of the field oxide layer 260 can be silicon oxide, such as silicon dioxide. A first low-doped region 232 is located directly below the first side of the field oxide layer 260. In one embodiment of this application, the field oxide layer 260 is formed by photolithography and etching after depositing an oxide layer on the epitaxial layer.
[0070] S840 forms a gate on the drift region that extends to the field oxide layer.
[0071] In one embodiment of this application, gate material is deposited on the front side of the wafer, and then the gate 270 is formed by photolithography and etching. The portion of the gate 270 located on the field oxide layer 260 is actually a gate field plate, which is referred to as the gate in this application. The second low-doped region 234 is located directly below the first side of the gate 270.
[0072] In S850, source and drain regions are formed on both sides of the drift region below the field oxygen layer.
[0073] Source region 242 and drain region 244 are formed by photolithography and implantation of ions of the first conductivity type. The first side of the gate is the side away from source region 242, and the first side of the field oxide layer 260 is the side away from drain region 244. The doping concentration of source region 242 and drain region 244 is greater than the doping concentration of drift region 212.
[0074] In one embodiment of this application, the source region 242 is formed in the body region 222. In one embodiment of this application, the drain region 244 is formed in the third well region 224.
[0075] The aforementioned LDMOS device fabrication method involves one N-type ion implantation and one P-type ion implantation, forming a first low-doped region 232 and a second low-doped region 234 at the overlapping location of the two implantations. These two low-doped (or inverted) regions can serve as electron cooling layers. This sparses the potential line distribution in these two regions, which were originally characterized by concentrated electric fields, thereby reducing the electric field and decreasing the collisional ionization rate, thus mitigating the hot carrier injection effect. The portion of the first conductivity type well region located between the first low-doped region 232 and the second low-doped region 234 can provide a current path, reducing the on-resistance of the device.
[0076] In one embodiment of this application, the step of forming a buffer 226 below the third well region 224 by photolithography and implantation of ions of a first conductivity type is also included.
[0077] In one embodiment of this application, the step of forming a body lead-out region 246 in the body region 222 by photolithography and implantation of ions of a second conductivity type is also included.
[0078] In one embodiment of this application, the distance between the side of the second conductivity type well region (P-well) near the source region 242 and the source region 242 is no greater than the distance between the side of the first conductivity type well region (N-well) near the source region 242 and the source region 242, and the distance between the side of the second conductivity type well region near the drain region 244 and the drain region 244 is no greater than the distance between the side of the first conductivity type well region near the drain region 244 and the drain region 244. Specifically, this distance can be adjusted according to the diffusion degree of the first conductivity type well region and the second conductivity type well region in actual application.
[0079] The manufacturing method of the LDMOS device in this application is based on the same inventive concept as the LDMOS device. For details not specifically described in the manufacturing method of the LDMOS device, please refer to the above introduction of the LDMOS device.
[0080] It should be understood that although the steps in the flowchart of this application are shown sequentially as indicated by the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowchart of this application may include multiple steps or multiple stages, which are not necessarily completed at the same time, but may be executed at different times, and the execution order of these steps or stages is not necessarily sequential, but may be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.
[0081] In the description of this specification, references to terms such as "some embodiments," "other embodiments," and "ideal embodiments" indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.
[0082] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0083] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.
Claims
1. An LDMOS device, characterized in that, include: The source region has the first type of conductivity. The drain region has the first conductivity type; The drift region has a first conductivity class, and at least a portion of the drift region is located between the source region and the drain region; An oxygen layer is located on the drift region; The gate extends from a position near the edge of the source region onto the field oxide layer; The first low-doped region is located directly below the side of the field oxygen layer closest to the source region; The second low-doped region is located directly below the side of the gate near the drain region, and the region between the first low-doped region and the second low-doped region has a first conductivity type. Wherein, the first low-doped region and the second low-doped region have a first conductivity type, and the doping concentration is lower than the doping concentration of the region between the first low-doped region and the second low-doped region; or the first low-doped region and the second low-doped region have a second conductivity type, wherein the second conductivity type is the opposite of the first conductivity type.
2. The LDMOS device according to claim 1, characterized in that, It also includes a first conductivity type region located between the first low-doped region and the second low-doped region, wherein the doping concentration of the first conductivity type region is greater than the doping concentration of the drift region.
3. The LDMOS device according to claim 1 or 2, characterized in that, Also includes: The body region has a second conductivity type, and the source region is located in the body region; The first well region, having a second conductivity type, is located below the first lightly doped region; The second well region, having a second conductivity type, is located below the second lightly doped region; The first low-doped region and the second low-doped region have a second conductivity type, and the doping concentration of the first low-doped region and the second low-doped region is less than the doping concentration of the body region, the first well region and the second well region.
4. The LDMOS device according to claim 2, characterized in that, It also includes a third well region, in which the drain region is at least partially located, and the doping concentration of the third well region is greater than that of the drift region.
5. The LDMOS device according to claim 4, characterized in that, It also includes a buffer located below the third well region and the drain region, the buffer having a first conductivity type and a doping concentration greater than that of the drift region.
6. The LDMOS device according to claim 1, characterized in that, The first conductivity type is N-type, the second conductivity type is P-type, and the LDMOS device is an N-channel LDMOS device.
7. The LDMOS device according to claim 1, characterized in that, The LDMOS device is a silicon carbide device.
8. A method for manufacturing an LDMOS device, comprising: Obtain a wafer with a drift region formed thereon, the drift region having a first conductivity type; By photolithography, ion implantation of a first conductivity type, and ion implantation of a second conductivity type, a first conductivity type well region and a second conductivity type well region are formed in the drift region, respectively. The region where the second conductivity type well region and the first conductivity type well region overlap on a first side is a first low-doped region, and the region where the second conductivity type well region and the first conductivity type well region overlap on a second side is a second low-doped region. The second conductivity type is the opposite of the first conductivity type. The first low-doped region and the second low-doped region have the first conductivity type and the doping concentration is lower than that of the first conductivity type well region, or the first low-doped region and the second low-doped region have the second conductivity type. A field oxygen layer is formed on the drift region, and the first low-doped region is located directly below the first side of the field oxygen layer; A gate extending to the field oxide layer is formed on the drift region, and the second low-doped region is located directly below the first side of the gate; A source region and a drain region are formed on both sides of the drift region below the field oxide layer; the first side of the gate is the side away from the source region, and the first side of the field oxide layer is the side away from the drain region.
9. The method for manufacturing an LDMOS device according to claim 8, characterized in that, The step of forming a first conductivity type well region and a second conductivity type well region in the drift region by photolithography, ion implantation of a first conductivity type and ion implantation of a second conductivity type respectively includes: forming a second conductivity type body region in the drift region at the same time as forming the second conductivity type well region by photolithography and ion implantation of a second conductivity type. The step of forming the source region is to form the source region in the body region.
10. The method for manufacturing an LDMOS device according to claim 8, characterized in that, The step of forming a first conductivity type well region and a second conductivity type well region in the drift region by photolithography, ion implantation of a first conductivity type and ion implantation of a second conductivity type respectively includes: forming a third well region of the first conductivity type in the drift region at the same time as forming the first conductivity type well region by photolithography and ion implantation of the first conductivity type.