A semiconductor device, a manufacturing method thereof, and an integrated circuit

Abstract

The semiconductor device provided by the embodiments of the present specification has a first trench penetrating a body region and a drift region, the first trench is filled with an isolation layer covering the sidewall of the first trench and a gate structure filled in the remaining first trench; based on the above structure, the flow direction of electrons in the device can be changed from horizontal to vertical during the operation of the semiconductor device, and in the case that the depletion layer provided in the drift region remains unchanged, the space in the vertical direction of the device can be fully utilized, the wafer area required by the device in the horizontal direction is reduced, the size of the device is reduced, and thus the overall cost of the device is reduced. In addition, compared with the conventional lateral channel LDMOS device, the device has better low on-resistance characteristics and can maintain higher withstand voltage performance. Further, the preparation process of the device can be realized based on the DTI process, which is compatible with the BCD process, and compared with the existing LDMOS preparation process, the gate mask plate can be saved, which is conducive to reducing the preparation cost.

Description

Technical Field

[0001] This specification relates to the field of semiconductor technology, and more specifically, to a semiconductor device and its fabrication method, and an integrated circuit. Background Technology

[0002] Semiconductor devices are the core components of modern electronic technology and are widely used in various fields such as communications, computers, and aerospace in production and daily life. Improvements in the structure and process of semiconductor devices are of great significance to the performance, reliability, and power consumption of the devices.

[0003] With the continuous development of semiconductor technology, the application scenarios of semiconductor devices are becoming increasingly widespread. In scenarios such as automotive electronics, industrial and consumer power supplies, high voltage withstand capability and low on-resistance are required for semiconductor devices. Semiconductor devices such as LDMOS (Laterally Diffused Metal Oxide Semiconductor) have good performance in meeting these requirements. How to further optimize LDMOS devices has become a key research focus. Summary of the Invention

[0004] This specification provides a semiconductor device and its fabrication method, as well as an integrated circuit, to achieve the goal of reducing the wafer area required for the semiconductor device and lowering the cost of the semiconductor device while improving the high voltage withstand capability and low on-resistance characteristics of the device.

[0005] To achieve the above technical objectives, the embodiments of this specification provide the following technical solutions:

[0006] In a first aspect, one embodiment of this specification provides a semiconductor device, comprising:

[0007] Substrate;

[0008] The functional region includes a drift region, a body region, a first electrode region, and a second electrode region; wherein the body region is located on the side of the drift region that is vertically away from the substrate; the first electrode region is located on the side of the body region that is vertically away from the substrate; and the second electrode region is located on the side of the drift region that is vertically away from the substrate.

[0009] A first trench penetrating the body region and the drift region;

[0010] An isolation layer and a gate structure are located in the first trench. The isolation layer is used to isolate the gate structure from the functional region. The gate structure is used to form a vertically extending channel in the body region when a control voltage is received. The channel connects the first electrode region and the drift region.

[0011] Secondly, one embodiment of this specification provides a method for fabricating a semiconductor device, comprising:

[0012] Provide substrate;

[0013] A first trench is formed through the substrate, and an isolation layer and a gate structure are formed in the first trench;

[0014] Using a BCD process, a functional region is formed on a portion of the substrate. The functional region includes a drift region, a body region, a first electrode region, and a second electrode region. The body region is located on the side of the drift region that is vertically away from the substrate. The first electrode region is located on the side of the body region that is vertically away from the substrate. The second electrode region is located on the side of the drift region that is vertically away from the substrate. A first trench penetrates the body region and the drift region.

[0015] Thirdly, one embodiment of this specification also provides an integrated circuit, including the semiconductor device as described in any of the preceding claims.

[0016] As can be seen from the above technical solution, the semiconductor device provided in the embodiments of this specification has a first trench penetrating the body region and the drift region. The first trench is filled with an isolation layer covering the sidewalls of the first trench and a gate structure filling the remaining first trench. Based on the above structure, during the operation of the semiconductor device, when the gate structure receives a control voltage, it can form a channel extending vertically in the body region. The channel connects the first electrode region and the drift region. In this way, the flow direction of electrons in the device can be changed from lateral to vertical. While the depletion layer provided by the drift region remains unchanged, the space in the vertical direction of the device can be fully utilized, reducing the wafer area required in the lateral direction, reducing the size of the device, and thus reducing the overall cost of the device. In addition, experimental comparisons have shown that the semiconductor device provided in the embodiments of this specification has better low on-resistance characteristics and can maintain higher withstand voltage performance compared with traditional lateral channel LDMOS devices.

[0017] Furthermore, the semiconductor device can be fabricated using a DTI (Deep Trench Isolation) process, which is compatible with the BCD process. Compared to the existing LDMOS device fabrication process, it not only eliminates the need to increase the number of masks used, but also saves on the mask templates required for fabricating the gate structure, thus helping to reduce the fabrication cost of the semiconductor device. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments or prior art of this specification, the drawings used in the description of the embodiments or prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this specification. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0019] Figure 1 This is a schematic diagram of the cross-sectional structure of an LDMOS device in related technologies.

[0020] Figure 2 This is a schematic diagram of the conduction state of an LDMOS device in related technologies.

[0021] Figure 3 This is a schematic diagram of the cutoff state of an LDMOS device in related technologies.

[0022] Figure 4 This is a cross-sectional structural diagram of a semiconductor device provided for one embodiment of this specification.

[0023] Figure 5 This is a schematic diagram of a semiconductor device in an on-state, provided as one embodiment of this specification.

[0024] Figure 6 This is a cross-sectional structural schematic diagram of another semiconductor device provided for one embodiment of this specification.

[0025] Figure 7 A schematic diagram comparing the performance of the semiconductor device provided in the embodiments of this specification with that of the LDMOS device in the related art.

[0026] Figure 8 This is a schematic flowchart illustrating a method for fabricating a semiconductor device according to one embodiment of this specification.

[0027] Figure 9 This is a schematic diagram illustrating the formation process of a first trench and a gate structure, provided for one embodiment of this specification.

[0028] Explanation of reference numerals in the attached figures:

[0029] 100 - Semiconductor devices;

[0030] 10-Substrate; 11-Drift region; 12-Isolation layer; 13-Gate structure; 14-First electrode region; 141-Source region; 142-Body electrode region; 15-Second electrode region; 16-Shallow trench isolation; 17-Channel; 18-First insulating layer; 19-Source; 20-Body electrode; 21-Drain; 22-Second insulating layer; 23-Mask layer; 231-First dielectric layer; 232-Second dielectric layer; 233-Photoresist layer; 24-First trench; 131-Polysilicon layer. Detailed Implementation

[0031] Unless otherwise defined, the technical or scientific terms used in the embodiments of this specification shall have the ordinary meaning understood by one of ordinary skill in the art to which this specification pertains. The terms "first," "second," and similar terms used in the embodiments of this specification do not indicate any order, quantity, or importance, but are merely used to avoid confusion of constituent elements.

[0032] Unless the context otherwise requires, throughout this specification, "a plurality of" means "at least two," and "including" is interpreted as open-ended or encompassing, that is, "including, but not limited to." In the description of this specification, terms such as "one embodiment," "some embodiments," "exemplary embodiment," "example," "specific example," or "some examples" are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this specification. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example.

[0033] The technical solutions in the embodiments of this specification will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this specification, and not all embodiments. Based on the embodiments in this specification, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this specification.

[0034] Overview

[0035] refer to Figure 1 , Figure 1 This diagram illustrates a cross-sectional structure of LDMOS in related technologies. Figure 1The diagram illustrates the P-type substrate (P-SUB), P-type body region (P-Body), N-type drift region (N-Drift), heavily doped P-type region (P+), heavily doped N-type region (N+), source, gate, and drain of an LDMOS device. In semiconductor devices like LDMOS, the drift region is the most significant difference from traditional MOS devices. The drift region is a lightly doped, high-resistivity layer used to improve the device's voltage withstand capability, functioning as both high-voltage blocking and current transport. Specifically, when the LDMOS device is off, the drift region, through depletion layer widening, withstands the high drain voltage, which is crucial for the LDMOS's high-voltage withstand capability. When the LDMOS is on, the drift region acts as a lateral channel for electrons to travel from the channel to the drain region, and its high resistance restricts the conduction characteristics. (Reference) Figure 2 When the gate of an LDMOS device receives a gate voltage, an N-type inversion layer (i.e., a channel) is formed on the surface of the P-body under the influence of the gate voltage. Electrons are transported from the source region to the drain region through the channel. Figure 2 In this process, the direction of electron transport is transverse (i.e., parallel to the substrate surface, or horizontal).

[0036] refer to Figure 3 When the gate does not receive a gate voltage, the drain voltage is mainly borne by the drift region, i.e., the depletion layer (in Figure 2 and Figure 3 In the diagram (represented by a light gray area), the widening of the depletion layer is primarily due to the drift region. Since the doping concentration of the drift region is much lower than that of the P-body, the N-type drift region acts as the breakdown voltage layer between the drain and the P-body. The depletion layer mainly extends into the drift region, thereby increasing the device's breakdown voltage. Simultaneously, the parasitic capacitance between the drain and source decreases, which is beneficial for improving the device's frequency characteristics. Furthermore, the drift region acts as a buffer between the drain and source, reducing the short-channel effect of the LDMOS device.

[0037] Furthermore, in LDMOS devices, the precise control of the channel length through the double diffusion process helps to reduce the channel resistance, thereby reducing the on-resistance of the device and giving LDMOS devices the characteristic of low on-resistance.

[0038] To further optimize the high voltage withstand and low on-resistance characteristics of semiconductor devices such as LDMOS, while reducing the size of the semiconductor device and thus reducing the required wafer area and cost, this specification provides a semiconductor device having a first trench penetrating the body region and the drift region. The first trench is filled with an isolation layer covering the sidewalls of the first trench and a gate structure filling the remaining portion of the first trench. Based on this structure, during operation, when the gate structure receives a control voltage, it can form a vertically extending channel in the body region, connecting the first electrode region and the drift region. This changes the electron flow direction in the device from lateral to vertical. While maintaining the same depletion layer in the drift region, the vertical space of the device can be fully utilized, reducing the wafer area required laterally, thus reducing the overall device size and cost. Furthermore, experimental comparisons show that the semiconductor device provided in this specification has better low on-resistance characteristics and maintains higher voltage withstand performance compared to traditional lateral-channel LDMOS devices.

[0039] Furthermore, the semiconductor device can be fabricated using a DTI (Deep Trench Isolation) process, which is compatible with the BCD process. Compared to the existing LDMOS device fabrication process, it not only eliminates the need to increase the number of masks used, but also saves on the mask templates required for fabricating the gate structure, thus helping to reduce the fabrication cost of the semiconductor device.

[0040] Exemplary devices

[0041] like Figure 4 As shown, this specification provides a semiconductor device 100, comprising:

[0042] Substrate 10;

[0043] The functional area includes a drift region 11, a body region, a first electrode region 14, and a second electrode region 15; wherein the body region is located on the side of the drift region 11 that is vertically away from the substrate 10; the first electrode region 14 is located on the side of the body region that is vertically away from the substrate 10; and the second electrode region 15 is located on the side of the drift region 11 that is vertically away from the substrate 10.

[0044] A first trench penetrating the body region and the drift region 11;

[0045] An isolation layer 12 and a gate structure 13 are located in the first trench. The isolation layer 12 is used to isolate the gate structure 13 from the functional region. The gate structure 13 is used to form a vertically extending channel 17 in the body region when a control voltage is received. The channel 17 connects the first electrode region 14 and the drift region 11.

[0046] In the semiconductor device 100, the substrate 10 and the body region can both be of a first conductivity type, and the drift region 11 and the second electrode region 15 can both be of a second conductivity type. In some embodiments, the first electrode region 14 may include a source region 141 and a body electrode region 142, where the source region 141 can be of a second conductivity type, the body electrode region 142 can be of a first conductivity type, and both the source region 141 and the body electrode region 142 are heavily doped regions. The first conductivity type and the second conductivity type are different. In some embodiments, the first conductivity type is P-type and the second conductivity type is N-type; in another embodiment, the first conductivity type is N-type and the second conductivity type is P-type. This specification does not limit this specific case.

[0047] The first trench can be fabricated using a DTI process, directly compatible with existing BCD (Bipolar-CMOS-DMOS) processes. Furthermore, after fabricating the first trench, the materials for fabricating the isolation layer and gate structure 13 can be directly filled into the first trench without a mask. Only CMP (Chemical Mechanical Polishing) and / or etching processes are needed to remove the isolation layer and gate materials located outside the first trench, eliminating the need for processes like those used in fabricating the first trench. Figure 1 In the traditional LDMOS device shown, a mask is used during the gate fabrication process. This reduces the procurement and manufacturing costs of the mask and avoids additional costs such as equipment investment, process debugging, and extended production cycles caused by new processes, thus significantly reducing the manufacturing cost of the device.

[0048] The isolation layer 12 can serve as the gate insulating layer of the gate structure 13. In some embodiments, the isolation layer 12 can be a silicon dioxide layer, and the gate structure 13 can be a polysilicon structure. The isolation layer 12 can be grown on the surface of the first isolation layer using liner oxide growth technology. The thickness of the isolation layer 12 can be relatively small, just enough to meet the gate insulation requirements.

[0049] refer to Figure 5 , Figure 5 A schematic diagram shows the formation of a channel 17 in the body region when the gate structure 13 receives a control voltage. Figure 5In this configuration, the extension direction of channel 17 is substantially parallel to the vertical direction, or in other words, the extension direction of channel 17 is substantially parallel to the extension direction of the first trench. After channel 17 is formed in the device, as... Figure 5 As shown by the dashed lines, electrons flow vertically from the source region 141, pass through the drift region 11 below the body region, and then flow towards the drain region. Thus, the extension direction of the channel 17 changes from the lateral direction (as shown by the dashed lines). Figure 2 As shown, the channel 17 is changed to a vertical orientation. While the path length provided by the channel 17 for current remains unchanged, the vertical channel 17 reduces the lateral area occupied, thereby reducing the lateral area of ​​the device. This feature allows for the fabrication of more semiconductor devices 100 on a wafer of the same size, and more devices can be integrated within the same chip area, increasing chip integration density and facilitating chip miniaturization to meet the stringent size requirements of portable electronic devices. Furthermore, the lateral area of ​​the channel 17 of the semiconductor device 100 provided in this embodiment is relatively smaller than... Figure 1 The LDMOS shown is further reduced, which significantly reduces the on-resistance of the device, while the drift region 11 does not become smaller due to the modification of the gate structure 13, thus ensuring that the device has high withstand voltage characteristics.

[0050] In summary, the semiconductor device 100 provided in the embodiments of this specification has a first trench penetrating the body region and the drift region 11. The first trench is filled with an isolation layer 12 covering the sidewalls of the first trench and a gate structure 13 filling the remaining first trench. Based on the above structure, during the operation of the semiconductor device 100, when the gate structure 13 receives a control voltage, a channel 17 extending vertically can be formed in the body region. The channel 17 connects the first electrode region 14 and the drift region 11. In this way, the flow direction of electrons in the device can be changed from lateral to vertical. While the depletion layer provided by the drift region 11 remains unchanged, the space in the vertical direction of the device can be fully utilized, reducing the wafer area required in the lateral direction, reducing the size of the device, and thus reducing the overall cost of the device. In addition, experimental comparisons have shown that the semiconductor device 100 provided in the embodiments of this specification has better low on-resistance characteristics and can maintain higher breakdown voltage performance compared to the conventional LDMOS device with a lateral channel 17.

[0051] Furthermore, the semiconductor device 100 can be fabricated using a DTI (Deep Trench Isolation) process, which is compatible with BCD technology. Compared to the existing LDMOS device fabrication process, this not only eliminates the need to increase the number of masks used, but also saves on the mask templates required for fabricating the gate structure 13, thus reducing the fabrication cost of the semiconductor device 100. For a detailed description of the feasible fabrication process of the semiconductor device 100 provided in this embodiment and the specific principles for saving the number of mask templates, please refer to the exemplary methods described below.

[0052] Understandable Figure 4 and Figure 5 The illustrated section only provides an exemplary view of a feasible cross-sectional structure of the semiconductor device 100. In some embodiments, the semiconductor device 100 may include more or fewer structures. For example, in some embodiments, to improve device isolation and voltage withstand performance, the substrate 10 may further include a high-voltage well layer. The conductivity type of the high-voltage well layer may be a second conductivity type, and functional regions may be formed in the high-voltage well layer through processes such as selective doping. Correspondingly, the number of each structure in the semiconductor device 100 may also be adjusted according to actual needs and design purposes. This specification does not limit this, and it depends on the specific circumstances. Furthermore, to clearly illustrate the various structures of the functional regions, Figure 4 and Figure 5 The source electrode 19 and drain electrode 21 located on the surface of the functional area are not shown in the figure.

[0053] In one implementation, reference is still made to Figure 5 The channel 17 can contact the sidewall of the isolation layer 12 away from the gate structure 13. In the semiconductor device 100 provided in the embodiments of this specification, the gate structure 13 is changed from a conventional lateral extension structure located on the surface of the first electrode region 14 to a longitudinal extension structure filled in the first trench. This change causes the gate structure 13 to induce a second conductivity type inversion layer (i.e., channel 17) on the surface of the body region adjacent to the isolation layer 12 when it receives a control voltage. The shape and extension direction of the channel 17 are similar to the shape and extension direction of the isolation layer 12. Thus, the channel 17 formed by the gate structure 13 is in the same vertical direction as the extension direction of the isolation layer 12 and the gate structure 13. In this way, while keeping the electron transport path length unchanged, at least part of the electron transport path can be changed from lateral to longitudinal. This reduces the area required for lateral movement of the device and lowers the device cost while ensuring that the depletion layer provided by the drift region 11 remains unchanged and thus ensuring the device's voltage withstand performance.

[0054] In one implementation, reference is still made to Figure 4 and Figure 5The semiconductor device 100 further includes:

[0055] The shallow trench isolation 16 extends through the drift region 11. In a second direction, the first electrode region 14 and the second electrode region 15 are located on both sides of the shallow trench isolation 16, respectively. The second direction is parallel to the surface of the substrate 10.

[0056] In this embodiment, the first electrode region 14 and the second electrode region 15 are defined by shallow trench isolation 16. This physical isolation blocks unnecessary current crosstalk, ensuring electrical isolation between the first electrode region 14 and the second electrode region 15, avoiding unnecessary current crosstalk, and ensuring the stable performance of the semiconductor device 100. Furthermore, in some embodiments, in addition to the shallow trench isolation 16 used to define the first electrode region 14 and the second electrode region 15, shallow trench isolation 16 may also be included to define other functional regions, and / or to define other devices formed on the same substrate 10 (such as bipolar transistors, complementary metal-oxide-semiconductor transistors, and double-diffused metal-oxide-semiconductor transistors formed on the same substrate 10 using BCD technology). This specification does not limit the number of shallow trench isolation 16; the specific number depends on the actual situation.

[0057] In one embodiment, the first electrode region 14 includes a source region 141 and a body electrode region 142, wherein the doping concentration of the body electrode region 142 is greater than the doping concentration of the body region.

[0058] The source electrode 19 of the semiconductor device 100 is located on the side of the source region 141 away from the substrate 10, and the body electrode 20 of the semiconductor device 100 is located on the side of the body electrode region 142 away from the substrate 10; the body electrode 20 is used to fix the potential of the body region at the fixed voltage when a fixed voltage is received.

[0059] In this embodiment, the body electrode 20 can be used to control the potential of the body region. The body electrode region 142 is electrically connected to the body electrode 20, and the voltage received by the body electrode 20 can be transmitted to the body electrode region 142. The body electrode region 142 can be a heavily doped first conductivity type region. The body electrode region 142 can be formed by locally heavily doping the body region with first conductivity type impurities, and its doping concentration can be much greater than that of the body region. The highly doped body electrode region 142 can form an ohmic contact with the body electrode 20, ensuring that the potential of the body electrode 20 can be quickly and uniformly transmitted to the entire body region, avoiding performance abnormalities caused by potential fluctuations in the body region. Furthermore, the body electrode region 142 can also suppress the conduction of parasitic NPN transistors. In semiconductor structures such as LDMOS, taking P-type as the first conductivity type and N-type as the second conductivity type as an example, a parasitic NPN transistor structure naturally exists: "N+ source region 141 → P-type body region → N-type drift region 11". Here, "→" indicates the direction of electron flow in the parasitic NPN transistor structure when the device is turned on. If the potential of the body region is not fixed, when a high voltage is applied to the drain 21, the base (body region) of the parasitic NPN may be turned on due to current injection, leading to a latch-up effect in the device, and may even cause the device to burn out. The body electrode region 142, which is adjacent to the source region 141, is connected to the potential of the source 19 or the ground potential through the body electrode 20. This can force the potential of the body region to be fixed at a low potential level (i.e., a fixed point), so that the base-emitter of the parasitic NPN is in a reverse bias state, thereby suppressing the conduction of the parasitic transistor and ensuring the reliability of the device.

[0060] refer to Figure 6 In one embodiment, to simplify the device structure, the source electrode 19 and the body electrode 20 are the same electrode, and the fixed voltage is the source electrode 19 voltage.

[0061] exist Figure 6 In this process, the source electrode 19 and the body electrode 20 can be the same electrode. This electrode is used to receive the voltage of the source electrode 19 and is connected to the source electrode region 141 and the body electrode region 142 respectively, so as to provide the voltage of the source electrode 19 to the source electrode region 141 and the body electrode region 142.

[0062] In this embodiment, the source electrode 19 and the body electrode 20 are the same electrode, which simplifies the device structure and fabrication process while still giving full play to the function of the body electrode 20.

[0063] In some implementations, reference is still made to Figure 6 To reduce the risk of short circuits caused by contact between electrodes, the semiconductor device 100 further includes: a first insulating layer 18 covering the first electrode region 14 and a second insulating layer 22 covering the second electrode region 15.

[0064] The source electrode 19 is located on the side of the first insulating layer 18 away from the substrate 10, and the body electrode 20 is located on the side of the first insulating layer 18 away from the substrate 10. The source electrode 19 is electrically connected to the source electrode region 141 through a via penetrating the first insulating layer 18, and the body electrode 20 is electrically connected to the body electrode region 142 through another via penetrating the first insulating layer 18.

[0065] The drain 21 is located on the side of the second insulating layer 22 away from the substrate 10, and the drain 21 is electrically connected to the drain region through a via penetrating the second insulating layer 22.

[0066] In this embodiment, the presence of the first insulating layer 18 and the second insulating layer 22 reduces the risk of short circuits caused by accidental contact between electrodes (e.g., the source 19 and the gate structure 13), thus ensuring the reliability of the device.

[0067] In one embodiment, the surface of the gate structure 13 facing away from the substrate 10 is flush with the surface of the functional region facing away from the substrate 10.

[0068] As mentioned above, in this embodiment, the gate structure 13 is transformed into a longitudinal electrode structure that cooperates with the first trench, which does not require the following... Figure 1 The gate structure 13 in the LDMOS device shown extends laterally along the surface of the functional region. Therefore, the gate structure 13 can completely fill the first trench without protruding from the surface of the functional region. While still being able to perform the function of the gate structure 13, it can prevent the gate structure 13 protruding from the surface of the functional region from accidentally touching other electrodes.

[0069] refer to Figure 7 , Figure 7 This diagram illustrates a performance comparison between the semiconductor device provided in the embodiments of this specification and the LDMOS device in related technologies. Figure 7 In the graph, the horizontal axis represents the off-state breakdown voltage (Off-state BV), measured in volts (V), and the vertical axis represents the specific on-resistance (Ron,sp), measured in milliohms square centimeters (mΩcm). 2 Among them, the off-state blocking voltage refers to the maximum reverse voltage that the drain and source can withstand when the device is in the off state, characterizing the device's withstand voltage characteristics; the specific on-resistance refers to the on-resistance per unit area when the device is in the on state. From Figure 7 As can be seen, the semiconductor device provided in the embodiments of this specification (in) Figure 7(This solution, as indicated in the text, has a lower specific on-resistance compared to LDMOS in related technologies, and can meet higher withstand voltage requirements.)

[0070] In summary, this specification provides a semiconductor device 100 having a first trench penetrating a body region and a drift region 11. The first trench is filled with an isolation layer 12 covering the sidewalls of the first trench and a gate structure 13 filling the remaining portion of the first trench. Based on this structure, during operation of the semiconductor device 100, when the gate structure 13 receives a control voltage, a vertically extending channel 17 can be formed in the body region. This channel 17 connects the first electrode region 14 and the drift region 11. This allows the electron flow direction in the device to change from lateral to vertical. While maintaining the same depletion layer in the drift region 11, the vertical space of the device can be fully utilized, reducing the wafer area required laterally, decreasing the device size, and thus reducing the overall cost. Furthermore, experimental comparisons show that the semiconductor device 100 provided in this specification has better low on-resistance characteristics and maintains higher breakdown voltage performance compared to conventional LDMOS devices with lateral channel 17.

[0071] Furthermore, the semiconductor device 100 can be fabricated using a DTI (Deep Trench Isolation) process, which is compatible with the BCD process. Compared with the existing LDMOS device fabrication process, it not only eliminates the need to increase the number of masks used, but also saves the mask templates required when fabricating the gate structure 13, thus reducing the fabrication cost of the semiconductor device 100.

[0072] Accordingly, embodiments of this specification also provide an integrated circuit, including the semiconductor device 100 as described in any of the above embodiments.

[0073] The integrated circuits mentioned include, but are not limited to, Field-Programmable Gate Arrays (FPGAs), Application Specific Integrated Circuits (ASICs), Digital Signal Processors (DSPs), Graphics Processing Units (GPUs), Data Processing Units (DPUs), Central Processing Units (CPUs), Random Access Memory (RAMs), Read-Only Memory (ROMs), and Microcontroller Units (MCUs), etc., but this specification does not limit them.

[0074] In the semiconductor device 100 of this integrated circuit, a first trench is provided that penetrates the body region and the drift region 11. The first trench is filled with an isolation layer 12 covering the sidewalls of the first trench and a gate structure 13 filling the remaining first trench. Based on the above structure, during the operation of the semiconductor device 100, when the gate structure 13 receives a control voltage, a vertically extending channel 17 can be formed in the body region. The channel 17 connects the first electrode region 14 and the drift region 11. In this way, the flow of electrons in the device can be changed from lateral to vertical. While the depletion layer provided by the drift region 11 remains unchanged, the vertical space of the device can be fully utilized, reducing the wafer area required in the lateral direction, reducing the size of the device, and thus reducing the overall cost of the device. In addition, experimental comparisons have shown that the semiconductor device 100 provided in this embodiment has better low on-resistance characteristics and can maintain higher voltage withstand performance compared to the conventional LDMOS device with a lateral channel 17.

[0075] Furthermore, the semiconductor device 100 can be fabricated using a DTI (Deep Trench Isolation) process, which is compatible with the BCD process. Compared with the existing LDMOS device fabrication process, it not only eliminates the need to increase the number of masks used, but also saves the mask templates required when fabricating the gate structure 13, thus reducing the fabrication cost of the semiconductor device 100.

[0076] Exemplary methods

[0077] Accordingly, this specification also provides a method for fabricating a semiconductor device 100, such as... Figure 8 As shown, it includes:

[0078] S701: Provides substrate 10;

[0079] S702: A first trench 24 is formed through the substrate 10, and an isolation layer 12 and a gate structure 13 are formed in the first trench 24;

[0080] S703: Using BCD process, a functional region is formed on a portion of the substrate 10. The functional region includes a drift region 11, a body region, a first electrode region 14, and a second electrode region 15. The body region is located on the side of the drift region 11 that is vertically away from the substrate 10. The first electrode region 14 is located on the side of the body region that is vertically away from the substrate 10. The second electrode region 15 is located on the side of the drift region 11 that is vertically away from the substrate 10. The first trench 24 penetrates the body region and the drift region 11.

[0081] The semiconductor device formed by the above method can be referenced. Figures 4-6 In this semiconductor device 100, a first trench is formed that penetrates the body region and the drift region 11. The first trench is filled with an isolation layer 12 covering the sidewalls of the first trench and a gate structure 13 filling the remaining first trench. Based on the above structure, during the operation of the semiconductor device 100, when the gate structure 13 receives a control voltage, a vertically extending channel 17 can be formed in the body region. The channel 17 connects the first electrode region 14 and the drift region 11. In this way, the flow of electrons in the device can be changed from lateral to vertical. While the depletion layer provided by the drift region 11 remains unchanged, the vertical space of the device can be fully utilized, reducing the wafer area required in the lateral direction, reducing the size of the device, and thus reducing the overall cost of the device. Furthermore, experimental comparisons have shown that the semiconductor device 100 provided in this embodiment has better low on-resistance characteristics and can maintain higher breakdown voltage performance compared to conventional LDMOS devices with lateral channel 17.

[0082] Furthermore, the semiconductor device 100 can be fabricated using a DTI (Deep Trench Isolation) process, which is compatible with BCD technology. Compared to the existing LDMOS device fabrication process, this not only eliminates the need to increase the number of masks used, but also saves on the mask templates required for fabricating the gate structure 13, thus reducing the fabrication cost of the semiconductor device 100. For a detailed description of the feasible fabrication process of the semiconductor device 100 provided in this embodiment and the specific principles for saving the number of mask templates, please refer to the exemplary methods described below.

[0083] Specifically, refer to Figure 9 , Figure 9A feasible fabrication process for the first trench 24, the isolation layer, and the gate structure 13, specifically, the formation of the first trench 24 penetrating the substrate 10 includes:

[0084] A mask layer 23 is formed on the surface of the substrate 10. The mask layer 23 includes a first dielectric layer 231, a second dielectric layer 232, and a photoresist layer 233, which are sequentially stacked from the surface of the substrate 10. The photoresist layer 233 includes a target opening that exposes a portion of the second dielectric layer 232. The first dielectric layer 231 and the second dielectric layer 232 are different semiconductor material layers.

[0085] Using the second dielectric layer 232 and the photoresist layer 233 as a mask, etching is performed to form a first trench 24 penetrating the first dielectric layer 231 and a portion of the substrate 10 at the target opening location.

[0086] In some embodiments, the first dielectric layer 231 and the second dielectric layer 232 can be a silicon dioxide layer and a silicon oxynitride layer, respectively. A DTI process can be used when etching to form the first trench 24. After etching, a portion of the first dielectric layer 231 is retained. In this embodiment, the first dielectric layer 231 and the second dielectric layer 232 are used as hard masks during the etching process, and the photoresist layer 233 is used as a soft mask. The core purpose is to precisely control the "depth, sidewall perpendicularity, and dimensional accuracy" of the deep trench, while protecting the substrate 10 surface from over-etching, thus meeting the "deep, steep, and precise" process requirements of DTI.

[0087] Optionally, forming the isolation layer 12 and the gate structure 13 in the first trench 24 includes:

[0088] Using the remaining first dielectric layer 231 as a mask, the isolation layer 12 is formed in the first trench 24. The isolation layer 12 and the first dielectric layer 231 are film layers made of the same material. This step can be performed using a liner oxide growth process. When growing the isolation layer 12, a thin and uniform oxide layer can be formed on the sidewalls and bottom of the trench by thermal oxidation or chemical vapor deposition.

[0089] A polysilicon layer 131 is deposited on the surface of the isolation layer 12 and the first dielectric layer 231. The polysilicon layer 131 fills the first trench 24 and covers at least part of the surface of the first dielectric layer 231. Before this step is performed, since the first trench 24 has already been formed, the polysilicon layer 131 can be deposited directly without additional gate pattern masks, which helps to reduce the number of masks required in the process.

[0090] The first dielectric layer 231 and the polysilicon layer 131 located outside the first trench 24 are removed to form a gate structure 13 filling the first trench 24. In this step, CMP and etching processes can be used to remove the polysilicon layer 131 outside the first trench 24, thereby retaining only the polysilicon layer 131 in the first trench 24 as the gate structure 13. This achieves the goal of eliminating the need for a gate pattern mask when fabricating the gate structure 13, which simplifies the process and reduces fabrication costs. After the gate structure 13 is formed, other device structures such as functional regions can be formed in the substrate 10 using BCD processes, which will not be elaborated here.

[0091] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0092] The embodiments described above are merely illustrative of several implementation methods outlined in this specification. While the descriptions are specific and detailed, they should not be construed as limiting the scope of the solutions provided in this specification. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this specification, and these all fall within the scope of protection of this specification. Therefore, the scope of protection for this patent should be determined by the appended claims.

Claims

1. A semiconductor device, characterized in that, include: Substrate; The functional region includes a drift region, a body region, a first electrode region, and a second electrode region; wherein the body region is located on the side of the drift region that is vertically away from the substrate; the first electrode region is located on the side of the body region that is vertically away from the substrate; and the second electrode region is located on the side of the drift region that is vertically away from the substrate. A first trench extends through the body region and the drift region; both sidewalls of the first trench are in direct contact with the body region, the first electrode region, and the drift region; the body region, the first electrode region, and the drift region are symmetrically distributed along the first trench; An isolation layer and a gate structure are located in the first trench. The isolation layer is used to isolate the gate structure from the functional region. The gate structure is used to form a vertically extending channel in the body region when a control voltage is received. The channel connects the first electrode region and the drift region. A shallow trench isolation penetrating the drift region, wherein in a second direction, the first electrode region and the second electrode region are respectively located on both sides of the shallow trench isolation; the second direction is parallel to the surface of the substrate; there are multiple shallow trench isolations, which are distributed on both sides of the first trench, and the shallow trench isolations are isolated from the first trench.

2. The semiconductor device according to claim 1, characterized in that, The channel contacts the sidewall of the isolation layer on the side away from the gate structure.

3. The semiconductor device according to claim 1, characterized in that, The first electrode region includes a source region and a body electrode region, wherein the doping concentration of the body electrode region is greater than the doping concentration of the body region; The source electrode of the semiconductor device is located on the side of the source region away from the substrate, and the body electrode of the semiconductor device is located on the side of the body electrode region away from the substrate; the body electrode is used to fix the potential of the body region at a fixed voltage when a fixed voltage is received.

4. The semiconductor device according to claim 3, characterized in that, The source electrode and the body electrode are the same electrode, and the fixed voltage is the source electrode voltage.

5. The semiconductor device according to any one of claims 1 to 4, characterized in that, The surface of the gate structure facing away from the substrate is flush with the surface of the functional region facing away from the substrate.

6. A method for fabricating a semiconductor device, characterized in that, include: Provide substrate; A first trench is formed through the substrate, and an isolation layer and a gate structure are formed in the first trench; Using a BCD process, functional regions are formed on a portion of the substrate. These functional regions include a drift region, a body region, a first electrode region, and a second electrode region. The body region is located on the side of the drift region that is vertically away from the substrate. The first electrode region is located on the side of the body region that is vertically away from the substrate. The second electrode region is located on the side of the drift region that is vertically away from the substrate. A first trench penetrates both the body region and the drift region. Both sidewalls of the first trench are in direct contact with the body region, the first electrode region, and the drift region. The body region, the first electrode region, and the drift region are symmetrically distributed along the first trench. A shallow trench isolation is formed that extends through the drift region. In a second direction, the first electrode region and the second electrode region are located on both sides of the shallow trench isolation, respectively. The second direction is parallel to the surface of the substrate. There are multiple shallow trench isolations, which are distributed on both sides of the first trench and are isolated from each other.

7. The method according to claim 6, characterized in that, The formation of the first trench penetrating the substrate includes: A mask layer is formed on the surface of the substrate. The mask layer includes a first dielectric layer, a second dielectric layer, and a photoresist layer stacked sequentially from the surface of the substrate. The photoresist layer includes a target opening that exposes a portion of the second dielectric layer. The first dielectric layer and the second dielectric layer are different semiconductor material layers. Using the second dielectric layer and the photoresist layer as a mask, etching is performed to form a first trench penetrating the first dielectric layer and a portion of the substrate at the target opening location.

8. The method according to claim 7, characterized in that, The formation of the isolation layer and gate structure in the first trench includes: Using the remaining first dielectric layer as a mask, the isolation layer is formed in the first trench, wherein the isolation layer and the first dielectric layer are film layers made of the same material; A polysilicon layer is deposited on the surfaces of the isolation layer and the first dielectric layer, the polysilicon layer filling the first trench and covering at least a portion of the surface of the first dielectric layer; The first dielectric layer and the polysilicon layer located outside the first trench are removed to form a gate structure filling the first trench.

9. An integrated circuit, characterized in that, include: The semiconductor device as described in any one of claims 1 to 5.

Images