A local strain silicon LDMOS device and a manufacturing method thereof
By implanting Ge ions into the drift region of the RF LDMOS device to form a local SiGe layer, the on-resistance and mobility issues are resolved, improving device efficiency and high-frequency performance while avoiding reliability problems.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SUZHOU WATECH ELECTRONICS CO LTD
- Filing Date
- 2021-11-05
- Publication Date
- 2026-05-15
AI Technical Summary
Existing RF LDMOS devices have relatively large on-resistance and output capacitance in the lightly doped drain region, which affects the efficiency of power amplification, especially in high-frequency applications. Furthermore, the mobility of traditional Si-based materials is not high, and SiGe epitaxial layers have reliability issues.
Ge ions are injected into the drift region to form a local SiGe layer. The SiGe layer generates stress in the drift region, which improves the carrier mobility. The SiGe layer is placed away from the surface of the drift region to avoid breakdown. The SiGe layer is formed only in the area where strain is required to reduce reliability issues.
It effectively improves the carrier transport capacity and conductivity in the drift region, reduces on-resistance, improves device efficiency and gain, avoids surface electric field breakdown, and optimizes high-frequency performance.
Smart Images
Figure CN116093157B_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of semiconductor devices, specifically relating to a locally strained silicon LDMOS device and its fabrication method. Background Technology
[0002] Strained silicon LDMOS power amplifier transistors possess excellent properties such as high breakdown voltage, high gain, high output power, efficiency, and reliability, making them suitable for applications such as base stations, mobile communication terminals, aerospace, radio frequency heating, medical devices, industrial (laser) and lighting fields. They are key components of RF power amplifiers (PAs).
[0003] RF LDMOS devices require a long, lightly doped drain region (drift region) to withstand voltage and improve operating voltage. However, the lightly doped drain region increases the device's on-resistance (Ron) and output capacitance (Cds), reducing the power amplification efficiency, which has a particularly significant impact on high-frequency applications.
[0004] Traditional RF LDMOS typically uses silicon-based materials to fabricate the substrate and epitaxial layer. However, Si itself has low mobility, and various scattering processes during electron and hole transport limit the improvement of device performance. Some technologies use SiGe epitaxial layers to fabricate devices to achieve higher mobility. However, since the on-resistance of the device is mainly limited in the drift region, the SiGe epitaxial layer approach is not direct or flexible enough and may also introduce other reliability issues due to strain. Summary of the Invention
[0005] The main objective of this invention is to provide a locally strained silicon LDMOS device and its fabrication method, thereby solving the problems existing in the prior art.
[0006] To achieve the aforementioned objectives, the technical solution adopted by this invention includes:
[0007] This invention provides a locally strained silicon LDMOS device, which includes a body region of a first conductivity type and a drift region of a second conductivity type. A source region of the second conductivity type is formed in the body region, and a drain region of the second conductivity type is formed in the drift region. A strain region distributed along the source-drain direction is also formed inside the drift region, which can at least generate stress on the drift region and improve the carrier mobility of the drift region. The strain region is disposed away from the surface of the drift region.
[0008] This invention also provides a method for fabricating the aforementioned locally strained silicon LDMOS device, comprising:
[0009] An epitaxial layer is formed on the substrate.
[0010] A gate dielectric and a polysilicon gate are formed on the epitaxial layer.
[0011] Within the epitaxial layer, a volume region, a volume region contact region, a drift region, a drain region, and a source region are formed; and
[0012] A strain region is formed in the drift region by ion implantation.
[0013] In one embodiment, Ge ions are implanted within the drift region to form the strain region.
[0014] Preferably, the implantation concentration of Ge ions is 1e. 14 -1e 17 atoms / cm 2 .
[0015] In one embodiment, the Ge ions can be implanted in multiple stages.
[0016] Compared with the prior art, the beneficial technical effects of the present invention are at least as follows:
[0017] 1) The present invention provides a locally strained silicon LDMOS device, in which Ge ions are injected into the drift region to form a SiGe layer. The SiGe layer generates stress on the silicon in the drift region, which increases the spacing between the silicon lattice, reduces lattice scattering, and effectively increases the carrier transport capacity of the drift region.
[0018] 2) The present invention provides a locally strained silicon LDMOS device, which improves the conductivity of the drift region through the high conductivity of the SiGe layer, thereby reducing the on-resistance of the drift region and increasing the efficiency and output gain of the device.
[0019] 3) The present invention provides a locally strained silicon LDMOS device in which the SiGe layer is disposed on the surface away from the drift region, which can avoid being broken down by the surface electric field of the device.
[0020] 4) The present invention provides a locally strained silicon LDMOS device, which forms a SiGe layer only in the area where strain is required by implanting Ge ions, thereby reducing other reliability problems caused by strain. Attached Figure Description
[0021] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0022] Figure 1This is a schematic diagram of the structure of a locally strained silicon LDMOS device according to an embodiment of the present invention;
[0023] Figures 2a to 2f This is a flowchart illustrating a method for fabricating a locally strained silicon LDMOS device according to an embodiment of the present invention. Detailed Implementation
[0024] In view of the shortcomings of the prior art, the inventors of this invention, through long-term research and extensive practice, have proposed the technical solution of this invention. Addressing the problems of low mobility of the silicon substrate itself and the impact on device performance caused by various scattering processes during electron and hole transport in traditional silicon-based radio frequency LDMOS device structures, this invention provides a locally strained silicon LDMOS device and its fabrication method. A SiGe layer is formed in the drift region of the device through implantation. On the one hand, the higher mobility of the SiGe layer enhances the carrier migration rate, thereby improving device performance; on the other hand, the SiGe layer causes lattice deformation of the silicon material, reducing lattice scattering and further improving carrier mobility. The technical solution of this invention will be clearly and completely described below.
[0025] This invention provides a locally strained silicon LDMOS device, which includes a body region of a first conductivity type and a drift region of a second conductivity type. A source region of the second conductivity type is formed in the body region, and a drain region of the second conductivity type is formed in the drift region. A strain region distributed along the source-drain direction is also formed inside the drift region, which can at least generate stress on the drift region and improve the carrier mobility of the drift region.
[0026] Furthermore, the strain zone is disposed on a surface away from the drift zone.
[0027] In some embodiments, the strain region includes a SiGe layer that overlaps with the leak region portion in the thickness direction of the drift region.
[0028] In a preferred embodiment, the distance between the SiGe layer and the upper surface of the drift region is greater than 100 nm to prevent breakdown by the surface electric field of the device, and the thickness of the SiGe layer is 50 nm to 2000 nm, with a Ge ion concentration of 1 e⁻¹. 14 -1e 17 atoms / cm 2 .
[0029] This locally strained silicon LDMOS device generates stress on the silicon in the drift region through the SiGe layer, which increases the spacing between the silicon lattice and reduces lattice scattering. This effectively increases the carrier transport capacity of the drift region. At the same time, the high conductivity of the SiGe layer can improve the conductivity of the drift region, thereby reducing the on-resistance of the drift region and improving the efficiency and output gain of the device.
[0030] In some cases, the SiGe layer in the drift region can be patterned.
[0031] Furthermore, the body region and the drift region are formed in an epitaxial layer of a first conductivity type, and the epitaxial layer is formed on a substrate of the first conductivity type.
[0032] The substrate and epitaxial layer can be a silicon substrate and a silicon epitaxial layer.
[0033] Furthermore, a gate dielectric and a polysilicon gate are formed on the surface of the epitaxial layer between the body region and the drift region. The second side of the polysilicon gate is self-aligned with the first side of the SiGe layer, and the first side of the polysilicon gate is self-aligned with the second side of the source region. The second side of the SiGe layer extends to the drain region so that the carriers in the device channel can be transported to the drain at a high rate in the first time.
[0034] Furthermore, a body region contact region of a first conductivity type is formed in the body region, and the body region contact region is in contact with the first side surface of the source region.
[0035] Furthermore, the contact area between the source region and the body region is electrically connected to the back metal of the substrate through conductive vias.
[0036] Furthermore, an oxide layer is formed on top of the epitaxial layer.
[0037] Furthermore, if either the first conductivity type or the second conductivity type is P-type and the other is N-type, the corresponding LDMOS device is PLDMOS or NLDMOS. In addition, depending on whether a channel region is formed in advance in the epitaxial layer, the LDMOS device is further divided into enhancement-type or depletion-type.
[0038] The locally strained silicon LDMOS device provided in this embodiment of the invention has a SiGe layer formed in the drift region. On the one hand, SiGe has a higher conductivity than Si, which can improve the conductivity of the drift region; on the other hand, SiGe can stretch the Si in the drift region to form strained silicon, increasing the spacing between the silicon lattice, reducing lattice scattering, and effectively increasing the carrier transport capacity of the drift region. This reduces the losses caused by the on-resistance of the drift region and improves the device's operating efficiency. Simultaneously, the high mobility can increase the gain, thereby raising the device's cutoff frequency and enhancing its high-frequency performance.
[0039] Furthermore, since SiGe has a lower breakdown voltage than Si, the SiGe layer in this embodiment of the invention is disposed on a surface far from the drift region, which can prevent the SiGe layer from being broken down prematurely.
[0040] This invention also provides a method for fabricating the aforementioned locally strained silicon LDMOS device, comprising:
[0041] An epitaxial layer is formed on the substrate.
[0042] A gate dielectric and a polysilicon gate are sequentially formed on the epitaxial layer.
[0043] A volume region, a volume region contact region, a drift region, a drain region, and a source region are formed within the epitaxial layer;
[0044] And a strain zone is formed in the drift region by ion implantation.
[0045] Furthermore, the manufacturing method also includes:
[0046] Conductive vias are formed within the epitaxial layer to electrically connect the contact area between the source region and the body region to the back metal of the substrate.
[0047] An oxide layer is formed on the epitaxial layer, and the polysilicon gate is embedded in the oxide layer;
[0048] And Ge ions are injected into the drift region to form the strain region.
[0049] In some preferred embodiments, the implantation concentration of Ge ions is 1e. 14 -1e 17 atoms / cm 2 Furthermore, the Ge ions are implanted in multiple stages.
[0050] Compared to traditional epitaxial SiGe layers for achieving higher mobility, the method in this invention is more direct and flexible. By implanting SiGe layers, patterned optimization can be achieved. Since the on-resistance of LDMOS devices is mainly limited to the drift region, it is unnecessary to create SiGe layers in the entire region. By implanting Ge ions only in the drift region to form SiGe layers, the conductivity of the drift region can be improved, optimizing device performance, while avoiding the impact of strain on other regions and preventing other reliability issues.
[0051] The technical solutions in the embodiments of the present invention will be explained in further detail below with reference to the accompanying drawings.
[0052] Please see Figure 1 A strained silicon-enhanced NLDMOS device includes a P-type heavily doped high-resistivity silicon substrate 10 and a P-type silicon epitaxial layer 20. A P-type body region 22 and an N-type shallowly doped drift region 21 are formed in the epitaxial layer 20. An N-type heavily doped source region 25 and a P-type heavily doped body region contact region 24 are formed in the body region 22. An N-type heavily doped drain region 23 and a SiGe layer 11 are formed in the drift region 21. The SiGe layer 11 is located away from the upper surface of the drift region 21 and is disposed along the length direction of the drift region, and overlaps longitudinally with the drain region 23.
[0053] Specifically, the distance between the SiGe layer 11 and the upper surface of the drift region 21 is more than 100 nm. This distance can prevent the SiGe layer 11 from being broken down by the surface electric field of the device. The thickness of the SiGe layer 11 is 50 nm to 2000 nm, and the Ge ion concentration is 1 e. 14 -1e 17 atoms / cm 2 .
[0054] Specifically, a gate dielectric 32 and a polysilicon gate 30 are formed on the surface of the silicon epitaxial layer 20 located between the source region 25 and the drain region 23. The first side of the polysilicon gate 30 is self-aligned with the second side of the source region 25, the second side of the polysilicon gate 30 is self-aligned with the first side of the SiGe layer, and the second surface of the SiGe layer extends to the drain region 23.
[0055] Specifically, the body region contact region 24 is in contact with the first side of the source region 25, and is electrically connected to the back metal of the high-resistivity silicon substrate 10 through the conductive via 31.
[0056] Specifically, an oxide layer 33 is formed above the entire silicon epitaxial layer 20.
[0057] Please see Figures 2a-2f A method for fabricating a strained silicon-enhanced NLDMOS device, comprising:
[0058] Step 1: Provide a P-type heavily doped high-resistivity silicon substrate 10, and form a P-type silicon epitaxial layer 20 on the high-resistivity silicon substrate 10;
[0059] Step 2: Form a gate dielectric 32 and a polysilicon gate 30 in a selected area on the upper surface of the silicon epitaxial layer 20;
[0060] Step 3: Implant N-type shallow doped drift regions 21 in selected areas of the silicon epitaxial layer 20;
[0061] Step 4: Inject Ge ions into the drift region 21 to form a SiGe layer 11;
[0062] Step 5: Implant N-type heavily doped drain region 23 in a selected area of drift region 21;
[0063] Step 6: Implant a selected region in the silicon epitaxial layer 20 to form a P-type body region 22, and implant an N-type heavily doped source region 25 and a P-type heavily doped body region contact region 24 in a selected region of the body region 22.
[0064] Step 7: Form conductive vias 31 in the silicon epitaxial layer 20 to electrically connect the source region 25 and the body region contact region 24 to the back metal of the high-resistivity silicon substrate 10.
[0065] Step 8: Form an oxide layer 33 over the entire epitaxial layer 20, and embed the polysilicon gate 30 within the oxide layer 33, thus completing the process. Figure 1 Fabrication of the device structure shown.
[0066] The implantation concentration of Ge ions is 1e. 14 -1e 17 atoms / cm 2 Furthermore, the Ge ions are implanted in multiple stages.
[0067] It should be noted that the order in which the structures are injected in steps three through five above can be interchanged.
[0068] In the description of this invention, it should be noted that the terms "middle", "upper", "lower", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.
[0069] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "connected" and "linked" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can also refer to the internal connection of two components; and they can refer to a wireless connection or a wired connection. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.
[0070] It should be understood that the technical solutions of the present invention are not limited to the specific embodiments described above. Any technical modifications made to the technical solutions of the present invention without departing from the spirit and scope of the claims are within the scope of protection of the present invention.
Claims
1. A locally strained silicon LDMOS device, comprising a body region of a first conductivity type and a drift region of a second conductivity type, wherein a source region of the second conductivity type is formed in the body region, and a drain region of the second conductivity type is formed in the drift region, characterized in that, The drift region also contains a strain region distributed along the source-drain direction, which can at least generate stress on the drift region and improve the carrier mobility of the drift region; the strain region includes a SiGe layer; The SiGe layer is formed in the drift region by ion implantation of Ge, and the strain region is disposed on the surface away from the drift region; The body region and the drift region are formed in an epitaxial layer of a first conductivity type. A gate dielectric and a polysilicon gate are sequentially formed on the surface of the epitaxial layer between the body region and the drift region. The second side of the polysilicon gate is self-aligned with the first side of the SiGe layer. The first side of the polysilicon gate is self-aligned with the second side of the source region. The second side of the SiGe layer extends to the drain region.
2. The locally strained silicon LDMOS device according to claim 1, characterized in that, The SiGe layer overlaps with the drain region in the thickness direction of the drift region; and / or, the distance between the SiGe layer and the surface of the drift region is greater than 100 nm; and / or, the thickness of the SiGe layer is 50 nm to 2000 nm; and / or, the Ge ion concentration in the SiGe layer is 1 e 14 -1e 17 atoms / cm 2 .
3. The locally strained silicon LDMOS device according to claim 2, characterized in that, The epitaxial layer is formed on a substrate of a first conductivity type.
4. The locally strained silicon LDMOS device according to claim 3, characterized in that, The body region also has a body region contact region of a first conductivity type, which is in contact with the first side surface of the source region.
5. The locally strained silicon LDMOS device according to claim 4, characterized in that, The contact area between the source region and the body region is electrically connected to the back metal of the substrate through conductive vias.
6. The locally strained silicon LDMOS device according to claim 3, characterized in that, An oxide layer is also formed above the epitaxial layer; and / or, the substrate and the epitaxial layer are a silicon substrate and a silicon epitaxial layer, respectively.
7. The locally strained silicon LDMOS device according to claim 3, characterized in that, Either the first conductivity type or the second conductivity type is P-type, and the other is N-type.
8. A method for fabricating a locally strained silicon LDMOS device as described in any one of claims 1-7, comprising: An epitaxial layer is formed on the substrate. A gate dielectric and a polysilicon gate are sequentially formed on the epitaxial layer. A volume region, a volume region contact region, a drift region, a drain region, and a source region are formed within the epitaxial layer; The manufacturing method is characterized by further comprising: A strain region is formed within the drift region by ion implantation; the strain region is disposed on a surface away from the drift region; the strain region includes a SiGe layer; The second side of the polysilicon gate is self-aligned with the first side of the SiGe layer, the first side of the polysilicon gate is self-aligned with the second side of the source region, and the second side of the SiGe layer extends to the drain region.
9. The manufacturing method according to claim 8, characterized in that... Also includes: Conductive vias are formed within the epitaxial layer to electrically connect the contact area between the source region and the body region to the back metal of the substrate. And / or, an oxide layer is provided on the epitaxial layer, and the polysilicon gate is embedded in the oxide layer; And / or, Ge ions are implanted within the drift region to form the strain region, wherein the implanted Ge ion concentration is 1e. 14 -1e 17 atoms / cm 2 The Ge ions are injected in multiple stages.