A power semiconductor device and a method of manufacturing the same

Abstract

This invention provides a power semiconductor device and its fabrication method, relating to the field of semiconductor technology. In this application, the power semiconductor device integrates a main power VDMOS cell array, sampling power VDMOS cells, and at least one discharge path control LDMOS cell on a SiC epitaxial layer. When the power semiconductor device is in operation, the sampling power VDMOS cell is used to acquire the real-time electrical signal of the JFET region; each discharge path control LDMOS cell is used to receive the real-time electrical signal, and when the real-time electrical signal exceeds a preset short-circuit threshold, it conducts a low-resistance discharge path to discharge the charge at the gate of the main power VDMOS cell array to the source of the main power VDMOS cell array. Based on this, this application improves its short-circuit withstand time by integrating a short-circuit protection structure, thereby enhancing the short-circuit reliability of the device.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more specifically, to a power semiconductor device and its fabrication method. Background Technology

[0002] With the rapid development of wide bandgap semiconductor technology, silicon carbide metal-oxide semiconductor field-effect transistors (SiC MOSFETs) have become key switching devices in medium- and high-voltage power electronic systems such as new energy power generation, electric vehicle drives, industrial frequency converters, and aerospace due to their advantages such as high breakdown electric field strength, high limiting operating temperature, high switching speed, low switching loss, and ease of driving. In system-level design, to improve power density and overall efficiency, the industry generally replaces traditional silicon-based insulated-gate bipolar transistors (IGBTs) with SiC MOSFETs of the same package size. However, although SiC MOSFETs of the same package size are only 25% the size of IGBTs, their chip thermal resistance is relatively high. At the same time, a parasitic JFET (Junction Field-Effect Transistor) region exists in its body region at a depth of 1–2 μm from the surface. Under short-circuit conditions, the short-circuit current is mainly concentrated in this narrow JFET channel, leading to a rapid accumulation of local Joule heat and a sudden rise in surface temperature, which can easily cause chip melting or permanent failure.

[0003] Currently, mainstream SiC MOSFET short-circuit protection solutions rely on external drive circuits to monitor the drain-source voltage (V) in real time. DS ) changes, for example, when V DS When the voltage rises abnormally and exceeds a preset threshold while in the ON state, it is determined to be a short circuit and triggers shutdown. However, the short-circuit withstand time of SiC MOSFETs is extremely short, typically only 0.5–1.5 μs, far lower than the 10 μs level of silicon-based IGBTs. External detection circuits are limited by signal transmission delay, comparator response time, and high-frequency switching noise interference, and must introduce a blanking time of hundreds of nanoseconds to microseconds to avoid false triggering. After this blanking time is superimposed on the logic judgment and drive signal transmission delay, the actual protection action lags behind the short circuit initiation moment. As a result, by the time the protection shutdown command is sent to the device gate, the JFET region of the chip has often already suffered irreversible thermal damage, leading to a serious lack of effectiveness of external circuits in protecting SiC MOSFETs from short circuits.

[0004] Therefore, there is an urgent need for a new SiC MOSFET solution to improve the reliability of the device during short circuits. Summary of the Invention

[0005] In view of this, the purpose of the present invention is to provide a power semiconductor device and a method for fabricating the same, which improves the short-circuit withstand time by integrating a short-circuit protection structure, thereby improving the short-circuit reliability of the device.

[0006] To achieve the above objectives, the technical solutions adopted in the embodiments of the present invention are as follows:

[0007] In a first aspect, the present invention provides a power semiconductor device, the power semiconductor device comprising a substrate, a SiC epitaxial layer and a top metal layer, and the power semiconductor device further comprising a main power VDMOS cell array, a sampling power VDMOS cell, and at least one discharge path control LDMOS cell integrated on the SiC epitaxial layer; wherein, the sampling power VDMOS cell and each main cell under the main power VDMOS cell array adopt the same P-type base region arrangement structure.

[0008] The sampling power VDMOS cell contacts the JFET region within the main power VDMOS cell array through a first type of contact hole; the sampling power VDMOS cell contacts the sampling signal metal in the top metal layer through a second type of contact hole.

[0009] The discharge path control LDMOS cell includes a first gate and a second gate; the first gate is in contact with the sampling signal metal through a second type of contact hole; the second gate is in contact with the gate of the main power VDMOS cell array through a first type of contact hole; the discharge path control LDMOS cell is also in contact with the source of the main power VDMOS cell array through a third type of contact hole, forming a low-resistance discharge path between the gate and the source.

[0010] When the power semiconductor device is in operation, the power VDMOS cell is sampled to obtain the real-time electrical signal of the JFET region.

[0011] Each discharge path controls the LDMOS cell to receive real-time electrical signals. When the real-time electrical signal exceeds a preset short-circuit threshold, it conducts a low-resistance discharge path to discharge the charge at the gate of the main power VDMOS cell array to the source of the main power VDMOS cell array.

[0012] In a second aspect, the present invention also provides a method for fabricating a power semiconductor device, applicable to the power semiconductor device of any one of the first aspects described above, the method comprising:

[0013] Provide a substrate;

[0014] SiC epitaxial layer is grown on the substrate;

[0015] In a SiC epitaxial layer, a main power VDMOS cell array, a sampling power VDMOS cell, and at least one discharge path control LDMOS cell are fabricated; the sampling power VDMOS cell and each main cell under the main power VDMOS cell array adopt the same P-type base region arrangement structure.

[0016] A top metal layer is fabricated on a SiC epitaxial layer;

[0017] The sampling power VDMOS cell contacts the JFET region within the main power VDMOS cell array through a first type of contact hole; the sampling power VDMOS cell contacts the sampling signal metal in the top metal layer through a second type of contact hole; when the power semiconductor device is in operation, the sampling power VDMOS cell is used to acquire the real-time electrical signal of the JFET region.

[0018] The discharge path control LDMOS cell includes a first gate and a second gate; the first gate is metal-connected to the sampling signal through a second type of contact hole; the second gate is in contact with the gate of the main power VDMOS cell array through a first type of contact hole; the discharge path control LDMOS cell is also in contact with the source of the main power VDMOS cell array through a third type of contact hole, forming a low-resistance discharge path between the gate and the source.

[0019] Each discharge path controls the LDMOS cell to receive real-time electrical signals. When the real-time electrical signal exceeds a preset short-circuit threshold, it conducts a low-resistance discharge path to discharge the charge at the gate of the main power VDMOS cell array to the source of the main power VDMOS cell array.

[0020] The power semiconductor device and its fabrication method provided in this invention have the following beneficial effects:

[0021] The power semiconductor device in this application includes a substrate, a SiC epitaxial layer, a top metal layer, and a main power VDMOS cell array, a sampling power VDMOS cell, and at least one discharge path control LDMOS cell integrated on the SiC epitaxial layer. The sampling power VDMOS cell and each main cell in the main power VDMOS cell array adopt the same P-type base region arrangement structure. The sampling power VDMOS cell contacts the JFET region within the main power VDMOS cell array through a first type of contact hole; the sampling power VDMOS cell contacts the sampling signal metal in the top metal layer through a second type of contact hole. The discharge path control LDMOS cell includes a first gate and a second gate; the first gate contacts the sampling signal metal through a second type of contact hole; the second gate contacts the gate of the main power VDMOS cell array through a first type of contact hole; the discharge path control LDMOS cell also contacts the source of the main power VDMOS cell array through a third type of contact hole, forming a low-resistance gate-source discharge path.

[0022] When the power semiconductor device is in operation, the sampling power VDMOS cells are used to acquire the real-time electrical signal of the JFET region; each discharge path control LDMOS cell is used to receive the real-time electrical signal, and when the real-time electrical signal exceeds a preset short-circuit threshold, a low-resistance discharge path is turned on to discharge the charge at the gate of the main power VDMOS cell array to the source of the main power VDMOS cell array. Based on this, this application improves its short-circuit withstand time by integrating a short-circuit protection structure, thereby improving the short-circuit reliability of the device.

[0023] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0024] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0025] Figure 1 A schematic diagram of the structure of the power semiconductor device provided in an embodiment of the present invention is shown;

[0026] Figure 2 A schematic diagram of a power semiconductor device provided in an embodiment of the present invention is shown;

[0027] Figure 3 One of the device layout diagrams of the power semiconductor device provided in the embodiment of the present invention is shown;

[0028] Figure 4 This is a second device distribution diagram of the power semiconductor device provided in an embodiment of the present invention;

[0029] Figure 5 The diagram shows the device structure of the main power VDMOS cell array provided in an embodiment of the present invention;

[0030] Figure 6 A cross-sectional view of the principal cell provided in an embodiment of the present invention is shown;

[0031] Figure 7 The diagram shows the device structure of a sampling power VDMOS cell provided in an embodiment of the present invention;

[0032] Figure 8 One of the cross-sectional views of a sampling power VDMOS cell provided in an embodiment of the present invention is shown;

[0033] Figure 9 This shows a second cross-sectional view of a sampling power VDMOS cell provided in an embodiment of the present invention;

[0034] Figure 10 The third cross-sectional view of the sampling power VDMOS cell provided in the embodiment of the present invention is shown;

[0035] Figure 11 The diagram shows the device structure of the LDMOS cell with discharge path control provided in an embodiment of the present invention.

[0036] Figure 12 One of the cross-sectional views of a discharge path controlled LDMOS cell provided in an embodiment of the present invention is shown;

[0037] Figure 13 This is a second cross-sectional view of a discharge path controlled LDMOS cell provided in an embodiment of the present invention;

[0038] Figure 14 A flowchart of the preparation method provided in an embodiment of the present invention is shown;

[0039] Figure 15 A rendering of the power semiconductor device provided in an embodiment of the present invention is shown.

[0040] Icons: 100 - Power semiconductor device; 101 - Substrate; 102 - SiC epitaxial layer; 103 - Main power VDMOS cell array; 104 - Sampling power VDMOS cell; 105 - Discharge path control LDMOS cell; 106 - Top metal layer; 1 - Drain metal; 2 - N+ substrate; 3 - N- Drift region; 4 - Carrier diffusion layer; 5 - P-type base region; 6 - P+ power source; 7 - N+ power source; 8 - Gate oxide 9-Polysilicon layer; 10-Interlayer dielectric layer; 11-Sampling metal layer; 12-First type contact hole; 13-Second type contact hole; 14-Third type contact hole; 15-Source metal layer; 51-First P-type base region; 52-Second P-type base region; 53-Third P-type base region; 54-Fourth P-type base region; 55-Fifth P-type base region; 56-Sixth P-type base region; 57-First P-type barrier control layer; 58-Second P-type barrier control layer; 71-First N+ power source; 72-Second N+ power source; 73-Third N+ power source; 81-First gate oxide region; 82-Second gate oxide region; 83-Third gate oxide region; 84-Fourth gate oxide region; 85-Fifth gate oxide region; 86-Sixth gate oxide region; 91-Gate polysilicon layer; 92-Sampling polysilicon layer. Detailed Implementation

[0041] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0042] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0043] It should be noted that relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0044] As described in the background section, existing SiC MOSFET chips of the same specifications have an area of ​​only 25% of that of IGBT chips, resulting in higher thermal resistance. Furthermore, a JFET region exists within the chip, 1-2 μm from the surface. During a short circuit, current accumulates in this JFET region, leading to heat concentration on the surface and making it highly susceptible to burnout. Additionally, short-circuit protection for SiC MOSFET chips typically relies on external circuitry to detect the drain-source voltage. However, SiC MOSFET chips have a very short short-circuit withstand time, and external detection circuitry is easily affected by fast switching. A blanking time must be set, and the driver can only issue a protection shutdown signal after the blanking time has elapsed. By the time the protection shutdown signal is received, the SiC MOSFET chip may have already burned out, resulting in poor protection of the SiC MOSFET chip from external circuitry during actual short circuits.

[0045] Based on this, this application provides a power semiconductor device and its fabrication method, which improves its short-circuit withstand time by integrating a short-circuit protection structure, thereby improving the short-circuit reliability of the device.

[0046] Please refer to Figure 1 , Figure 1 The diagram illustrates the structure of a power semiconductor device provided in an embodiment of the present invention. The present invention provides a power semiconductor device 100, which includes a substrate 101, a SiC epitaxial layer 102, and a top metal layer 106. The power semiconductor device 100 also includes a main power VDMOS cell array 103, at least one sampling power VDMOS cell 104, and at least one discharge path control LDMOS cell 105 integrated on the SiC epitaxial layer 102. The sampling power VDMOS cell 104 and the main power VDMOS cell array 103 adopt the same P-type base region arrangement structure.

[0047] In this embodiment, the sampling power VDMOS cell contacts the JFET region within the main power VDMOS cell array through a first type of contact hole; the sampling power VDMOS cell contacts the sampling signal metal in the top metal layer through a second type of contact hole.

[0048] The discharge path control LDMOS cell includes a first gate and a second gate. The first gate is in metal contact with the sampling signal through a second type of contact hole. The second gate is in gate contact with the main power VDMOS cell array through a first type of contact hole. The discharge path control LDMOS cell is also in source contact with the main power VDMOS cell array through a third type of contact hole, forming a low-resistance gate-source discharge path.

[0049] In this embodiment, the JFET region is used to characterize the reverse bias PN junction pinch-off region formed by the N-type drift regions of two adjacent P-type body regions in the first direction, and a current bottleneck channel formed in the vertical direction (from source to drain) that is regulated by the P-region depletion layer.

[0050] This embodiment grows sampling power VDMOS cells, discharge path control LDMOS cells, and main power VDMOS cell arrays on a SiC epitaxial layer. This can be understood as inserting sampling power VDMOS cells and discharge path control LDMOS cells into a traditional main power VDMOS cell array, and forming a short-circuit self-protection circuit through the top metal layer on the power semiconductor device and various types of contact holes (first type contact hole, second type contact hole, and third type contact hole).

[0051] Please refer to Figure 2 , Figure 2 The schematic diagram of the power semiconductor device provided in the embodiment of the present invention is shown. When the power semiconductor device is in the working state, the power VDMOS cell 104 is sampled to obtain the real-time electrical signal of the JFET region. At this time, the power semiconductor device is in the conducting state and the first gate is at a high level.

[0052] Each discharge path controls an LDMOS cell 105 to receive real-time electrical signals. When the real-time electrical signal exceeds a preset short-circuit threshold, a low-resistance discharge path is activated, allowing the LDMOS cells controlled by each discharge path to discharge the charge at the gate of the main power VDMOS cell array to the source of the main power VDMOS cell array. At this time, the power semiconductor device is in a short-circuit state, with the first gate at a high level and the second gate also at a high level.

[0053] It should be noted that in this embodiment, each discharge path control LDMOS cell constitutes a low-resistance discharge path. When the real-time electrical signal exceeds the preset short-circuit threshold, that is, when the current power semiconductor device is in a short-circuit state, its own low-resistance discharge path will be turned on, thereby realizing the discharge of charge at the gate of the main power VDMOS cell array to the source of the main power VDMOS cell array.

[0054] In this embodiment, the power semiconductor device includes two states: a normal operating state, in which the first gate is at a high level and the second gate is at a low level; and an abnormal state, which is a short circuit state where the real-time electrical signal exceeds the preset short circuit threshold. In this state, the first gate is at a high level and the second gate is at a high level. At this time, each discharge path controls the LDMOS cell to conduct its own low-resistance discharge path, discharging the charge at the gate of the main power VDMOS cell array to the source of the main power VDMOS cell array.

[0055] Based on this, this embodiment uses a short-circuit self-protection circuit composed of sampling power VDMOS cells and discharge path control LDMOS cells to quickly respond when the power semiconductor is in a short-circuit state, and establishes a self-discharge loop between the gate and source of the main power VDMOS cell array, reducing the voltage between the gate and source electrodes, thereby significantly reducing the short-circuit current of the power semiconductor device, improving the short-circuit withstand time of the power semiconductor device, and reducing the risk of device short-circuit failure.

[0056] In one possible implementation method, please refer to Figure 3 , Figure 3 The diagram shows the device distribution of the power semiconductor device provided in this embodiment of the invention. In this embodiment, the sampling power VDMOS is located within the power VDMOS region (i.e., the region where the main power VDMOS cell array 103 is located), and (i.e., the distribution area of ​​each sampling power VDMOS cell 104) is distributed around the gate PAD region and partially encloses the gate PAD region.

[0057] In this embodiment, the region where the discharge path control LDMOS is located (i.e., the distribution region of each discharge path control LDMOS cell 105) is located is set around the power VDMOS region and partially includes the power VDMOS region (i.e., the region where the main power VDMOS cell array 103 is located).

[0058] In this embodiment, the power VDMOS region, the sampling power VDMOS region, the discharge path control LDMOS region, and the gate PAD region are all located in the power semiconductor device in regions other than the transition region and the termination region, and are surrounded by the transition region and the termination region.

[0059] In this embodiment, the gate PAD region can be understood as a metallized region on a power semiconductor device specifically designed to provide an external interface for the gate signal. In this embodiment, the transition region and termination region can be understood as regions on a power semiconductor device specifically designed to prevent edge collapse and to withstand voltage.

[0060] It should be noted that this embodiment does not limit the distribution of the transition region & termination region, the gate PAD region, and the power VDMOS region. Figure 3 above is only one possible solution.

[0061] Please Figure 3 Based on, refer to Figure 4 , Figure 4 This diagram illustrates another device distribution of the power semiconductor device provided in an embodiment of the present invention. In this embodiment, the top metal layer includes at least a sampling metal layer and a source metal layer. The source metal layer covers the power VDMOS region, while the sampling metal layer covers the sampling power VDMOS region and the discharge path control LDMOS region, so as to feed back the real-time electrical signal of the JFET region to each cell under the discharge path control LDMOS region.

[0062] Furthermore, taking any main cell in the main power VDMOS cell array as an example, please refer to... Figure 5 , Figure 5 This diagram illustrates the device structure of a main power VDMOS cell array provided in an embodiment of the present invention. When the power semiconductor device 100 includes, from bottom to top, a drain metal 1, an N+ substrate 2, an N- drift region 3, and a carrier diffusion layer 4, the arrangement structure of the P-type base region 5 includes:

[0063] Multiple P-type base regions 5 are disposed on the surface of the carrier diffusion layer 4; wherein the P-type base regions 5 are arranged at periodic intervals along a first direction, so as to form a JFET region in the middle region between any two adjacent P-type base regions 5.

[0064] N+ power source 7 is embedded along the second direction on the surface of each P-type base region 5.

[0065] Multiple P+ power sources 6 are embedded along the second direction in each N+ power source 7; the N+ power source 7 encloses the P+ power source 6.

[0066] The first direction and the second direction are perpendicular to each other and are both parallel to the plane containing the P-type base region.

[0067] Please continue to refer to this. Figure 5 With the lateral direction of the power semiconductor device as the X-axis, the vertical direction of the power semiconductor device as the Y-axis, and the third dimension of the power semiconductor device as the Z-axis, in this embodiment, the first direction and the second direction are the aforementioned X-axis and Z-axis directions, respectively.

[0068] In this embodiment, the P-type body region is characterized as a single semiconductor P-type doped region formed on the surface of the N-drift region by implantation and activation of P-type impurities (such as aluminum, Al), possessing a specific junction depth, surface concentration, and longitudinal doping profile. Correspondingly, the aforementioned JFET region is distributed between the regions of two adjacent P-type body regions in the X-axis direction. This JFET region uses the heavily doped N+ power source region as the electron source and the lightly doped N-drift region as the main breakdown layer.

[0069] In one possible implementation, taking any main cell in a main power VDMOS cell array as an example, please refer to... Figure 6 , Figure 6 A cross-sectional view of the main cell provided in an embodiment of the present invention is shown. When the power semiconductor device 100 further includes, from bottom to top, a gate oxide layer, a polysilicon layer 9, an interlayer dielectric layer, and a top metal layer 106, the main cell also achieves contact between the top metal layer 106 (mainly the source metal layer) and the semiconductor layer of the power semiconductor device 100 through a third type of contact hole 14. The third type of contact hole 14 is periodically disposed in the interlayer dielectric layer and penetrates the interlayer dielectric layer, the gate oxide layer, and the polysilicon layer 9.

[0070] In this embodiment, the semiconductor layer of the power semiconductor device is composed of the above-mentioned N+ substrate 2, N- drift region 3, carrier diffusion layer 4, P-type base region 5, N+ power source 7 and P+ power source 6.

[0071] Since the sampling power VDMOS cell and any main cell in the main power VDMOS cell array are both integrated on the SiC epitaxial layer and use the same P-type base region arrangement structure, similarly, please refer to... Figure 7 , Figure 7 The diagram shows the device structure of a sampling power VDMOS cell 104 provided in an embodiment of the present invention. The sampling power VDMOS cell 104 includes, from bottom to top, a drain metal 1, an N+ substrate 2, an N- drift region 3, a carrier diffusion layer 4, a P-type base region 5, an N+ power source 7, and a P+ power source 6.

[0072] Since the sampling power VDMOS is located within the power VDMOS region, that is, each sampling power VDMOS cell in the sampling power VDMOS region is distributed within the power VDMOS region. The difference between the sampling power VDMOS cell and the main cells in the power VDMOS cell array is that: along the X-axis direction, for any two adjacent P-type base regions, the left side of the first P-type base region 5 in the sampling power VDMOS cell is covered with a polysilicon layer 9, and its channel is the normal power VDMOS channel; the polysilicon layer 9 above the right part of the channel is periodically broken to form a sampling window to obtain the real-time electrical signal of the JFET region.

[0073] For details, please refer to Figure 8 , Figure 8 A cross-sectional view of a sampling power VDMOS cell provided in an embodiment of the present invention is shown. When the power semiconductor device 100 further includes, from bottom to top, a gate oxide layer, a polysilicon layer, an interlayer dielectric layer, and a top metal layer, the sampling power VDMOS cell 104 is also provided with a first type of contact hole 12 and a second type of contact hole 13.

[0074] In this embodiment, the first type of contact hole 12 is periodically disposed in the gate oxide layer and penetrates the gate oxide layer to achieve contact between the semiconductor layer of the power semiconductor device and the polysilicon layer 9. The second type of contact hole 13 is periodically disposed in the interlayer dielectric layer and penetrates the interlayer dielectric layer to achieve contact between the polysilicon layer 9 and the top metal layer 106.

[0075] Based on this, this embodiment can acquire the real-time electrical signal of the JFET region based on the first type of contact hole 12, and transmit the real-time electrical signal to the polysilicon layer 9, and along the X-axis direction to the polysilicon layer 9 where the second type of contact hole 13 is located, and transmit the real-time electrical signal to the sampling signal metal in the top metal layer 106 through the second type of contact hole 13.

[0076] It should be noted that when the power semiconductor device is subjected to reverse breakdown voltage, the depletion layer of the adjacent P-type base region below the first type contact hole in the sampling power VDMOS cell absorbs most of the electric field lines, thereby providing a protective effect on the area where the first type contact hole is located.

[0077] In one possible implementation, the real-time electrical signal can be the voltage signal at the N-drift region 3 in the JFET region.

[0078] Further, please refer to Figure 9 , Figure 9 This diagram shows another cross-sectional view of the sampling power VDMOS cell provided in an embodiment of the present invention. When any two adjacent P-type base regions along the first direction, i.e., the aforementioned X-axis direction, include the first P-type base region 51 and the second P-type base region 52, the sampling power VDMOS cell 104 further includes:

[0079] A gate oxide layer 8 is disposed on the surface of the first P-type base region 51 and the surface of the second P-type base region 52, and the gate oxide layer 8 covers the first P-type base region 51 and the second P-type base region 52.

[0080] A gate polysilicon layer 91 and a sampling polysilicon layer 92 are disposed on the surface of the gate oxide layer 8. In this embodiment, the gate polysilicon layer 91 covers the first gate oxide region 81 in the gate oxide layer 8 to form a power VDMOS channel; the sampling polysilicon layer 92 covers the second gate oxide region 82 in the gate oxide layer 8, and the sampling polysilicon layer is periodically provided with multiple sampling regions along the second direction (i.e., the Z-axis direction) so that the sampling polysilicon layer contacts the N-drift region of the JFET region through the sampling regions, and the real-time electrical signal of the JFET region is transmitted to the sampling polysilicon layer.

[0081] It should be noted that in this embodiment, each sampling region is used to characterize the projection region of the JFET region in the sampling polysilicon layer. The first gate oxide region 81 is used to characterize the projection region of the left side region of the first P-type base region 51 in the gate oxide layer 8. The second gate oxide region 82 is used to characterize the projection regions of the JFET region and the second P-type base region 52 in the gate oxide layer 8.

[0082] In this embodiment, the area on the right side of the second P-type base region 52 and the surface of the carrier diffusion layer 4 is also covered by a P+ power source 6. At the same time, the gate oxide layer 8 also covers the P+ power source 6 corresponding to this area.

[0083] Please refer to Figure 10 , Figure 10 This illustration shows another cross-sectional view of the sampling power VDMOS cell provided in an embodiment of the present invention. In this embodiment, the sampling power VDMOS cell 104 further includes:

[0084] Multiple first-type contact holes 12 are disposed in the first target region of the gate oxide layer 8. The first-type contact holes 12 penetrate the gate oxide layer 8 to contact the sampling polysilicon layer and the N-drift region of the JFET region.

[0085] The first target region is used to characterize the projection region of the sampling region in the gate oxide layer, and is located within the JFET region.

[0086] Please continue to refer to this. Figure 10 In this embodiment, the sampling power VDMOS cell 104 further includes:

[0087] An interlayer dielectric layer 10 is disposed on the surface of the gate polysilicon layer 91 and the sampling polysilicon layer 92; the interlayer dielectric layer 10 covers the gate polysilicon layer 91 and the sampling polysilicon layer 92.

[0088] Multiple second-type contact holes 13 are disposed in the second target region of the interlayer dielectric layer 10. The second-type contact holes 13 penetrate the interlayer dielectric layer 10 and each second-type contact hole contacts the sampling polysilicon layer 92 and the sampling signal metal, respectively, so as to transmit the real-time electrical signal of the JFET region from the sampling polysilicon layer 92 to the sampling signal metal in the top metal layer 106.

[0089] The second target region is used to characterize the projection region of the sampling signal metal on the interlayer dielectric layer 10. The second target region is located to the right of the second P-type base region 52 and on the surface of the carrier diffusion layer 4.

[0090] In this embodiment, the left side of the first P-type base region 51 is covered by a gate polysilicon layer 91, whose channel is a normal power VDMOS channel; the gate polysilicon above the right part of the channel is periodically disconnected to form a sampling window; along the z-axis direction, a sampling polysilicon layer 92 is periodically embedded in this sampling window. Simultaneously, a first type of contact hole 12 is periodically opened at the projection region of the sampling area in the gate oxide layer 8 within the sampling power VDMOS cell 104, to sample the voltage of the N-drift region 3 based on the first type of contact hole 12, and to transmit the sampled signal to the sampling polysilicon layer 92. Along the X-axis direction, the interlayer dielectric layer 10 transmits the real-time electrical signal from the sampling polysilicon layer 92 to the sampling signal metal, which then transmits the real-time electrical signal to the first gate of the discharge path control LDMOS cell 105.

[0091] In summary, the sampling power VDMOS cell integrated on the power semiconductor device in this embodiment periodically opens holes in the JFET region between the P-type base regions and fills them with contact metal to directly transfer the potential of the N-drift region in the JFET region to the upper sampling polysilicon layer. Then, the potential on the sampling polysilicon layer is connected to the sampling signal metal characterized by the device through the contact metal (the contact metal corresponding to the second type of contact hole), thereby achieving accurate and fast sampling of short-circuit signals.

[0092] The principle of the power semiconductor device in this embodiment is as follows:

[0093] When a short circuit occurs, the voltage of the drain electrode of the power semiconductor device is the bus voltage, and the source electrode is grounded, so its voltage is zero. At this time, the drain-source voltage is the bus voltage. Since the resistance of the drift region and JFET region inside the power semiconductor device is higher than that of the channel region, they will bear most of the drain-source voltage. The N-drift region voltage of the JFET region is about 20~30V.

[0094] When the power semiconductor device is working normally, the drain-source voltage is very low, usually only 1-2V. By directly sampling the voltage of the N-drift region of the JFET region and connecting this voltage directly to the sampling signal gate (first gate) of the LDMOS cell that controls the discharge path, it is possible to quickly and without interference determine whether a short circuit event has occurred in the power semiconductor device, thereby responding quickly and protecting the device.

[0095] Based on this, please refer to Figure 11 , Figure 11This diagram illustrates the device structure of a discharge path controlled LDMOS cell according to an embodiment of the present invention. In this embodiment, the lateral direction of the power semiconductor device is taken as the X-axis, the vertical direction as the Y-axis, and the third dimension as the Z-axis. The first and second directions in this embodiment are the aforementioned X-axis and Z-axis directions, respectively. When the power semiconductor device includes a drain metal 1, an N+ substrate 2, an N- drift region 3, and a carrier diffusion layer 4 arranged sequentially from bottom to top (i.e., along the Y-axis), the discharge path controlled LDMOS cell 105 in this embodiment further includes:

[0096] Along the first direction (i.e., the X-axis direction), the third P-type base region 53 and the P+ power source 6 are disposed on the surface of the carrier diffusion layer 4.

[0097] In this embodiment, the P+ power source 6 is in contact with the third P-type base region 53.

[0098] A discharge path control structure is disposed on the surface of the P+ power source 6; the P+ power source 6 encloses the discharge path control structure, which includes a first gate and a second gate to contact the sampling signal metal and the gate of the main power VDMOS cell array, respectively; the discharge path control structure also contacts the source of the main power VDMOS cell array through a third type of contact hole.

[0099] Please continue to refer to this. Figure 11 In this embodiment, the discharge path control LDMOS cell 105 further includes:

[0100] A gate oxide layer disposed in the region to the left of the third P-type base region 53;

[0101] A gate polysilicon layer is disposed on the surface of the gate oxide layer, and the gate polysilicon layer covers the third gate oxide region 83 in the gate oxide layer to form a power VDMOS channel.

[0102] In this embodiment, the third gate oxide region 83 is used to characterize the projection region of the left side region of the third P-type base region 53 in the gate oxide layer 8.

[0103] A source metal layer 15 is disposed on the surface of the gate polysilicon layer.

[0104] Along the second direction, second type contact holes 13 are periodically embedded in the gate polysilicon layer to make the gate polysilicon layer contact the source metal layer.

[0105] Please continue to refer to this. Figure 11 In this embodiment, the discharge path control LDMOS cell 105 further includes:

[0106] Along the first direction (i.e., the X-axis direction), the fourth P-type base region 54, the first P-type barrier control layer 57, the fifth P-type base region 55, the second P-type barrier control layer 58, and the sixth P-type base region 56 are sequentially disposed on the surface of the P+ power source 6.

[0107] In this embodiment, the first P-type barrier control layer 57 is sandwiched between the fourth P-type base region 54 and the fifth P-type base region 55, and the second P-type barrier control layer 58 is sandwiched between the fifth P-type base region 55 and the sixth P-type base region 56.

[0108] The first N+ power source 71, the second N+ power source 72, and the third N+ power source 73 are sequentially embedded in the fourth P-type base region 54, the fifth P-type base region 55, and the sixth P-type base region 56.

[0109] In this configuration, the first N+ power source 71 serves as the first gate and is in metal contact with the sampling signal through the second type of contact hole 13; the second N+ power source 72 is floating; and the third N+ power source 73 serves as the second gate and is in gate contact with the main power VDMOS cell array 103 through the first type of contact hole 12.

[0110] In this embodiment, four P-type base regions are provided along the X-axis. The first P-type base region along the X-axis (i.e., the third P-type base region 53 mentioned above) is a conventional VDMOS base region, with a polysilicon layer (i.e., gate polysilicon layer) covering its upper left side, which is connected to the gate potential. The channel on its left side is the normal operating VDMOS power channel. The next three P-type base regions along the X-axis (the fourth P-type base region 54, the fifth P-type base region 55, and the sixth P-type base region 56 mentioned above) are P-type base regions of LDMOS cells with discharge path control. They are all wrapped by P+ power sources. Two P-type barrier control layers (the first P-type barrier control layer 57 and the second P-type barrier control layer 58, respectively) are sandwiched between the fourth P-type base region 54, the fifth P-type base region 55, and the sixth P-type base region 56. At the same time, each of the fourth P-type base region 54, the fifth P-type base region 55, and the sixth P-type base region 56 is wrapped with an N+ power source.

[0111] Please refer to Figure 12 , Figure 12 A cross-sectional view of a discharge path controlled LDMOS cell provided in an embodiment of the present invention is shown. In this embodiment, the discharge path controlled LDMOS cell 105 further includes:

[0112] A gate oxide layer 8 is disposed on the surface of the fourth P-type base region 54, the first P-type barrier control layer 57, the fifth P-type base region 55, the second P-type barrier control layer 58, and the sixth P-type base region 56; wherein the gate oxide layer 8 covers the fourth P-type base region 54, the first P-type barrier control layer 57, the fifth P-type base region 55, the second P-type barrier control layer 58, and the sixth P-type base region 56.

[0113] A gate polysilicon layer 91 and a sampling polysilicon layer 92 are disposed on the surface of the gate oxide layer 8.

[0114] In this embodiment, the gate polysilicon layer 91 covers the fourth gate oxide region 84 of the gate oxide layer 8.

[0115] In this embodiment, the fourth gate oxide region 84 is used to characterize the projection region of the sixth P-type base region 56, the second P-type barrier control layer 58 and the first part of the region on the gate oxide layer 8. The first part of the region is used to characterize the right side region of the fifth P-type base region 55 except for the region where the second N+ power source 72 is located, so as to partially expose the second N+ power source 72 in the fifth P-type base region 55.

[0116] In this embodiment, the sampling polysilicon layer 92 covers the fifth gate oxide region 85 of the gate oxide layer 8. The fifth gate oxide region 85 is used to characterize the projection region of the second part region, the first P-type barrier control layer 57, and the third part region on the gate oxide layer 8. The third part region is used to characterize the left side region of the fifth P-type base region 55, excluding the region where the second N+ power source 72 is located. The second part region is used to characterize the right side region of the fourth P-type base region 54, excluding the region where the first N+ power source 7 is located.

[0117] A sampling metal layer 11 is disposed on the surface of the sampling polysilicon layer 92.

[0118] Multiple first-type contact holes 12 are disposed in the gate oxide layer 8. The first-type contact holes 12 penetrate the gate oxide layer 8 and contact the gate polysilicon layer 91 and the third N+ power source 73, so that the third N+ power source 73 serves as the second gate and contacts the gate of the main power VDMOS cell array 103.

[0119] Multiple second-type contact holes 13 are embedded in the sampling polysilicon layer 92 and contact the sampling polysilicon layer 92 and the sampling metal layer 11, so that the first N+ power source 7 acts as the first gate and contacts the sampling signal metal to receive the real-time electrical signal of the JFET region.

[0120] In summary, in this embodiment, along the X-axis direction from right to left, the first N+ power source (i.e., the third N+ power source 73) in the P-type base region of the LDMOS cell controlled by the dot path is connected to the polysilicon layer (i.e., the gate polysilicon) connected to the gate through the first type of contact hole 12, the second N+ power source (i.e., the second N+ power source 72) is floating, and the third N+ power source (i.e., the first N+ power source 71) is connected to the sampling signal metal through the second type of contact hole 13.

[0121] Please continue to refer to this. Figure 12 In this embodiment, the discharge path control LDMOS cell 105 further includes:

[0122] A source metal layer 15 is disposed on the surface of the sixth gate oxide region 86 in the gate oxide layer 8;

[0123] In this embodiment, the sixth gate oxide region 86 is used to characterize the projection region of the P+ power source in the first N+ power source in the gate oxide layer.

[0124] Along the second direction, a third type of contact hole 14 is periodically embedded in the sixth gate oxide region 86. The third type of contact hole 14 penetrates the sixth gate oxide region 86 so that the P+ power source is in contact with the source metal layer.

[0125] Further, please refer to Figure 13 , Figure 13 Another cross-sectional view of the discharge path control LDMOS cell provided in the embodiment of the present invention is shown. From right to left, on the leftmost side of the structure where the discharge path control LDMOS cell 105 is located, that is, the first N+ power source 71 in the P-type base region 5 of the discharge path control LDMOS cell, a third type of contact hole 14 is periodically provided along the Z-axis direction for connecting the P+ power source 6 to the source.

[0126] In summary, the discharge path control LDMOS cell integrated on the power semiconductor device in this embodiment consists of three P-type base regions. Each P-type base region has an N+ power source generated by a self-aligned process. The gap between adjacent P-type base regions is a P-type barrier control layer used to adjust its own threshold voltage.

[0127] In one possible implementation, this embodiment can limit the potential of the N-drift region below the first type of contact hole (in the sampling power VDMOS cell 104) to 20-30V, and then by thickening the gate oxide layer of the discharge path control LDMOS cell portion, the threshold voltage and gate withstand voltage of the discharge path control LDMOS cell can be adjusted to match the potential on the sampling signal when a short circuit event occurs.

[0128] In this embodiment, the adjacent P-type base regions and their enclosed N+ source regions (i.e., N+ power sources) arranged in sequence constitute two series-connected lateral MOSFETs. The source of the left lateral MOSFET is also the drain of the right lateral MOSFET. This common electrode is defined as the intermediate electrode. Since this electrode is not needed when processing signals, the N+ region corresponding to this electrode (i.e., the second N+ power source mentioned above) is left floating.

[0129] Furthermore, a polysilicon layer (gate polysilicon) is applied over the drain of the left-side lateral MOSFET and the corresponding gate oxide layer 8, forming a gate-drain short-circuit structure. The source of the other lateral MOSFET is grounded, and a polysilicon island is applied over the gate oxide layer 8, which is connected to the sampling metal layer 11 through a second type of contact hole 13.

[0130] Based on this, in this embodiment, the P-type base region potential of the LDMOS cell 105 is controlled by the external P+ power source to ground, and its threshold voltage is the ground voltage of the P-type base region, which is not affected by the connected source and drain voltage.

[0131] Meanwhile, the entire discharge path controls the two gates of the LDMOS cell 105, one of which is connected to the gate electrode (i.e., the second gate) of the power semiconductor device 100, and the other is connected to the sampling metal layer 11 (i.e., the first gate).

[0132] When the gate electrode potential of a power semiconductor device is high, it indicates that it has received an external turn-on signal. If the power semiconductor device is working normally, the voltage on the sampling signal layer is 1-2V. At this time, the discharge path controls the side of the LDMOS cell connected to the gate electrode (second gate) to conduct, and the discharge path controls the side of the LDMOS cell connected to the sampling metal layer (first gate) to turn off, thus turning off the discharge path from the gate to the source.

[0133] When a short circuit occurs in a power semiconductor device, the voltage on the sampling metal layer will rise to about 20V, turning on both the second and first gates. At this time, a low-resistance discharge path from the gate to the source will be opened, allowing the positive charge on the gate of the power semiconductor device to quickly flow into the source through this low-resistance discharge path, reducing the gate-source voltage of the device and thus reducing the short-circuit current, achieving a rapid protection effect. At the same time, this low-resistance discharge path integrated inside the power semiconductor device is not affected by the high-speed switching of the device, and has a very strong anti-interference capability. It effectively prevents short-circuit burnout that may be caused by the blanking time of the external gate drive during the short-circuit protection process, significantly improving the short-circuit reliability of the device.

[0134] In summary, the embodiments of the present invention provide a power semiconductor device with integrated short-circuit protection function. By inserting sampling power VDMOS cells and lateral discharge path control LDMOS cells into a conventional main power VDMOS cell array, the three are interconnected through the top metal layer to form a short-circuit self-protection circuit.

[0135] In this embodiment, the short-circuit self-protection circuit can respond quickly when a short circuit occurs in the power semiconductor device, forming a self-discharge loop between the gate electrode and the source electrode, reducing the voltage between the gate and source electrodes, thereby significantly reducing the short-circuit current of the power semiconductor device, improving the short-circuit withstand time of the power semiconductor device, reducing the risk of device short-circuit failure, and this short-circuit protection method has the characteristics of rapid response, strong anti-interference ability, high integration, and low cost.

[0136] In addition, please refer to Figure 14 , Figure 14A flowchart of the fabrication method provided in this embodiment of the invention is shown. This embodiment also provides a method for fabricating a power semiconductor device, which includes steps 100 to 600.

[0137] Step 100: Provide a substrate.

[0138] Step 200: Grow a SiC epitaxial layer on the substrate.

[0139] Step 300: Fabricate a main power VDMOS cell array, a sampling power VDMOS cell, and at least one discharge path control LDMOS cell in the SiC epitaxial layer.

[0140] In this embodiment, the sampling power VDMOS cells and the main power VDMOS cells in the array adopt the same P-type base region arrangement structure.

[0141] Step 400: Prepare the top metal layer on the SiC epitaxial layer.

[0142] The sampling power VDMOS cell is connected to the JFET region within the main power VDMOS cell array via a first type of contact hole; the sampling power VDMOS cell is connected to the sampling signal metal in the top metal layer via a second type of contact hole. The discharge path control LDMOS cell includes a first gate and a second gate; the first gate is connected to the sampling signal metal via a second type of contact hole; the second gate is connected to the gate of the main power VDMOS cell array via a first type of contact hole; the discharge path control LDMOS cell is also connected to the source of the main power VDMOS cell array via a third type of contact hole, forming a low-resistance gate-source discharge path.

[0143] When the power semiconductor device is in operation, the sampling power VDMOS cell is used to acquire the real-time electrical signal of the JFET region; each discharge path control LDMOS cell is used to receive the real-time electrical signal, and when the real-time electrical signal exceeds the preset short-circuit threshold, the low-resistance discharge path is turned on to discharge the charge at the gate of the main power VDMOS cell array to the source of the main power VDMOS cell array.

[0144] In one possible implementation, the substrate in this embodiment may be an N+ substrate.

[0145] In this embodiment, the SiC epitaxial layer includes at least: an N-drift region and a carrier diffusion layer. Based on this, step 200 in this embodiment can be implemented as follows:

[0146] An N-drift region is grown on an N+ substrate. In this embodiment, the upper surface of the N+ substrate is in contact with the lower surface of the N-drift region.

[0147] Subsequently, a SiO2 hard mask layer is deposited on the front side of the power semiconductor device, and an (N-type) carrier diffusion layer injection window is formed on the SiO2 hard mask layer using photolithography. Then, N-type impurities are injected through the injection window, and the SiO2 hard mask layer is removed to form an N-type carrier diffusion layer. The upper surface of the N-drift region is in contact with the lower surface of the N-type carrier diffusion layer.

[0148] After the SiC epitaxial layer is prepared, a main power VDMOS cell array, at least one sampling power VDMOS cell, and at least one discharge path control LDMOS cell can be fabricated on the SiC epitaxial layer. In one possible implementation, step 300 in this embodiment can be implemented as follows:

[0149] In this embodiment, a SiO2 hard mask layer is deposited on the front side of the power semiconductor device, i.e., the surface of the SiC epitaxial layer. Then, a portion of the SiO2 is etched to form a P-type base region implantation window. Next, P-type impurities are implanted to obtain the P-type base region. Then, a spacer with a width equal to the power VDMOS channel length is grown on the SiO2 hard mask layer corresponding to the P-type base region. Self-alignment is then used to form the N+ power source region in the main power VDMOS cell and the N+ source / drain implantation window in the discharge path control LDMOS cell. N-type impurities are then implanted, and finally, the SiO2 hard mask layer is removed.

[0150] Next, a SiO2 hard mask layer is deposited on the front side of the power semiconductor device (i.e., the surface of the P-type base region). After photolithography, a portion of the SiO2 is etched to form a P+ power source region injection window. Then, P-type impurities are injected, and finally the SiO2 hard mask layer is removed.

[0151] Subsequently, a SiO2 hard mask layer is deposited on the front side of the device, and part of the SiO2 is etched to form a P-type barrier control region implantation window, and then P-type impurities are implanted.

[0152] After implantation is complete, the device is subjected to high-temperature annealing to activate the implanted impurities and obtain a P-type base region, an embedded N+ power source, a P+ power source embedded in the N+ power source, and a P-type barrier control layer.

[0153] In this embodiment, the upper surface of the N-type carrier diffusion layer 4 is in contact with the P-type base region and the P-type barrier control layer in the discharge path control LDMOS cell. Simultaneously, the N+ source region in the main power VDMOS cell and the N+ source / drain in the discharge path control LDMOS cell are embedded in the P-type base region and completely enclosed by it.

[0154] Next, SiN is deposited on the front side of the device, photolithography is performed, and after etching part of the SiN, the gate oxide layer of the exposed discharge path control LDMOS cell is thickened a second time.

[0155] In this embodiment, the gate oxide layer covers the upper surface of the semiconductor layer of the power semiconductor device, separating the polysilicon layer from the semiconductor layer.

[0156] Subsequently, photolithography was performed on the front side of the device, and part of the gate oxide layer was etched to form a first type of contact hole.

[0157] After the first type of contact hole is prepared, a polysilicon layer is deposited on the front side of the device, and photolithography is performed to etch a portion of the polysilicon to form the gate polysilicon region (i.e., the aforementioned gate polysilicon layer) and the sampling signal polysilicon region (i.e., the aforementioned sampling polysilicon layer). In this embodiment, the lower surface of the polysilicon layer is in contact with the upper surface of the gate oxide layer.

[0158] Next, an isolation dielectric layer is deposited on the front side of the device, photolithography is performed, and then a portion of the isolation dielectric layer is etched to form a second type of contact hole; at the same time, a portion of the isolation dielectric layer and the underlying gate oxide layer are etched to form a third type of contact hole.

[0159] In this embodiment, the first type of contact hole passes through the gate oxide layer and is surrounded by the N-drift region at its bottom, so as to connect the sampling polysilicon layer above the sampling power VDMOS cell with the N-drift region at the center of the JFET region. At the same time, the first type of contact hole also connects the drain of the discharge path control LDMOS cell on the gate side with the polysilicon layer above it.

[0160] In this embodiment, the second type of contact hole penetrates the isolation dielectric layer, connecting the polysilicon layer to the gate metal or the sampling signal metal. The bottom of this second type of contact hole is surrounded by N+ source regions and P+ source regions. Simultaneously, the bottom of the second type of contact hole that contacts the sampling signal metal is wrapped by the sampling polysilicon layer.

[0161] In this embodiment, the third type of contact hole penetrates the gate oxide layer and the isolation dielectric layer, connecting the N+ source region and P+ source region in the power VDMOS to the source metal layer.

[0162] Once the first type of contact hole, the second type of contact hole, and the third type of contact hole have been prepared, the top metal layer can be prepared.

[0163] In one possible implementation, this embodiment may deposit a top metal layer on the front side of the device and etch a portion of the metal to form a gate metal layer, a source metal layer, and a sampling metal layer.

[0164] Finally, the back of the device is thinned and then metal is deposited to form the drain metal.

[0165] It should be noted that this embodiment is only an illustrative description of the above-described method for fabricating power semiconductor devices. The fabrication methods provided in this embodiment include, but are not limited to, the above-described photolithography, deposition, and other methods.

[0166] Furthermore, to verify the beneficial effects of the power semiconductor device in this embodiment, please refer to... Figure 15 , Figure 15 The diagram shows the effect of a power semiconductor device provided in an embodiment of the present invention. The horizontal axis represents time, and the vertical axis represents the drain-source current I during a short circuit. DS As can be seen from the figure, the power semiconductor device (i.e., integrated short-circuit protection) in this embodiment has a lower drain-source current I compared to traditional power semiconductor devices. DS In this embodiment, the power semiconductor device needs to withstand lower short-circuit energy under the same short-circuit time. That is, under the same short-circuit withstand energy, the power semiconductor device in this embodiment is beneficial to enhance the maximum short-circuit withstand time of the chip.

[0167] In summary, this application provides a power semiconductor device and its fabrication method, which improves the short-circuit withstand time by integrating a short-circuit protection structure, thereby enhancing the short-circuit reliability of the device.

[0168] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can also be implemented in other ways. The apparatus embodiments described above are merely illustrative; for example, the flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of apparatus, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions marked in the blocks may occur in a different order than those marked in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in a block diagram and / or flowchart, and combinations of blocks in block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0169] In addition, the functional modules in the various embodiments of the present invention can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0170] If the aforementioned functions are implemented as software functional modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this invention, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0171] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A power semiconductor device, the power semiconductor device comprising a substrate, a SiC epitaxial layer, and a top metal layer, characterized in that, The power semiconductor device further includes a main power VDMOS cell array, a sampling power VDMOS cell, and at least one discharge path control LDMOS cell integrated on the SiC epitaxial layer; wherein the sampling power VDMOS cell and each main cell under the main power VDMOS cell array adopt the same P-type base region arrangement structure. The sampling power VDMOS cell contacts the JFET region within the main power VDMOS cell array through a first type of contact hole; the sampling power VDMOS cell contacts the sampling signal metal in the top metal layer through a second type of contact hole. The discharge path control LDMOS cell includes a first gate and a second gate; the first gate is in metal contact with the sampling signal through the second type of contact hole; the second gate is in gate contact with the main power VDMOS cell array through the first type of contact hole; the discharge path control LDMOS cell is also in source contact with the main power VDMOS cell array through the third type of contact hole, forming a low-resistance gate-source discharge path. When the power semiconductor device is in operation, the sampling power VDMOS cell is used to acquire the real-time electrical signal of the JFET region. Each of the discharge path control LDMOS cells is used to receive the real-time electrical signal and, when the real-time electrical signal exceeds a preset short-circuit threshold, to conduct the low-resistance discharge path to discharge the charge at the gate of the main power VDMOS cell array to the source of the main power VDMOS cell array.

2. The power semiconductor device according to claim 1, characterized in that, When the power semiconductor device includes an N+ substrate, an N- drift region, and a carrier diffusion layer arranged sequentially from bottom to top, the P-type base region arrangement structure includes: A plurality of P-type base regions are disposed on the surface of the carrier diffusion layer; wherein the P-type base regions are arranged at periodic intervals along a first direction to form a JFET region in the middle region between any two adjacent P-type base regions. N+ power sources embedded along the second direction on the surface of each P-type base region; Multiple P+ power sources are embedded along the second direction in each N+ power source; the N+ power source surrounds the P+ power source. The first direction and the second direction are perpendicular to each other and are both parallel to the plane containing the P-type base region.

3. The power semiconductor device according to claim 1 or 2, characterized in that, When the P-type base region arrangement structure along the first direction includes multiple P-type base regions, and a JFET region is formed in the middle region between any two adjacent P-type base regions, and when any two adjacent P-type base regions include a first P-type base region and a second P-type base region, the sampling power VDMOS cell further includes: A gate oxide layer is disposed on the surface of the first P-type base region and the surface of the second P-type base region, the gate oxide layer covering the first P-type base region and the second P-type base region; A gate polysilicon layer and a sampling polysilicon layer are disposed on the surface of the gate oxide layer; the gate polysilicon layer covers the first gate oxide region in the gate oxide layer to form a power VDMOS channel; the sampling polysilicon layer covers the second gate oxide region in the gate oxide layer, and the sampling polysilicon layer is periodically provided with multiple sampling regions along a second direction, so that the sampling polysilicon layer contacts the N-drift region of the JFET region through the sampling regions, and the real-time electrical signal of the JFET region is transmitted to the sampling polysilicon layer; Wherein, each of the sampling regions is used to characterize the projection region of the JFET region in the sampling polysilicon layer; the first gate oxide region is used to characterize the projection region of the left side region of the first P-type base region in the gate oxide layer; the second gate oxide region is used to characterize the projection regions of the JFET region and the second P-type base region in the gate oxide layer; The first direction and the second direction are perpendicular to each other and are both parallel to the plane containing the P-type base region.

4. The power semiconductor device according to claim 3, characterized in that, The sampling power VDMOS cell also includes: A plurality of first-type contact holes are disposed in a first target region in the gate oxide layer, the first-type contact holes penetrating the gate oxide layer to contact the sampling polysilicon layer and the N-drift region of the JFET region; wherein, the first target region is used to characterize the projection region of the sampling region in the gate oxide layer.

5. The power semiconductor device according to claim 3, characterized in that, The sampling power VDMOS cell also includes: An interlayer dielectric layer is disposed on the surface of the gate polysilicon layer and the surface of the sampling polysilicon layer; the interlayer dielectric layer covers the gate polysilicon layer and the sampling polysilicon layer; Multiple second-type contact holes are disposed in the second target region of the interlayer dielectric layer. The second-type contact holes penetrate the interlayer dielectric layer and contact the sampling polysilicon layer and the sampling signal metal to transmit the real-time electrical signal of the JFET region from the sampling polysilicon layer to the sampling signal metal. The second target region is used to characterize the projection region of the sampled signal metal in the interlayer dielectric layer.

6. The power semiconductor device according to claim 2, characterized in that, When the power semiconductor device includes an N+ substrate, an N- drift region, and a carrier diffusion layer arranged sequentially from bottom to top, the discharge path control LDMOS cell includes: Along the first direction, a third P-type base region and a P+ power source are disposed on the surface of the carrier diffusion layer, and the P+ power source is in contact with the third P-type base region. A discharge path control structure is disposed on the surface of the P+ power source electrode; the P+ power source electrode encloses the discharge path control structure, the discharge path control structure includes a first gate and a second gate, which are respectively in contact with the sampling signal metal and the gate of the main power VDMOS cell array; the discharge path control structure is also in contact with the source electrode of the main power VDMOS cell array through the third type of contact hole.

7. The power semiconductor device according to claim 6, characterized in that, The discharge path control LDMOS cell also includes: A gate oxide layer disposed in the region to the left of the third P-type base region; A gate polysilicon layer is disposed on the surface of the gate oxide layer, the gate polysilicon layer covering the third gate oxide region in the gate oxide layer to form a power VDMOS channel; wherein, the third gate oxide region is used to characterize the projection region of the left side region of the third P-type base region in the gate oxide layer; A source metal layer disposed on the surface of the gate polysilicon layer; Along the second direction, a second type of contact hole is periodically embedded in the gate polysilicon layer to make the gate polysilicon layer contact the source metal layer.

8. The power semiconductor device according to claim 6, characterized in that, Along the first direction, the discharge path control structure includes: A fourth P-type base region, a first P-type barrier control layer, a fifth P-type base region, a second P-type barrier control layer, and a sixth P-type base region are sequentially disposed on the surface of the P+ power source electrode; wherein, the first P-type barrier control layer is sandwiched between the fourth P-type base region and the fifth P-type base region, and the second P-type barrier control layer is sandwiched between the fifth P-type base region and the sixth P-type base region; The first N+ power source, the second N+ power source, and the third N+ power source are sequentially embedded in the fourth P-type base region, the fifth P-type base region, and the sixth P-type base region; The first N+ power source, the second N+ power source, and the third N+ power source are respectively embedded in the fourth P-type base region, the fifth P-type base region, and the sixth P-type base region; Wherein, the first N+ power source serves as the first gate; the second N+ power source is floating; and the third N+ power source serves as the second gate.

9. The power semiconductor device according to claim 8, characterized in that, The discharge path control LDMOS cell also includes: A gate oxide layer is disposed on the surface of the fourth P-type base region, the first P-type barrier control layer, the fifth P-type base region, the second P-type barrier control layer, and the sixth P-type base region; wherein the gate oxide layer covers the fourth P-type base region, the first P-type barrier control layer, the fifth P-type base region, the second P-type barrier control layer, and the sixth P-type base region. A gate polysilicon layer and a sampling polysilicon layer are disposed on the surface of the gate oxide layer; wherein, the gate polysilicon layer covers the fourth gate oxide region of the gate oxide layer; the fourth gate oxide region is used to characterize the projection region of the sixth P-type base region, the second P-type barrier control layer, and the first part region on the gate oxide layer; the first part region is used to characterize the right side region of the fifth P-type base region excluding the region where the second N+ power source is located; the sampling polysilicon layer covers the fifth gate oxide region of the gate oxide layer, and the fifth gate oxide region is used to characterize the projection region of the second part region, the first P-type barrier control layer, and the third part region on the gate oxide layer; the third part region is used to characterize the left side region of the fifth P-type base region excluding the region where the second N+ power source is located; the second part region is used to characterize the right side region of the fourth P-type base region excluding the region where the first N+ power source is located; A sampling metal layer is disposed on the surface of the sampling polysilicon layer; Multiple first-type contact holes are disposed in the gate oxide layer. The first-type contact holes penetrate the gate oxide layer and contact the gate polysilicon layer and the third N+ power source, so that the third N+ power source serves as the second gate and contacts the gate of the main power VDMOS cell array. A plurality of second-type contact holes are embedded in the sampling polysilicon layer. The plurality of second-type contact holes contact the sampling polysilicon layer and the sampling metal layer respectively, so that the first N+ power source acts as the first gate and contacts the sampling signal metal to receive the real-time electrical signal of the JFET region.

10. A method for fabricating a power semiconductor device, characterized in that, The method of fabrication, applied to the power semiconductor device according to any one of claims 1 to 9, comprises: Provide a substrate; A SiC epitaxial layer is grown on the substrate; In the SiC epitaxial layer, a main power VDMOS cell array, a sampling power VDMOS cell, and at least one discharge path control LDMOS cell are fabricated; wherein, the sampling power VDMOS cell and each main cell under the main power VDMOS cell array adopt the same P-type base region arrangement structure. A top metal layer is prepared on the SiC epitaxial layer; The sampling power VDMOS cell is in contact with the JFET region within the main power VDMOS cell array through a first type of contact hole; the sampling power VDMOS cell is in contact with the sampling signal metal in the top metal layer through a second type of contact hole; the discharge path control LDMOS cell includes a first gate and a second gate; the first gate is connected to the sampling signal metal through the second type of contact hole; the second gate is in contact with the gate of the main power VDMOS cell array through the first type of contact hole; and the discharge path control LDMOS cell is also in contact with the source of the main power VDMOS cell array through a third type of contact hole, forming a low-resistance gate-source discharge path. When the power semiconductor device is in operation, the real-time electrical signal of the JFET region is obtained by the sampling power VDMOS cell. The LDMOS cells are controlled by each of the discharge paths to receive the real-time electrical signal, and when the real-time electrical signal exceeds a preset short-circuit threshold, the low-resistance discharge path is turned on to discharge the charge at the gate of the main power VDMOS cell array to the source of the main power VDMOS cell array.

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