Power transistor device
By introducing a control circuit and an inverter into the LDMOS transistor, and adjusting the field plate control voltage using different gate control voltages, the trade-off between on-resistance and breakdown voltage of the LDMOS transistor under high voltage conditions is solved, achieving a balance between low on-resistance and high breakdown voltage.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- UNITED MICROELECTRONICS CORP
- Filing Date
- 2021-08-27
- Publication Date
- 2026-06-26
AI Technical Summary
Existing LDMOS transistors struggle to simultaneously meet the requirements of low on-resistance and high breakdown voltage under high-voltage conditions, as these two characteristics often conflict.
A design incorporating LDMOS transistor elements and control circuitry is employed. By using an inverter, first and second transistors in the control circuitry, and different gate control voltages, the field plate control voltage is adjusted to optimize the on-resistance and breakdown voltage performance in different modes.
It achieves a balance between low on-resistance and high breakdown voltage under high voltage conditions, thus improving the performance of LDMOS transistors.
Smart Images
Figure CN115913215B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to a power transistor device, and more particularly to a power transistor device that can simultaneously meet the requirements of low on-resistance and high breakdown voltage when operating in a high-voltage environment. Background Technology
[0002] Double-diffused MOS (DMOS) transistors are power devices capable of handling high voltages. Common structures include vertical double-diffused MOS (VDMOS) and lateral double-diffused MOS (LDMOS) transistors. LDMOS transistors, in particular, offer high operating bandwidth and efficiency, and their planar structure facilitates integration with other integrated circuits. They are widely used in high-voltage operating environments, such as CPU power supplies, power management systems, AC / DC converters, and high-power or high-frequency power amplifiers. A key characteristic of LDMOS transistors is their large, low-doped lateral diffusion drift region, designed to mitigate the high voltage between the source and drain terminals. The doping concentration and length of this lateral diffusion drift region affect the breakdown voltage (BV) and on-resistance (R) of the LDMOS transistor. ON ).
[0003] The two main characteristics sought in LDMOS transistors are low on-resistance and high breakdown voltage, and these two requirements are often conflicting and difficult to balance. Therefore, a solution is needed that can operate normally under high voltage conditions while simultaneously meeting the requirements of low on-resistance and high breakdown voltage. Summary of the Invention
[0004] This invention provides a power transistor device comprising an LDMOS transistor element and a control circuit. The LDMOS transistor element includes a first terminal coupled to a first bias voltage, a second terminal coupled to a second bias voltage, a gate terminal coupled to a gate control voltage, and a field plate coupled to a field plate control voltage. The control circuit provides the field plate control voltage based on the gate control voltage and includes an inverter, a first transistor, and a second transistor. The inverter is used to invert the gate control voltage to generate an inverted gate control voltage; its first terminal is coupled to the gate control voltage, and its second terminal is used to output the inverted gate control voltage. The first transistor includes a first terminal coupled to a third bias voltage, a second terminal coupled to the field plate, and a control terminal coupled to the gate control voltage. The second transistor includes a first terminal coupled to the field plate, a second terminal coupled to a fourth bias voltage, and a control terminal coupled to the second terminal of the inverter to receive the inverted gate control voltage. Attached Figure Description
[0005] Figure 1 This is a schematic diagram of a power transistor device according to an embodiment of the present invention;
[0006] Figure 2 This is a schematic diagram illustrating the implementation of an LDMOS transistor element in a power transistor device according to an embodiment of the present invention;
[0007] Figure 3 This is a schematic diagram illustrating the implementation of an LDMOS transistor element in a power transistor device according to an embodiment of the present invention;
[0008] Figure 4 This is a schematic diagram illustrating the implementation of an LDMOS transistor element in a power transistor device according to an embodiment of the present invention;
[0009] Figure 5 This is a schematic diagram illustrating the implementation of an LDMOS transistor element in a power transistor device according to an embodiment of the present invention;
[0010] Figure 6 This is a schematic diagram illustrating the implementation of an LDMOS transistor element in a power transistor device according to an embodiment of the present invention.
[0011] Explanation of main component symbols
[0012] 10: LDMOS transistor device
[0013] 20: Control Circuit
[0014] 22: Inverter
[0015] 30: P-type semiconductor substrate
[0016] 32: P-type doped region
[0017] 34: N-type doped region
[0018] 36: N-type doped region
[0019] 38: Interlayer dielectric layer
[0020] 42: P-type trap
[0021] 44: N-type trap
[0022] 46: Gate dielectric layer
[0023] 48: Field Oxide Layer
[0024] 52: STI layer
[0025] 54: Contact hole etching stop layer
[0026] 100: Power transistor device
[0027] D: Leakage extreme
[0028] S: Source Extreme
[0029] G: Gate terminal
[0030] FP: Field Board
[0031] T1-T4: Transistors
[0032] V G Gate control voltage
[0033] V G ': Reverse gate control voltage
[0034] V F : Field plate control voltage
[0035] Vsupply, Vdd, GND, V F +、V F -:bias Detailed Implementation
[0036] Figure 1 This is a schematic diagram of a power transistor device 100 according to an embodiment of the present invention. The power transistor device 100 includes an LDMOS transistor element 10 and a control circuit 20. The LDMOS transistor element 10 includes a drain terminal D, a source terminal S, a gate terminal G, and a field plate FP, wherein the drain terminal D is coupled to a first bias voltage (e.g., a positive voltage Vsupply), the source terminal S is coupled to a second bias voltage (e.g., ground potential GND), and the gate terminal G is coupled to a gate control voltage V G The field plate FP is coupled to the field plate control voltage V. FTo illustrate the purpose, Figure 1 The LDMOS transistor element 10 shown is an N-type transistor, but this does not limit the scope of the present invention.
[0037] The control circuit 20 includes a first transistor T1, a second transistor T2, and an inverter 22, which can receive a gate control voltage V at an input terminal. G Then, based on the gate control voltage V G Provides the field plate control voltage V at one output terminal F The input of inverter 22 is coupled to the gate control voltage V. G It can control the gate voltage V G To perform the reverse operation, an inverting gate control voltage V is then provided at its output. G The first terminal of the first transistor T1 is coupled to a third bias voltage (e.g., a positive bias voltage V). F +), the second terminal is coupled to the field plate FP, and the control terminal is coupled to the gate control voltage V. G The first terminal of the second transistor T2 is coupled to the field plate FP, and the second terminal is coupled to a fourth bias voltage (e.g., a negative bias voltage V). F -), while the control terminal is coupled to the output terminal of inverter 22 to receive the reverse gate control voltage V. G '.
[0038] In this embodiment of the invention, the first transistor T1 has the same doping type as the second transistor T2. More specifically, when the gate control voltage V... G When the first transistor T1 and the second transistor T2 have an enable potential, the reverse gate control voltage V G 'The first transistor T1 and the second transistor T2 have a deactivation potential, therefore when the gate control voltage V G At a specific potential, one of the first transistor T1 and the second transistor T2 will be turned on, while the other transistor will be turned off. For illustrative purposes, Figure 1 The first transistor T1 and the second transistor T2 shown are N-type transistors, but this does not limit the scope of the present invention.
[0039] In one embodiment of the present invention, the inverter 22 includes a third transistor T3 and a fourth transistor T4, wherein the doping type of the third transistor T3 is different from that of the fourth transistor T4. The first terminal of the third transistor T3 is coupled to a fifth bias voltage (e.g., a positive bias voltage Vdd), and its second terminal is coupled to the control terminal of the second transistor T2, which is coupled to the gate control voltage V. G The first terminal of the fourth transistor T4 is coupled to the control terminal of the second transistor T2, its second terminal is coupled to a sixth bias voltage (e.g., ground potential GND), and its control terminal is coupled to the gate control voltage V. GTo illustrate the purpose, Figure 1 The third transistor T3 shown is a P-type transistor, while the fourth transistor T4 is an N-type transistor. However, the implementation of inverter 22 does not limit the scope of this invention.
[0040] Next Figure 1 The illustrated embodiment demonstrates the operation of the power transistor device 100 of the present invention, wherein the LDMOS transistor element 10, the first transistor T1, the second transistor T2, and the fourth transistor T4 are N-type transistors, and the third transistor T3 is a P-type transistor. When the gate control voltage V... G When the logic level is 1, the inverted gate control voltage V provided by inverter 22 G At logic 0 potential, LDMOS transistor element 10, first transistor T1, and fourth transistor T4 will be controlled by gate control voltage V. G When the transistor is turned on, the second transistor T2 will be controlled by the reverse gate control voltage V. G 'Cut off, and the third transistor T3 and the gate control voltage V' will be controlled. G Cut off. Therefore, the output of control circuit 20 will be pulled to a positive bias voltage V through the conducting first transistor T1. F The high potential of + provides a high-potential field plate control voltage V. F To the field plate FP. In this case, the LDMOS transistor 10 operates in the strong inversion region because its gate terminal G is biased to logic 1, while the field plate FP is biased to a high potential so that the diffusion drift region below it can increase the on-current value in accumulation mode and reduce the on-resistance R. ON The value of .
[0041] When the gate control voltage V G When the logic level is 0, the inverted gate control voltage V provided by inverter 22 G At a logic 1 potential, LDMOS transistor element 10, first transistor T1, and fourth transistor T4 will be controlled by the gate control voltage V. G When cut off, the second transistor T2 will be controlled by the reverse gate control voltage V. G 'Turns on, and the third transistor T3 is controlled by the gate voltage V' G The circuit is turned on. Therefore, the output of the control circuit 20 will be pulled to a negative bias voltage V through the turned-on second transistor T2. F - This provides a negatively charged field plate control voltage V. FTo the field plate FP. In this case, the LDMOS transistor 10 operates in the cut-off region because its gate terminal G is biased to logic 0, while the field plate FP is biased to a negative potential so that the diffusion drift region below it can increase the on-resistance R in depletion mode. ON And the value of the breakdown voltage, thereby ensuring that the current flowing through the diffusion drift region is 0.
[0042] Figure 2 This is a schematic diagram illustrating the implementation of an LDMOS transistor element 10 in a power transistor device 100 according to an embodiment of the present invention. The LDMOS transistor element 10 includes a P-type doped region 32, an N-type doped region 34, an N-type doped region 36, an interlayer dielectric (ILD) 38, a P-type well 42, and an N-type well 44, and is disposed on a P-type semiconductor substrate 30. The source terminal S is disposed on the P-type doped region 32 and the N-type doped region 34 formed above the P-type well 42, the drain terminal D is disposed on the N-type doped region 36 formed above the N-type well 44, and the gate terminal G and the field plate FP are disposed between the source terminal S and the drain terminal D. The interlayer dielectric 38 is formed on the P-type semiconductor substrate 30. In this embodiment of the invention, the field plate FP may be formed on the interlayer dielectric 38.
[0043] Figure 3 This is a schematic diagram illustrating the implementation of an LDMOS transistor element 10 in a power transistor device 100 according to an embodiment of the present invention. The LDMOS transistor element 10 includes a P-type doped region 32, an N-type doped region 34, an N-type doped region 36, a P-type well 42, an N-type well 44, and a gate dielectric layer 46, disposed on a P-type semiconductor substrate 30. The source terminal S is disposed on the P-type doped region 32 and the N-type doped region 34 formed above the P-type well 42, the drain terminal D is disposed on the N-type doped region 36 formed above the N-type well 44, and the gate terminal G and the field plate FP are disposed between the source terminal S and the drain terminal D. The gate dielectric layer 46 is formed on the P-type semiconductor substrate 30. In this embodiment of the present invention, the field plate FP may be formed on the gate dielectric layer 46.
[0044] Figure 4This is a schematic diagram illustrating the implementation of an LDMOS transistor element 10 in a power transistor device 100 according to an embodiment of the present invention. The LDMOS transistor element 10 includes a P-type doped region 32, an N-type doped region 34, an N-type doped region 36, a P-type well 42, an N-type well 44, a gate dielectric layer 46, and a field oxide layer 48, disposed on a P-type semiconductor substrate 30. The source terminal S is disposed on the P-type doped region 32 and the N-type doped region 34 formed above the P-type well 42, the drain terminal D is disposed on the N-type doped region 36 formed above the N-type well 44, and the gate terminal G and the field plate FP are disposed between the source terminal S and the drain terminal D. The gate dielectric layer 46 is formed between the gate terminal G and the P-type semiconductor substrate 30. The field oxide layer 48 is an isolation structure in the LDMOS transistor element 10 and can be formed by local oxidation of silicon (LOCOS). In this embodiment of the present invention, the field plate FP can be formed on the field oxide layer 48.
[0045] Figure 5 This is a schematic diagram illustrating the implementation of an LDMOS transistor element 10 in a power transistor device 100 according to an embodiment of the present invention. The LDMOS transistor element 10 includes a P-type doped region 32, an N-type doped region 34, an N-type doped region 36, an interlayer dielectric layer 38, a P-type well 42, an N-type well 44, and a shallow trench isolation (STI) layer 52, disposed on a P-type semiconductor substrate 30. The source terminal S is disposed on the P-type doped region 32 and the N-type doped region 34 formed above the P-type well 42, the drain terminal D is disposed on the N-type doped region 36 formed above the N-type well 44, and the gate terminal G and the field plate FP are disposed between the source terminal S and the drain terminal D. The STI layer 52 is the isolation structure in the LDMOS transistor element 10. In this embodiment of the invention, the field plate FP may be formed on the STI layer 52.
[0046] Figure 6This is a schematic diagram illustrating the implementation of an LDMOS transistor element 10 in a power transistor device 100 according to an embodiment of the present invention. The LDMOS transistor element 10 includes a P-type doped region 32, an N-type doped region 34, an N-type doped region 36, a P-type well 42, an N-type well 44, and a contact etch stop layer (CESL) 54, disposed on a P-type semiconductor substrate 30. The source terminal S is disposed on the P-type doped region 32 and the N-type doped region 34 formed above the P-type well 42, the drain terminal D is disposed on the N-type doped region 36 formed above the N-type well 44, and the gate terminal G and the field plate FP are disposed between the source terminal S and the drain terminal D. The contact etch stop layer 54 is formed on the P-type semiconductor substrate 30. In this embodiment of the invention, the field plate FP may be formed on the contact etch stop layer 54.
[0047] Figures 2 to 6 The example described uses an N-type diffusion drift region, but does not limit the scope of the invention. For instance, in an embodiment where the LDMOS transistor element 10 is a P-type transistor, reference numeral 32 may correspond to an N-type doped region, reference numeral 34 may correspond to a P-type doped region, reference numeral 36 may correspond to a P-type doped region, reference numeral 42 may correspond to an N-type well, reference numeral 44 may correspond to a P-type well 44, and reference numeral 30 may correspond to an N-type semiconductor substrate.
[0048] In summary, the power transistor device of the present invention includes an LDMOS transistor element and a control circuit, wherein the LDMOS transistor element includes a drain terminal, a source terminal, a gate terminal, and a field plate. The field plate control voltage applied to the field plate by the control circuit is related to the gate control voltage applied to the gate terminal: when the LDMOS transistor element operates in the strong inversion region in response to the gate control voltage with an enable potential, the field plate control voltage applied to the field plate can increase the conduction current in the diffusion drift region and reduce the on-resistance; when the LDMOS transistor element operates in the cutoff region in response to the gate control voltage with an disable potential, the field plate control voltage applied to the field plate can increase the on-resistance and breakdown voltage. Therefore, the power transistor device of the present invention can simultaneously meet the requirements of low on-resistance and high breakdown voltage when operating in a high-voltage environment.
[0049] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention should be included within the scope of the present invention.
Claims
1. A power transistor device comprising: Laterally double-diffused metal-oxide-semiconductor (LDMOS) transistor devices, comprising: The first terminal is coupled to the first bias voltage; The second terminal is coupled to the second bias voltage; The gate terminal is coupled to the gate control voltage; as well as The field plate is coupled to the field plate control voltage; as well as The control circuit provides the field plate control voltage based on the gate control voltage, and includes an inverter, a first transistor, and a second transistor, wherein: The inverter is used to reverse the gate control voltage to generate an inverted gate control voltage. The inverter includes: The first terminal is coupled to the gate control voltage; and The second terminal is used to output the reverse gate control voltage. The first transistor includes: The first terminal is coupled to the third bias voltage; The second end is coupled to the field plate; and The control terminal is coupled to the gate control voltage; The second transistor includes: The first end is coupled to the field plate; The second terminal is coupled to the fourth bias voltage; and The control terminal is coupled to the second terminal of the inverter to receive the reverse gate control voltage.
2. The power transistor device of claim 1, wherein the doping type of the first transistor and the doping type of the second transistor are the same.
3. The power transistor device of claim 1, wherein the inverter comprises: The third transistor includes: The first terminal is coupled to the fifth bias voltage; The second terminal is coupled to the control terminal of the second transistor; and The control terminal is coupled to the gate control voltage; The fourth transistor includes: The first terminal is coupled to the control terminal of the second transistor; The second terminal is coupled to the sixth bias voltage; as well as The control terminal is coupled to the gate control voltage.
4. The power transistor device of claim 3, wherein the doping type of the third transistor is different from that of the fourth transistor.
5. The power transistor device of claim 1, wherein the field plate is formed between the first end and the second end of the LDMOS transistor element.
6. The power transistor device of claim 5, further comprising a contact etchstop layer (CESL), wherein the field plate is formed on the contact etchstop layer.
7. The power transistor device of claim 5, further comprising a gate dielectric layer, wherein the field plate and the gate terminal are formed on the gate dielectric layer.
8. The power transistor device of claim 5, further comprising a field oxide layer formed between the first end and the second end of the LDMOS transistor element, wherein the field plate is formed on the field oxide layer.
9. The power transistor device of claim 5, further comprising a shallow trench isolation structure formed between the first end and the second end of the LDMOS transistor element, wherein the field plate is formed on the STI structure.
10. The power transistor device of claim 5, further comprising an interlayer dielectric (ILD), wherein the field plate is formed on the interlayer dielectric.
11. The power transistor device of claim 1, wherein: When the LDMOS transistor is turned on by the gate control voltage with an enable potential, the control circuit outputs the third bias voltage as the field plate control voltage; and When the LDMOS transistor element is turned off by the gate control voltage with a deactivation potential, the control circuit is used to output the fourth bias voltage as the field plate control voltage.