SOI-LDMOS device and manufacturing method thereof

Abstract

This application relates to the field of semiconductor integrated circuit manufacturing technology, specifically to an SOI-LDMOS device and its fabrication method. The SOI-LDMOS device includes: a substrate layer, a buried oxide layer, and an epitaxial layer stacked sequentially from bottom to top; a drift region is formed in the epitaxial layer; a source region and a drain region are formed on both sides of the drift region; a doped polysilicon field plate is formed on the drift region, and a vertical heterojunction is formed between the doped polysilicon field plate and the drift region. When the device is in the off state, the vertical heterojunction is depleted; one end of the doped polysilicon field plate contacts and overlaps with the source region to form a vertical homojunction; the other end of the doped polysilicon field plate is doped with a first conductivity type impurity to form a first conductivity type doped region; the main body of the doped polysilicon field plate forms a lateral heterojunction with the first conductivity type doped region; the doped polysilicon field plate contacts the metal electrode of the drain region through the heterojunction. The fabrication method is used to fabricate the above-mentioned SOI-LDMOS device.

Description

Technical Field

[0001] This application relates to the field of semiconductor integrated circuit manufacturing technology, specifically to an SOI-LDMOS device and its fabrication method. Background Technology

[0002] Lateral double-diffused metal-oxide-semiconductor field-effect transistors (LDMOS), as lateral power devices, are widely used in power integrated circuits due to their advantages such as high voltage withstand capability, high gain, and low distortion. The high voltage and high current characteristics of power integrated circuits often require LDMOS devices to have high breakdown voltage (BV) and low specific on-resistance (Ron,sp). However, BV and Ron,sp are contradictory values; an increase in BV is often accompanied by an increase in Ron,sp.

[0003] Silicon on Insulator (SOI) is a fully dielectric isolation technology where the semiconductor device is fabricated within a top layer of silicon, with a buried oxide layer forming between the top silicon and the substrate silicon as an isolation layer, completely eliminating electrical connections between the parts. This structural feature eliminates the latch-up effect of traditional bulk silicon technology, bringing advantages such as low parasitic capacitance, high speed, low power consumption, and high integration density to SOI.

[0004] In related technologies, a field oxide layer is formed on the top silicon drift region located between the source and drain to act as a field plate. This weakens the surface electric field of the drift region, which helps to improve the device's breakdown voltage. However, the device's breakdown voltage is very sensitive to the thickness and quality of the field oxide layer. If there are differences in the thickness and quality of the field oxide layer, the device's breakdown voltage cannot be improved, making it impossible to control and guarantee the device's breakdown voltage in large-scale production. Summary of the Invention

[0005] This application provides an SOI-LDMOS device and its fabrication method, which can solve the problem in related technologies where the use of oxide layers as field plates makes it impossible to mass-produce and control the device's withstand voltage.

[0006] In order to solve the technical problems described in the background art, the first aspect of this application provides an SOI-LDMOS device, the SOI-LDMOS device comprising: a substrate layer, a buried oxide layer and an epitaxial layer stacked sequentially from bottom to top, wherein a drift region is formed in the epitaxial layer;

[0007] The drift region forms a source region and a drain region on both sides;

[0008] A doped polysilicon field electrode is formed on the drift region, and a vertical irregular junction is formed between the doped polysilicon field electrode and the drift region. When the device is in the off state, the vertical irregular junction is depleted.

[0009] One end of the doped polycrystalline silicon field electrode plate is in contact with and overlaps with the source region to form a longitudinal isomorphic junction;

[0010] The other end of the doped polycrystalline silicon field electrode is doped with a first type of conductivity impurity to form a first type of conductivity doped region. The main body of the doped polycrystalline silicon field electrode forms a lateral irregular junction with the first type of conductivity doped region. The doped polycrystalline silicon field electrode is in contact with the metal electrode of the drain region through the irregular junction.

[0011] Optionally, the lateral width of the first conductivity type doped region is 9 μm.

[0012] Optionally, the thickness of the doped polycrystalline silicon field plate is 1800 angstroms.

[0013] Optionally, the doping concentration of the main body of the doped polycrystalline silicon field plate decreases linearly from one end to the other.

[0014] One end of the doped polycrystalline silicon field electrode is the end of the doped polycrystalline silicon field electrode that is closer to the source region;

[0015] The other end of the doped polycrystalline silicon field plate is the end of the doped polycrystalline silicon field plate that is closer to the drain region.

[0016] Optionally, a trench gate structure is also formed in the epitaxial layer. The trench gate structure is located on the source region side away from the drain region, and the trench gate structure extends downward from the upper surface of the epitaxial layer to contact the buried oxide layer.

[0017] To address the technical problems described in the background section, a second aspect of this application provides a method for fabricating an SOI-LDMOS device, the method comprising the following steps:

[0018] It provides a substrate layer, a buried oxide layer, and an epitaxial layer stacked sequentially from bottom to top;

[0019] A first type of conductivity impurity is injected into the epitaxial layer to form a drift region;

[0020] A second type of conductivity impurity is injected into one side of the drift region to form a source region;

[0021] A polysilicon layer is deposited on the drift region such that one end of the polysilicon layer overlaps with the source region.

[0022] A second type of conductivity impurity is doped into the polycrystalline silicon layer to form a doped polycrystalline silicon field plate, such that the concentration of the second type of conductivity impurity in the doped polycrystalline silicon field plate decreases linearly from one end of the doped polycrystalline silicon field plate to the other end.

[0023] A first type of conductivity impurity is injected into the other end of the doped polysilicon field electrode and the other side of the drift region, so that a first type of conductivity doped region is formed at the other end of the doped polysilicon field electrode and a drain region is formed on the other side of the drift region.

[0024] A metal layer is fabricated such that the metal electrode of the drain region is in contact with the doped region of the first conductivity type.

[0025] Optionally, the step of doping the polycrystalline silicon layer with a second type of impurity to form a doped polycrystalline silicon field plate, such that the concentration of the second type of impurity in the doped polycrystalline silicon field plate decreases linearly from one end of the doped polycrystalline silicon field plate to the other end, includes:

[0026] Multiple impurity injection windows are defined on the polysilicon layer by a photoresist layer, and the lateral width of the impurity injection windows decreases linearly from one end of the polysilicon layer to the other.

[0027] According to the impurity injection windows in descending order of size, second conductivity type impurities with linearly decreasing impurity concentrations are injected into each of the impurity injection windows.

[0028] After rapid thermal annealing, the second type of impurities in the polycrystalline silicon layer diffuse, forming a doped polycrystalline silicon field plate with an impurity concentration that decreases linearly from one end to the other.

[0029] Optionally, in the step of doping the polycrystalline silicon layer with a second type of impurity to form a doped polycrystalline silicon field plate, such that the concentration of the second type of impurity in the doped polycrystalline silicon field plate decreases linearly from one end of the doped polycrystalline silicon field plate to the other end, the thickness of the doped polycrystalline silicon field plate is 1800 angstroms.

[0030] Optionally, in the step of injecting a first conductivity type impurity into the other end of the doped polysilicon field electrode and the other side of the drift region, such that a first conductivity type doped region is formed at the other end of the doped polysilicon field electrode and a drain region is formed on the other side of the drift region, the lateral width of the first conductivity type doped region is 9 μm.

[0031] The technical solution of this application includes at least the following advantages: The vertically shaped junction formed on the drift region enables charge compensation in the vertical direction, allowing for a higher doping concentration in the drift region. This, in turn, reduces the on-resistance of the device, alleviating the conflict between breakdown voltage and on-resistance to some extent. The vertically shaped junction avoids the formation of strong electric field points on the overlapping portion, significantly improving the reliability of the device. The laterally shaped junction ensures that the doped polysilicon field plate can withstand the high voltage applied to the drain region. Attached Figure Description

[0032] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0033] Figure 1 This paper shows a partial cross-sectional view of an SOI-LDMOS device provided in an embodiment of this application;

[0034] Figure 2 A flowchart illustrating a method for fabricating an SOI-LDMOS device according to an embodiment of this application is shown;

[0035] Figure 2a A partial cross-sectional view of the device after step S3 is shown;

[0036] Figure 2b A schematic diagram of the cross-sectional structure of the device after step S4 is shown;

[0037] Figure 2c A schematic diagram of the cross-sectional structure of the device after step S5 is shown;

[0038] Figure 2d A schematic diagram of the cross-sectional structure of the device after step S6 is shown;

[0039] Figure 3a A schematic diagram of the cross-sectional structure of the device after step S51 is shown;

[0040] Figure 3b The graph shows the relationship between the size of the impurity injection window and the change in impurity injection concentration. Detailed Implementation

[0041] The technical solutions of this application will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0042] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0043] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal connection of two components; and they can refer to a wireless connection or a wired connection. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0044] Furthermore, the technical features involved in the different embodiments of this application described below can be combined with each other as long as they do not conflict with each other.

[0045] The conductivity type of the semiconductor region in this application includes an opposite first conductivity type and a second conductivity type, that is, when the first conductivity type is N-type, the second conductivity type is P-type; when the first conductivity type is P-type, the second conductivity type is N-type.

[0046] N-type and P-type semiconductors are produced by doping semiconductors with different types of impurities. Doping a semiconductor with an element from Group V of the periodic table, such as arsenic or antimony, as a donor impurity, yields an N-type semiconductor. Doping a semiconductor with an element from Group III of the periodic table, such as boron or indium, as an acceptor impurity, yields a P-type semiconductor.

[0047] The conductivity of N-type semiconductors and P-type semiconductors is different.

[0048] Figure 1A partial cross-sectional view of an SOI-LDMOS device provided in an embodiment of this application is shown. The structure of the SOI-LDMOS device is described below using an example where the first conductivity type is N-type and the second conductivity type is P-type.

[0049] from Figure 1 As can be seen from the diagram, the SOI-LDMOS device in this embodiment includes a substrate layer 101, a buried oxide layer 102, and an epitaxial layer stacked sequentially from bottom to top. A drift region 103 is formed in the epitaxial layer, and the conductivity type of the drift region 103 is N-type. A source region 105 is formed on one side of the drift region 103, and a drain region 106 is formed on the other side.

[0050] A doped polysilicon field electrode 104 of P-type conductivity is formed on the drift region 103. A vertically oriented junction is formed between the doped polysilicon field electrode 104 and the drift region 103. This vertically oriented junction is depleted when the device is in the off state. This vertically oriented junction is a semiconductor contact junction with opposite conductivity types in the vertical direction. In this embodiment, the PN junction formed by the drift region 103 with different conductivity types contacting the doped polysilicon field electrode 104 is oriented as follows: Figure 1 The vertical direction is shown. When a high voltage is applied to the drain region 106 and the source and gate regions are grounded, the device is in the off state. A depletion region is formed between the P-type doped polysilicon field plate 104 and the N-type drift region 103. When the P-type doped polysilicon field plate 104 is depleted, it can perform charge compensation on the N-type drift region 103 in the vertical direction, thereby allowing the drift region 103 to have a higher doping concentration, which in turn reduces the on-resistance of the device and alleviates the contradiction between breakdown voltage and on-resistance to a certain extent.

[0051] The thickness of the doped polysilicon field electrode 104 is 1800 angstroms, and the doped polysilicon field electrode 104 is completely depleted when the device is off.

[0052] Continue to refer to Figure 1 One end of the doped polysilicon field electrode 104 overlaps with the source region 105 to form a vertically homojunction. The vertically homojunction is a semiconductor contact junction with the same conductivity type in the vertical direction. In this embodiment, the P-type doped polysilicon field electrode 104 overlaps with the P-type well region 115 of the source region 105 to form a vertical PP junction. This vertical PP junction does not trap charge, avoiding the formation of strong electric field points on the overlapping portion, thus significantly improving the reliability of the device.

[0053] The other end of the doped polysilicon field plate 104 forms a lateral junction, through which the doped polysilicon field plate 104 contacts the metal electrode 108 of the drain region 106. This lateral junction is a semiconductor contact junction with opposite conductivity types in the lateral direction. In this embodiment, an N-type impurity with the opposite conductivity type to the main body of the doped polysilicon field plate 104 is doped at the other end, forming an N-type doped region 107. After the N-type impurity is doped at the other end of the doped polysilicon field plate 104, the N-type doped region 107 forms a lateral PN junction with the main body of the doped polysilicon field plate 104. The main body of the doped polysilicon field plate 104 contacts the metal electrode 108 of the drain region 106 through this lateral PN junction. This lateral PN junction ensures that the doped polysilicon field plate 104 can withstand the high voltage applied to the drain region 106.

[0054] It should be noted that the part of the doped polycrystalline silicon field electrode 104 other than the N-type doped region 107 located at the other end is the main body of the doped polycrystalline silicon field electrode 104.

[0055] In this embodiment, the lateral width of the N-type doped region 107 is 9 μm. The width of the N-type doped region 107 is related to the high voltage withstand capability of the doped polycrystalline silicon electrode 104. The longer the width of the N-type doped region 107, the higher the voltage withstand capability of the doped polycrystalline silicon electrode 104.

[0056] In this embodiment, the doping concentration of the main body of the doped polysilicon field plate 104 decreases linearly from one end to the other. One end of the doped polysilicon field plate 104 is the end closest to the source region 105; the other end is the end closest to the drain region 106.

[0057] Because the doping concentration of the main body of the doped polysilicon field electrode 104 decreases linearly from one end to the other, the potential distribution of the field electrode tends to change linearly and uniformly in the lateral direction. This makes the surface electric field of the drift region 103 modulated uniformly in the lateral direction, avoiding the problem of uneven lateral potential distribution and strong surface electric field points, and reliably improving the withstand voltage of the device.

[0058] Continue to refer to Figure 1 The epitaxial layer also has a trench gate structure 109, which is located on the side of the source region 105 away from the drain region 106. The trench gate structure 109 extends downward from the upper surface of the epitaxial layer to contact the buried oxide layer 102.

[0059] Figure 2This application illustrates a flowchart of a method for fabricating an SOI-LDMOS device according to an embodiment of the present application. This method for fabricating an SOI-LDMOS device can produce… Figure 1 The SOI-LDMOS device shown in the embodiment.

[0060] from Figure 2 As can be seen from this, the fabrication method of this SOI-LDMOS device includes the following steps S1 to S7 performed sequentially, wherein:

[0061] Step S1: Provide a substrate layer, a buried oxide layer, and an epitaxial layer stacked sequentially from bottom to top.

[0062] Step S2: Inject N-type impurities into the epitaxial layer to form a drift region.

[0063] Step S3: Inject P-type impurities into one side of the drift region to form a source region.

[0064] Reference Figure 2a It shows a partial cross-sectional view of the device after step S3 is completed, from Figure 2a As can be seen, the substrate layer 101, the buried oxide layer 102, and the epitaxial layer are stacked sequentially from bottom to top. A drift region 103 is formed in the epitaxial layer, and a source region 105 is formed on one side of the drift region 103. The source region 105 extends downward from the upper surface of the epitaxial layer to a certain depth.

[0065] Step S4: Deposit a polysilicon layer on the drift region such that one end of the polysilicon layer contacts and overlaps with the source region.

[0066] Reference Figure 2b It shows a schematic cross-sectional view of the device after step S4 is completed, from Figure 2b As can be seen, one end of the polycrystalline silicon layer 114 is in contact with and overlaps with the source region 105.

[0067] The polysilicon layer 114 located on the drift region 103 can be deposited in the same process step as the filled polysilicon 119 in the trench gate structure 109, and then formed by photolithography etching.

[0068] For example, after completing step S3 and before proceeding to step S4, a gate trench can be etched in the epitaxial layer to form a gate trench located on the source region side away from the drain region. The gate trench extends downward from the upper surface of the epitaxial layer to contact the buried oxide layer. Then, a gate oxide layer is deposited in the gate trench. Next, polysilicon is deposited, filling the gate trench and covering the drift region. Finally, the polysilicon is etched to form a gate oxide layer. Figure 2b The trench gate structure 109 shown is a polysilicon layer 114 located on the drift region 103. The trench gate structure 109 forms a filled polysilicon layer 119.

[0069] Step S5: P-type impurities are doped into the polycrystalline silicon layer to form a doped polycrystalline silicon field plate, such that the concentration of P-type impurities in the doped polycrystalline silicon field plate decreases linearly from one end of the doped polycrystalline silicon field plate to the other end.

[0070] Wherein, one end of the doped polysilicon field electrode is the end of the doped polysilicon field electrode that is close to the source region 105; the other end of the doped polysilicon field electrode is the end of the doped polysilicon field electrode that is close to the drain region.

[0071] Reference Figure 2c It shows a schematic cross-sectional view of the device after step S5 is completed, from Figure 2c As can be seen, the higher the concentration of P-type impurities in the doped polycrystalline silicon field plate closer to the source region 105, the lower the concentration of P-type impurities in the doped polycrystalline silicon field plate farther away from the source region 105.

[0072] Optionally, a doped polycrystalline silicon field plate can be formed by the following steps S51 to S53, wherein the P-type impurity concentration decreases linearly from one end to the other.

[0073] Step S51: Multiple impurity injection windows are defined on the polysilicon layer by a photoresist layer, and the lateral width of the impurity injection windows decreases linearly from one end of the polysilicon layer to the other end.

[0074] Reference Figure 3a It shows a schematic cross-sectional view of the device after step S51 is completed. Figure 3a As can be seen, on the polysilicon layer 114, the photoresist layer 110 defines multiple impurity implantation windows, such as the first impurity implantation window 111, the second impurity implantation window 112, ... the nth impurity implantation window 113, etc. The first impurity implantation window 111 is closest to the source region 105 and has the largest lateral width. The nth impurity implantation window 113 is closest to the drain region 106 (i.e., furthest from the source region 105) and has the smallest lateral width. From the first impurity implantation window 111 to the nth impurity implantation window 113, the lateral width of the impurity implantation window gradually decreases linearly.

[0075] Step S52: Inject type P impurities with linearly decreasing impurity concentrations into each impurity injection window in descending order of impurity injection window concentration.

[0076] Reference Figure 3b It shows a graph illustrating the relationship between the size of the impurity injection window and the change in impurity injection concentration. Figure 3bAs can be seen, the first impurity injection window 111, which has the largest horizontal width, has the largest impurity injection concentration, while the nth impurity injection window 113, which has the smallest horizontal width, has the smallest impurity injection concentration. From the first impurity injection window 111 to the nth impurity injection window 113, the impurity concentration injected into each impurity injection window gradually decreases linearly.

[0077] Step S53: After rapid thermal annealing, the second type of impurities in the polycrystalline silicon layer diffuse, forming a doped polycrystalline silicon field plate with the impurity concentration decreasing linearly from one end to the other.

[0078] In particular, the rapid thermal annealing in step S53 enables the impurities injected in each impurity injection window in step S52 to diffuse and merge laterally, avoiding the situation of impurity concentration abrupt change, so that the P-type impurity concentration of the formed doped polycrystalline silicon field plate decreases linearly and slowly from one end to the other.

[0079] Step S6: Inject a first type of conductivity impurity into the other end of the doped polysilicon field plate and the other side of the drift region, so that a first type of conductivity doped region is formed at the other end of the doped polysilicon field plate and a drain region is formed on the other side of the drift region.

[0080] Reference Figure 2d It shows a schematic cross-sectional view of the device after step S6 is completed, from Figure 2d As can be seen, a drain region 106 is formed on the other side of the drift region 103 away from the source region 105, and an N-type doped region 107 is formed on the other end of the doped polysilicon field plate 104 near the drain region 106. The N-type doped region 107 and the main body of the doped polysilicon field plate 104 form a lateral PN junction.

[0081] Step S7: Fabricate a metal electrode layer such that the metal electrode of the drain region is in contact with the first conductivity type doped region.

[0082] After step S7 is completed, the main body of the doped polysilicon field plate 104 is in contact with the metal electrode 108 of the drain region 106 through the lateral PN junction. The lateral PN junction can ensure that the doped polysilicon field plate 104 can withstand the high voltage applied by the drain region 106.

[0083] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this application.

Claims

1. An SOI-LDMOS device, characterized in that, The SOI-LDMOS device includes a substrate layer, a buried oxide layer, and an epitaxial layer stacked sequentially from bottom to top, wherein a drift region is formed in the epitaxial layer; The drift region forms a source region and a drain region on both sides; A doped polysilicon field electrode is formed on the drift region, and a vertical irregular junction is formed between the doped polysilicon field electrode and the drift region. When the device is in the off state, the vertical irregular junction is depleted. One end of the doped polycrystalline silicon field electrode plate is in contact with and overlaps with the source region to form a longitudinal isomorphic junction; The other end of the doped polycrystalline silicon field electrode is doped with a first type of conductivity impurity to form a first type of conductivity doped region. The main body of the doped polycrystalline silicon field electrode forms a lateral irregular junction with the first type of conductivity doped region. The doped polycrystalline silicon field electrode is in contact with the metal electrode of the drain region through the irregular junction.

2. The SOI-LDMOS device as described in claim 1, characterized in that, The lateral width of the first conductivity type doped region is 9 μm.

3. The SOI-LDMOS device as described in claim 1, characterized in that, The thickness of the doped polycrystalline silicon field plate is 1800 angstroms.

4. The SOI-LDMOS device as described in claim 1, characterized in that, The doping concentration of the main body of the doped polycrystalline silicon field plate decreases linearly from one end to the other. One end of the doped polycrystalline silicon field electrode is the end of the doped polycrystalline silicon field electrode that is closer to the source region; The other end of the doped polycrystalline silicon field plate is the end of the doped polycrystalline silicon field plate that is closer to the drain region.

5. The SOI-LDMOS device as described in claim 1, characterized in that, A trench gate structure is also formed in the epitaxial layer. The trench gate structure is located on the source region side away from the drain region. The trench gate structure extends downward from the upper surface of the epitaxial layer to contact the buried oxide layer.

6. A method for fabricating an SOI-LDMOS device, characterized in that, The fabrication method of the SOI-LDMOS device includes the following steps: It provides a substrate layer, a buried oxide layer, and an epitaxial layer stacked sequentially from bottom to top; A first type of conductivity impurity is injected into the epitaxial layer to form a drift region; A second type of conductivity impurity is injected into one side of the drift region to form a source region; A polysilicon layer is deposited on the drift region such that one end of the polysilicon layer overlaps with the source region. A second type of conductivity impurity is doped into the polycrystalline silicon layer to form a doped polycrystalline silicon field plate, such that the concentration of the second type of conductivity impurity in the doped polycrystalline silicon field plate decreases linearly from one end to the other. One end of the doped polycrystalline silicon field plate is the end closest to the source region; the other end is the end closest to the drain region. A first type of conductivity impurity is injected into the other end of the doped polysilicon field electrode and the other side of the drift region, so that a first type of conductivity doped region is formed at the other end of the doped polysilicon field electrode and a drain region is formed on the other side of the drift region. A metal layer is fabricated such that the metal electrode of the drain region is in contact with the doped region of the first conductivity type.

7. The method for fabricating an SOI-LDMOS device as described in claim 6, characterized in that, The step of doping the polycrystalline silicon layer with a second type of impurity to form a doped polycrystalline silicon field plate, such that the concentration of the second type of impurity in the doped polycrystalline silicon field plate decreases linearly from one end of the doped polycrystalline silicon field plate to the other end, includes: Multiple impurity injection windows are defined on the polysilicon layer by a photoresist layer, and the lateral width of the impurity injection windows decreases linearly from one end of the polysilicon layer to the other. According to the impurity injection windows in descending order of size, second conductivity type impurities with linearly decreasing impurity concentrations are injected into each of the impurity injection windows. After rapid thermal annealing, the second type of impurities in the polycrystalline silicon layer diffuse, forming a doped polycrystalline silicon field plate with an impurity concentration that decreases linearly from one end to the other.

8. The method for fabricating an SOI-LDMOS device as described in claim 6, characterized in that, In the step of doping the polycrystalline silicon layer with a second type of impurity to form a doped polycrystalline silicon field plate, such that the concentration of the second type of impurity in the doped polycrystalline silicon field plate decreases linearly from one end of the doped polycrystalline silicon field plate to the other end, the thickness of the doped polycrystalline silicon field plate is 1800 angstroms.

9. The method for fabricating an SOI-LDMOS device as described in claim 6, characterized in that, In the step of injecting a first type of conductivity impurity into the other end of the doped polysilicon field electrode and the other side of the drift region, so that a first type of conductivity doped region is formed at the other end of the doped polysilicon field electrode and a drain region is formed on the other side of the drift region, the lateral width of the first type of conductivity doped region is 9 μm.

Images