Semiconductor device

Abstract

The present disclosure provides a semiconductor device including a P-type substrate, an N-type buried layer disposed on the P-type substrate, and an LDMOS device disposed on the N-type buried layer. The LDMOS device includes an N-type source contact region and a P-type body contact region contiguous with the N-type source contact region, a source electrode disposed on the N-type source contact region and the P-type body contact region, an N-type drain contact region, a drain electrode disposed on the N-type drain contact region, a gate dielectric extending from an upper surface of the N-type source contact region to an upper surface of the N-type drain contact region and contiguous with the drain electrode, a semiconductor layer disposed on the gate dielectric, an edge of the semiconductor layer aligned with an edge of the gate dielectric, the semiconductor layer including a gate contact region formed on a side proximate to the source electrode, and a gate electrode disposed on the gate contact region, the semiconductor layer having an open region exposing the gate dielectric. The semiconductor device according to the present disclosure has the advantages of high breakdown voltage, low specific on-resistance, and high switching speed.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more specifically, to a semiconductor device including a novel laterally diffused metal-oxide-semiconductor (LDMOS) device. Background Technology

[0002] In recent years, LDMOS devices have been widely used in power integrated circuits due to their advantages such as easy compatibility with complementary metal-oxide-semiconductor (CMOS) processes, low drive power, and negative temperature coefficient.

[0003] However, a trade-off exists between breakdown voltage and specific on-resistance, which are important metrics for evaluating the performance of LDMOS devices. Specifically, a higher breakdown voltage requires a longer drift region length and a lower drift region doping concentration, which in turn results in a higher specific on-resistance for the LDMOS device.

[0004] Therefore, improvements are still needed to existing LDMOS devices to reduce their specific on-resistance while maintaining high breakdown voltage. Summary of the Invention

[0005] The information disclosed above in the "Background Art" section is only for understanding the background of the inventive concept and may therefore contain information that does not constitute prior art.

[0006] To address the aforementioned problems in the prior art, this disclosure proposes a semiconductor device including a novel laterally diffused metal-oxide-semiconductor (LDMOS) device.

[0007] According to one aspect of this disclosure, a semiconductor device is provided, which may include: a P-type substrate; an N-type buried layer disposed on the P-type substrate; and a laterally diffused metal-oxide-semiconductor (LDMOS) device disposed on the N-type buried layer, wherein the LDMOS device may include: an N-type source contact region and a P-type body contact region adjacent to the N-type source contact region; a source electrode disposed on the N-type source contact region and the P-type body contact region; an N-type drain contact region; a drain electrode disposed on the N-type drain contact region; a gate dielectric extending from the upper surface of the N-type source contact region to the upper surface of the N-type drain contact region and adjacent to the drain electrode; a semiconductor layer disposed on the gate dielectric, the edge of the semiconductor layer being aligned with the edge of the gate dielectric, the semiconductor layer including a gate contact region formed on the side near the source electrode; and a gate electrode disposed on the gate contact region, wherein the semiconductor layer has an opening region that exposes the gate dielectric.

[0008] According to embodiments of this disclosure, the opening region may have one opening or multiple openings parallel to each other.

[0009] According to embodiments of the present disclosure, from the gate contact region to the drain electrode, the semiconductor layer may sequentially have: a gate-side ohmic contact region formed by heavy doping with P-type impurities; a high-resistivity region formed by light doping with P-type impurities; a field-stop region formed by heavy doping with N-type impurities; and a drain-side ohmic contact region formed by heavy doping with P-type impurities, wherein an opening region is disposed in the high-resistivity region.

[0010] According to embodiments of the present disclosure, the opening region in the semiconductor layer can be configured to have a plurality of openings arranged in a grid.

[0011] According to embodiments of the present disclosure, the semiconductor device may further include: a deep N-type well disposed on an N-type buried layer and adjacent to an LDMOS device; and an N-type well disposed on a deep N-type well and adjacent to an LDMOS device, wherein the N-type well, the deep N-type well, and the N-type buried layer surround the LDMOS device.

[0012] According to embodiments of this disclosure, an N-type ohmic contact region and an isolation electrode disposed on the N-type ohmic contact region can be provided in the N-type well, and the isolation electrode can be connected to a high power supply voltage.

[0013] According to embodiments of the present disclosure, the LDMOS device may further include: a P-type epitaxial layer disposed on an N-type buried layer; a high-voltage P-type well disposed on the N-type buried layer and adjacent to the P-type epitaxial layer; a P-type well disposed on the P-type epitaxial layer, wherein an N-type source contact region and a P-type body contact region are disposed in the P-type well; and a high-voltage N-type well disposed on and adjacent to the high-voltage P-type well, wherein an N-type drain contact region is disposed in the high-voltage N-type well, and wherein the P-type well, the P-type epitaxial layer, and the high-voltage P-type well surround the high-voltage N-type well.

[0014] According to embodiments of this disclosure, the interface between the P-type well and the high-voltage N-type well can be aligned with the interface between the P-type epitaxial layer and the high-voltage P-type well.

[0015] According to embodiments of this disclosure, the gate dielectric can be formed of silicon oxide, and the semiconductor layer can be formed of polysilicon.

[0016] According to embodiments of this disclosure, a shallow trench isolation zone may be provided between the P-type trap and the N-type trap.

[0017] According to the semiconductor device of this disclosure, an extended gate structure is provided on the surface of the drift region of the LDMOS device, thereby reducing the specific on-resistance while ensuring a high breakdown voltage. Furthermore, according to the semiconductor device of this disclosure, the extended gate structure of the LDMOS device has an opening region exposing the gate dielectric, thereby reducing the capacitance between the gate electrode and the drain electrode to improve the switching speed of the LDMOS device. Additionally, according to the semiconductor device of this disclosure, the LDMOS device is provided with a fully isolated structure, thereby ensuring reliable operation of the LDMOS device.

[0018] However, the effects of this disclosure are not limited to those described above, and various extensions can be made without departing from the spirit and scope of this disclosure. It should be understood that the general description above and the detailed description below are exemplary and illustrative, and not intended to limit the scope of this disclosure. Attached Figure Description

[0019] The accompanying drawings are provided to offer a further understanding of this disclosure. The drawings illustrate exemplary embodiments of this disclosure and, together with the description, serve to explain the concept of this disclosure.

[0020] Figure 1 This is a cross-sectional view showing a semiconductor device according to an embodiment of the present disclosure.

[0021] Figure 2 This is a top view showing a semiconductor layer according to an embodiment of the present disclosure.

[0022] Figure 3 This illustrates the implementation of embodiments according to this disclosure. Figure 2 A cross-sectional view of the semiconductor device taken by line X1-X1'.

[0023] Figure 4 This illustrates the implementation of embodiments according to this disclosure. Figure 2 A cross-sectional view of a semiconductor device taken by line Y-Y'.

[0024] Figure 5 A top view of a semiconductor layer according to an alternative embodiment of the present disclosure is shown.

[0025] Figure 6 A top view of a semiconductor layer according to an alternative embodiment of the present disclosure is shown.

[0026] Figure 7 A top view of a semiconductor layer according to an alternative embodiment of the present disclosure is shown.

[0027] Figures 8A to 8C A simulation view of a semiconductor device according to an embodiment of the present disclosure is shown. Detailed Implementation

[0028] The present disclosure will now be described more fully below with reference to the accompanying drawings, in which various embodiments are illustrated. However, the present disclosure may be implemented in many different ways and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that the disclosure will be exhaustive and complete, and will fully convey the scope of the disclosure to those skilled in the art. The same reference numerals denote the same parts throughout the drawings. Furthermore, in the drawings, the thickness, proportions, and dimensions of parts are enlarged for clarity.

[0029] The terminology used herein is for the purpose of describing particular embodiments and is not intended to limit the scope of this disclosure. Unless the context clearly indicates otherwise, the singular terms “a” and “the” as used herein should also include the plural forms. Furthermore, the terms “comprising” and / or “including” as used herein are intended to indicate the presence of the stated features, quantities, operations, elements, components, and / or combinations thereof, but do not exclude the presence or addition of one or more other features, quantities, steps, operations, elements, components, and / or combinations thereof. It should also be noted that the terms “substantially,” “about,” and other similar terms used herein should be understood as indicating similarity rather than degree, and therefore can take into account inherent deviations in measurements, calculations, and / or provided numerical values ​​that are generally recognized by those skilled in the art.

[0030] Although the terms “first,” “second,” etc., may be used herein to describe various types of elements, these elements are not limited by these terms. These terms are used only to distinguish one element from another. Therefore, without departing from the teachings of this disclosure, the first element discussed below may be referred to as the second element, and vice versa.

[0031] Furthermore, terms such as "below," "below," "above," and "upper" are used to describe the relationships between the components shown in the diagram. These terms can be relative concepts and are described based on the directions presented in the diagram.

[0032] In this specification, it will also be understood that when a component (or region, layer, part, etc.) is referred to relative to other components, such as "on," "connected to," or "coupled to" other components, that component may be directly disposed on / directly connected to / directly coupled to that component, or there may be an intervening third component. Conversely, when a component (or region, layer, part, etc.) is referred to relative to other components in this specification, such as "directly" on, "directly connected to," or "directly coupled to" other components, there is no intervening component between them.

[0033] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains, and shall not be interpreted in an idealized or overly formal sense, unless expressly defined herein.

[0034] This document describes embodiments with reference to cross-sectional views of schematic diagrams as idealized implementations. Thus, variations in shape relative to the illustrations are anticipated as a result of, for example, manufacturing techniques and / or tolerances. Therefore, the embodiments described herein should not be construed as limited to the specific shapes of the regions shown herein, but should include deviations in shape due to, for example, manufacturing processes. For example, regions shown or described as flat may typically have rough and / or non-linear characteristics. Furthermore, acute angles shown may be rounded. Therefore, the regions shown in the figures are schematic in nature, and their shapes are not intended to show precise shapes of the regions and are not intended to limit the scope of the claims.

[0035] The semiconductor device according to various embodiments of the present disclosure is described below with reference to the accompanying drawings.

[0036] Figure 1 A cross-sectional view of a semiconductor device 100 according to an embodiment of the present disclosure is shown.

[0037] like Figure 1 As shown, the semiconductor device 100 according to an embodiment of the present disclosure may include a lightly doped P-type substrate (P-sub) 101 and an N-type buried layer (NBL) 102 disposed on the P-type substrate 101. According to an embodiment of the present disclosure, the N-type buried layer 102 may be used as a barrier layer or isolation layer to separate the laterally diffused metal-oxide-semiconductor (LDMOS) device 103, described later, from the P-type substrate 101. Furthermore, as... Figure 1 As shown, according to an embodiment of the present disclosure, the end of the N-type buried layer 102 may terminate at the first P-type epitaxial layer (P-epi) 104.

[0038] like Figure 1 As shown, according to an embodiment of this disclosure, the LDMOS device 103 disposed on the N-type buried layer 102 may include a heavily doped N-type source contact region 105 disposed in the first P-type well (PW) 114 (which may also be referred to as the P-type body region) and a heavily doped P-type body contact region 106 adjacent to the N-type source contact region 105. Throughout the drawings, light doping can be represented by a negative sign "-", and heavy doping can be represented by a positive sign "+".

[0039] like Figure 1As shown, according to an embodiment of this disclosure, the (body) source electrode (B&S) 107 of the LDMOS device 103 can be disposed on the N-type source contact region 105 and the P-type body contact region 106. According to an embodiment of this disclosure, the source electrode 107 can be a metallized source electrode.

[0040] like Figure 1 As shown, according to embodiments of this disclosure, the LDMOS device 103 may include a heavily doped N-type drain contact region 108 disposed in a shallow high-voltage N-type well (SHVNW) 115. For example... Figure 1 As shown, according to an embodiment of the present disclosure, the drain electrode (D) 109 of the LDMOS device 103 can be disposed on the N-type drain contact region 108. According to an embodiment of the present disclosure, the drain electrode 109 can be a metallized drain electrode.

[0041] like Figure 1 As shown, according to embodiments of this disclosure, the LDMOS device 103 may further include a shallow high-voltage P-type well (SHVPW) 116 disposed below the shallow high-voltage N-type well 115. The shallow high-voltage N-type well 115 may also be referred to as a drift region or extended drain structure, configured to deplete in the off-state of the LDMOS device 103 to establish a reduced surface electric field (RESURF) structure, thereby improving breakdown performance. Furthermore, as... Figure 1 As shown, according to an embodiment of the present disclosure, the LDMOS device 103 can be implemented as having a dual RESURF structure, wherein the PN junction formed by the first P-type well 114 and the adjacent shallow high-voltage N-type well 115 can be used as a horizontal RESURF structure, and the PN junction formed by the shallow high-voltage P-type well 116 and the shallow high-voltage N-type well 115 above it can be used as a vertical RESURF structure.

[0042] like Figure 1 As shown, according to an embodiment of the present disclosure, the LDMOS device 103 can be disposed in a second P-type epitaxial layer (P-epi) 117 on the N-type buried layer 102. According to an embodiment of the present disclosure, the first P-type epitaxial layer 104 and the second P-type epitaxial layer 117 can be formed of the same material.

[0043] According to embodiments of this disclosure, the first P-type well 114 can be formed in the second P-type epitaxial layer 117 by an ion implantation process. Furthermore, according to embodiments of this disclosure, the shallow high-pressure N-type well 115 and the shallow high-pressure P-type well 116 can be formed in the second P-type epitaxial layer 117 using the same mask through different ion implantation processes, such that the interface between the first P-type well 114 and the shallow high-pressure N-type well 115 can be aligned with the interface between the second P-type epitaxial layer 117 and the shallow high-pressure P-type well 116. Furthermore, although in Figure 1The lower surface of the shallow high-pressure P-type well 116 is adjacent to the upper surface of the N-type buried layer 102, such that there is no portion of the second P-type epitaxial layer 117 between the lower surface of the shallow high-pressure P-type well 116 and the upper surface of the N-type buried layer 102. However, this disclosure is not limited thereto. According to embodiments of this disclosure, a portion of the second P-type epitaxial layer 117 may also exist between the lower surface of the shallow high-pressure P-type well 116 and the upper surface of the N-type buried layer 102.

[0044] like Figure 1 As shown, according to embodiments of this disclosure, the semiconductor device 100 may further include a deep N-well (DNW) 118 disposed on the N-type buried layer 102 and adjacent to the LDMOS device 103. Furthermore, as... Figure 1 As shown, according to an embodiment of the present disclosure, the semiconductor device 100 may further include an N-type well (NW) 119 disposed on a deep N-type well 118 and adjacent to the LDMOS device 103. According to an embodiment of the present disclosure, the N-type well 118 and the deep N-type well 119 may be configured to have a ring structure in the horizontal direction, so as to surround the LDMOS device 103 together with the N-type buried layer 102.

[0045] Therefore, as Figure 1 As shown, according to embodiments of this disclosure, the first P-type well 114, the second P-type epitaxial layer 117, and the shallow high-voltage P-type well 116 can together form a P-type structure surrounding the shallow high-voltage N-type well 115. Furthermore, as... Figure 1 As shown, according to an embodiment of this disclosure, the N-type well 118, the deep N-type well 119, and the N-type buried layer 102 can together form an N-type structure surrounding the aforementioned P-type structure. Therefore, according to an embodiment of this disclosure, the aforementioned P-type structure and N-type structure can together form a fully isolated structure, thereby ensuring high reliability of the LDMOS device 103.

[0046] like Figure 1 As shown, according to embodiments of the present disclosure, the semiconductor device 100 may further include an N-type ohmic contact region 120 disposed in an N-type well 119 and an isolation electrode (Nring) 121 disposed on the N-type ohmic contact region 120. According to embodiments of the present disclosure, the isolation electrode 121 may be a metallized electrode and is connected to the highest potential, such as a high power supply voltage.

[0047] like Figure 1 As shown, according to embodiments of the present disclosure, the semiconductor device 100 may further include a second P-type well (PW) 122 disposed on the first P-type epitaxial layer 104, a heavily doped P-type substrate contact region 123 disposed in the second P-type well 122, and a substrate electrode (Psub) 124 disposed on the P-type substrate contact region 123. According to embodiments of the present disclosure, the substrate electrode 124 may be a metallized electrode and is connected to a lowest potential, such as ground voltage.

[0048] like Figure 1 As shown, according to embodiments of the present disclosure, the semiconductor device 100 may further include a shallow trench isolation (STI) region 126 disposed between the first P-type well 114 and the N-type well 118 and between the N-type well 118 and the second P-type well 122.

[0049] In addition, such as Figure 1 As shown, according to an embodiment of the present disclosure, the LDMOS device 103 may include a gate dielectric 110 extending from the upper surface of the N-type source contact region 105 to the upper surface of the N-type drain contact region 108 and adjacent to the drain electrode 109. That is, the gate dielectric 110 may cover the upper surfaces of the first P-type well 114 and the shallow high-voltage N-type well 115. According to an embodiment of the present disclosure, the gate dielectric 110 may be formed of silicon oxide.

[0050] like Figure 1 As shown, according to embodiments of this disclosure, the LDMOS device 103 may further include a semiconductor layer 111 disposed on the gate dielectric 110, wherein the edge of the semiconductor layer 111 is aligned with the edge of the gate dielectric 110. Figure 1 As shown, according to an embodiment of the present disclosure, the semiconductor layer 111 may include a gate contact region 112 formed on the side near the source electrode 107 and a gate electrode 113 disposed on the gate contact region 112. According to an embodiment of the present disclosure, the gate electrode 113 may be a metallized electrode. According to an embodiment of the present disclosure, the semiconductor layer 111 may be formed of polysilicon. According to an embodiment of the present disclosure, the semiconductor layer 111 may form an extended gate structure.

[0051] like Figure 1 As shown, according to an embodiment of the present disclosure, from the gate contact region 112 to the drain electrode 109, the semiconductor layer 111 may sequentially include a gate-side ohmic contact region 111a formed by heavy doping of P-type impurities, a high-resistivity region 111b formed by light doping of P-type impurities, a field-stop region 111c formed by heavy doping of N-type impurities, and a drain-side ohmic contact region 111d formed by heavy doping of P-type impurities.

[0052] According to an embodiment of the present disclosure, the extended gate structure formed by the semiconductor layer 111 introduces a PN junction formed by the field cutoff region 111c and the drain-side ohmic contact region 111d near the gold drain electrode 109. This junction is reverse biased when the LDMOS device 103 is in the on state to withstand the voltage difference between the gate electrode 113 and the drain electrode 109, thereby reducing leakage current.

[0053] Furthermore, according to embodiments of this disclosure, the extended gate structure can form a capacitor structure with the shallow high-voltage N-type well 115 (drift region), wherein the low-potential side of the extended gate structure is connected to the gate electrode 113, and the high-potential side is connected to the drain electrode 109. Therefore, in the on-state of the LDMOS device 103, when the voltage difference V between the gate electrode 113 and the source electrode 107... GS Greater than the voltage difference V between the drain electrode 109 and the source electrode 107 DS At that time, an accumulation layer of majority carriers (electrons) is formed in the drift region near the surface of the gate dielectric 110.

[0054] According to embodiments of this disclosure, as the voltage applied to the gate electrode 113 increases, when V GS >V TH When the threshold voltage of the LDMOS device is reached, inversion begins on the surface of the body region below the gate electrode 113, forming a channel for majority carriers (electrons). Therefore, majority carriers flow from the source region through the channel to the drift region and then into the drain through the electron accumulation layer on the surface of the drift region, providing a channel with extremely low resistance. Thus, the vast majority of the current passes through the accumulation layer to the drift region, significantly reducing the specific on-resistance of the LDMOS device 103.

[0055] Furthermore, according to embodiments of this disclosure, since the strength of the electron accumulation layer depends on the magnitude of the voltage applied to the gate electrode 113 and is independent of the thickness of the gate dielectric 110 and the doping concentration of the drift region, the implantation dose of the shallow high-voltage N-type well 115 can be increased.

[0056] Furthermore, according to the embodiments of this disclosure, when the LDMOS device 103 is in the off state, there is a charge balance effect between the shallow high voltage N-type well 115 (drift region) and the semiconductor layer 111 above it and the shallow high voltage P-type well 116 below it, which can help adjust the electric field distribution in the drift region. Therefore, the injection dose of the shallow high voltage N-type well 115 can be further increased while ensuring that the breakdown voltage remains unchanged.

[0057] Figure 2 A top view of a semiconductor layer 111 according to an embodiment of the present disclosure is shown. Figure 3 The following is illustrated according to an embodiment of the present disclosure. Figure 2 A cross-sectional view of the semiconductor device 100 taken by line X1-X1'. Figure 4 The following is illustrated according to an embodiment of the present disclosure. Figure 2 A cross-sectional view of the semiconductor device 100 taken by line Y-Y'. Furthermore, it should be understood that... Figure 1 The cross-sectional view of the semiconductor device 100 shown can be along... Figure 2 The cross-sectional view intercepted by line X2-X2'. Figures 2 to 4In, with Figure 1 The same parts are indicated by the same reference numerals, and their detailed descriptions will not be repeated.

[0058] like Figure 2 As shown, according to an embodiment of the present disclosure, the semiconductor layer 111 may have an opening region 125 that exposes the gate dielectric 110. According to an embodiment of the present disclosure, the opening region 125 may have a rectangular opening extending from the gate-side ohmic contact region 111a to the field-stop region 111c.

[0059] Figure 5 A top view of a semiconductor layer 111 according to an alternative embodiment of the present disclosure is shown. Figure 5 In, with Figure 1 Identical parts are indicated by the same reference numerals. For example... Figure 5 As shown, according to an embodiment of the present disclosure, the opening region 125 may have two or more openings that are parallel to each other, extending from the gate-side ohmic contact region 111a to the field-stop region 111c.

[0060] Figure 6 A top view of a semiconductor layer 111 according to an alternative embodiment of the present disclosure is shown. Figure 6 In, with Figure 1 Identical parts are indicated by the same reference numerals. For example... Figure 6 As shown, according to an embodiment of the present disclosure, the opening region 125 can be completely disposed in the high-resistivity region 111b, that is, each opening of the opening region 125 is surrounded by the high-resistivity region 111b.

[0061] Figure 7 A top view of a semiconductor layer 111 according to an alternative embodiment of the present disclosure is shown. Figure 7 In, with Figure 1 Identical parts are indicated by the same reference numerals. For example... Figure 7 As shown, according to an embodiment of the present disclosure, the opening region 125 can be configured to have a plurality of openings arranged in a grid.

[0062] According to embodiments of this disclosure, by providing an opening region 125 in the semiconductor layer 111, the area of ​​the shallow high-voltage N-type well 115 (drift region) facing the high-resistivity region 111b can be reduced, thereby reducing the capacitance C between the gate electrode 113 and the drain electrode 109. GD This can improve the switching speed of the LDMOS device 103.

[0063] As described above, according to the semiconductor device of this disclosure, an extended gate structure is provided on the surface of the drift region of the LDMOS device, thereby reducing the specific on-resistance while ensuring a high breakdown voltage. Furthermore, according to the semiconductor device of this disclosure, the extended gate structure of the LDMOS device has an opening region, thereby improving the switching speed of the LDMOS device. Additionally, according to the semiconductor device of this disclosure, the LDMOS device is provided with a fully isolated structure, thereby ensuring reliable operation of the LDMOS device.

[0064] Although, for ease of description, the various components of the semiconductor devices in the above embodiments are shown and described as having specific conduction types, such as N-type and P-type, this disclosure is not limited thereto. Instead, other types of semiconductor devices can be provided by, for example, replacing semiconductor regions of different conduction types or doping processes. Therefore, each semiconductor region, layer, or other structure in the semiconductor devices of the above embodiments may have a different conduction type than that described in the above embodiments. All such variations should be covered within the scope of this disclosure.

[0065] Figures 8A to 8C A simulated view of a semiconductor device 100 according to an embodiment of the present disclosure is shown.

[0066] Figure 8A The semiconductor device 100 according to an embodiment of the present disclosure is shown in the off state when V DS Potential distribution at 51V. For example... Figure 8A As shown, the semiconductor device 100 can meet the requirements of an NMOS design with an operating voltage of 40V.

[0067] also, Figure 8B The diagram illustrates the distribution of current density within a shallow high-voltage N-type well 115 of a semiconductor device 100 according to an embodiment of the present disclosure in the on-state, relative to the distance from the upper surface, wherein a voltage of 5V is applied to the gate electrode 113 and a voltage of 0.1V is applied to the drain electrode. Figure 8B As shown, due to the formation of an electron accumulation layer on the surface of the shallow high-voltage N-type well 115, the current density at the surface is significantly increased, compared to the on-resistance R. sp 21mΩ·mm 2 When the interface charge concentration is 1×10 11 At that time, it has almost no effect on the on-state voltage drop.

[0068] also, Figure 8C The on-resistance of a semiconductor device 100 according to an embodiment of the present disclosure is shown in comparison with that of the prior art. Figure 8C The black and gray curves shown illustrate the specific on-resistance at different breakdown voltages obtained according to existing technology. Figure 8CAs shown, when the breakdown voltage BV is 51V, the specific on-resistance of the semiconductor device 100 according to the embodiments of this disclosure can be significantly reduced compared to the prior art.

[0069] Although this disclosure has been described with reference to embodiments thereof, those skilled in the art will understand that various modifications and changes may be made to this disclosure without departing from the spirit and scope of the disclosure as disclosed in the appended claims.

Claims

1. A semiconductor device, comprising: P-type substrate; An N-type buried layer is disposed on the P-type substrate; as well as A laterally diffused metal-oxide-semiconductor (LDMOS) device is disposed on the N-type buried layer. The LDMOS device includes: N-type source contact region and P-type body contact region adjacent to the N-type source contact region; The source electrode is disposed on the N-type source contact region and the P-type body contact region; N-type leakage contact area; A drain electrode is disposed on the N-type drain contact area; A gate dielectric extends from the upper surface of the N-type source contact region to the upper surface of the N-type drain contact region and is adjacent to the drain electrode; A semiconductor layer disposed on the gate dielectric, the edge of the semiconductor layer being aligned with the edge of the gate dielectric, the semiconductor layer including a gate contact region formed on the side near the source electrode; and The gate electrode is disposed on the gate contact area. The semiconductor layer has an opening region that exposes the gate dielectric.

2. The semiconductor device according to claim 1, wherein The opening region has one opening or multiple openings that are parallel to each other.

3. The semiconductor device according to claim 1, wherein, From the gate contact region to the drain electrode, the semiconductor layer sequentially comprises: Gate-side ohmic contact region formed by heavy doping with P-type impurities; High-resistivity region formed by light doping with P-type impurities; The field cutoff region is formed by heavy doping with N-type impurities; as well as The drain-side ohmic contact region formed by heavy doping of P-type impurities, and The opening region is located within the high-resistivity region.

4. The semiconductor device according to claim 3, wherein, The opening region in the semiconductor layer is configured to have multiple openings arranged in a grid.

5. The semiconductor device according to claim 1, further comprising: A deep N-type well is disposed on the N-type buried layer and adjacent to the LDMOS device; as well as An N-type well is disposed on the deep N-type well and adjacent to the LDMOS device. The N-type well, the deep N-type well, and the N-type buried layer surround the LDMOS device.

6. The semiconductor device according to claim 5, wherein, The N-type well is provided with an N-type ohmic contact region and an isolation electrode disposed on the N-type ohmic contact region, and the isolation electrode is connected to a high power supply voltage.

7. The semiconductor device according to claim 5, wherein, The LDMOS device also includes: A P-type epitaxial layer is disposed on the N-type buried layer; A high-voltage P-type trap is disposed on the N-type buried layer and adjacent to the P-type epitaxial layer; A P-type well is disposed on the P-type epitaxial layer, wherein the N-type source contact region and the P-type body contact region are disposed within the P-type well; and A high-voltage N-type sink is disposed on and adjacent to the high-voltage P-type sink, wherein the N-type leakage contact area is disposed within the high-voltage N-type sink, and The P-type well, the P-type epitaxial layer, and the high-voltage P-type well surround the high-voltage N-type well.

8. The semiconductor device according to claim 7, wherein, The interface between the P-type well and the high-voltage N-type well is aligned with the interface between the P-type epitaxial layer and the high-voltage P-type well.

9. The semiconductor device according to claim 1, wherein, The gate dielectric is formed of silicon oxide, and the semiconductor layer is formed of polycrystalline silicon.

10. The semiconductor device according to claim 7, wherein, A shallow trench isolation zone is provided between the P-type well and the N-type well.

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