Method for improving voltage withstanding performance of ldmos
By forming a stepped dielectric layer and field plate structure in LDMOS devices, the problem of electric field concentration is solved, the breakdown voltage and device reliability are improved, the production cost is reduced, and the withstand voltage performance and conduction performance are optimized.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- HUA HONG SEMICONDUCTOR MANUFACTURING (WUXI) LTD
- Filing Date
- 2026-03-20
- Publication Date
- 2026-07-14
AI Technical Summary
In the existing technology, LDMOS devices have low breakdown voltage due to electric field concentration, and adjusting the field plate structure by conventional means requires additional photomasks and complex processes, which increases costs and alignment errors.
By forming a stepped dielectric layer on the surface of a semiconductor substrate, defining the bulk region position using photolithography and etching processes, and combining two growth processes to form a stepped field plate structure, adjusting the thickness and length of the first and second dielectric layers, an adjustable field plate structure is formed.
Without increasing the number of photomasks, it effectively smooths the electric field distribution, improves breakdown voltage and device reliability, reduces production costs, and enhances the synergistic optimization of withstand voltage performance and on-resistance.
Smart Images
Figure CN122395978A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of integrated circuit manufacturing, and in particular to a method for improving the breakdown voltage performance of LDMOS. Background Technology
[0002] In power semiconductor devices, laterally diffused metal-oxide-semiconductor (LDMOS) devices are widely used due to their ease of integration and good high-voltage characteristics. However, in conventional LDMOS structures, due to the geometric factors of the device structure, when a high voltage is applied, the electric field tends to concentrate at locations such as the gate edge, shallow trench isolation corners, and PN junctions. This electric field concentration effect leads to a decrease in the device's breakdown voltage (BV), thereby limiting the device's operating range and reliability.
[0003] To alleviate the problem of electric field concentration, existing technologies typically introduce gate field plates to optimize the electric field distribution on the drift region surface. The field plate utilizes its potential to induce an accumulation layer on the drift region surface, thereby achieving a bidirectional increase in breakdown voltage (BV) and specific on-resistance (Rsp). However, achieving ideal electric field modulation often requires fine optimization of parameters such as the morphology, length, and dielectric thickness of the field plate. Especially in high-voltage LDMOS applications, its withstand voltage capability faces a bottleneck, and relying solely on traditional field plate structures is insufficient to further improve performance.
[0004] In addition, existing field plate structure optimization schemes often require the addition of additional photomask layers or complex process steps to define oxide layers of different thicknesses. This not only increases the complexity of the process and production costs, but may also introduce new alignment errors, affecting the consistency of the device.
[0005] Therefore, there is an urgent need for a process method that can flexibly adjust the dielectric layer structure under the field plate without increasing the number of photomasks, thereby forming an adjustable stepped field plate structure to effectively improve the withstand voltage performance of LDMOS. Summary of the Invention
[0006] This invention provides a method to improve the breakdown voltage performance of LDMOS, in order to solve the problems of low breakdown voltage caused by electric field concentration in existing LDMOS devices, and the need to add additional photomasks, complex processes and high costs when adjusting the field plate structure by conventional means.
[0007] This invention provides a method for improving the breakdown voltage performance of LDMOS, comprising the following steps:
[0008] Step 1: Provide a semiconductor substrate, on which an isolation structure and a drift region located within the semiconductor substrate have been formed;
[0009] Step 2: Form a first dielectric layer on the surface of the semiconductor substrate, the first dielectric layer covering the drift region;
[0010] Step 3: Using photolithography and etching processes, remove the first dielectric layer located above the preset position of the body region, expose the semiconductor substrate surface at the preset position of the body region, and retain the first dielectric layer located between the isolation structure and the preset position of the body region.
[0011] Step 4: Perform the growth process to form a second dielectric layer on the exposed semiconductor substrate surface, while simultaneously thickening the retained first dielectric layer to form a stepped dielectric layer.
[0012] Step 5: Deposit and pattern conductive material over the second dielectric layer, the stepped dielectric layer, and the isolation structure to form the gate and field plate structure;
[0013] The stepped medium layer is located between the isolation structure and the second medium layer and is covered by the field plate structure, forming a stepped field plate structure.
[0014] Preferably, in step one, the isolation structure is a shallow trench isolation structure or a field oxide layer structure.
[0015] Preferably, in step one, the semiconductor substrate is made of silicon.
[0016] Preferably, in step two, the material of the first dielectric layer is silicon oxide.
[0017] Preferably, in step two, the first dielectric layer is a pad oxide layer grown by a thermal oxidation process.
[0018] Preferably, prior to step two, the method further includes removing the natural oxide layer on the surface of the semiconductor substrate.
[0019] Preferably, in step three, the photolithography process uses a photomask in the defined body region for exposure, without the need to add an additional photomask layer.
[0020] Preferably, in step four, the second dielectric layer is a gate oxide layer.
[0021] Preferably, in step four, the thickness of the second dielectric layer is less than the thickness of the stepped dielectric layer.
[0022] Preferably, in step four, the thickness Y of the stepped dielectric layer satisfies the following relationship: Y = Y1 + 1 / 2Y2; where Y1 is the thickness of the first dielectric layer formed in step two, and Y2 is the thickness of the second dielectric layer formed in step four.
[0023] Preferably, in step four, the length of the stepped medium layer corresponds to the distance between the edge of the isolation structure and the edge of the preset position of the body region.
[0024] Preferably, in step five, the conductive material is polycrystalline silicon.
[0025] Preferably, after step five, the method further includes step six: using the gate and field plate structure as a mask, performing an ion implantation process to form a source heavily doped region at a preset position in the body region and a drain heavily doped region in the drift region.
[0026] As described above, the method for improving the breakdown voltage performance of LDMOS according to the present invention has the following beneficial effects:
[0027] This invention improves the process flow by simultaneously defining the position of the first dielectric layer using a photomask defining the volume region without increasing the number of photomasks. Combined with the superposition effect of two growth processes, an adjustable stepped field plate structure is successfully formed. This structure utilizes a topologically controllable stepped dielectric layer located between the gate oxide and the isolation structure to effectively smooth the electric field distribution on the drift region surface, solving the problem of electric field concentration at the gate edge and the corner of the isolation structure. Furthermore, by adjusting the process parameters of the first and second dielectric layers, the thickness of the stepped dielectric layer can be flexibly adjusted, thus providing a larger process window for the synergistic optimization of breakdown voltage and specific on-resistance in laterally diffused metal-oxide-semiconductor devices. This reduces production costs while improving the device's breakdown voltage performance and reliability. Attached Figure Description
[0028] Figure 1 The diagram shows a process flow diagram of the method for improving the breakdown voltage performance of LDMOS according to the present invention;
[0029] Figure 2 The diagram shows a cross-sectional structure of the device after providing a semiconductor substrate in the method for improving the breakdown voltage performance of LDMOS according to the present invention.
[0030] Figure 3 The diagram shows a cross-sectional structure of the device after the formation of the first dielectric layer in the method for improving the withstand voltage performance of LDMOS according to the present invention.
[0031] Figure 4 The diagram shows a cross-sectional structure of the device after the preset position of the bulk region is exposed by photolithography and etching in the method for improving the breakdown voltage performance of LDMOS according to the present invention.
[0032] Figure 5 The diagram shows a cross-sectional structure of the device after forming the second dielectric layer and the stepped dielectric layer in the method for improving the withstand voltage performance of LDMOS according to the present invention.
[0033] Figure 6 The diagram shows a cross-sectional structure of the device after forming the gate and field plate structures and the source / drain heavily doped regions in the method for improving the withstand voltage performance of LDMOS according to the present invention. Detailed Implementation
[0034] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.
[0035] like Figure 1 The diagram shown is a flowchart illustrating the method for improving the breakdown voltage performance of LDMOS provided by this invention. This method is achieved by adjusting the field plate structure and mainly includes the following steps.
[0036] First, step one is performed: a semiconductor substrate 101 is provided, on which an isolation structure 103 and a drift region 102 located within the semiconductor substrate 101 are formed. For example... Figure 2 As shown, the surface of the initially provided substrate is typically covered with a natural oxide layer 104.
[0037] In some embodiments, the semiconductor substrate 101 is made of silicon. However, the scope of the invention is not limited thereto. The semiconductor substrate 101 may comprise basic semiconductor materials, such as crystalline silicon (Si) or crystalline germanium (Ge); it may also comprise compound semiconductor materials, such as silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), or indium antimonide (InSb); it may also comprise alloy semiconductor materials, such as silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), or gallium arsenide phosphide indium (GaInAsP). Furthermore, the semiconductor substrate 101 may be a silicon-on-insulator (SOI) structure, a germanium-on-insulator (GOI) structure, or a silicon-on-germanium-on-insulator (SGOI) structure. In the case of an SOI structure, the semiconductor substrate 101 typically includes an operation processing wafer, a buried oxide (BOX) layer on the operation processing wafer, and a semiconductor top layer on the buried oxide layer. The semiconductor substrate 101 may also include various doping configurations, depending on design requirements, such as a p-type substrate or an n-type substrate, where the impurity concentration can be adjusted according to the different needs of logic devices, memory devices, or power devices. An epitaxial layer can be formed on the semiconductor substrate 101 using an epitaxial growth process. This epitaxial layer can be homoepitaxial (e.g., silicon on silicon) or heteroepitaxial (e.g., silicon-germanium on silicon), and the epitaxial layer can be doped in situ or subsequently ion-implanted to provide a background concentration suitable for the formation of the drift region 102 and the body region. Furthermore, the semiconductor substrate 101 may also include strain structures for performance enhancement, such as introducing compressive stress by embedding silicon-germanium source / drain regions in the silicon substrate, or introducing tensile stress by embedding silicon carbide source / drain regions to improve carrier mobility. The drift region 102 is typically formed by ion implantation of N-type impurities (e.g., phosphorus) followed by high-temperature driven push-junction; its depth and concentration distribution determine the device's basic breakdown voltage capability.
[0038] In some embodiments, in step one, the isolation structure 103 is a shallow trench isolation structure or a field oxide layer structure. For example... Figure 2As shown, the isolation structure 103 is a shallow trench isolation (STI). Its formation process includes: etching trenches in the semiconductor substrate 101 using photolithography and dry etching processes; depositing a linear oxide layer within the trenches; depositing a filling dielectric material using high-density plasma chemical vapor deposition (HDP-CVD) or flowing chemical vapor deposition (FCVD) processes. The filling dielectric material may include silicon oxide, silicon nitride, silicon oxynitride, or spin-coated glass (SOG); and finally, removing excess filling dielectric material using chemical mechanical planarization (CMP) to flush its surface with the active region surface. When the isolation structure 103 is a field oxide, it can be grown using localized silicon oxidation (LOCOS) processes. The main function of the isolation structure 103 is to provide lateral electrical isolation and increase the path length of charge carriers on the surface of the drift region 102, assisting in the depletion of the drift region 102.
[0039] Subsequently, step two is performed: a first dielectric layer 105 is formed on the surface of the semiconductor substrate 101, and the first dielectric layer 105 covers the drift region 102.
[0040] In some embodiments, prior to step two, the method further includes removing the native oxide layer 104 from the surface of the semiconductor substrate 101. This is typically achieved using a wet cleaning process with hydrofluoric acid (HF) solution or buffered oxide etchant (BOE), or alternatively, a plasma-based dry cleaning process. Removing the native oxide layer 104 ensures good interface quality for the subsequently grown dielectric layer, reduces interface state density, and improves device reliability.
[0041] In some embodiments, in step two, the material of the first dielectric layer 105 is silicon oxide. For example... Figure 3 As shown, the silicon oxide layer can be formed by thermal oxidation, chemical vapor deposition (CVD) processes (such as low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), or atomic layer deposition (ALD). In addition to silicon oxide, the material of the first dielectric layer 105 can also be selected from silicon nitride, silicon oxynitride, high-k dielectric materials (such as hafnium oxide, zirconium oxide, aluminum oxide, hafnium silicate, etc.), or combinations thereof.
[0042] In some embodiments, in step two, the first dielectric layer 105 is a pad oxide layer grown by a thermal oxidation process. The pad oxide layer serves as a buffer layer for subsequent processes, mitigating stress generated during thin film deposition or thermal processes. When using a thermal oxidation process, the semiconductor substrate 101 can be placed in an oxidation furnace and oxidized under an atmosphere primarily containing oxygen or water vapor. The thickness Y1 of the first dielectric layer 105 is one of the key parameters for forming the final stepped field plate structure height, and its thickness uniformity directly affects the consistency of the electric field distribution in the final device.
[0043] Next, step three is performed: using photolithography and etching processes, the first dielectric layer 105 located above the preset position of the body region is removed, exposing the surface of the semiconductor substrate 101 at the preset position of the body region, while retaining the first dielectric layer 105 located between the isolation structure 103 and the preset position of the body region.
[0044] In some embodiments, in step three, the photolithography process utilizes the photomask defining the body region 107 for exposure, without the need for an additional photomask layer. For example... Figure 4 As shown, photoresist 106 covers the drift region 102 and part of the isolation structure 103, exposing the area where the body region 107 is located. This is a process strategy of self-aligned or multiplexed photomasks. Specifically, after forming a pattern of photoresist 106 to expose the area above the preset position of the body region, ion implantation is first performed using photoresist 106 as an implantation mask. P-type impurities (e.g., boron, boron difluoride) or N-type impurities are implanted into the semiconductor substrate 101, thereby defining the doping concentration and junction depth of the body region 107. During this implantation process, photoresist 106 effectively blocks ions from entering the area covered by the drift region 102 and the isolation structure 103. After the ion implantation to form the body region 107 (or the body implantation region) is completed, photoresist 106 is not immediately removed, but is used as an etching mask to etch and remove the exposed first dielectric layer 105. The etching process can be wet etching (e.g., using a diluted hydrofluoric acid solution), which utilizes the high selectivity between silicon oxide and silicon to ensure complete removal of the oxide layer without damaging the underlying silicon surface; or it can be dry etching (e.g., reactive ion etching, RIE), which can obtain steeper sidewall morphologies. This process sequence not only saves on photomask costs, but more importantly, it achieves self-alignment between the implantation boundary of the body region 107 and the etching boundary of the first dielectric layer 105, eliminating alignment errors that may occur between the two photolithography steps. This ensures that the length of the subsequently formed stepped dielectric layer 109 is precisely controllable, thereby improving the stability and yield of the process.
[0045] Subsequently, step four is performed to carry out the growth process, forming a second dielectric layer 108 on the exposed semiconductor substrate 101 surface, while thickening the retained first dielectric layer 105 to form a stepped dielectric layer 109.
[0046] In some embodiments, in step four, the second dielectric layer 108 is a gate oxide layer. For example... Figure 5As shown, this growth process is typically a high-quality thermal oxidation process to ensure that the gate oxide layer has excellent insulation and breakdown characteristics. In the oxidizing atmosphere for growing the second dielectric layer 108, the exposed silicon surface (i.e., the surface of the body region 107) reacts with the oxidant to grow a new oxide layer, namely the second dielectric layer 108. At the same time, although the oxidant originally retained below the first dielectric layer 105 diffuses more slowly, it will still penetrate through the first dielectric layer 105 and react with the silicon below, or the first dielectric layer 105 itself will undergo densification and additional oxidation growth at high temperature, thereby increasing the total thickness of this region and forming a stepped dielectric layer 109.
[0047] In some embodiments, in step four, the thickness of the second dielectric layer 108 is less than the thickness of the stepped dielectric layer 109. For example... Figure 5 As shown, this thickness difference forms a unique stepped morphology. The thinner second dielectric layer 108 is located above the channel region, ensuring that the device has a lower threshold voltage and higher transconductance, achieving good turn-on characteristics; the thicker stepped dielectric layer 109 is located on the side of the drift region 102 near the channel, and can withstand a higher gate leakage potential difference.
[0048] In some embodiments, in step four, the thickness Y of the stepped dielectric layer 109 satisfies the following relationship: Y = Y1 + 1 / 2Y2. Wherein, Y1 is the thickness of the first dielectric layer 105 formed in step two, and Y2 is the thickness of the second dielectric layer 108 formed in step four. This formula reflects the superposition effect of the two oxidation processes. By precisely controlling the initial growth parameters of the first dielectric layer 105 (determining Y1) and the growth parameters of the second dielectric layer 108 (determining Y2), the final thickness Y of the stepped dielectric layer 109 can be flexibly and precisely modulated. It should be noted that the above relationship is based on empirical formulas or approximate calculations under specific oxidation process conditions. In other embodiments, the relationship between the final thickness Y of the stepped dielectric layer 109 and the initial thickness Y1 and the thickness Y2 of the second dielectric layer 108 may be affected by various factors and exhibit different functional relationships. For example, during the cleaning step before growing the second dielectric layer 108 (such as using hydrofluoric acid to remove the native oxide layer), the surface of the first dielectric layer 105 may undergo pre-etching, resulting in partial loss; or, due to the limited diffusion rate of the oxidant through the existing first dielectric layer 105 to the silicon interface, the oxidation rate decreases with increasing thickness, causing the actual thickness increase ratio to change. Therefore, the coefficients in the relationship may not be strictly 0.5, but may fluctuate within a certain range, or follow a more complex nonlinear superposition relationship. Regardless of the specific mathematical relationship, the core technical feature of this embodiment is that by retaining the first dielectric layer 105 and performing secondary growth, the thickness Y of the final stepped dielectric layer 109 located below the field plate is significantly greater than the thickness Y2 of the second dielectric layer 108 located above the channel, thereby forming a physically stepped structure to optimize the electric field.
[0049] In some embodiments, in step four, the length of the stepped dielectric layer 109 corresponds to the distance between the edge of the isolation structure 103 and the edge of the preset position of the body region. This length is the dimension of the stepped oxide layer in the horizontal direction. Since the etching boundary of the first dielectric layer 105 is defined by the body mask (corresponding to the edge of the body region 107), and the other boundary is the edge of the isolation structure 103, the length of the stepped dielectric layer 109 is actually determined by the spacing between the opening edge of the body mask and the isolation structure 103. This dimension defines the length of the region where the field plate extends above the drift region 102 and is supported by a thicker dielectric, thus playing a geometrical role in smoothing the electric field distribution.
[0050] Then, step five is performed: conductive material is deposited and patterned over the second dielectric layer 108, the stepped dielectric layer 109, and the isolation structure 103 to form the gate and field plate structure 110. The stepped dielectric layer 109 is located between the isolation structure 103 and the second dielectric layer 108 and is covered by the field plate structure 110 to form a stepped field plate structure.
[0051] like Figures 5 to 6 As shown, after forming the gate and field plate structure 110 and before performing source and drain ion implantation, it is necessary to remove the dielectric layer above the preset positions of the source and drain. Specifically, using the gate and field plate structure 110 as a self-aligned mask, or in conjunction with additional photolithography processes, the portion of the second dielectric layer 108 and the portion of the stepped dielectric layer 109 not covered by the gate and field plate structure 110 are removed by wet etching or dry etching. This step exposes the surfaces of the body region 107 and the drift region 102, ensuring that the subsequent heavily doped source and drain regions 111 and 112 can be formed directly on the surface of the semiconductor substrate.
[0052] In some embodiments, in step five, the conductive material is polycrystalline silicon. For example... Figure 6 As shown, the conductive material can also include amorphous silicon, metals (such as aluminum, copper, tungsten, titanium, tantalum), metal nitrides (such as titanium nitride, tantalum nitride), metal silicides (such as cobalt silicide, nickel silicide, tungsten silicide), or their composite stacked structures. The deposition process can employ low-pressure chemical vapor deposition (LPCVD) to deposit polycrystalline silicon, and can perform in-situ doping or subsequent ion implantation doping to reduce resistivity. The patterning process includes coating the conductive material with photoresist, performing exposure and development using a gate photomask, and using an anisotropic dry etching process to remove excess conductive material. The formed gate and field plate structure 110 not only serves as the gate electrode for controlling the channel but also extends and covers the stepped dielectric layer 109 and part of the isolation structure 103, forming a polycrystalline silicon field plate. This stepped field plate structure utilizes the stepped transition StepOxide (i.e., the stepped dielectric layer 109) to achieve a smooth transition from thin gate oxide to thick field oxide. When a voltage is applied to the gate, the field plate induces charges on the surface of the drift region 102. Due to the presence of the stepped dielectric layer 109, the potential lines are stretched in the horizontal direction, effectively reducing the electric field peaks at the gate edge and on the surface of the drift region 102, thus preventing premature breakdown. At the same time, the accumulation layer formed on the surface of the drift region 102 by the field plate effect facilitates current conduction, thereby significantly improving the breakdown voltage (BV) of the device without sacrificing or even reducing the specific on-resistance (Rsp), achieving bidirectional optimization of breakdown voltage performance and conduction performance.
[0053] In some embodiments, after step five, the method further includes step six: using the gate and field plate structure 110 as a mask, performing an ion implantation process to form a heavily doped source region at a preset location in the body region and a heavily doped drain region in the drift region. For example... Figure 6As shown, this step employs a self-aligned process. Using the gate and field plate structure 110 and a pre-formed photoresist pattern as a barrier layer, high concentrations of N-type impurities (such as arsenic and phosphorus) or P-type impurities (such as boron and boron difluoride) are implanted into the semiconductor substrates on both sides. A heavily doped source region 111 is formed on one side of the body region 107, and a heavily doped drain region 112 is formed on the side of the drift region 102 away from the channel. For N-type LDMOS, the heavily doped source and drain regions are N+ type; for P-type LDMOS, the heavily doped source and drain regions are P+ type. After implantation, a rapid thermal annealing (RTA) process is typically required to repair implantation damage and activate impurities, ultimately forming source and drain regions with good ohmic contact characteristics. This step completes the construction of the transistor's main structure, establishing the current input and output terminals.
[0054] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.
[0055] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.
Claims
1. A method for improving the breakdown voltage performance of LDMOS, characterized in that, At least including: Step 1: Provide a semiconductor substrate, on which an isolation structure and a drift region located within the semiconductor substrate have been formed; Step 2: Form a first dielectric layer on the surface of the semiconductor substrate, the first dielectric layer covering the drift region; Step 3: Using photolithography and etching processes, remove the first dielectric layer located above the preset position of the body region, expose the semiconductor substrate surface at the preset position of the body region, and retain the first dielectric layer located between the isolation structure and the preset position of the body region. Step 4: Perform a growth process to form a second dielectric layer on the exposed surface of the semiconductor substrate, while simultaneously thickening the retained first dielectric layer to form a stepped dielectric layer. Step 5: Deposit and pattern conductive material over the second dielectric layer, the stepped dielectric layer and the isolation structure to form the gate and field plate structure; The stepped medium layer is located between the isolation structure and the second medium layer, and is covered by the field plate structure to form a stepped field plate structure.
2. The method for improving the breakdown voltage performance of LDMOS according to claim 1, characterized in that: In step one, the isolation structure is a shallow trench isolation structure or a field oxide layer structure.
3. The method for improving the breakdown voltage performance of LDMOS according to claim 1, characterized in that: In step one, the semiconductor substrate is made of silicon.
4. The method for improving the breakdown voltage performance of LDMOS according to claim 1, characterized in that: In step two, the material of the first dielectric layer is silicon oxide.
5. The method for improving the breakdown voltage performance of LDMOS according to claim 1, characterized in that: In step two, the first dielectric layer is a pad oxide layer grown by a thermal oxidation process.
6. The method for improving the breakdown voltage performance of LDMOS according to claim 1, characterized in that: Prior to step two, the method further includes removing the natural oxide layer on the surface of the semiconductor substrate.
7. The method for improving the breakdown voltage performance of LDMOS according to claim 1, characterized in that: In step three, the photolithography process uses a photomask in the defined body region for exposure, without the need for an additional photomask layer.
8. The method for improving the breakdown voltage performance of LDMOS according to claim 1, characterized in that: In step four, the second dielectric layer is a gate oxide layer.
9. The method for improving the breakdown voltage performance of LDMOS according to claim 1, characterized in that: In step four, the thickness of the second dielectric layer is less than the thickness of the stepped dielectric layer.
10. The method for improving the breakdown voltage performance of LDMOS according to claim 1, characterized in that: In step four, the thickness Y of the stepped dielectric layer satisfies the following relationship: Y = Y1 + 1 / 2Y2, where Y1 is the thickness of the first dielectric layer formed in step two, and Y2 is the thickness of the second dielectric layer formed in step four.
11. The method for improving the breakdown voltage performance of LDMOS according to claim 1, characterized in that: In step four, the length of the stepped medium layer corresponds to the distance between the edge of the isolation structure and the edge of the preset position of the body region.
12. The method for improving the breakdown voltage performance of LDMOS according to claim 1, characterized in that: In step five, the conductive material is polycrystalline silicon.
13. The method for improving the breakdown voltage performance of LDMOS according to claim 1, characterized in that: After step five, the method further includes step six: using the gate and field plate structure as a mask, performing an ion implantation process to form a source heavily doped region at a preset position in the body region, and to form a drain heavily doped region in the drift region.