LDMOS device and method of manufacturing the same

Abstract

The application discloses an LDMOS device and a preparation method thereof, and belongs to the technical field of semiconductors. The LDMOS device comprises a first field plate and a second field plate; the first field plate is inserted into a drift region and penetrates through a gate oxide layer; the first field plate comprises a first PN junction; a PN junction interface of the first PN junction is higher than a surface of the drift region; the first PN junction only comprises first type ions in the drift region; in a gate structure opening state, a first PN junction depletion region boundary is moved due to electrostatic effect, so that a conductive channel is formed on the surface of the drift region; the first type ions are opposite to a conductive type of the drift region; and the conductive channel is the same as the conductive type of the drift region; and the second field plate is located on a surface of the gate oxide layer and close to one end of a drain region. The LDMOS device can have a higher breakdown voltage without affecting specific on-resistance.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, in particular to a LDMOS device and a preparation method thereof. BACKGROUND

[0002] LDMOS (Lateral double diffusion MOS) device is a key component of the whole power integrated circuit. The main parameters for measuring the performance of LDMOS include breakdown voltage (BV) and specific on-resistance (Rsp), and in general, the smaller the specific on-resistance is, the better, and the greater the breakdown voltage is, the better.

[0003] The LDMOS in the related art reduces the leakage current and increases the breakdown voltage by adding STI (Shallow Trench Isolation) between the source and the drain, but this also causes the Rsp of the LDMOS device to increase. SUMMARY

[0004] The present application provides a LDMOS device and a preparation method thereof, which can have a higher breakdown voltage without affecting the specific on-resistance. The technical solution at least includes the following solutions:

[0005] In a first aspect, the present application provides a LDMOS device, comprising a well region and a drift region on a semiconductor substrate, the conductivity type of the well region and the drift region being opposite, a source region being provided in the well region, a drain region being provided in the drift region, an upper surface of the junction of the well region and the drift region being provided with a gate structure, the gate structure comprising a polysilicon gate connected to the well region and the drift region, and a gate oxide layer between the polysilicon gate and the drift region; the LDMOS device further comprises a first field plate and a second field plate; the first field plate is inserted into the drift region and penetrates through the gate oxide layer, the first field plate comprises a first PN junction, the PN junction interface of the first PN junction is higher than the surface of the drift region, so that the first PN junction only includes first type ions in the drift region, and under the open state of the gate structure, the depletion region boundary of the first PN junction moves due to electrostatic effect, so that the first PN junction forms a conductive channel on the surface of the drift region, the first type ions are opposite to the conductivity type of the drift region, and the conductive channel is the same as the conductivity type of the drift region; the second field plate is located at one end of the surface of the gate oxide layer close to the drain region.

[0006] Optionally, the first PN junction further comprises a second type of ion, wherein the first type of ion and the second type of ion form a PN junction interface in the first PN junction, the first type of ion and the second type of ion are one of P+ ion and N+ ion, and the second type of ion is of the same conductivity type as the drift region.

[0007] Optionally, the source region, the drain region, the drift region, the conductive channel and the second type of ion are of a second conductivity type, the first type of ion and the well region are of a first conductivity type, and the first conductivity type is opposite to the second conductivity type.

[0008] Optionally, the first field plate is inserted into the drift region to a depth greater than a thickness of the gate oxide layer.

[0009] Optionally, the thickness of the gate oxide layer ranges from 1000 to 3000 angstroms, and the depth of the first field plate inserted into the drift region ranges from 3000 to 5000 angstroms.

[0010] Optionally, the second field plate is polysilicon.

[0011] In a second aspect, the present application further provides a preparation method of an LDMOS device, comprising: providing a semiconductor substrate, wherein an active region is formed on the semiconductor substrate; forming a shallow trench isolation structure STI in a drift region of the active region, and filling the STI; performing ion implantation on the drift region to form the drift region into a second conductivity type; performing ion implantation on a well region to form the well region into a first conductivity type, wherein the first conductivity type is opposite to the second conductivity type; depositing a gate oxide layer above the drift region; based on a first photolithography pattern, etching the gate oxide layer and an isolation material of the STI to obtain a first recess inserted into the drift region and penetrating through the gate oxide layer; depositing polysilicon on a surface of the first photolithography pattern to obtain a first polysilicon layer, and planarizing the first polysilicon layer to stay on the surface of the first photolithography pattern; using the first photolithography pattern as a mask, performing ion implantation twice on the polysilicon in the first recess to obtain a first field plate; after removing the first photolithography pattern, depositing polysilicon on a surface of the gate oxide layer to obtain a second polysilicon layer, wherein the residual polysilicon on both sides of the gate oxide layer is removed together with the first photolithography pattern; based on a second photolithography pattern, etching the second polysilicon layer to obtain a polysilicon gate and a second field plate.

[0012] Optionally, the etching the isolation material of the STI and the gate oxide layer based on the first photoetching pattern to obtain the first recess inserted into the drift region and penetrating the gate oxide layer comprises: etching from the surface of the gate oxide layer based on the first photoetching pattern until the isolation material of the STI is etched completely, and the first recess is obtained after a pad oxide layer is formed on the surface of the trench; and the twice ion implantation of the polysilicon in the first recess with the first photoetching pattern as a mask to obtain the first field plate comprises: implanting a first type of ion into the polysilicon in the first recess first, and then implanting a second type of ion into the polysilicon in the first recess with the first photoetching pattern as a mask to obtain the first field plate, the first type of ion being of a first conductive type, and the second type of ion being of a second conductive type.

[0013] Optionally, the depth of the STI is greater than the thickness of the gate oxide layer.

[0014] Optionally, the method further comprises: performing ion implantation on the well region and the drift region to form a source region and a drain region.

[0015] The technical scheme provided by the embodiment of the present application has at least the following beneficial effects:

[0016] In the embodiment, the LDMOS device comprises a well region and a drift region on a semiconductor substrate, the well region and the drift region are of opposite conductive types, the well region is provided with a source region, the drift region is provided with a drain region, an upper surface of a junction of the well region and the drift region is provided with a gate structure, the gate structure comprises a polysilicon gate connected to the well region and the drift region, and a gate oxide layer between the polysilicon gate and the drift region; the LDMOS device further comprises a first field plate and a second field plate; the first field plate is inserted into the drift region and penetrates the gate oxide layer, the first field plate comprises a first PN junction, a PN junction interface of the first PN junction is higher than a surface of the drift region, so that the first PN junction only comprises a first type of ion in the drift region, and in a turned-on state of the gate structure, a depletion region boundary of the first PN junction is moved due to electrostatic effect, so that a conductive channel is formed on the surface of the drift region by the first PN junction, the first type of ion is of a conductive type opposite to that of the drift region, and the conductive channel is of a conductive type same to that of the drift region; the second field plate is located at one end of the surface of the gate oxide layer close to the drain region.

[0017] The unexpected technical effect achieved by the present application is that: in the case of the gate structure of the LDMOS device being turned on, since the first field plate is inserted into the drift region and penetrates the gate oxide layer, the voltage of the gate structure will affect the first PN junction in the first field plate, and the depletion region boundary of the first PN junction moves due to the electrostatic effect, and a reverse type conduction channel (i.e. a conduction channel) is formed in the first type of ions at the first PN junction. In the case of the carrier being an electron, the electron can move along the surface of the drift region from the source electrode and pass through the conduction channel to reach the drain region, forming a current path. The current path is the same as the current path of the conventional LDMOS located on the surface of the drift region, and does not affect the Rsp of the LDMOS. Since the second field plate is located on the surface of the gate oxide layer close to one end of the drain region, in the case of the gate structure being turned on, the second field plate here is equivalent to a controllable conductor equipotential surface, and therefore the existence of the second field plate is equivalent to introducing a new equipotential surface into the drain region, which can make the electric field of the drain region redistribute (convert the concentrated peak of the electric field from the drain region into a more uniform distribution), avoid the electric field lines being too concentrated at the drain region, and thus improve the on-state breakdown voltage of the LDMOS. BRIEF DESCRIPTION OF DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without creative labor.

[0019] Figure 1 A structural schematic diagram of an LDMOS device in the case of a gate structure being turned on is shown according to an exemplary embodiment of the present application;

[0020] Figure 2 A structural schematic diagram of an LDMOS device in the case of a gate structure being turned off is shown according to an exemplary embodiment of the present application;

[0021] Figure 3 I-V curve diagrams of LDMOS devices before and after adding a second field plate are shown;

[0022] Figure 4 Spatial distribution diagrams of electric field intensity of LDMOS devices before and after adding a second field plate are shown;

[0023] Figure 5 Collision ionization rate diagrams of LDMOS devices before and after adding a second field plate are shown;

[0024] Figure 6 A flowchart of a preparation method of an LDMOS device is shown according to an exemplary embodiment of the present application;

[0025] Figure 7 is a process flow diagram for preparing the first recess;

[0026] Figure 8 is a process flow diagram for preparing the first field plate;

[0027] Figure 9 is a process flow diagram for preparing the second field plate and the polysilicon gate.

[0028] BRIEF DESCRIPTION OF DRAWINGS

[0029] 10 - semiconductor substrate; 11 - well region; 12 - drift region; 13 - body region; 14 - source region; 15 - drain region; 16 - gate oxide layer; 17 - gate; 18 - first field plate; 181 - second type of ions in the first field plate; 182 - first type of ions in the first field plate; 183 - conductive channel; first recess 180; 19 - second field plate; 71 - first photoetching pattern; 72 - first polysilicon layer; 73 - second polysilicon layer; 74 - third photoetching pattern. DETAILED DESCRIPTION

[0030] Unless otherwise defined, technical or scientific terms used herein shall have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains. The terminology used in the description of the application herein and the claims that follow is not intended to be limiting of the application. Similarly, the terms "first", "second", "third", etc. are used herein and in the claims to mean "first", "second", "third" etc. respectively, and are not intended to denote or imply any ordinal, quantitative or importance relationship between the entities so described. Likewise, the terms "a" and "an" and "the" and similar referents in the context of describing the application are to be construed to be a "one" or "one or more" unless otherwise indicated. The terms "comprise", "comprising", "comprises", "include", "including", "includes", "contain", "containing", "contains", "characterized by" and the like are not intended to be limiting of the component, element or object that "comprises", "comprising", "includes", "including", "contains", "characterized by" or the like to the exclusion of any other component, element or object not expressly listed or enumerated. Recitation of ranges of values herein are merely intended to serve as a shorthand method of referring individually to each separate value falling within the range, unless otherwise indicated herein and each separate value is incorporated in the specification as if it were individually recited herein. The use of any and all examples, or exemplary language (e.g., "such as" and "preferably"), provided herein, is intended merely to better illuminate the application and does not pose a limitation on the scope of the application unless otherwise claimed. The use of "about" in reference to a given value is intended to encompass the given value and variations of the given value that are within the range of error for the particular measurement, device, or apparatus being employed to measure the given value, unless otherwise indicated.

[0031] In order to make the objects, technical solutions and advantages of the present application clearer, the following will further describe the embodiments of the present application in detail with reference to the accompanying drawings.

[0032] Figure 1 shows a structure diagram of an LDMOS device in an on state of a gate structure provided by an exemplary embodiment of the present application.

[0033] Reference is made to Figure 1The LDMOS device comprises a well region 11 and a drift region 12 on a semiconductor substrate 10, the well region 11 and the drift region 12 are opposite in conductive type, a source region 14 is arranged in the well region 11, a drain region 15 is arranged in the drift region 12, and a gate structure is arranged on the upper surface of the junction of the well region 11 and the drift region 12, the gate structure comprises a polysilicon gate 17 connecting the well region and the drift region, and a gate oxide layer 16 between the polysilicon gate 17 and the drift region 12.

[0034] The LDMOS device further comprises a first field plate 18 and a second field plate 19.

[0035] The first field plate 18 is inserted into the drift region 12 and penetrates the gate oxide layer 16, the first field plate 18 comprises a first PN junction, the PN junction interface of the first PN junction is higher than the upper surface of the drift region 12, so that the first PN junction only comprises first type ions 182 in the drift region, and in the open state of the gate structure, the depletion region boundary of the first PN junction moves due to the electrostatic effect, so that a conductive channel 183 is formed on the surface of the drift region 12, the first type ions 182 are opposite in conductive type to the drift region 12, and the conductive channel 183 is the same in conductive type to the drift region 12.

[0036] The second field plate 19 is arranged at one end of the gate oxide layer surface close to the drain region 15, and the polysilicon gate 17 and the second field plate 19 are arranged with a spacing, and the first field plate 18 is arranged in the spacing region.

[0037] In the open state of the gate structure of the LDMOS device, since the first field plate 18 is inserted into the drift region 12 and penetrates the gate oxide layer 16, the voltage of the gate structure will affect the first PN junction in the first field plate, the depletion region boundary of the first PN junction moves due to the electrostatic effect, and a reverse type conductive channel (i.e. the conductive channel 183) is formed in the first type ions 182 of the first PN junction. In the case of electrons as carriers, the electrons can move along the surface of the drift region 12 from the source region 14 and pass through the conductive channel 183 to reach the drain region 15, forming a current path. The current path is the same as the current path of the conventional LDMOS located on the surface of the drift region, and does not affect the Rsp of the LDMOS. Since the second field plate is arranged at one end of the gate oxide layer surface close to the drain region, in the open state of the gate structure, the second field plate 19 here is equivalent to a controllable conductor equipotential surface, so the existence of the second field plate 19 is equivalent to introducing a new equipotential surface into the drain region, which can make the electric field of the drain region redistribute (convert the concentrated peak of the electric field of the drain region into a more uniform distribution), avoid the electric field lines of the drain region 15 being too concentrated, and thus improve the on-state breakdown voltage of the LDMOS.

[0038] In the present embodiment, the semiconductor substrate 10 can be any substrate material in the related art, such as a bulk silicon substrate or a silicon-on-insulator substrate, etc., which is not limited in the present embodiment. Optionally, the semiconductor substrate 10 has a first conductivity type (e.g., P-type).

[0039] The LDMOS device includes a well region 11 and a drift region 12 on the semiconductor substrate 10, the well region 11 and the drift region 12 having opposite conductivity types. The well region 11 is of a first conductivity type (e.g., P-type), and the drift region 12 is of a second conductivity type (e.g., N-type).

[0040] In an N-type LDMOS, the first conductivity type is P-type, and the second conductivity type is N-type. In a P-type LDMOS, the first conductivity type is N-type, and the second conductivity type is P-type. Hereinafter, an N-type LDMOS is taken as an example for illustration, which is not limited in this way.

[0041] The well region 11 and the drift region 12 are adjacent and in contact. The well region 11 has a source region 14 therein, the source region 14 being of the second conductivity type (e.g., N-type). Optionally, the well region 11 further has a body region 13 therein, the body region 13 being adjacent and in contact with the source region 14 and located on a side of the source region 14 away from the drift region 12. The body region 13 is of the first conductivity type (e.g., P-type).

[0042] The drift region 12 has a drain region 15 therein, the drain region 15 being of the second conductivity type (e.g., N-type).

[0043] An upper surface of a junction between the well region 11 and the drift region 12 is provided with a gate structure, the gate structure including a polysilicon gate 17 connecting the well region and the drift region, and a gate oxide layer 16 between the polysilicon gate 17 and the drift region 12. In the present embodiment, the gate oxide layer 16 is only located above the drift region 12 and is not connected with the well region 11. In some embodiments, the gate oxide layer 16 connects the well region 11 and the drift region 12, and the polysilicon gate 17 is stacked on the gate oxide layer 16 and is not in contact with the well region 11.

[0044] Optionally, the gate oxide layer 16 is silicon dioxide.

[0045] A first field plate 18 is inserted into the drift region 12 and penetrates the gate oxide layer 16, the first field plate 18 including a first PN junction.

[0046] In the off state of the gate structure, the PN junction interface of the first PN junction (i.e. the position where the first type of ions 182 and the second type of ions 181 intersect) is higher than the surface of the drift region 12, so that the first PN junction only includes the first type of ions 182 in the drift region 12. The first type of ions 182 is opposite to the conduction type of the drift region 12. The first type of ions and the second type of ions are one of P+ ions and N+ ions. Here, the P+ ions represent heavily doped P-type ions (such as boron ions, indium ions, gallium ions), and the N+ ions represent heavily doped N-type ions (such as phosphorus ions, arsenic ions, antimony ions).

[0047] Optionally, the first type of ions 182 is of a first conduction type (for example, P-type), and the second type of ions 181 is of a second conduction type (for example, N-type).

[0048] Optionally, the first field plate is polycrystalline silicon into which P+ ions and N+ ions are implanted.

[0049] Figure 2 A structural schematic diagram of the LDMOS device in the off state of the gate structure provided by an exemplary embodiment of the present application is shown.

[0050] For example, the case where the LDMOS is an N-type LDMOS is taken as an example to be described in combination with Figure 2 When the LDMOS is an N-type LDMOS, the conduction type of the drift region 12 is N-type, and the first type of ions 182 is P+ ions. In the off state of the gate structure, the first field plate 18 in the drift region 12 only includes the first type of ions 182, and there is no conduction channel 183 in the first field plate 18, that is, the N-type drift region only includes P+ ions. At this time, due to the existence of the first type of ions 182 (the P+ ions block the surface of the drift region 12), the source region 14 and the drain region 15 cannot move on the surface of the drift region 12. Therefore, in the off state of the gate structure, the moving path of the electrons is from the source region 14 to the drain region 15 by bypassing the position below the first field plate 18. Compared with the movement of the electrons directly on the drift region 12, the length of the moving path of the electrons in the off state of the gate structure is increased, thereby improving the off-state breakdown voltage of the LDMOS.

[0051] In summary, in combination with the influence of the first field plate 18 on the LDMOS in the on state of the gate structure and the influence of the first field plate 18 on the LDMOS in the off state of the gate structure, it can be seen that the first field plate 18 can improve the off-state breakdown voltage of the LDMOS without affecting the Rsp of the LDMOS.

[0052] Optionally, the depth at which the first field plate 18 is inserted into the drift region 12 is greater than the thickness of the gate oxide layer 16. In this way, the length of the conduction path formed in the off state of the gate structure can be increased as much as possible.

[0053] Optionally, the thickness of the gate oxide layer ranges from 1000 to 3000 angstroms, for example, 1000 angstroms, 2000 angstroms or 3000 angstroms.

[0054] The depth at which the first field plate is inserted into the drift region ranges from 3000 to 5000 angstroms, for example, 3000 angstroms, 4000 angstroms, or 5000 angstroms.

[0055] The second field plate 19 is located on the surface of the gate oxide layer near the drain region 15. When the gate structure is turned on, the second field plate 19 here is equivalent to a controllable conductor equipotential surface. Therefore, the presence of the second field plate 19 is equivalent to introducing a new equipotential surface in the drain region. This equipotential surface can redistribute the electric field in the drain region (transforming the electric field from a concentrated peak in the drain region to a more uniform distribution), avoiding excessive concentration of electric field lines at the drain region 15, thereby improving the on-state breakdown voltage of the LDMOS.

[0056] Optionally, both the polysilicon gate 17 and the second field plate 19 are polysilicon structures.

[0057] Figure 3 This is a schematic diagram of the IV curves of the LDMOS before and after adding the second field plate. Figure 3 Part (a) is a schematic diagram of the IV curve of the LDMOS before the addition of the second field plate 19 (that is, before the addition of the second field plate 19). Figure 3 Part (b) is a schematic diagram of the IV curve of the LDMOS after adding the second field plate 19. The horizontal axis represents the voltage of the LDMOS (unit: V), and the vertical axis represents the current density of the LDMOS (unit: ...). ). Figure 3 In this case, the gate voltage (Vg) is constant at 5V. Figure 3 Both IV curves in the diagram illustrate how the drain current changes with the drain-source voltage when the gate voltage (Vg) is constant at 5V.

[0058] contrast Figure 3 part (a) and Figure 3 As can be seen from part (b), without the addition of the second field plate 19, the breakdown voltage of the LDMOS is approximately 43V, while with the addition of the second field plate, the breakdown voltage of the LDMOS is greater than 50V. This demonstrates that adding the second field plate can increase the on-state breakdown voltage of the LDMOS.

[0059] Figure 4 This is a schematic diagram of the spatial distribution of the electric field intensity of the LDMOS before and after adding the second field plate. Figure 5 This is a schematic diagram of the collisional ionization rate of LDMOS before and after adding the second field plate. Figure 4 Part (a) is the spatial distribution of the electric field intensity of the LDMOS in front of the second field plate;Figure 4 Part (b) shows the spatial distribution of the electric field intensity of the LDMOS after the addition of the second field plate; Figure 5 Part (a) is a schematic diagram of increasing the collisional ionization rate of the LDMOS in front of the second field plate; Figure 5 Part (b) is a schematic diagram of the impact ionization rate of the LDMOS after adding a second field plate. Figure 4 and Figure 5 The horizontal axis represents the horizontal coordinate of the device cross-section diagram, and the vertical axis represents the vertical coordinate of the device cross-section diagram.

[0060] Figure 4 In the diagram, colors from blue to red represent increasing electric field strength. The red and yellow areas represent regions where the electric field is concentrated and at its highest intensity; these are the weakest points where the device is most susceptible to electrical breakdown. An ideal design should ensure a as uniform as possible electric field distribution, avoiding sharp peaks. For example... Figure 4 As shown in part (a), before the addition of the second field plate, the area of ​​electric field concentration and highest intensity is relatively large; Figure 4 As shown in part (b), the range of electric field concentration and highest intensity is significantly reduced after adding the second field plate. Therefore, the presence of the second field plate enables the electric field in the drain region to be redistributed (transforming the electric field from the concentrated peak value in the drain region to a more uniform distribution), avoiding excessive concentration of the electric field lines at drain region 15, thereby improving the on-state breakdown voltage of the LDMOS.

[0061] Figure 5 In the diagram, warm-colored areas represent regions with high collisional ionization rates, with the transition from blue to yellow to red indicating an increase in collisional ionization rate from low to high. Orange represents the high collisional ionization rate region, while blue represents the low collisional ionization rate region. The trigger point for open-state avalanche breakdown is the location with the highest collisional ionization rate along the carrier path.

[0062] like Figure 5 As shown in part (a), before the addition of the second field plate, the region with the highest collisional ionization rate of the LDMOS is concentrated below the gate, meaning that the drift region below the gate is prone to on-state breakdown. Figure 5 As shown in section (b), after adding the second field plate, the region with the highest collisional ionization rate of the LDMOS shifts to the drift region below the region between the gate and the second field plate. Therefore, the presence of the second field plate changes the location of the region with the highest collisional ionization rate, protecting the area below the gate and resulting in a smoother electric field distribution along the current path. Consequently, the device can withstand a higher drain voltage in the on-state, which is equivalent to increasing the on-state breakdown voltage.

[0063] Although the presence of the second field plate 19 can improve the on-state breakdown voltage, since the second field plate 19 is located on the surface of the gate oxide layer 16 close to one end of the drain region 15 and the distance between the second field plate 19 and the source region 14 is closer than that between the second field plate 19 and the drain region 15, the presence of the second field plate 19 shortens the distance between the drain region 15 and the source region 14, resulting in a decrease in the off-state breakdown voltage of the LDMOS. Since the first field plate 18 can increase the off-state breakdown voltage without affecting the Rsp of the LDMOS, the off-state breakdown voltage increased by the first field plate 18 offsets the decrease in the breakdown voltage caused by the second field plate 19. Quantitative research and analysis show that the value of the off-state breakdown voltage increased by the first field plate 18 is greater than the value of the decrease in the breakdown voltage caused by the second field plate 19, that is, the off-state breakdown voltage of the final LDMOS device is increased.

[0064] In summary, after the first field plate 18 and the second field plate 19 are added to the LDMOS, the off-state breakdown voltage of the LDMOS is increased, and the Rsp of the LDMOS is not affected. Since the second field plate 19 has the effect of increasing the on-state breakdown voltage of the LDMOS, after the first field plate 18 and the second field plate 19 are added to the LDMOS, the on-state breakdown voltage and the off-state breakdown voltage of the LDMOS can be increased, and the Rsp of the LDMOS is not affected.

[0065] Figure 6 A flowchart of a method for manufacturing an LDMOS device provided by an exemplary embodiment of the present application is shown. The method is used to manufacture the LDMOS device described in the above embodiment. Figure 1 to Figure 2 The method includes the following steps. Figure 6

[0066] In step 601, a semiconductor substrate is provided, and an active region is formed on the semiconductor substrate.

[0067] In this embodiment, before the active region is formed on the semiconductor substrate 10, a zero layer for marking can be first formed on the semiconductor substrate 10 by a photolithography process; then N-type buried layer ion implantation, P-type epitaxial layer growth and deep N-well ion implantation can be performed on the zero layer, and finally the active region is formed.

[0068] In step 602, an STI is formed in the drift region of the active region.

[0069] In implementation, any etching process in the related art can be used to form a trench in the drift region 12 of the active region, and then the STI (Shallow Trench Isolation) is formed by filling the trench with an isolation material and then planarizing, and the isolation material filled can be silicon dioxide.

[0070] ​In the filling of the isolation material, a HDP DEP (High Density Plasma Chemical Vapor Deposition) process can be used to deposit silicon dioxide, and a CMP (Chemical Mechanical Planarization) process can be used to remove the excess silicon dioxide, so that the surface of the active region is restored to be flat.

[0071] After the STI is filled, the isolation material in the STI is etched and polysilicon is filled, so as to form the first field plate 18 in the drift region 12.

[0072] In step 603, ions are implanted into the drift region, so that the drift region is formed to be of the second conductivity type.

[0073] In the case where the LDMOS is an N-type LDMOS, the second conductivity type is N-type, and the type of the ions implanted into the drift region 12 in step 603 is N-type.

[0074] In the case where the LDMOS is a P-type LDMOS, the second conductivity type is P-type, and the type of the ions implanted into the drift region 12 in step 603 is P-type.

[0075] In the ion implantation, a mask plate is formed by a photoresist process to shield the non-implanted region.

[0076] In step 604, ions are implanted into the well region, so that the well region is formed to be of the first conductivity type.

[0077] In the case where the LDMOS is an N-type LDMOS, the first conductivity type is P-type, and the type of the ions implanted into the well region 11 in step 604 is P-type.

[0078] In the case where the LDMOS is a P-type LDMOS, the first conductivity type is N-type, and the type of the ions implanted into the well region 11 in step 604 is N-type.

[0079] As can be seen, after the filling of the isolation material, a plurality of ion implantation processes (such as steps 603 and 604) are still needed. If the material of the field plate (polysilicon) is directly used as the isolation material, the plurality of ion implantation processes will introduce impurities into the field plate, and thus the first PN junction of the first field plate 18 formed later may have impurities. In order to ensure the purity of the ions in the first PN junction, silicon dioxide is used as the isolation material in step 602, and the first field plate 18 is prepared later.

[0080] In step 605, a gate oxide layer is prepared above the drift region.

[0081] Optionally, the gate oxide layer 16 is made of silicon dioxide.

[0082] Optionally, the depth of the STI is greater than the thickness of the gate oxide layer when the STI and the gate oxide layer 16 are prepared. The depth of the STI determines the depth of the first field plate 18 inserted into the drift region 12, so the depth of the STI should be greater than the thickness of the gate oxide layer.

[0083] In step 606, the gate oxide layer and the isolation material of the STI are etched based on the first photoetching pattern, to obtain a first groove inserted into the drift region and penetrating through the gate oxide layer.

[0084] Optionally, step 606 comprises: etching from the surface of the gate oxide layer until the isolation material of the STI is etched completely, and obtaining the first groove after a pad oxide layer is formed on the surface of the groove based on the first photoetching pattern.

[0085] Figure 7 is a process flow diagram for preparing the first groove. Figure 7 (a) of is a diagram of the device after the gate oxide layer 16 is deposited in step 605; Figure 7 (b) of is a diagram of coating photoresist and exposing and developing to obtain the first photoetching pattern 71, Figure 7 (c) of is a diagram of etching the first groove 180. As Figure 7 As shown in (a) and (b) of, first, the first photoetching pattern 71 is formed on the surface of the gate oxide layer, and then etching is performed with the first photoetching pattern 71 as a mask. During etching, the etching depth is equal to the depth of the gate oxide layer plus the depth of the STI. After etching, the groove is exposed, and at this time, a pad oxide layer (silicon dioxide generated by thermal oxidation) can be formed on the surface of the groove. In this way, a first groove 180 inserted into the drift region and penetrating through the gate oxide layer is obtained as shown in (c) of. Figure 7

[0086] In step 607, polycrystalline silicon is deposited on the surface of the first photoetching pattern to obtain a first polycrystalline silicon layer, the first polycrystalline silicon layer is planarized to stay on the surface of the first photoetching pattern, and then the polycrystalline silicon in the first groove is ion implanted twice with the first photoetching pattern as a mask to obtain the first field plate.

[0087] Optionally, step 607 comprises the following three steps. Figure 8 is a process flow diagram for preparing the first field plate, and the following will describe step 607 in combination with Figure 8 .

[0088] First, polycrystalline silicon is deposited on the surface of the first photoetching pattern to obtain a first polycrystalline silicon layer.

[0089] As shown in (a) of, the first polycrystalline silicon layer is deposited on the surface of the first photoetching pattern. Figure 8 ​As shown in part (a) of FIG. 6, after etching the first recess 180 based on the first photoetching pattern 71, the first photoetching pattern is not removed, but polycrystalline silicon is directly deposited on the surface of the first photoetching pattern, at this time, the first recess 180 is also filled with polycrystalline silicon, thereby obtaining the first polycrystalline silicon layer 72. And due to the existence of the first recess 180, the position corresponding to the first recess 180 in the surface of the first polycrystalline silicon layer 72 is slightly concave.

[0090] In the second step, the first polycrystalline silicon layer is planarized by the CMP process and remains on the surface of the first photoetching pattern.

[0091] As shown in part (b) of FIG. 6, after planarizing the first polycrystalline silicon layer 72 and remaining on the surface of the first photoetching pattern 71, there is still polycrystalline silicon in the first recess 180, and in addition, there is residual polycrystalline silicon on both sides of the gate oxide layer 16. Figure 8

[0092] In the third step, the first polycrystalline silicon in the first recess is first implanted with the first type of ions and then implanted with the second type of ions, thereby obtaining the first field plate.

[0093] The first type of ions is of the first conductivity type, and the second type of ions is of the second conductivity type.

[0094] Due to the difference in conductivity type between the first type of ions and the second type of ions, a PN junction (i.e., the first PN junction) will be formed in the polycrystalline silicon in the first recess, and finally the first field plate 18 is obtained.

[0095] As shown in part (c) of FIG. 6, under the shielding of the first photoetching pattern 71, ion implantation can be realized on the polycrystalline silicon in the first recess 180 (the ion implantation will also affect the residual polycrystalline silicon on both sides of the gate oxide layer 16, but the residual polycrystalline silicon on both sides of the gate oxide layer 16 will be removed later, so it does not affect the preparation process of the first field plate 18,The effect of ion implantation on the residual polycrystalline silicon on both sides of the gate oxide layer 16 is not shown in part (c) of FIG. 6). When ion implantation is performed, the first type of ions 182 is first implanted, and then the second type of ions 181 is implanted. The implantation depth is adjusted by adjusting the ion implantation dose and energy to form the first PN junction, and the PN junction interface of the first PN junction is higher than the surface of the drift region 12. Figure 8 Figure 8 In step 608, after removing the first photoetching pattern, polycrystalline silicon is deposited on the surface of the gate oxide layer to obtain a second polycrystalline silicon layer. When the first photoetching pattern is removed, the residual polycrystalline silicon on both sides of the gate oxide layer is also removed.

[0096] As shown in part (d) of FIG. 6, after removing the residual polycrystalline silicon on both sides of the gate oxide layer 16, the first field plate 18 is obtained.

[0097] As shown in part (a) of FIG. 6, after etching the first recess 180 based on the first photoetching pattern 71, the first photoetching pattern is not removed, but polycrystalline silicon is directly deposited on the surface of the first photoetching pattern, at this time, the first recess 180 is also filled with polycrystalline silicon, thereby obtaining the first polycrystalline silicon layer 72. And due to the existence of the first recess 180, the position corresponding to the first recess 180 in the surface of the first polycrystalline silicon layer 72 is slightly concave. Figure 8 ​As shown in section (d), after removing the first photolithographic pattern 71, it can be seen that the upper surface of the first field plate 18 is slightly higher than the upper surface of the gate oxide layer 16, and the height difference between the upper surface of the first field plate 18 and the upper surface of the gate oxide layer 16 is equal to the thickness of the first photolithographic pattern 71. When the first photolithographic pattern is removed, the residual polysilicon on both sides of the gate oxide layer 16 is also removed.

[0098] Figure 9 This is a schematic diagram of the process flow for fabricating the second field plate and the polysilicon gate. Figure 9 Part (a) is a schematic diagram of the fabrication of the second polysilicon layer 73 and the second photolithographic pattern 74; Figure 9 Part (b) is a schematic diagram of the fabrication of the polysilicon gate 17 and the second field plate 19. Figure 9 Part (c) is a schematic diagram of the LDMOS provided in this embodiment.

[0099] like Figure 9 As shown in part (a), after depositing polysilicon on the surface of the gate oxide layer 16 to obtain the second polysilicon layer 73, photoresist is coated on the second polysilicon layer 73 and the second photolithographic pattern 74 is formed by exposure and development.

[0100] In step 609, based on the second photolithography pattern, the second polysilicon layer is etched to obtain the polysilicon gate and the second field plate.

[0101] like Figure 9 As shown in part (b), after etching the second polysilicon layer 73 based on the second photolithography pattern 74, a polysilicon gate 17 and a second field plate 19 can be obtained.

[0102] When etching the second polysilicon layer 73 based on the second photolithography pattern 74, selective etching (i.e., etching only the polysilicon without etching the well region 11, drift region 12, and gate oxide layer 16) can be performed on the second polysilicon layer 73, while setting the etching depth. This set etching depth can etch away the portion of the second polysilicon layer 73 that is not covered by the second photolithography pattern 74. Since the etching depth is set and the first field plate 18 is essentially located in the groove of the gate oxide layer 16, the contact surface between the first field plate 18 and the etching material is small. The small contact surface means that even though both the first field plate 18 and the second polysilicon layer 73 are made of polysilicon, the etching rate of the first field plate 18 during this etching process is also low. Therefore, the etching process may only slightly damage the upper surface of the first field plate 18 (the surface of the second type of ions 181), without affecting the performance of the first field plate. Even if the top of the first field plate 18 is simultaneously etched to the same height as the upper surface of the gate oxide layer 16, it will not affect the solution of the technical problem of the present invention.

[0103] After obtaining the polysilicon gate 17 and the second field plate 19, the second photolithography pattern 74 needs to be removed.

[0104] Optionally, the method further comprises: performing ion implantation in the well region and the drift region to form the source region, the drain region and the body region. The implementation of forming the source region and the drain region is more in the related art, and thus the detailed description is omitted here.

[0105] As shown in part (c) of FIG. 1, after the body region 13, the source region 14 and the drain region 15 are formed, the LDMOS device in the embodiment can be obtained. Figure 9 Figure 9

[0106] The above description is only optional embodiments of the present application, and is not intended to limit the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.​

Claims

1. An LDMOS device, characterized in that, The device includes a well region and a drift region located on a semiconductor substrate, wherein the well region and the drift region have opposite conductivity types, a source region is provided in the well region, a drain region is provided in the drift region, and a gate structure is provided on the upper surface at the junction of the well region and the drift region. The gate structure includes a polysilicon gate connecting the well region and the drift region, and a gate oxide layer between the polysilicon gate and the drift region. The LDMOS device further includes: a first field plate and a second field plate. The first field plate is inserted into the drift region and penetrates the gate oxide layer. The first field plate includes a first PN junction. The PN junction interface of the first PN junction is higher than the surface of the drift region, so that the first PN junction includes only first-type ions in the drift region. When the gate structure is turned on, the depletion region boundary of the first PN junction moves due to electrostatic effect, so that the first PN junction forms a conductive channel on the surface of the drift region. The first-type ions have the opposite conductivity type to the drift region, and the conductive channel has the same conductivity type as the drift region. The second field plate is located on the surface of the gate oxide layer near the drain region.

2. The LDMOS device according to claim 1, characterized in that, The first PN junction also includes a second type of ion. In the first PN junction, the position where the first type of ion and the second type of ion intersect forms a PN junction interface. The first type of ion and the second type of ion are respectively one of P+ ions and N+ ions. The second type of ion has the same conductivity type as the drift region.

3. The LDMOS device according to claim 2, characterized in that, The source region, the drain region, the drift region, the conductive channel, and the second type of ions constitute a second conductivity type, while the first type of ions and the well region constitute a first conductivity type, the first conductivity type being the opposite of the second conductivity type.

4. The LDMOS device according to any one of claims 1 to 3, characterized in that, The depth to which the first field plate is inserted into the drift region is greater than the thickness of the gate oxide layer.

5. The LDMOS device according to claim 4, characterized in that, The thickness of the gate oxide layer ranges from 1000 to 3000 angstroms; The depth at which the first field plate is inserted into the drift region ranges from 3000 to 5000 angstroms.

6. The LDMOS device according to any one of claims 1 to 3, characterized in that, The second field plate is polycrystalline silicon.

7. A method for fabricating an LDMOS device, characterized in that, The method includes: A semiconductor substrate is provided, and an active region is formed on the semiconductor substrate; A shallow trench isolation structure (STI) is formed in the drift region of the active region. Ion implantation is performed into the drift region to form a second conductivity type in the drift region; Ion implantation is performed into the well region to form a first conductivity type, which is opposite to the second conductivity type. A gate oxide layer is deposited above the drift region; Based on the first photolithography pattern, the gate oxide layer and the isolation material of the STI are etched to obtain a first groove that is inserted into the drift region and penetrates the gate oxide layer; Polysilicon is deposited on the surface of the first photolithographic pattern to obtain a first polysilicon layer. The first polysilicon layer is planarized and left on the surface of the first photolithographic pattern. Then, using the first photolithographic pattern as a mask, the polysilicon in the first groove is implanted with ions twice to obtain a first field plate. The first field plate is inserted into the drift region and penetrates the gate oxide layer. The first field plate includes a first PN junction. The PN junction interface of the first PN junction is higher than the surface of the drift region, so that the first PN junction in the drift region includes only the first type of ions. When the gate structure is turned on, the depletion region boundary of the first PN junction moves due to electrostatic effect, so that the first PN junction forms a conductive channel on the surface of the drift region. The first type of ions has the opposite conductivity type to the drift region, and the conductive channel has the same conductivity type as the drift region. After removing the first photolithography pattern, polysilicon is deposited on the surface of the gate oxide layer to obtain a second polysilicon layer. When the first photolithography pattern is removed, the residual polysilicon on both sides of the gate oxide layer is also removed. Based on the second photolithography pattern, the second polysilicon layer is etched to obtain the polysilicon gate and the second field plate.

8. The method for fabricating an LDMOS device according to claim 7, characterized in that, The process of etching the gate oxide layer and the STI isolation material based on the first photolithography pattern to obtain a first groove inserted into the drift region and penetrating the gate oxide layer includes: Based on the first photolithography pattern, etching begins from the surface of the gate oxide layer until the isolation material of the STI is completely etched, and after forming a pad oxide layer on the surface of the trench, the first groove is obtained. The step of performing two ion implantations on the polysilicon in the first groove using the first photolithographic pattern as a mask to obtain the first field plate includes: Using the first photolithographic pattern as a mask, first type of ions are implanted into the polysilicon in the first groove, and then second type of ions are implanted to obtain the first field plate. The first type of ions is of the first conductivity type, and the second type of ions is of the second conductivity type.

9. The method for fabricating an LDMOS device according to claim 7, characterized in that, The depth of the STI is greater than the thickness of the gate oxide layer.

10. The method for fabricating an LDMOS device according to claim 7, characterized in that, The method further includes ion implantation in the trap region and drift region to form the source region and drain region.

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