Semiconductor equipment

Abstract

The present invention provides a semiconductor device that can linearly change the electrical characteristics of an LDMOS transistor with respect to the number of fingers. [Solution] The semiconductor device (DEV1, DEV2, DEV3) comprises at least one LDMOS transistor (Tr) and a semiconductor substrate (SUB) having a top surface (F1). Each of the at least one LDMOS transistor has a plurality of impurity diffusion layers (ILD) formed inside and on the top surface of the semiconductor substrate, a plurality of drain layers (DRA) formed inside and on the top surface of the semiconductor substrate, and a plurality of insulating films (IF) formed on the top surface. Each of the plurality of impurity diffusion layers, each of the plurality of drain layers, and each of the plurality of insulating films extends along a first direction (DR1) in a plan view. The plurality of impurity diffusion layers are arranged with a gap between two adjacent impurity diffusion layers along a second direction (DR2) perpendicular to the first direction in a plan view.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device.

Background Art

[0002] The semiconductor device disclosed in Japanese Patent Application Laid-Open No. 2017-45884 (Patent Document 1) has a semiconductor substrate and a LDMOS (Laterally Diffused Metal Oxide Semiconductor) transistor.

[0003] The semiconductor substrate has an upper surface. The semiconductor substrate has a first impurity diffusion layer, a second impurity diffusion layer, a drain layer, a first body layer, a second body layer, and a drift layer. The first impurity diffusion layer and the second impurity diffusion layer are formed on the upper surface of the semiconductor substrate within the semiconductor substrate. Each of the first impurity diffusion layer and the second impurity diffusion layer extends along a first direction in a plan view. The first impurity diffusion layer and the second impurity diffusion layer are arranged side by side with a gap therebetween along a second direction perpendicular to the first direction in a plan view. The drift layer is formed on the upper surface of the semiconductor substrate within the semiconductor substrate. The drift layer extends along the first direction and is located between the first impurity diffusion layer and the second impurity diffusion layer.

[0004] The first body layer is formed on the upper surface of the semiconductor substrate so as to surround the first impurity diffusion layer in a cross-sectional view within the semiconductor substrate. The second body layer is formed on the upper surface of the semiconductor substrate so as to surround the second impurity diffusion layer in a cross-sectional view within the semiconductor substrate. The drift layer is formed on the upper surface of the semiconductor substrate so as to surround the drain layer in a cross-sectional view within the semiconductor substrate. Each of the first impurity diffusion layer and the second impurity diffusion layer has a source layer and a back gate layer.

[0005] An LDMOS transistor has a first impurity diffusion layer and a second impurity diffusion layer, a first body layer and a second body layer, a drain layer, and a drift layer. The LDMOS transistor further has a first insulating film and a second insulating film, a first gate insulating film and a second gate insulating film, a first gate electrode and a second gate electrode.

[0006] The first insulating film is formed on the upper surface of the semiconductor substrate so as to be in contact with the drift layer and away from the first impurity diffusion layer. The second insulating film is formed on the upper surface of the semiconductor substrate so as to be in contact with the drift layer and away from the second impurity diffusion layer. The first gate insulating film is formed on the upper surface of the semiconductor substrate located between the first insulating film and the first impurity diffusion layer. The second gate insulating film is formed on the upper surface of the semiconductor substrate located between the second insulating film and the second impurity diffusion layer. The first gate electrode is formed on the first gate insulating film and the first insulating film, and the second gate insulating film is formed on the second gate insulating film and the second insulating film. [Prior art documents] [Patent Documents]

[0007] [Patent Document 1] Japanese Patent Publication No. 2017-45884 [Overview of the project] [Problems that the invention aims to solve]

[0008] In the LDMOS transistor of the semiconductor device disclosed in Patent Document 1, when the number of fingers increases, i.e., when the number of drain layers increases, the electrical characteristics of the LDMOS transistor do not change linearly with respect to the number of fingers. Other problems and novel features will become apparent from the description herein and the accompanying drawings. [Means for solving the problem]

[0009] The semiconductor device of this disclosure comprises at least one LDMOS transistor and a semiconductor substrate having an upper surface. Each of the at least one LDMOS transistor has a plurality of impurity diffusion layers formed in and on the upper surface of the semiconductor substrate, a plurality of drain layers formed in and on the upper surface of the semiconductor substrate, and a plurality of insulating films formed on the upper surface. Each of the plurality of impurity diffusion layers, each of the plurality of drain layers, and each of the plurality of insulating films extends along a first direction in a plan view. The plurality of impurity diffusion layers are arranged with a gap between two adjacent impurity diffusion layers in a second direction perpendicular to the first direction in a plan view. The plurality of impurity diffusion layers have a first impurity diffusion layer and a second impurity diffusion layer located at both ends in the second direction, and a third impurity diffusion layer located between the first impurity diffusion layer and the second impurity diffusion layer. Each of the plurality of drain layers is located between two adjacent impurity diffusion layers. Each of the multiple insulating films is positioned between adjacent drain layers and one of the multiple impurity diffusion layers such that it is in contact with one of the multiple drain layers and away from one of the multiple impurity diffusion layers. In the first LDMOS transistor of at least one LDMOS transistor, each of the first and second impurity diffusion layers has a first back gate layer but no source layer. In the first LDMOS transistor, the third impurity diffusion layer has a second back gate layer and a first source layer that are alternately arranged along a first direction. [Effects of the Invention]

[0010] The semiconductor device described herein allows for a linear change in the electrical characteristics of an LDMOS transistor with respect to the number of fingers. [Brief explanation of the drawing]

[0011] [Figure 1] This is a plan view of semiconductor device DEV1 on LDMOS transistor Tr1. [Figure 2] This is a cross-sectional view of semiconductor device DEV1 in line II-II in Figure 1. [Figure 3] It is a cross-sectional view of the semiconductor device DEV1 at III-III in FIG. 1. [Figure 4] It is a plan view of the semiconductor device DEV1 on the LDMOS transistor Tr2. [Figure 5] It is a cross-sectional view of the semiconductor device DEV1 at V-V in FIG. 4. [Figure 6] It is a cross-sectional view of the semiconductor device DEV1 at VI-VI in FIG. 4. [Figure 7] It is a plan view of the semiconductor device DEV1 on the LDMOS transistor Tr2. [Figure 8] It is a cross-sectional view of the semiconductor device DEV1 at VIII-VIII in FIG. 7. [Figure 9] It is a cross-sectional view of the semiconductor device DEV1 at IX-IX in FIG. 7. [Figure 10] It is a circuit diagram of the current mirror circuit. [Figure 11] It is a manufacturing process diagram of the semiconductor device DEV1. [Figure 12] It is a cross-sectional view for explaining the ion implantation process S1. [Figure 13] It is a cross-sectional view for explaining the insulating film formation process S2. [Figure 14] It is a cross-sectional view for explaining the gate insulating film formation process S3. [Figure 15] It is a cross-sectional view for explaining the gate electrode film formation process S4. [Figure 16] It is a cross-sectional view for explaining the gate electrode etching process S5. [Figure 17] It is a cross-sectional view for explaining the ion implantation process S6. [Figure 18] It is a cross-sectional view for explaining the sidewall spacer formation process S7. [Figure 19] It is a cross-sectional view for explaining the ion implantation process S8. [Figure 20] It is a cross-sectional view for explaining the ion implantation process S9. [Figure 21] It is a cross-sectional view for explaining the interlayer insulating film formation process S10. [Figure 22]This is a cross-sectional view illustrating the contact plug forming process S11. [Figure 23] This is a plan view of semiconductor device DEV4 on LDMOS transistor Tr3. [Figure 24] This is a cross-sectional view of semiconductor device DEV4 in XXIV-XXIV in Figure 23. [Figure 25] This is a cross-sectional view of semiconductor device DEV4 at XXV-XXV in Figure 23. [Figure 26] This is a cross-sectional view of semiconductor device DEV2. [Figure 27] This is a manufacturing process diagram for the semiconductor device DEV2. [Figure 28] This is a cross-sectional view illustrating the ion implantation step S1 in the manufacturing method of a semiconductor device DEV2. [Figure 29] This is a cross-sectional view illustrating the gate electrode etching process S5 in the manufacturing method of semiconductor device DEV2. [Figure 30] This is a cross-sectional view illustrating the ion implantation step S13 in the manufacturing method of semiconductor device DEV2. [Figure 31] This is a cross-sectional view of semiconductor device DEV3. [Figure 32] This is a cross-sectional view illustrating the ion implantation step S1 in the manufacturing method of semiconductor device DEV3. [Figure 33] This is a cross-sectional view illustrating the gate electrode etching process S5 in the manufacturing method of semiconductor device DEV3. [Figure 34] This is a cross-sectional view illustrating the ion implantation step S13 in the manufacturing method of semiconductor device DEV3. [Modes for carrying out the invention]

[0012] The embodiments of this disclosure will be described in detail with reference to the drawings. In the following drawings, the same or corresponding parts are denoted by the same reference numerals, and redundant descriptions will not be repeated.

[0013] (First Embodiment) The semiconductor device DEV1 according to the first embodiment will be described.

[0014] <Configuration of Semiconductor Device DEV1> As shown in Figures 1 to 9, the semiconductor device DEV1 has a plurality of LDMOS transistors Tr. The number of LDMOS transistors in the semiconductor device DEV1 may be one. The semiconductor device DEV1 has a semiconductor substrate SUB. The semiconductor substrate SUB has an upper surface F1 and a lower surface F2 located on the opposite side of the upper surface F1. The semiconductor substrate SUB has a plurality of impurity diffusion layers IDL, a plurality of drain layers DRA, a plurality of body layers BDL, and a plurality of drift layers DRI.

[0015] Multiple impurity diffusion layers (IDL) and multiple drain layers (DRA) are formed on the upper surface F1 within the semiconductor substrate SUB. In a plan view, the impurity diffusion layers (IDL) and drain layers (DRA) extend along a first direction (DR1). In a plan view, the multiple impurity diffusion layers (IDL) are arranged with a gap between two adjacent layers of the multiple impurity diffusion layers (IDL) along a second direction (DR2) perpendicular to the first direction (DR1). The drain layers (DRA) are located between two adjacent layers of the multiple impurity diffusion layers (IDL).

[0016] The impurity diffusion layer (IDL) has a first portion (IDLa) and a second portion (IDLb). The first portion (IDLa) is located between the second portion (IDLb) and the drain layer (DRA). In other words, the impurity diffusion layer (IDL) has an LDD (Lightly Doped Diffusion) structure.

[0017] The body layer BDL is formed on the upper surface F1 so as to surround the impurity diffusion layer IDL in a cross-sectional view. The drift layer DRI is formed on the upper surface F1 so as to surround the drain layer DRA in a cross-sectional view. The semiconductor substrate SUB may further have a plurality of well layers WEL. In a cross-sectional view, the well layers WEL are formed so as to surround the drain layer DRA and are surrounded by the drift layer DRI.

[0018] The semiconductor substrate SUB is formed from, for example, single-crystal silicon. The conductivity type of the semiconductor substrate SUB is the first conductivity type. The conductivity type of the body layer BDL is the first conductivity type. The conductivity types of the drain layer DRA, the well layer WEL, and the drift layer DRI are the second conductivity types, opposite to the first conductivity type. The first conductivity type is, for example, p-type, and the second conductivity type is, for example, n-type. The first conductivity type may be n-type, and the second conductivity type may be p-type.

[0019] The semiconductor device DEV1 further has a plurality of insulating films IF1. The insulating films IF1 are formed on the upper surface F1. The insulating films IF1 extend along a first direction DR1. A plurality of trenches TR1 are formed on the upper surface F1. The trenches TR1 extend toward the lower surface F2. The trenches TR1 are located between adjacent impurity diffusion layers IDL and drain layers DRA. The trenches TR1 are in contact with the drain layer DRA and separated from the impurity diffusion layer IDL. The insulating films IF1 are formed within the trenches TR1. Therefore, the insulating films IF are formed on the upper surface F1 so as to be in contact with the drain layer DRA and separated from the impurity diffusion layer IDL. The insulating films IF1 are formed of, for example, silicon oxide.

[0020] The semiconductor device DEV1 further has a plurality of gate insulating films GI and a plurality of gate electrodes GE. The gate insulating films GI are formed on an upper surface F1 located between adjacent insulating films IF1 and impurity diffusion layers IDL. The gate insulating films GI are made of, for example, silicon oxide. The gate electrodes GE are formed on adjacent gate insulating films GI and insulating films IF1. The gate electrodes GE are made of, for example, polysilicon.

[0021] The LDMOS transistor Tr has multiple impurity diffusion layers IDL, multiple drain layers DRA, multiple body layers BDL, multiple drift layers DRI, multiple insulating films IF1, multiple gate insulating films GI, and multiple gate electrodes GE. The semiconductor device DEV1 also has an insulating film IF2. The insulating film IF2 is formed on the upper surface F1 so as to surround the LDMOS transistor Tr in a plan view. A trench TR2 is formed on the upper surface F1 extending toward the lower surface F2, and the insulating film IF2 is formed within the trench TR2. The insulating film IF2 electrically isolates the LDMOS transistor Tr from other elements. The insulating film IF2 is formed of, for example, silicon oxide.

[0022] The semiconductor device DEV1 further includes a sidewall spacer SWS. The sidewall spacer SWS is formed on the upper surface F1 (on the first portion IDLa) and on the insulating film IF1 so as to be in contact with both sides of the gate electrode GE. The sidewall spacer SWS is made of, for example, silicon nitride.

[0023] The semiconductor device DEV1 further has an interlayer insulating film ILD. The interlayer insulating film ILD is formed on the upper surface F1 so as to cover the insulating film IF1, insulating film IF2, gate electrode GE, and sidewall spacer SWS. The interlayer insulating film ILD is formed of, for example, silicon oxide.

[0024] The semiconductor device DEV1 further includes wiring WL1 and wiring WL2, and contact plugs CP1 and contact plugs CP2. Wiring WL1 and wiring WL2 are formed on the interlayer insulating film ILD. Wiring WL1 and wiring WL2 are made of, for example, aluminum or an aluminum alloy. Contact plugs CP1 and contact plugs CP2 are formed within the interlayer insulating film ILD. Contact plug CP1 electrically connects wiring WL1 to the drain layer DRA. Contact plug CP2 electrically connects wiring WL2 to the impurity diffusion layer IDL. Contact plugs CP1 and contact plugs CP2 are made of, for example, tungsten.

[0025] As shown in Figures 1 to 3, in LDMOS transistor Tr1, one of the multiple LDMOS transistors Tr, each of the impurity diffusion layers IDL1 and IDL2 located at both ends in the second direction DR2 of the multiple impurity diffusion layers IDL has only a back gate layer BGL. That is, each of the impurity diffusion layers IDL1 and IDL2 has a back gate layer BGL, but no source layer. The conductivity type of the back gate layer BGL is the first conductivity type. In addition, in LDMOS transistor Tr1, the impurity diffusion layer IDL3 located between the multiple impurity diffusion layers IDL1 and IDL2 has back gate layers BGL and a source layer SL arranged alternately along the first direction DR1. The conductivity type of the source layer SL is the second conductivity type.

[0026] As shown in Figures 4 to 6, in LDMOS transistor Tr2, one of the multiple LDMOS transistors Tr, each of the impurity diffusion layers IDL1 and IDL2 has only a back gate layer BGL. That is, each of the impurity diffusion layers IDL1 and IDL2 has a back gate layer BGL, but no source layer. In LDMOS transistor Tr2, the impurity diffusion layer IDL3 has back gate layers BGL and a source layer SL that are alternately arranged along the first direction DR1. Note that the number of drain layers DRA in LDMOS transistor Tr2 may differ from the number of drain layers DRA in LDMOS transistor Tr1.

[0027] As shown in Figure 10, the semiconductor device DEV1 may have a current mirror circuit. The current mirror circuit includes an LDMOS transistor Tr1, an LDMOS transistor Tr2, a resistor R, and a load L. The drain layers DRA of LDMOS transistor Tr1 and LDMOS transistor Tr2 are connected to the drain voltage V DD They are electrically connected. The source layer SL of LDMOS transistor Tr1 and the source layer SL of LDMOS transistor Tr2 are grounded. In other words, LDMOS transistors Tr1 and LDMOS transistors Tr2 are connected in parallel.

[0028] The gate electrode GE of LDMOS transistor Tr1 is electrically connected to the gate electrode GE of LDMOS transistor Tr2. The gate electrode GE of LDMOS transistor Tr1 and the gate electrode GE of LDMOS transistor Tr2 are electrically connected to the drain layer DRA of LDMOS transistor Tr1. The resistor R is connected to the drain layer DRA of LDMOS transistor Tr1 and the drain voltage V DD It is electrically connected between the load L and the drain layer DRA of the LDMOS transistor Tr2 and the drain voltage V DD It is electrically connected to [the other].

[0029] In a current mirror circuit, the ratio of the current I1 flowing through LDMOS transistor Tr1 to the current I2 flowing through LDMOS transistor Tr2 is determined by the Miller ratio, that is, the ratio between the size of LDMOS transistor Tr1 and the size of LDMOS transistor Tr2. For example, if the gate lengths of LDMOS transistor Tr1 and LDMOS transistor Tr2 are equal, and the gate widths of LDMOS transistor Tr1 and LDMOS transistor Tr2 are equal, the Miller ratio is 1:1, and the current I2 is equal to the current I1. Also, if the gate lengths of LDMOS transistor Tr1 and LDMOS transistor Tr2 are equal, and the gate width of LDMOS transistor Tr2 is twice the gate width of LDMOS transistor Tr1, the Miller ratio is 1:2, and the current I2 is twice the current I1. Note that the gate width of LDMOS transistor Tr1 and LDMOS transistor Tr2 is proportional to the number of fingers.

[0030] In LDMOS transistors Tr1 and Tr2, the number of drain layers DRA is, for example, 6 or less. If the number of drain layers DRA is n (n: a natural number), then the number of fingers of LDMOS transistor Tr1 and LDMOS transistor Tr2 are 2n-2.

[0031] As shown in Figures 7 to 9, a plurality of LDMOS transistors Tr may include an LDMOS transistor Tr3. In the LDMOS transistor Tr3, each of the impurity diffusion layers IDL1, IDL2, and IDL3 has a back gate layer BGL and a source layer SL that are alternately arranged along the first direction DR1.

[0032] <Manufacturing method for semiconductor device DEV1> As shown in Figure 11, the manufacturing method for semiconductor device DEV1 includes an ion implantation step S1, an insulating film formation step S2, a gate insulating film formation step S3, a gate electrode film formation step S4, a gate electrode etching step S5, an ion implantation step S6, a sidewall spacer formation step S7, an ion implantation step S8, and an ion implantation step S9. Furthermore, the manufacturing method for semiconductor device DEV1 also includes an interlayer insulating film formation step S10, a contact plug formation step S11, and a wiring formation step S12.

[0033] As shown in Figure 12, in the ion implantation step S1, ion implantation is performed using the resist pattern formed on the upper surface F1 as a mask, thereby forming the body layer BDL, the well layer WEL, and the drift layer DRI.

[0034] As shown in Figure 13, insulating film IF1 and insulating film IF2 are formed in insulating film formation step S2. In insulating film formation step S2, firstly, a hard mask is formed on the upper surface F1. Secondly, trenches TR1 and TR2 are formed on the upper surface F1 by dry etching of the semiconductor substrate SUB through the openings in the hard mask. Thirdly, constituent materials such as insulating film IF1 are deposited in trench TR1, trench TR2 and on the hard mask by, for example, CVD (Chemical Vapor Deposition). Fourthly, constituent materials such as insulating film IF1 formed outside trench TR1 and outside trench TR2 are removed by, for example, CMP or etch-back.

[0035] As shown in Figure 14, in the gate insulating film formation step S3, for example, thermal oxidation of the upper surface F1 is performed to form the gate insulating film GI on the upper surface F1. As shown in Figure 15, in the gate electrode film deposition step S4, for example, the gate electrode GE is formed on the gate insulating film GI by the CVD method. As shown in Figure 16, in the gate electrode etching step S5, the gate electrode GE is patterned by dry etching through the openings in the resist pattern formed on the gate electrode GE. At this time, the gate insulating film GI located elsewhere than beneath the patterned gate electrode GE is also removed.

[0036] As shown in Figure 17, in the ion implantation step S6, the first partial IDLa is formed by ion implantation using the gate electrode GE, insulating film IF1, and insulating film IF2 as masks.

[0037] As shown in Figure 18, in the sidewall spacer formation step S7, sidewall spacers SWS are formed on the upper surface F1 (first portion IDLa) and on the insulating film IF1 so as to be in contact with both sides of the gate electrode GE. In the sidewall spacer formation step S7, firstly, the constituent material of the sidewall spacer SWS is deposited on the upper surface F1 so as to cover the insulating film IF1, insulating film IF2, gate electrode GE and gate insulating film GI, for example by CVD. Secondly, etch-back is performed on the constituent material of the sidewall spacer SWS.

[0038] As shown in Figure 19, in ion implantation step S8, the second portion IDLb (source layer SL) of the impurity diffusion layer IDL3 is formed by ion implantation using the gate electrode GE, sidewall spacer SWS, insulating film IF1, and the resist pattern formed on the top surface F1 as a mask, and the drain layer DRA is formed. As shown in Figure 20, in ion implantation step S9, the second portion IDLb (back gate layer BGL) of the impurity diffusion layer IDL1 and impurity diffusion layer IDL2 is formed by ion implantation using the gate electrode GE, sidewall spacer SWS, insulating film IF1, insulating film IF2, and the resist pattern formed on the top surface F1 as a mask. At this time, the second portion IDLb (back gate layer BGL) of the impurity diffusion layer IDL3 is also formed.

[0039] As shown in Figure 21, in the interlayer insulating film formation step S10, an interlayer insulating film ILD is formed on the upper surface F1 so as to cover the insulating film IF1, insulating film IF2, sidewall spacer SWS, and gate electrode GE. In the interlayer insulating film formation step S10, firstly, the constituent material of the interlayer insulating film ILD is deposited on the upper surface F1 so as to cover the insulating film IF1, insulating film IF2, sidewall spacer SWS, and gate electrode GE. Secondly, the upper surface of the constituent material of the interlayer insulating film ILD is planarized, for example, by the CMP method.

[0040] As shown in Figure 22, in the contact plug formation step S11, contact plugs CP1 and CP2 are formed within the interlayer insulating film ILD. In the contact plug formation step S11, firstly, contact holes are formed within the interlayer insulating film ILD by dry etching of the interlayer insulating film ILD through openings in the resist pattern formed on the interlayer insulating film ILD. Secondly, constituent materials such as contact plug CP1 are deposited in the contact holes and on the interlayer insulating film ILD, for example by CVD. Thirdly, constituent materials such as contact plug CP1 formed outside the contact holes are removed, for example by CMP.

[0041] In the wiring formation process S12, wiring WL1 and wiring WL2 are formed on the interlayer insulating film ILD. In the wiring formation process S12, firstly, the constituent material such as wiring WL1 is deposited on the interlayer insulating film ILD, for example by sputtering. Secondly, dry etching is performed on the constituent material such as wiring WL1 through the openings of the resist pattern formed on the constituent material such as wiring WL1. As a result, the structure of the semiconductor device DEV1 shown in Figures 1 to 9 is formed.

[0042] <Effects of Semiconductor Device DEV1> In LDMOS transistor Tr3, both the impurity diffusion layer IDL1 and the impurity diffusion layer IDL2 have not only a back gate layer BGL but also a source layer SL. Therefore, the gate width of LDMOS transistor Tr3 is larger than that of LDMOS transistors Tr1 and Tr2. As a result, the current capability of LDMOS transistor Tr3 is higher than that of LDMOS transistors Tr1 and Tr2.

[0043] However, when forming the insulating film IF1, the insulating films IF1 located at both ends in the second direction DR2 are affected by the insulating film IF2, unlike the insulating films IF1 located elsewhere in the second direction DR2. As a result, the shape of the insulating films IF1 located at both ends in the second direction DR2 is different from that of the insulating films IF1 located elsewhere in the second direction DR2. This is also true for the body layer BDL, drift layer DRI, and gate electrode GE located at both ends in the second direction DR2.

[0044] As a result, in the LDMOS transistor Tr3, the electrical characteristics such as threshold voltage, on-resistance, and saturated drain current in the channel between the source layer SL and drain layer DRA of the impurity diffusion layer IDL1 (impurity diffusion layer IDL2) differ from the electrical characteristics in the channel between the source layer SL and drain layer DRA of the impurity diffusion layer IDL3. In other words, the electrical characteristics of the LDMOS transistor Tr3 do not change linearly with respect to the number of fingers. Therefore, when the LDMOS transistor Tr3 is used in a current mirror circuit, even if the number of fingers between the transistors is adjusted to obtain a desired current ratio, the current ratio will deviate from the desired ratio, resulting in low accuracy of the current mirror circuit.

[0045] On the other hand, in LDMOS transistors Tr1 and Tr2, the impurity diffusion layer IDL1 (IDL2) does not have a source layer SL, so the space between the impurity diffusion layer IDL1 (IDL2) and the drain layer DRA is not used as a channel. Therefore, the electrical characteristics of LDMOS transistors Tr1 and Tr2 change more linearly with respect to the number of fingers compared to the electrical characteristics of LDMOS transistor Tr3. As a result, semiconductor device DEV1 can improve the accuracy of analog circuits such as current mirror circuits.

[0046] As shown in Figures 23 to 25, the semiconductor device DEV4 in the comparative example has an LDMOS transistor Tr4 as the LDMOS transistor Tr. In the LDMOS transistor Tr4, each of the impurity diffusion layers IDL1 and IDL2 has only a back gate layer BGL. In the LDMOS transistor Tr4, the insulating film IF1 located at both ends in the second direction DR2 is in contact with both the impurity diffusion layer IDL1 (impurity diffusion layer IDL2) and the drain layer DRA. In the LDMOS transistor Tr4, no gate electrode GE is formed on the insulating film IF1 located at both ends in the second direction DR2.

[0047] In LDMOS transistor Tr4, similar to LDMOS transistors Tr1 and Tr2, the impurity diffusion layer IDL1 (IDL2) does not have a source layer SL, so the space between the impurity diffusion layer IDL1 (IDL2) and the drain layer DRA is not used as a channel. Therefore, the electrical characteristics of LDMOS transistor Tr4 change more linearly with respect to the number of fingers compared to the electrical characteristics of LDMOS transistor Tr3.

[0048] However, in LDMOS transistor Tr4, since the gate electrode GE is not formed on the insulating film IF1 located at both ends in the second direction DR2, the dielectric breakdown voltage is lower than that of LDMOS transistors Tr1 and Tr2 due to the difference in field plate effect. From another perspective, in LDMOS transistor Tr4, in order to obtain the same dielectric breakdown voltage as LDMOS transistors Tr1 and Tr2, the distance between the impurity diffusion layer IDL1 (impurity diffusion layer IDL2) and the drain layer DRA needs to be larger than that of LDMOS transistors Tr1 and Tr2. Thus, semiconductor device DEV1 allows for a reduction in the planar dimensions of LDMOS transistors Tr1 and Tr2.

[0049] As described above, LDMOS transistor Tr3 is difficult to apply to analog circuits that require high precision. However, if analog circuits that do not require high precision but require high current capability are integrated into semiconductor device DEV1, then LDMOS transistor Tr3 can be applied to such analog circuits that require high current capability.

[0050] In LDMOS transistor Tr3, the fewer the number of fingers, i.e., the fewer the number of drain layers DRA, the greater the influence of the electrical characteristics in the channel between the source layer SL and the drain layer DRA of the impurity diffusion layer IDL1 (impurity diffusion layer IDL2). Therefore, LDMOS transistors Tr1 and Tr2 are particularly effective when the number of fingers is 10 or less, i.e., when the number of drain layers DRA is 6 or less.

[0051] (Second Embodiment) The semiconductor device DEV2 according to the second embodiment will be described. Here, we will mainly explain the differences from the semiconductor device DEV1, and will avoid repeating redundant explanations.

[0052] <Configuration of Semiconductor Device DEV2> As shown in Figure 26, the semiconductor device DEV2 has an LDMOS transistor Tr1 as one of a plurality of LDMOS transistors Tr1. In the LDMOS transistor Tr1 of the semiconductor device DEV2, the depth of body layer BDL1 surrounding the impurity diffusion layer IDL1 in a cross-sectional view among the plurality of body layers BDL, and the depth of body layer BDL2 surrounding the impurity diffusion layer IDL2 in a cross-sectional view among the plurality of body layers BDL, are greater than the depth of body layer BDL3 surrounding the impurity diffusion layer IDL3 in a cross-sectional view among the plurality of body layers BDL. The depth of body layer BDL3 is less than the depth of the drift layer DRI. The depth of body layer BDL (drift layer DRI) is the distance between the bottom surface and the top surface F1 of body layer BDL (drift layer DRI).

[0053] Furthermore, in the LDMOS transistor Tr1 of the semiconductor device DEV2, in a plan view, the overlap width between the gate electrode GE and the body layer BDL3 in the second direction DR2 is smaller than the overlap width between the gate electrode GE and the body layer BDL1 and the overlap width between the gate electrode GE and the body layer BDL2 in the second direction DR2.

[0054] <Manufacturing method for semiconductor device DEV2> As shown in Figure 27, the method for manufacturing the semiconductor device DEV2 further includes an ion implantation step S13.

[0055] As shown in Figure 28, in the manufacturing method of semiconductor device DEV2, the body layer BDL3 is not formed in the ion implantation step S1. As shown in Figure 29, in the manufacturing method of semiconductor device DEV2, in the gate electrode etching step S5, the gate electrode GE located above the area where the body layer BDL3 is formed is not removed by etching.

[0056] As shown in Figure 30, in the ion implantation step S13, the body layer BDL3 is formed self-aligned by ion implantation. In the ion implantation step S13, firstly, a resist pattern RP is formed on the upper surface F1 so as to cover the gate electrode GE, insulating film IF1, and insulating film IF2. The resist pattern RP has an opening above the location where the body layer BDL3 is formed. Secondly, dry etching is performed on the gate electrode GE and gate insulating film GI through the opening in the resist pattern RP, thereby removing the gate electrode GE and gate insulating film GI that are exposed from the opening in the resist pattern RP. Thirdly, ion implantation is performed through the opening in the resist pattern RP. At this time, the direction of ion implantation is inclined with respect to the normal direction of the upper surface F1.

[0057] As a result, in a plan view, the overlap width between the gate electrode GE and the body layer BDL3 in the second direction DR2 is smaller than the overlap width between the gate electrode GE and the body layer BDL1 and the overlap width between the gate electrode GE and the body layer BDL2 in the second direction DR2. Also, the depth of the body layer BDL3 is smaller than the depth of the body layer BDL1 and the depth of the body layer BDL2. After the ion implantation process S13, the processes from the ion implantation process S6 to the wiring formation process S12 are carried out sequentially to form the structure of the semiconductor device DEV2 shown in Figure 26.

[0058] <Effects of Semiconductor Device DEV2> In the LDMOS transistor Tr1 of semiconductor device DEV2, the overlap width between the gate electrode GE and the body layer BDL3 is smaller than the overlap width between the gate electrode GE and the body layer BDL1 in the second direction DR2, and also smaller than the overlap width between the gate electrode GE and the body layer BDL2 in the second direction DR2. Therefore, the channel length is shorter compared to the LDMOS transistor Tr1 of semiconductor device DEV2. Consequently, the electrical characteristics (on-resistance) of the LDMOS transistor Tr1 in semiconductor device DEV2 are reduced.

[0059] (Third embodiment) The semiconductor device DEV3 according to the third embodiment will be described. Here, the differences from the semiconductor device DEV2 will be mainly explained, and redundant explanations will not be repeated.

[0060] <Semiconductor device DEV3> As shown in Figure 31, the semiconductor device DEV3 has an LDMOS transistor Tr1 as one of a plurality of LDMOS transistors Tr1. In the LDMOS transistor Tr1 of the semiconductor device DEV3, the depths of the body layers BDL1 and BDL2 are approximately the same as the depth of the body layer BDL3, and smaller than the depth of the drift layer DRI. Furthermore, in the LDMOS transistor Tr1 of the semiconductor device DEV3, the overlap width between the body layer BDL1 and the gate electrode GE in the second direction DR2, and the overlap width between the body layer BDL2 and the gate electrode GE in the second direction DR2, are approximately the same as the overlap width between the body layer BDL3 and the gate electrode GE in the second direction DR2.

[0061] In semiconductor device DEV3, the semiconductor substrate SUB may further have an impurity diffusion layer IDL4 and an impurity diffusion layer IDL5. The impurity diffusion layer IDL4 is formed below the body layer BDL1 within the semiconductor substrate SUB and is in contact with the body layer BDL1. The impurity diffusion layer IDL5 is formed below the body layer BDL2 within the semiconductor substrate SUB and is in contact with the body layer BDL2. The conductivity type of the impurity diffusion layer IDL4 and the conductivity type of the impurity diffusion layer IDL5 are the first conductivity type.

[0062] <Manufacturing method for semiconductor device DEV3> As shown in Figure 32, in the manufacturing method of semiconductor device DEV3, in the ion implantation step S1, the impurity diffusion layer IDL4 and the impurity diffusion layer IDL5 are formed together with the well layer WEL and the drift layer DRI by ion implantation.

[0063] As shown in Figures 33 and 34, in the manufacturing method of semiconductor device DEV3, body layers BDL1 and BDL2 are formed self-aligned, similar to body layer BDL3. More specifically, as shown in Figure 33, in the gate electrode etching step S5, the gate electrodes GE located above the formation locations of body layer BDL1, body layer BDL2, and body layer BDL3 remain unetched. As shown in Figure 34, in the ion implantation step S13, dry etching is performed on the gate electrodes GE and gate insulating film GI through the openings in the resist pattern RP located above the formation locations of body layer BDL1, body layer BDL2, and body layer BDL3. Then, ion implantation is performed through these openings from a direction inclined with respect to the normal direction of the upper surface F1.

[0064] <Effects of Semiconductor Device DEV3> In semiconductor device DEV3, the same processes are applied to both ends of the LDMOS transistor Tr1 in the second direction DR2 and to the parts of the LDMOS transistor Tr1 other than both ends in the second direction DR2, for both the gate electrode etching process S5 and the ion implantation process S13. Therefore, in the LDMOS transistor Tr1 of semiconductor device DEV3, compared to the LDMOS transistor Tr1 of semiconductor device DEV2, the gate electrode GE and body layer BDL3 located other than the ends in the second direction DR2 can be properly formed even with a smaller number of fingers, and the electrical characteristics of the LDMOS transistor Tr1 change more linearly with respect to the number of fingers.

[0065] Although the present invention has been specifically described above based on embodiments, it goes without saying that the present invention is not limited to the above embodiments and can be modified in various ways without departing from its essence. [Explanation of Symbols]

[0066] BDL Body layer, BDL1, BDL2, BDL3 Body layer, BGL Back gate layer, CP1, CP2 Contact plug, DEV1, DEV2, DEV3, DEV4 Semiconductor device, DR1 First direction, DR2 Second direction, DRA Drain layer, DRI Drift layer, F1 Top surface, F2 Bottom surface, GE Gate electrode, GI Gate insulating film, I1, I2 Current, IDL Impurity diffusion layer, IDL1, IDL2, IDL3 Impurity diffusion layer, IDLa First part, IDLb Second part, IF1 Insulating film, IF2 Insulating film, ILD Interlayer insulating film, L Load, R Resistance, RP Resist pattern, S1 Ion implantation process, S2 Insulating film formation process, S3 Gate insulating film formation process, S4 Gate electrode film formation process, S5 Gate electrode etching process, S6 Ion implantation process, S7 Sidewall spacer formation process, S8 Ion implantation process, S9 Ion implantation process, S10 Interlayer insulating film formation process, S11 Contact plug formation process, S12 Wiring formation process, S13 Ion implantation process, SL Source layer, SUB Semiconductor substrate, SWS Sidewall spacer, TR1, TR2 Trench, Tr, Tr1, Tr2, Tr3, Tr4 Transistor, V DD Drain voltage, WEL well layer, WL1, WL2 wiring.

Claims

1. At least one LDMOS transistor, It comprises a semiconductor substrate having an upper surface, Each of the at least one LDMOS transistors is A plurality of impurity diffusion layers formed within and on the upper surface of the semiconductor substrate, A plurality of drain layers formed within and on the upper surface of the semiconductor substrate, It has a plurality of insulating films formed on the upper surface, Each of the plurality of impurity diffusion layers, each of the plurality of drain layers, and each of the plurality of insulating films extends along the first direction in a plan view. The plurality of impurity diffusion layers are arranged in a second direction perpendicular to the first direction in a plan view, with a gap between any two adjacent impurity diffusion layers. The plurality of impurity diffusion layers include a first impurity diffusion layer and a second impurity diffusion layer located at both ends in the second direction, and a third impurity diffusion layer located between the first impurity diffusion layer and the second impurity diffusion layer. Each of the aforementioned drain layers is located between two adjacent impurity diffusion layers. Each of the plurality of insulating films is positioned between adjacent drain layers and impurity diffusion layers such that it is in contact with one of the plurality of drain layers and is separated from one of the plurality of impurity diffusion layers. In the first LDMOS transistor among the at least one LDMOS transistor, each of the first impurity diffusion layer and the second impurity diffusion layer has a first back gate layer, while it does not have any source layer. The first LDMOS transistor is a semiconductor device in which the third impurity diffusion layer has a second back gate layer and a first source layer that are alternately arranged along the first direction.

2. Each of the at least one LDMOS transistors further comprises a plurality of gate insulating films and a plurality of gate electrodes. In the first LDMOS transistor, each of the plurality of gate insulating films is formed on the upper surface located between one of the plurality of adjacent impurity diffusion layers and one of the plurality of insulating films. The semiconductor device according to claim 1, wherein in the first LDMOS transistor, each of the plurality of gate electrodes is formed on one of the plurality of adjacent gate insulating films and one of the plurality of insulating films.

3. Each of the at least one LDMOS transistors further comprises a plurality of drift layers formed in the semiconductor substrate and a plurality of body layers formed in the semiconductor substrate. Each of the plurality of drift layers is formed on the upper surface such that it surrounds each of the plurality of drain layers in a cross-sectional view. The semiconductor device according to claim 1, wherein each of the plurality of body layers is formed on the upper surface such that, in a cross-sectional view, it surrounds each of the plurality of impurity diffusion layers.

4. The semiconductor device according to claim 3, wherein in the first LDMOS transistor, the depth of the first body layer surrounding the first impurity diffusion layer among the plurality of body layers and the depth of the second body layer surrounding the second impurity diffusion layer among the plurality of body layers are smaller than the depth of the third body layer surrounding the third impurity diffusion layer among the plurality of body layers.

5. The semiconductor device according to claim 3, wherein in the first LDMOS transistor, the depth of each of the plurality of drift layers is greater than the depth of the first body layer surrounding the first impurity diffusion layer among the plurality of body layers, the depth of the second body layer surrounding the second impurity diffusion layer among the plurality of body layers, and the depth of the third body layer surrounding the third impurity diffusion layer among the plurality of body layers.

6. The semiconductor device according to claim 1, wherein the number of drain layers in the first LDMOS transistor is 6 or less.

7. The at least one LDMOS transistor has a plurality of LDMOS transistors, In the second LDMOS transistor among the plurality of LDMOS transistors, each of the first impurity diffusion layer and the second impurity diffusion layer has a third back gate layer, while it does not have any source layer. In the second LDMOS transistor, the third impurity diffusion layer has a fourth back gate layer and a second source layer that are alternately arranged along the first direction. The number of drain layers in the first LDMOS transistor is different from the number of drain layers in the second LDMOS transistor. The semiconductor device according to claim 1, wherein the first LDMOS transistor and the second LDMOS transistor constitute a current mirror circuit.

8. The at least one LDMOS transistor has a plurality of LDMOS transistors, The semiconductor device according to claim 1, wherein the third LDMOS transistor among the plurality of LDMOS transistors has a fifth back gate layer and a third source layer which are alternately arranged along the first direction, each of the first impurity diffusion layer, the second impurity diffusion layer and the third impurity diffusion layer.

9. The semiconductor device according to claim 1, wherein the length of the first back gate layer in the first direction is greater than the length of the second back gate layer in the first direction.

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