Super-junction LDMOS device and manufacturing method thereof
By setting shallow trenches in the superjunction LDMOS device and filling a specific dielectric constant layer, the electric field distribution is optimized, which solves the problem that the device cannot meet the requirements in a specific scenario, and achieves higher voltage withstandability and lower on-resistance.
Patent Information
- Application Number
- CN202510121939.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-24
- Publication Date
- 2025-06-03
AI Technical Summary
Superjunction LDMOS devices cannot meet the requirements in certain specific scenarios, and further improvements to LDMOS devices are needed to enhance their adaptability.
By optimizing the device structure, a shallow trench is provided and a trench dielectric layer is provided on its inner wall, a silicon dioxide layer and a low dielectric constant layer are successively filled, and the electric field distribution is adjusted to improve the withstand voltage capability and doping concentration, thereby reducing the on-resistance.
A more uniform surface electric field distribution is achieved, the device's voltage withstandability and doping concentration is improved, the on-resistance is reduced, and the device's adaptability is enhanced.
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Figure CN120091605A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor manufacturing technology, and more particularly, to a superjunction LDMOS device and a manufacturing method thereof. Background Art
[0002] LDMOS (Laterally Diffused Metal Oxide Semiconductor) is a special type of metal oxide semiconductor field effect transistor (MOSFET). It uses double diffusion technology to perform two successive diffusions of boron and phosphorus in the same window. The channel length can be accurately determined by the difference in the lateral junction depth of the two impurity diffusions. Compared with bipolar transistors, LDMOS transistors have higher gain. The gain of LDMOS transistors can reach more than 14 dB, while that of bipolar transistors is 5 - 6 dB. The gain of the second conductive type A module using LDMOS transistors can reach about 60 dB. This indicates that fewer devices are required for the same output power, thereby increasing the reliability of the power amplifier.
[0003] Superjunction LDMOS is an improved LDMOS, that is, the low-doped N-type drift region of traditional LDMOS is replaced by a group of alternately arranged N-type doped regions and P-type doped regions. Theoretically, due to the charge compensation between the P / N column regions, superjunction LDMOS can obtain a very high breakdown voltage, while the highly doped N-type column regions can obtain a very low on-resistance. Therefore, superjunction devices can achieve a good balance between breakdown voltage and on-resistance.
[0004] However, in some specific scenarios, superjunction LDMOS still cannot meet the requirements. Therefore, it is necessary to further improve the LDMOS device to enhance its adaptability. Summary of the Invention
[0005] Based on this, in view of the above problems, it is necessary to provide a superjunction LDMOS device and a manufacturing method thereof to meet the requirements of specific scenarios by optimizing the device structure and selecting more suitable materials.
[0006] To achieve the above object, the technical solutions adopted by the present invention are as follows:
[0007] A superjunction LDMOS device, comprising:
[0008] A substrate and a drift region located on the surface of the substrate. In the longitudinal direction, the drift region is composed of alternately arranged doping regions of a first conductivity type and a second conductivity type; in the transverse direction, a gate region is provided on one side wall of the drift region, a source region is provided near the gate region, a channel region of the second conductivity type is provided in the drift region below the source region and near the gate region, a drain region is provided on the other side of the drift region, a shallow trench is provided in the drift region between the source region and the drain region, a trench dielectric layer is provided on the inner wall of the shallow trench, and a silicon dioxide layer and a low dielectric constant layer located on the surface of the silicon dioxide layer and filling the trench are sequentially filled in the shallow trench.
[0009] In the superjunction LDMOS device disclosed in the present invention, a shallow trench is provided in the drift region between the source region and the drain region, and the structure of the shallow trench can realize the isolation of semiconductor devices. Moreover, a trench dielectric layer is provided on the inner wall of the shallow trench, and a silicon dioxide layer and a low dielectric constant layer located on the surface of the silicon dioxide layer and filling the trench are sequentially filled in the shallow trench. Due to the significant difference in the dielectric constants of silicon and silicon dioxide, most of the electric flux tends to pass through silicon rather than silicon dioxide, and this structure will generate new electric field peaks, making the surface electric field more uniform. Moreover, the dielectric constant difference between the low dielectric constant layer and the silicon dioxide layer will also cause electric field peaks on both sides of the junction between the low dielectric constant layer and the silicon dioxide layer, and this electric field peak will improve the breakdown voltage and doping concentration on both sides of the shallow trench, thereby reducing the on-resistance of this region at the same time.
[0010] In one embodiment, the volume ratio of the silicon dioxide layer to the low dielectric constant layer in the shallow trench is 1:1.
[0011] In this embodiment, the position of the electric field peak can also be adjusted by adjusting the volume ratio of the silicon dioxide layer to the low dielectric constant layer, so that the superjunction LDMOS device meets the requirements of more scenarios.
[0012] In one embodiment, the material for making the low dielectric constant layer is SiLK, FOx or MSQ.
[0013] In one embodiment, the material for making the trench dielectric layer is a high dielectric constant material.
[0014] Due to the relatively high dielectric constant of the trench dielectric layer, the electric field concentration phenomenon in silicon can be effectively alleviated, thereby further depleting the drift region. This structure can effectively improve the breakdown voltage of the drift region and further increase the doping concentration of the doping region of the first conductivity type in this region, thereby reducing the on-resistance.
[0015] In one embodiment, the material for making the gate dielectric layer of the gate region is a high dielectric constant material.
[0016] The metal electrode wrapped with high dielectric constant material is used as the gate of the device, which can produce a sandwich structure of metal-high dielectric constant material-second conductivity type doping, that is, the conduction channel is a vertical structure. When the gate is pressurized, that is, the device is turned on, the structure can be regarded as a capacitor, accumulating a certain number of electrons in the second conductivity type channel region near the edge of the gate dielectric layer, thereby reducing the on-resistance of the channel and increasing the current.
[0017] In one embodiment, the high dielectric constant material is silicon oxynitride or hafnium oxide.
[0018] In one of the embodiments, an SOI thin film layer is further disposed between the substrate and the drift region.
[0019] The SOI thin film layer is arranged below the super junction structure, which can effectively avoid the depletion of the first conductive type column and the second conductive type high-resistance substrate in the super junction drift region, so that the second conductive type column in the super junction drift region can be completely depleted, thereby improving the vertical withstand voltage characteristics of the device, and utilizing the difference in dielectric constants to assist in depleting the lower half of the super junction structure, thereby increasing the lateral breakdown voltage and doping of the first conductive type region, and reducing the on-resistance.
[0020] In one of the embodiments, in the lateral direction, a surface of the SOI thin film layer corresponding to the source region is provided with a plurality of “Γ” shaped protruding regions.
[0021] The structure of the multiple "Γ"-shaped protruding areas prevents the source end from extracting charges from the interface inversion layer, thereby increasing the interface hole concentration in the structure, making the electric field distribution in the original area more uniform and the depletion more thorough, effectively increasing the breakdown voltage of the area, and thereby increasing the doping concentration of the area, thereby reducing its on-resistance at the same time.
[0022] Another embodiment discloses a method for manufacturing a super junction LDMOS device, comprising:
[0023] providing a substrate;
[0024] forming a drift region on the surface of the substrate, wherein the drift region is composed of first conductivity type doped regions and second conductivity type doped regions that are alternately arranged;
[0025] Etching the drift region to form a shallow trench in a preset shallow trench region;
[0026] forming a trench dielectric layer on the inner surface of the shallow trench;
[0027] forming a silicon dioxide layer in the trench;
[0028] forming a low dielectric constant layer on the surface of the silicon dioxide layer, wherein the low dielectric constant layer fills the groove;
[0029] A gate region is formed on the sidewall of the drift region on one side of the shallow trench;
[0030] A channel region of a second conductivity type is formed in the drift region between the gate region and the trench;
[0031] A source region is formed in the drift region above the channel region of the second conductivity type;
[0032] A drain region is formed in the drift region on the other side of the shallow trench.
[0033] In one embodiment, the method for manufacturing the superjunction LDMOS device further includes:
[0034] An SOI film is formed on the surface of the substrate;
[0035] The drift region is fabricated on the surface of the SOI film. Description of the Drawings
[0036] Figure 1 It is a schematic structural diagram of a superjunction LDMOS device provided by an embodiment of the present invention;
[0037] Figure 2 It is a schematic structural diagram of another superjunction LDMOS device provided by another embodiment of the present invention;
[0038] Figure 3 It is a schematic structural diagram of another superjunction LDMOS device provided by other embodiments of the present invention.
[0039] In the figure, 1, substrate; 2, drift region; 3, channel region of the second conductivity type; 41, trench dielectric layer; 42, silicon dioxide layer; 43, low dielectric constant layer; 51, gate dielectric layer; 52, gate electrode; 61, heavily doped region of the second conductivity type; 62, heavily doped region of the first conductivity type; 63, source electrode; 71, heavily doped region of the first conductivity type of the drain region; 72, drain electrode; 8, SOI film layer. Detailed Embodiments
[0040] To facilitate the understanding of the present invention, the present invention will be described in more detail below. However, it should be understood that the present invention can be implemented in many different forms and is not limited to the embodiments or examples described herein. On the contrary, the purpose of providing these embodiments or examples is to make the understanding of the disclosure content of the present invention more thorough and comprehensive.
[0041] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the technical field to which this invention belongs. The terms used in the specification of this invention are for the purpose of describing specific embodiments or examples only and are not intended to limit the invention. The optional scope of the term "and / or" used herein includes any one of two or more related listed items, and also includes any and all combinations of the related listed items. The said any and all combinations include combinations of any two related listed items, any more than two related listed items, or all related listed items.
[0042] As Figure 1 shown, an embodiment of the present invention discloses a superjunction LDMOS device, including:
[0043] A substrate 1 and a drift region 2 located on the surface of the substrate 1. In the longitudinal direction (Z direction), the drift region 2 is composed of alternately arranged first-conductivity-type doped regions and second-conductivity-type doped regions; in the lateral direction (X direction), a gate region is provided on one side wall of the drift region 2, an active region is provided near the gate region, a second-conductivity-type channel region 3 is provided in the drift region 2 below the source region and near the gate region, a drain region is provided on the other side of the drift region 2, a shallow trench is provided in the drift region between the source region and the drain region, a trench dielectric layer 41 is provided on the inner wall of the shallow trench, and a silicon dioxide layer 42 and a low dielectric constant layer 43 that is located on the surface of the silicon dioxide layer 42 and fills the trench are sequentially filled in the shallow trench.
[0044] Among them, the substrate in this embodiment may include semiconductor elements, such as silicon or silicon germanium (SiGe) with single crystal, polycrystalline or amorphous structures, or may also include a mixed semiconductor structure, such as silicon carbide, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide or gallium antimonide, alloy semiconductors or combinations thereof. Although several examples of materials that can form the substrate are described herein, any material that can be used as a semiconductor substrate falls within the spirit and scope of the present invention. The substrate in this embodiment may adopt a silicon substrate, and the substrate has a second-conductivity-type epitaxy.
[0045] The silicon dioxide layer and the low dielectric constant layer sequentially filled in the shallow trench divide the shallow trench into upper and lower parts, and the area ratio of the two fillings can be adjusted. In this embodiment, the volume ratio of the silicon dioxide layer to the low dielectric constant layer is 1:1. In addition, the position of the electric field peak can also be adjusted by adjusting the volume ratio of the silicon dioxide layer to the low dielectric constant layer, so that the superjunction LDMOS device meets the requirements of more scenarios. Specifically, the volume ratio of the silicon dioxide layer to the low dielectric constant layer can be adjusted to 2:1, 1:2 and other ratios according to requirements.
[0046] Specifically, the material for fabricating the low dielectric constant layer can be SiLK, FOx, MSQ, and other materials with a dielectric constant lower than 3.9.
[0047] In the superjunction LDMOS device disclosed in the embodiment of the present invention, a shallow trench is provided in the drift region between the source region and the drain region. The structure of the shallow trench can achieve isolation of the semiconductor device. Moreover, a trench dielectric layer is provided on the inner wall of the shallow trench, and a silicon dioxide layer and a low dielectric constant layer located on the surface of the silicon dioxide layer and filling the shallow trench are sequentially filled in the shallow trench. Due to the significant difference in the dielectric constants of silicon and silicon dioxide, most of the electric flux tends to pass through silicon rather than silicon dioxide, and this structure will generate new electric field peaks, making the surface electric field more uniform. Moreover, the difference in the dielectric constants between the low dielectric constant layer and the silicon dioxide layer will also cause electric field peaks on both sides of the junction between the low dielectric constant layer and the silicon dioxide layer, and this electric field peak will improve the breakdown voltage resistance and doping concentration on both sides of the shallow trench, thereby reducing the on-resistance of this region at the same time.
[0048] Among them, as Figure 1 shown, the gate region includes:
[0049] A gate dielectric layer 51, which is located on the side of the drift region 2 and penetrates into the interior of the drift region 2, and is connected to the second-conductivity-type channel region 3 and the source region;
[0050] A gate electrode 52, which is surrounded by the gate dielectric layer 51.
[0051] The source region includes:
[0052] A second-conductivity-type heavily doped region 61, which is located on the surface of the drift region 2 near one side of the shallow trench;
[0053] A first-conductivity-type heavily doped region 62, which is located on the surface of the drift region 2 between the second-conductivity-type heavily doped region 61 and the gate region;
[0054] A source electrode 63, which is located on the surfaces of the second-conductivity-type heavily doped region 61 and the first-conductivity-type heavily doped region 62.
[0055] The second-conductivity-type channel region 3 is located below the source region, one side is connected to the gate region, and the other side is connected to the trench dielectric layer 41.
[0056] The drain region includes:
[0057] A drain region first-conductivity-type heavily doped region 71, which is located on the surface of the drift region 2 on the other side of the shallow trench;
[0058] The drain electrode 72 is located on the surface of the heavily doped region 71 of the first conductivity type in the drain region.
[0059] In another embodiment, the trench dielectric layer is made of a high-k dielectric material. Specifically, the high-k dielectric material is silicon oxynitride, hafnium oxide, or other materials with a dielectric constant higher than 3.9.
[0060] In this embodiment, the trench dielectric layer is made of a high-k dielectric material. Due to its relatively high dielectric constant, it can effectively alleviate the electric field concentration phenomenon in silicon, thereby further depleting the drift region. This structure can effectively improve the breakdown voltage of the drift region and further increase the doping concentration in this region, thereby reducing the on-resistance.
[0061] In another embodiment, the gate dielectric layer in the gate region is made of a high-k dielectric material.
[0062] In this embodiment, the gate dielectric layer made of a high-k dielectric material can form a metal-high-k dielectric material-second conductivity type doping sandwich structure, that is, the conduction channel is a vertical structure. When the gate of the device is under pressure, that is, when the device is in the on state, this structure can be regarded as a capacitor, and a certain number of electrons are accumulated at the edge of the second conductivity type channel region close to the gate dielectric layer, thereby reducing the on-resistance of the channel and increasing the current.
[0063] In another embodiment, as Figure 2 shown, an SOI thin film layer 8 is provided between the substrate 1 and the drift region 2.
[0064] SOI (Silicon on Insulator) is a special semiconductor material structure, which consists of a thin single-crystalline silicon film, a buried oxide layer (usually silicon dioxide), and a silicon substrate supporting this layer structure. In this embodiment, the SOI thin film layer 8 and the substrate 1 form an SOI structure.
[0065] For a superjunction LDMOS device, when it is in the off state, the first conductivity type doped regions in the superjunction drift region are not only depleted by the adjacent second conductivity type doped regions, but also depleted by the second conductivity type high-resistance substrate. This process results in incomplete depletion of the second conductivity type doped regions, limiting the superjunction breakdown voltage region to withstand a higher breakdown voltage and weakening the overall performance of the device.
[0066] In this embodiment, the SOI thin film layer 8 is arranged below the super junction structure, which can effectively avoid the depletion of the first conductive type column and the second conductive type high-resistance substrate in the super junction drift region, so that the second conductive type column in the super junction drift region can be completely depleted, thereby improving the vertical withstand voltage characteristics of the device, and utilizing the difference in dielectric constants to assist in depleting the lower half of the super junction structure, thereby increasing the lateral breakdown voltage and the doping of the first conductive type region, and reducing the on-resistance.
[0067] Through research by the inventors, it was further discovered that although the application of the SOI thin film layer 8 under the super junction structure can increase the lateral breakdown voltage, increase the doping of the first conductive type region and reduce the on-resistance, the drift region on the side close to the source region under the shallow trench is not completely depleted, and the electric field tends to concentrate at the bottom of the second conductive type channel region, making the electric field distribution in this area extremely uneven and easy to breakdown.
[0068] So in another embodiment, if Figure 3 As shown, a plurality of “Γ”-shaped protruding regions are provided on the surface of the SOI thin film layer 8 corresponding to the source region.
[0069] In this embodiment, considering that the drift region on the side close to the source region below the shallow trench is not completely depleted and the electric field is easily concentrated at the bottom of the second conductive type channel region, a plurality of "Γ"-shaped protruding regions are arranged on the surface of the SOI thin film layer 8 corresponding to the source region. The structure of the plurality of "Γ"-shaped protruding regions prevents the source end from extracting charges from the interface inversion layer, thereby increasing the interface hole concentration in the structure, making the electric field distribution in the original region more uniform and the depletion more thorough, effectively increasing the breakdown voltage of the region, and thereby increasing the doping concentration of the region, thereby reducing its on-resistance at the same time.
[0070] In the present invention, the source electrode, the drain electrode and the gate electrode are metal electrodes. Aluminum or silver is used in the device to conduct voltage and control the function and use of the device.
[0071] Another embodiment of the present invention discloses a method for manufacturing a super junction LDMOS device, comprising:
[0072] providing a substrate;
[0073] forming a drift region on the surface of the substrate, wherein the drift region is composed of first conductive type doped regions and second conductive type doped regions that are alternately arranged;
[0074] Etching the drift region to form a shallow trench in a preset shallow trench region;
[0075] forming a trench dielectric layer on the inner surface of the shallow trench;
[0076] forming a silicon dioxide layer in the trench;
[0077] A low-k dielectric layer is formed on the surface of the silicon dioxide layer, and the low-k dielectric layer fills the trench;
[0078] A gate region is formed on the sidewall of the drift region on one side of the shallow trench;
[0079] A channel region of the second conductivity type is formed in the drift region between the gate region and the trench;
[0080] A source region is formed in the drift region above the channel region of the second conductivity type;
[0081] A drain region is formed in the drift region on the other side of the shallow trench.
[0082] For the superjunction LDMOS device fabricated by the method for fabricating a superjunction LDMOS device disclosed in this embodiment, a shallow trench is provided in the drift region between the source region and the drain region, a trench dielectric layer is provided on the inner wall of the shallow trench, and the shallow trench is sequentially filled with a silicon dioxide layer and a low-k dielectric layer located on the surface of the silicon dioxide layer and filling the shallow trench. Due to the difference in dielectric constants between the low-k dielectric layer and the silicon dioxide layer, electric field peaks will be induced on both sides of the junction between the low-k dielectric layer and the silicon dioxide layer, and these electric field peaks will improve the breakdown voltage and doping concentration on both sides of the shallow trench, thereby reducing the on-resistance of this region.
[0083] In another embodiment, the silicon dioxide layer and the low-k dielectric layer sequentially filled in the shallow trench of the superjunction LDMOS device fabricated by the method divide the shallow trench into upper and lower parts, and the area ratios of the two fillings can be adjusted. In this embodiment, the ratio of the silicon dioxide layer to the low-k dielectric layer is 1:1, and it can also be adjusted to other ratios such as 2:1 and 1:2 according to requirements.
[0084] In another embodiment, the material for fabricating the trench dielectric layer is a high-k dielectric material.
[0085] In this embodiment, the material for fabricating the trench dielectric layer is a high-k dielectric material, and its dielectric constant is relatively high, which can effectively alleviate the electric field concentration phenomenon in the shallow trench, thereby further depleting the drift region. This structure can effectively improve the breakdown voltage of the drift region and further increase the doping concentration of the first conductivity type region in this region, thereby reducing the on-resistance.
[0086] In another embodiment, the process of forming a gate region on the sidewall of the drift region on one side of the shallow trench includes:
[0087] Etching the preset gate region on the surface of the drift region to form a gate groove;
[0088] Depositing a gate dielectric layer in the gate groove, and the gate dielectric layer is connected to the channel region of the second conductivity type and the source region;
[0089] Deposit metal on the surface of the gate dielectric layer to form a gate electrode.
[0090] Specifically, a thermal oxidation process or a CVD process can be used to form the gate dielectric layer material on the inner surface of the gate trench.
[0091] In another embodiment, the material for fabricating the gate dielectric layer in the gate region is a high-k dielectric material.
[0092] In this embodiment, the gate dielectric layer made of a high-k dielectric material can produce a metal-high-k dielectric material-second conductivity type doping sandwich structure, that is, the conduction channel is a vertical structure. When the gate of the device is in a pressurized state, that is, when the device is in the on state, this structure can be regarded as a capacitor, and a certain number of electrons are accumulated at the edge of the second conductivity type channel region close to the gate dielectric layer, thereby reducing the on-resistance of the channel and increasing the current.
[0093] In another embodiment, the process of forming the source region in the drift region between the gate region and the shallow trench includes:
[0094] Using an ion implantation process, implant second conductivity type impurity ions into the drift region corresponding to the source region, then implant first conductivity type impurity ions on the side of the drift region between the gate region and the shallow trench close to the gate region, implant second conductivity type impurity ions on the side close to the shallow trench, and then use a thermal annealing process to activate the impurity ions to form a second conductivity type heavily doped region and a first conductivity type heavily doped region of the source region. The second conductivity type doped region below the second conductivity type heavily doped region and the first conductivity type heavily doped region of the source region is the second conductivity type channel region. Then form a source electrode on the surface of the second conductivity type heavily doped region and the first conductivity type heavily doped region.
[0095] In another embodiment, the process of forming the drain region in the drift region on the other side of the shallow trench includes:
[0096] Using an ion implantation process, implant first conductivity type impurity ions into the drift region on the other side of the shallow trench, and then use a thermal annealing process to activate the impurity ions to form a first conductivity type heavily doped region of the drain region. Then form a drain electrode on the surface of the first conductivity type heavily doped region of the drain region.
[0097] In another embodiment, the method for manufacturing the superjunction LDMOS device further includes: forming an SOI thin film layer 8 between the substrate and the drift region.
[0098] Specifically, an SOI thin film layer 8 may be formed on the surface of the substrate by using processes such as implanted oxygen separation technology, bonding etch-back technology or smart shearing technology. Then, an intrinsic polysilicon layer is deposited on the surface of the SOI thin film layer 8 by using processes such as L second conductivity type CVD, second conductivity type ECVD, second conductivity type EALD or A second conductivity type CVD. Finally, an ion implantation process is used to alternately implant first conductivity type impurity ions and second conductivity type impurity ions into the intrinsic polysilicon layer, and a thermal annealing process is used to activate the impurity ions to form a drift region.
[0099] The super junction LDMOS device manufactured by the method described in this embodiment is provided with an SOI thin film layer 8. The SOI thin film layer 8 is provided below the super junction structure, which can effectively avoid the phenomenon of depletion of the first conductive type column and the second conductive type high resistance substrate in the super junction drift region, so that the second conductive type column in the super junction drift region can be completely depleted, thereby improving the vertical withstand voltage characteristics of the device, and utilizing the difference in dielectric constants to assist in depleting the lower half of the super junction structure, thereby improving the lateral breakdown voltage and the doping of the first conductive type region, and reducing the on-resistance.
[0100] In another embodiment, the method for manufacturing the super junction LDMOS device further includes:
[0101] forming an SOI thin film layer 8 between the substrate and the drift region;
[0102] A plurality of “Γ”-shaped protrusions are formed on the surface of the SOI thin film layer 8 on the side corresponding to the source region.
[0103] Specifically, a plurality of “Γ”-shaped protruding structures may be formed on the surface of the SOI thin film layer 8 corresponding to the source region by using a photolithography process.
[0104] The super junction LDMOS device obtained by the method described in this embodiment takes into account that the drift region on the side close to the source region below the shallow trench is not completely depleted, and the electric field is easily concentrated at the bottom of the second conductive type column structure, and multiple "Γ"-shaped protruding regions are set on the surface of the SOI film layer 8 corresponding to the source region. The structure of the multiple "Γ"-shaped protruding regions prevents the source end from extracting charges from the interface inversion layer, so that the interface hole concentration in the structure increases, the electric field distribution in the original area is more uniform, and the depletion is more thorough, which effectively increases the breakdown voltage of the area, and can thereby increase the doping concentration of the area, thereby reducing its on-resistance at the same time.
[0105] It should be noted that, in the present invention, the first conductivity type may be N type, and the corresponding second conductivity type may be P type. Conversely, the first conductivity type may be P type, and the corresponding second conductivity type may be N type.
[0106] The technical features of the above-described embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered to be within the scope described in this specification. The "first" and "second" mentioned in the text are only for distinction and do not limit the content of the present invention.
[0107] The above-described embodiments only express several implementation manners of the present invention, and the description is relatively specific and detailed, but it should not be construed as a limitation on the scope of the invention patent. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present invention, several modifications and improvements can still be made, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the present invention patent shall be subject to the appended claims.
Claims
1. A super junction LDMOS device, comprising: A substrate and a drift region located on a surface of the substrate, wherein in a vertical direction, the drift region is composed of first conductivity type doped regions and second conductivity type doped regions that are alternately arranged; In the lateral direction, a gate region is arranged on a side wall of the drift region, a source region is arranged near the gate region, a second conductive type channel region is arranged in the drift region below the source region and near the gate region, and a drain region is arranged on the other side of the drift region. It is characterized in that a shallow trench is arranged in the drift region between the source region and the drain region, a trench dielectric layer is arranged on the inner wall of the shallow trench, and the shallow trench is filled with a silicon dioxide layer and a low dielectric constant layer located on the surface of the silicon dioxide layer and filling the trench in sequence.
2. The super junction LDMOS device according to claim 1, characterized in that: The volume ratio of the silicon dioxide layer and the low dielectric constant layer in the shallow trench is 1:
1.
3. The super junction LDMOS device according to claim 1, characterized in that: The low dielectric constant layer is made of SiLK, FOx or MSQ.
4. The super junction LDMOS device according to claim 1, characterized in that: The trench dielectric layer is made of a high dielectric constant material.
5. The super junction LDMOS device according to claim 1, characterized in that: The gate dielectric layer in the gate region is made of a high dielectric constant material.
6. The super junction LDMOS device according to claim 4 or 5, characterized in that: The high dielectric constant material is silicon oxynitride or hafnium oxide.
7. The super junction LDMOS device according to claim 1, characterized in that: An SOI thin film layer is also arranged between the substrate and the drift region.
8. The super junction LDMOS device according to claim 7, characterized in that: In the lateral direction, a plurality of “Γ” shaped protruding regions are arranged on the surface of the SOI thin film layer corresponding to the source region.
9. A method for manufacturing a super junction LDMOS device, characterized in that: include: providing a substrate; forming a drift region on the surface of the substrate, wherein the drift region is composed of first conductivity type doped regions and second conductivity type doped regions that are alternately arranged; Etching the drift region to form a shallow trench in a preset shallow trench region; forming a trench dielectric layer on the inner surface of the shallow trench; forming a silicon dioxide layer in the trench; forming a low dielectric constant layer on the surface of the silicon dioxide layer, wherein the low dielectric constant layer fills the groove; forming a gate region on a sidewall of the drift region on one side of the shallow trench; forming a second conductive type channel region in the drift region between the gate region and the trench; forming a source region in the drift region above the second conductivity type channel region; A drain region is formed in the drift region at the other side of the shallow trench.
10. The method for manufacturing a super junction LDMOS device according to claim 9, characterized in that: Also includes: forming an SOI thin film on the surface of the substrate; The drift region is prepared on the surface of the SOI film.