Test method and device based on frequency division isolation mechanism, test system, and computer readable storage medium

Abstract

The application relates to the chip testing technical field and discloses a test method based on a frequency division isolation mechanism, which comprises the following steps: constructing a center frequency sequence according to an adaptive working frequency band of a to-be-tested chip and the number of test units; the center frequency sequence comprises mutually different center frequencies; distributing the center frequencies to the test units according to the frequency division isolation mechanism; the frequency division isolation mechanism satisfies the condition that the interval between the center frequencies corresponding to any two test units with adjacent physical positions is not less than a preset frequency domain isolation threshold; and in response to a test enabling signal, a multi-path radio frequency driving signal is configured according to the center frequencies distributed to the test units to drive all the to-be-tested chips to perform parallel testing. The method can suppress the spatial superposition of multi-path same-frequency reflection signals to form a standing wave, weaken the radio frequency signal crosstalk between adjacent test units, and improve the stability and reliability of chip parallel testing. The application further discloses a test device based on the frequency division isolation mechanism, a chip testing system and a storage medium.

Description

Technical Field

[0001] This application relates to the field of chip testing technology, and for example to a testing method and apparatus, a testing system, and a computer-readable storage medium based on a frequency division isolation mechanism. Background Technology

[0002] Currently, in the FT testing of UHF RFID (Ultra High Frequency Radio Frequency Identification) chips, the industry widely adopts parallel testing technology with multiple test units to improve testing efficiency. For example, eight or even 16 chips under test are placed simultaneously on a single test substrate, and excitation signals are sent to multiple chips under test and responses are received simultaneously through an RF distribution network. However, with the increase in the number of parallel test units, RF crosstalk between adjacent test units becomes a problem. When multiple test units are working simultaneously, the transmit link of each test unit radiates energy into space and onto the PCB (Printed Circuit Board) traces. Once this energy couples into the receive link of adjacent test units, it will cause a decrease in receiver sensitivity, an increase in bit error rate, and in severe cases, even cause the test results to become completely invalid.

[0003] The relevant technology configures crosstalk suppression circuitry in the RF link of each test unit.

[0004] In the process of implementing the embodiments of this disclosure, at least the following problems were found in the related art: While crosstalk suppression circuits can suppress crosstalk, their isolation is limited (typically 50~60dB). In high-sensitivity testing scenarios, it is difficult to overcome RF crosstalk between adjacent test units. Moreover, hardware methods cannot avoid standing wave interference formed in space by multiple co-frequency reflected signals, which affects the stability and reliability of parallel chip testing.

[0005] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this application, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0006] To provide a basic understanding of some aspects of the disclosed embodiments, a brief summary is given below. This summary is not intended as a general commentary, nor is it intended to identify key / important components or describe the scope of protection of these embodiments, but rather as a prelude to the detailed description that follows.

[0007] This disclosure provides a test method, apparatus, and system based on a frequency division isolation mechanism, as well as a computer-readable storage medium, to suppress the formation of standing waves by the spatial superposition of multiple co-frequency reflected signals, thereby improving the stability and reliability of parallel chip testing.

[0008] In some embodiments, the testing method is applied to a chip testing system, which includes an RF generation module and multiple test units. The RF generation module generates multiple RF drive signals. The input of each test unit is connected to the RF generation module, and the output of each test unit is connected to a chip under test. The testing method includes: constructing a center frequency sequence based on the operating frequency band adapted to the chip under test and the number of test units; wherein the center frequency sequence includes distinct center frequencies; allocating center frequencies to each test unit according to a frequency division isolation mechanism; wherein the frequency division isolation mechanism satisfies that the center frequency interval between any two physically adjacent test units is not less than a preset frequency domain isolation threshold; and configuring multiple RF drive signals according to the center frequencies allocated to each test unit to drive all chips under test to perform parallel testing in response to a test enable signal.

[0009] In some embodiments, a center frequency sequence is constructed based on the operating frequency band adapted to the chip under test and the number of test units, including: determining the bandwidth of the operating frequency band; determining the frequency step size based on the bandwidth and the number of test units; using a lower frequency threshold as the starting center frequency, successively adding frequency step sizes to obtain different center frequencies, and constructing a generated center frequency sequence.

[0010] In some embodiments, determining the frequency step size based on the bandwidth and the number of test units includes: determining the frequency step size based on the ratio of the bandwidth to the number of test units.

[0011] In some embodiments, the absolute value of the center frequency difference between test units that are physically adjacent is greater than the absolute value of the center frequency difference between test units that are not physically adjacent.

[0012] In some embodiments, allocating a center frequency to each test unit according to a frequency division isolation mechanism includes: allocating a corresponding center frequency to each test unit according to the physical layout of the test units by using an alternating arrangement of high and low frequencies.

[0013] In some embodiments, allocating a center frequency to each test unit according to the frequency division isolation mechanism includes: sequentially allocating a corresponding center frequency to each test unit according to the physical layout location of the test unit and the sequence number of the center frequency sequence.

[0014] In some embodiments, the method further includes: in response to a test enable signal, configuring multiple radio frequency drive signals according to the center frequency allocated to each test unit to drive all chips under test to perform parallel tests, and obtaining test results corresponding to each chip under test; if the test result indicates a test failure, adjusting the current center frequency of the test unit corresponding to the test result according to a preset frequency offset to obtain a radio frequency drive offset frequency; and reconfiguring the radio frequency drive signal of the corresponding test unit according to the radio frequency drive offset frequency.

[0015] In some embodiments, the testing apparatus includes a processor and a memory storing program instructions, the processor being configured to execute the frequency division isolation mechanism-based testing method described above when running the program instructions.

[0016] In some embodiments, the chip testing system includes: an RF generation module for generating multiple RF drive signals; a test channel including multiple test units, the input of each test unit being connected to the RF generation module, and the output of each test unit being connected to a chip under test; and a main control module connected to the multiple test units, including the test device based on the frequency division isolation mechanism described above.

[0017] In some embodiments, the computer-readable storage medium stores program instructions that, when executed, cause the computer to perform the test method based on the frequency division isolation mechanism described above.

[0018] The testing method, apparatus, system, and computer-readable storage medium based on frequency division isolation mechanism provided in this disclosure can achieve the following technical effects: This embodiment first defines the effective frequency domain range based on the operating frequency band adapted to the chip under test (DUT), and constructs a center frequency sequence containing multiple distinct center frequencies based on the number of test units. This ensures that all generated center frequencies are within the DUT's operating frequency band, avoiding the configuration of invalid frequencies outside the operating frequency band. Then, according to the frequency division isolation mechanism, the center frequency interval between any two physically adjacent test units is constrained to be no less than a preset frequency domain isolation threshold. Under these constraints, in response to the test enable signal, multiple RF drive signals are configured according to the center frequencies allocated to each test unit to perform parallel testing. Through the frequency division isolation mechanism, the frequency spacing of RF drive signals in adjacent test channels can be increased, eliminating the condition of multiple RF drive signals propagating at the same frequency, suppressing the spatial superposition of multiple co-frequency reflected signals to form standing waves, reducing RF signal crosstalk between adjacent test units, and improving the stability and reliability of parallel chip testing.

[0019] The above general description and the description below are exemplary and illustrative only and are not intended to limit this application. Attached Figure Description

[0020] One or more embodiments are illustrated by way of example with reference to the accompanying drawings. These illustrations and drawings do not constitute a limitation on the embodiments. Elements having the same reference numerals in the drawings are shown as similar elements. The drawings are not to be scaled. And wherein: Figure 1 This is a schematic diagram of the architecture of a chip testing system provided in an embodiment of this disclosure; Figure 2 This is a schematic diagram of a test method based on a frequency division isolation mechanism provided in an embodiment of this disclosure; Figure 3 This is a schematic diagram of another test method based on a frequency division isolation mechanism provided in an embodiment of this disclosure; Figure 4 This is a schematic diagram of another test method based on a frequency division isolation mechanism provided in an embodiment of this disclosure; Figure 5 This is a schematic diagram of the architecture of another chip testing system provided in this embodiment of the disclosure; Figure 6 This is a radio frequency link TX signal stream connection of a test unit provided in an embodiment of this disclosure; Figure 7 This is a radio frequency link RX signal flow connection of a test unit provided in an embodiment of this disclosure; Figure 8 This is a schematic diagram of a test device based on a frequency division isolation mechanism provided in an embodiment of this disclosure.

[0021] Figure label: 10: Chip testing system; 100: RF generation module; 200: Test channels; 300: Main control module; 400: Chip under test; 200a: Test unit; 2001: Unidirectional electromagnetic wave transmitter; 2002: Isolator; 2003: Attenuator; 2004: Multiplexer; 100a: Local oscillator signal source; 100b: Radio frequency signal distribution network; 100c: Amplifier; 1001: Primary power divider network; 1002: Secondary power divider network; 500: Coupler; 601: First balun; 602: Second balun; 70: Device for testing chips; 700: Processor; 701: Memory; 702: Communication interface; 703: Bus. Detailed Implementation

[0022] To provide a more detailed understanding of the features and technical content of the embodiments of this disclosure, the implementation of the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. The accompanying drawings are for illustrative purposes only and are not intended to limit the embodiments of this disclosure. In the following technical description, for ease of explanation, several details are used to provide a full understanding of the disclosed embodiments. However, one or more embodiments may still be implemented without these details. In other cases, well-known structures and devices may be simplified in their depiction to simplify the drawings.

[0023] The terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this disclosure are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of this disclosure described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion.

[0024] Unless otherwise stated, the term "multiple" means two or more.

[0025] In this embodiment of the disclosure, the character " / " indicates that the objects before and after it are in an "or" relationship. For example, A / B means: A or B.

[0026] The term "correspondence" can refer to an association or binding relationship. The correspondence between A and B means that there is an association or binding relationship between A and B.

[0027] Combination Figure 1 As shown, this embodiment of the present disclosure provides a chip testing system 10, including an RF generation module and multiple test units. The RF generation module is used to generate multiple RF drive signals. The input terminal of each test unit is connected to the RF generation module, and the output terminal of each test unit is connected to a chip under test.

[0028] Based on the chip testing system 10 described above, combined with Figure 2 As shown, this disclosure provides a testing method based on a frequency division isolation mechanism, including: S01, the main control module constructs a center frequency sequence based on the operating frequency band adapted to the chip under test and the number of test units. This center frequency sequence includes distinct center frequencies.

[0029] S02, the main control module allocates a center frequency to each test unit according to the frequency division isolation mechanism. The frequency division isolation mechanism satisfies the following condition: the center frequency interval between any two physically adjacent test units is not less than a preset frequency domain isolation threshold.

[0030] In this step, physical proximity means that test stations that are adjacent to each other on the test carrier are considered to be physically adjacent, according to the array arrangement of the test units.

[0031] S03, the main control module responds to the test enable signal and configures multiple RF drive signals according to the center frequency allocated to each test unit to drive all chips under test to perform parallel tests.

[0032] The test method based on frequency division isolation mechanism provided in this disclosure first defines the effective frequency domain range according to the operating frequency band adapted to the chip under test (DUT), and constructs a center frequency sequence containing multiple distinct center frequencies based on the number of test units. This ensures that all generated center frequencies are within the operating frequency band adapted to the DUT, avoiding the configuration of invalid frequencies outside the operating frequency band. Then, according to the frequency division isolation mechanism, the center frequency interval between any two physically adjacent test units is not less than a preset frequency domain isolation threshold. Under the above constraints, in response to the test enable signal, multiple RF drive signals are configured according to the center frequencies allocated to each test unit to perform parallel testing. Through the frequency division isolation mechanism, the frequency spacing of RF drive signals in adjacent test channels can be increased, eliminating the condition of multiple RF drive signals propagating at the same frequency, suppressing the formation of standing waves by the spatial superposition of multiple co-frequency reflected signals, weakening RF signal crosstalk between adjacent test units, and improving the stability and reliability of parallel chip testing.

[0033] Optionally, combined Figure 3 As shown, the main control module constructs the center frequency sequence, including: S11, the main control module determines the bandwidth of the operating frequency band. The operating frequency band is... , This is the lower limit threshold for frequency. This is the upper limit threshold for frequency.

[0034] S12, the main control module determines the frequency step size based on the bandwidth and the number of test units.

[0035] S13, the main control module uses the lower limit threshold as the starting center frequency, and successively adds frequency steps to obtain different center frequencies, and constructs a center frequency sequence.

[0036] In this way, the main control module first determines the bandwidth based on the operating frequency band adapted to the chip under test (DUT), then calculates the frequency step size based on the number of test units. Subsequently, using the lower frequency threshold as the starting center frequency, the frequency step size is successively added to obtain distinct center frequencies, thus constructing the center frequency sequence. This method of constructing the center frequency sequence ensures that the center frequencies are evenly distributed within the effective frequency domain of the DUT, guaranteeing that all generated center frequencies fall within the effective frequency domain. Simultaneously, the orderly generated, arithmetically distributed multiple sets of frequency points facilitate subsequent frequency allocation according to the frequency division isolation mechanism, effectively avoiding the problem of insufficient center frequency spacing and providing controllable frequency domain resources for suppressing standing wave crosstalk.

[0037] In some optional implementations, the main control module uses a lower frequency threshold as the starting center frequency, successively adds frequency steps to obtain distinct center frequencies, and constructs a sequence of generated center frequencies, including: , For sequence number, For frequency step size, For the first One center frequency.

[0038] Optionally, the main control module determines the frequency step size based on the bandwidth and the number of test units, including: The main control module determines the frequency step size based on the ratio of bandwidth to the number of test units.

[0039] In this way, the ratio of bandwidth to the number of test units is determined as the frequency step size, achieving a uniform division of the working frequency band and ensuring that the generated center frequencies are evenly distributed within the working frequency band. This uniform arrangement reduces the risk of insufficient frequency spacing during subsequent center frequency allocation, makes it easier to meet the constraints of the frequency division isolation mechanism, and thus effectively suppresses spatial standing wave crosstalk generated during parallel testing.

[0040] In some optional implementations, the main control module determines the frequency step size based on the ratio of bandwidth to the number of test units, including: the main control module uses the ratio of bandwidth to the number of test units as the frequency step size. In other optional embodiments, the main control module determines the frequency step size based on the ratio of bandwidth to the number of test units, including: the main control module obtains the theoretical frequency step size based on the ratio of bandwidth to the number of test units; the main control module selects the largest standard frequency range smaller than the theoretical frequency step size as the frequency step size. As an example, if the theoretical frequency step size is 12.5 MHz (megahertz) and the largest standard frequency range smaller than the theoretical frequency step size is 10 MHz, then the main control module uses 10 MHz as the frequency step size.

[0041] Optionally, the absolute value of the center frequency difference corresponding to test units that are physically adjacent is greater than the absolute value of the center frequency difference corresponding to test units that are not physically adjacent.

[0042] This allows for a greater frequency domain spacing between test units that are physically close together, prioritizing the compliance of test units that are physically close together with the frequency division isolation mechanism, reducing the coupling and superposition effect of RF signals between adjacent test units, suppressing the formation of spatial standing waves from multiple co-frequency reflected signals, reducing standing wave crosstalk, and improving the stability and reliability of parallel chip testing.

[0043] Optionally, the main control module allocates a center frequency to each test unit according to the frequency division isolation mechanism, including: the main control module allocates the corresponding center frequency to each test unit in sequence according to the physical layout location of the test unit and the number of the center frequency sequence.

[0044] This suppresses the formation of spatial standing waves from multiple co-frequency reflected signals, reduces standing wave crosstalk, and improves the stability and reliability of parallel chip testing.

[0045] In some optional implementations, the operating frequency band of the chip under test is the UHF band, specifically [860, 960] MHz. The chip test system includes eight test units mounted on a test carrier board, numbered Site1 to Site8. Site1 and Site2 are physically adjacent, Site2 and Site3 are physically adjacent, and so on, with Site7 and Site8 being physically adjacent. The center frequency sequence is {860, 870, 880, 890, 900, 910, 920, 930}. The unit is MHz.

[0046] The center frequencies assigned to each test unit are shown in Table 1. Referring to Table 1, the main control module assigns center frequencies to each test unit sequentially according to their physical location and center frequency sequence number. The center frequencies of the eight test units are evenly distributed within a 70MHz bandwidth, resembling a comb. Since the frequency step size is 10MHz, which is much larger than the typical signal bandwidth of a UHF RFID chip, the receiver can filter out signals from adjacent test units using digital or analog filters, achieving frequency division multiple access (FDMA). The typical signal bandwidth is usually 250~500kHz.

[0047] Table 1 Center Frequency Allocation Table

[0048] Optionally, the main control module allocates a center frequency to each test unit according to the frequency division isolation mechanism, including: the main control module allocates a corresponding center frequency to each test unit according to the physical layout of the test unit by using an alternating arrangement of high and low frequencies.

[0049] In this way, since the coupling between test units that are physically adjacent is the strongest, the alternating arrangement of high and low frequencies can maximize the absolute value of the center frequency difference between test units that are physically adjacent, making it easier to meet the frequency division isolation mechanism constraints of adjacent test units, avoiding the situation of concentrated clustering of center frequencies, and further reducing adjacent frequency leakage.

[0050] In some optional implementations, the operating frequency band of the chip under test is [860, 960] MHz. The chip test system includes eight test units mounted on the test carrier board, numbered Site1 to Site8. Site1 and Site2 are physically adjacent, Site2 and Site3 are physically adjacent, and so on, with Site7 and Site8 being physically adjacent. The center frequency sequence is {860, 870, 880, 890, 900, 910, 920, 930}. The unit is MHz.

[0051] The center frequencies assigned to each test unit are shown in Table 2. Based on Table 2, the main control module allocates center frequencies using an alternating arrangement of high and low frequencies according to the physical location of the test units.

[0052] Table 2 Center Frequency Alternation Table

[0053] Combination Figure 4 As shown in the embodiments of this disclosure, a test method based on a frequency division isolation mechanism is also provided, including: S21, the main control module constructs a center frequency sequence based on the operating frequency band adapted to the chip under test and the number of test units. This center frequency sequence includes distinct center frequencies.

[0054] S22, the main control module allocates a center frequency to each test unit according to the frequency division isolation mechanism. The frequency division isolation mechanism satisfies the following condition: the center frequency interval between any two physically adjacent test units is not less than a preset frequency domain isolation threshold.

[0055] S23, the main control module responds to the test enable signal and configures multiple RF drive signals according to the center frequency allocated to each test unit to drive all chips under test to perform parallel tests.

[0056] S24, the main control module obtains the test results corresponding to each chip under test.

[0057] S25, if the test result indicates that the test has failed, the main control module adjusts the current center frequency of the test unit corresponding to the test result according to the preset frequency offset to obtain the RF drive offset frequency.

[0058] In this step, the preset frequency offset is less than the frequency step size; or, the preset frequency offset is an integer multiple of the frequency step size. When the preset frequency offset is an integer multiple of the frequency step size, the main control module adjusts the current center frequency of the test unit corresponding to the test result according to the preset frequency offset to obtain the RF drive offset frequency. This includes: the main control module adjusting the current center frequency of the test unit corresponding to the test result according to the preset frequency offset to obtain an idle center frequency as the RF drive offset frequency. In this way, the current center frequency is adjusted to an idle frequency point with less interference, avoiding interference sources. It should be noted that adjusting the current center frequency of the test unit corresponding to the test result according to the preset frequency offset can be either a sum of the current center frequency and the preset frequency offset, or a difference between the current center frequency and the preset frequency offset.

[0059] S26, the main control module reconfigures the RF drive signal of the corresponding test unit according to the RF drive offset frequency.

[0060] The test method based on the frequency division isolation mechanism provided in this disclosure achieves frequency domain isolation through the frequency division isolation mechanism, suppressing standing wave crosstalk caused by the superposition of multiple co-frequency reflected signals in parallel testing scenarios, and ensuring the signal-to-noise ratio of the test environment. After the chip under test fails to test, the current center frequency of the test unit is offset and adjusted, and the test is restarted based on the RF drive offset frequency. Some test failures are caused by standing waves and RF coupling interference at specific frequency points. By offsetting the frequency point, the spatial RF interference conditions can be changed, avoiding the interference pole of the current center frequency, achieving adaptive interference suppression, reducing the probability of false positives, and further improving the reliability of parallel chip testing.

[0061] Combination Figure 8 As shown, this disclosure provides a test apparatus 70 based on a frequency division isolation mechanism, including a processor 700 and a memory 701. Optionally, the apparatus 70 may further include a communication interface 702 and a bus 703. The processor 700, communication interface 702, and memory 701 can communicate with each other via the bus 703. The communication interface 702 can be used for information transmission. The processor 700 can call logical instructions in the memory 701 to execute the frequency division isolation mechanism-based test method of the above embodiment.

[0062] Furthermore, the logic instructions in the aforementioned memory 101 can be implemented as software functional units and, when sold or used as independent products, can be stored in a computer-readable storage medium.

[0063] The memory 701, as a computer-readable storage medium, can be used to store software programs and computer-executable programs, such as program instructions / modules corresponding to the methods in the embodiments of this disclosure. The processor 100 executes functional applications and data processing by running the program instructions / modules stored in the memory 701, thereby implementing the test method based on the frequency division isolation mechanism in the above embodiments.

[0064] The memory 701 may include a program storage area and a data storage area. The program storage area may store the operating system and application programs required for at least one function; the data storage area may store data created based on the use of the terminal device. Furthermore, the memory 701 may include high-speed random access memory and may also include non-volatile memory.

[0065] Combination Figure 1 and Figure 5 As shown in the figure, this disclosure also provides a chip testing system 10, including an RF generation module 100, a test channel 200 and a main control module 300.

[0066] The radio frequency generation module 100 is used to generate multiple radio frequency drive signals.

[0067] The test channel 200 includes multiple test units 200a. The input terminal of each test unit 200a is connected to the radio frequency generation module 100, and the output terminal of each test unit 200a is connected to a chip under test 400.

[0068] The main control module 300 is connected to multiple test units 200a, including the test device 70 based on the frequency division isolation mechanism as described above. The main control module 300 is used to generate parallel test commands in response to serial test commands to trigger each test unit 200a to perform parallel finished product tests on the corresponding chip under test 400.

[0069] Test unit 200a includes: The unidirectional electromagnetic wave transmitter 2001 includes a first end Port1 and a second end Port2. The first end Port1 is connected to the output end of the radio frequency generation module 100 and is used to transmit a single radio frequency drive signal based on the unidirectional transmission characteristics.

[0070] Isolator 2002 has its input connected to the second terminal Port2 and its output connected to a chip under test 400, and is used to suppress reverse noise based on its reverse isolation characteristics.

[0071] The chip testing system provided in this disclosure uses a unidirectional electromagnetic wave transmitter and an isolator connected in series in each test unit to form an isolated RF front end. The unidirectional electromagnetic wave transmitter isolates the transmit and receive links through its unidirectional transmission characteristics, while the isolator blocks the reverse noise of the chip under test through its reverse isolation characteristics. The two work together to suppress link crosstalk, effectively avoiding test errors caused by signal reflection and crosstalk, ensuring the purity and stability of the RF signal, and improving the accuracy and reliability of parallel chip testing.

[0072] By responding to serial test commands through the main control module, parallel test commands are generated to simultaneously trigger each test unit to perform parallel finished product tests on the corresponding chip under test, thereby realizing parallel stimulation and response acquisition at the physical layer and improving the finished product testing efficiency of the chip.

[0073] In addition, the test system has a simple control logic, is not limited by the input and output port resources of the machine, and can synchronously and accurately control the attenuators and multiplexers of multiple test channels, effectively ensuring the consistency of multi-station parallel testing.

[0074] Optionally, the main control module 300 includes an STM32F103 microcontroller. This allows the use of its general-purpose input / output interface to drive the control pins of the attenuators in each test unit, enabling parallel final product testing of the chip.

[0075] Optionally, the unidirectional electromagnetic wave transmitter 2001 includes a circulator. This allows for isolation of the transmit and receive links based on the unidirectional transmission characteristics of the circulator, effectively blocking the backflow of transmitted signals into the receive link, avoiding test errors caused by signal reflection and crosstalk, and ensuring the purity and stability of the radio frequency signal.

[0076] Optionally, combined Figure 7 As shown, the unidirectional electromagnetic wave transmitter 2001 also includes a third port 3. The test unit 200a also includes an attenuator 2003.

[0077] Attenuator 2003 has its input connected to the third terminal Port3 and its output connected to the input of isolator 2002. It is used to adjust the signal strength at the output of isolator 2002.

[0078] In this way, by configuring an attenuator connected to the third terminal of the unidirectional electromagnetic wave transmitter, the signal strength at the isolator output can be adjusted, enabling flexible control of the RF drive signal power level. This avoids damage to the chip under test due to excessive power or test failure due to insufficient power. Simultaneously, it can match the signal parameter requirements of different test conditions, improving the adaptability and versatility of parallel chip testing.

[0079] Optionally, the main control module 300 is also used to parse serial test commands and send enable signals to the attenuators 2003 of each test unit 200a to trigger the corresponding unidirectional electromagnetic wave transmitter 2001 to receive the radio frequency drive signal and send it to the chip under test via the corresponding isolator 2002; and The system receives echo signals transmitted sequentially via a unidirectional electromagnetic wave transmitter 2001 and an attenuator 2003. The echo signals are generated when the signal under test receives a radio frequency drive signal.

[0080] This enables integrated timing control of RF drive signal transmission and echo acquisition, precisely regulating the working state of each test unit, ensuring the synchronization of multi-channel signal transmission and reception, avoiding channel timing misalignment and signal acquisition lag, and ensuring synchronization during chip parallel testing. In addition to improving the accuracy and reliability of chip parallel testing, it also improves the efficiency of chip parallel testing.

[0081] Optionally, combined Figure 5 As shown, the radio frequency generation module 100 includes a local oscillator signal source 100a and a radio frequency signal distribution network 100b.

[0082] Local oscillator signal source 100a is used to generate radio frequency local oscillator signals.

[0083] The RF signal distribution network 100b is connected to the local oscillator signal source and the input terminals of each test unit. It is used to distribute the input RF local oscillator signal into multiple RF drive signals and send each RF drive signal to the corresponding test unit. Here, N represents the number of test units, that is, the number of chips under test.

[0084] This approach enables the even distribution of a single RF signal across multiple output channels, eliminating the need for multiple independent local oscillator signal sources, simplifying the hardware architecture of the test system, and reducing wiring complexity. Simultaneously, it ensures that multiple RF drive signals are output from the same source, laying the hardware foundation for multi-channel parallel synchronous testing.

[0085] Optionally, the RF generation module 100 further includes an amplifier 100c. The input terminal of the amplifier is connected to the local oscillator signal source 100a, and the output terminal of the amplifier 100c is connected to the RF signal distribution network 100b. The amplifier 100c is used to amplify the RF local oscillator signal to serve as the input signal for the RF signal distribution network 100b.

[0086] Optionally, the radio frequency drive signal includes a primary radio frequency drive signal and a secondary radio frequency drive signal. Combined with Figure 5 As shown, the radio frequency signal distribution network 100b includes a primary power divider network 1001 and a secondary power divider network 1002.

[0087] The primary power divider network 1001 is used to initially distribute radio frequency signals to generate multiple primary radio frequency drive signals.

[0088] The secondary power divider network 1002 has its input connected to the output of the primary power divider network. The secondary power divider network is used to redistribute each primary RF drive signal to generate a secondary RF drive signal.

[0089] Thus, the chip testing system provided in this embodiment of the present disclosure also adopts cascaded primary power divider network and secondary power divider network to construct tree-shaped local oscillator distribution network, which can synchronously generate eight or more RF drive signals, ensure that the local oscillator phase of each test channel is consistent and the amplitude is stable, provide a unified mechanism for multi-channel parallel testing, eliminate multi-channel test deviation, and effectively improve the consistency and reliability of multi-channel batch testing.

[0090] Optionally, the primary power splitting network 1001 includes at least two power splitters; and / or, the secondary power splitting network 1002 includes at least four power splitters.

[0091] In this way, a tree-shaped local oscillator distribution network is constructed by cascading primary and secondary power divider networks, which synchronously generates eight or more RF drive signals, ensuring that the local oscillator phase of each test channel is consistent and the amplitude is stable.

[0092] In some alternative embodiments, the primary power divider network includes a first two-way power divider, and the secondary power divider network includes a first four-way power divider and a second four-way power divider. This generates eight RF drive signals. In other alternative embodiments, the primary power divider network includes a second two-way power divider and a third two-way power divider connected in series, and the secondary power divider network includes a third four-way power divider, a fourth four-way power divider, a fifth four-way power divider, and a sixth four-way power divider. This generates sixteen RF drive signals.

[0093] Optionally, the first end is electrically connected to the output of the RF generation module 100 via an SMA connector.

[0094] In this way, the first end of the unidirectional electromagnetic transmitter is electrically connected to the output end of the RF generation module through an SMA connector, rather than through spatial radiation coupling, ensuring the reliability and stability of the test signal transmission.

[0095] Optionally, the chip under test 400 is a UHF band RFID chip. The chip under test 400 includes an RF input terminal and a DC power supply terminal, and the output terminal of each test unit 200a is connected to the RF input terminal of one chip under test 400.

[0096] Thus, the parallel testing of UHF band RFID chips in this embodiment of the present disclosure is beneficial for accurately adapting to the radio frequency testing scenarios of UHF band RFID chips. Considering the characteristics of this type of chip, such as frequency sensitivity, high signal reception accuracy requirements, and large batch testing needs, it relies on a high isolation, high synchronization, and high efficiency test architecture to accurately complete batch finished product testing of chip radio frequency performance and read / write performance, adapting to the mass production testing needs of industrial RFID chips.

[0097] In this embodiment of the disclosure, the radio frequency signal distribution network includes a two-way power divider 1001a and a four-way power divider. R10U1 represents the local oscillator signal source 100a. The radio frequency link TX signal flow of a test unit 200a is connected to a reference. Figure 6 A test unit 200a's RF link RX signal flow connection reference. Figure 4 The arrows indicate the unidirectional transmission path of the signal.

[0098] In some alternative embodiments, combined with Figure 6 and Figure 7 As shown, the R10U1 and the RF signal distribution network together constitute the RF front-end module. The RF front-end module has transmit / local oscillator distribution function and transmit / receive isolation function.

[0099] The transmit / local oscillator allocation function is as follows: After the R10U1 generates the RF local oscillator signal, it is amplified by amplifier 100c and then input to the two-way power divider 1001a. One RF drive signal output from the two-way power divider 1001a enters the unidirectional electromagnetic wave transmitter 2001 through Port1, while the other RF drive signal output from the two-way power divider 1001a is distributed to other test units through a four-way power divider. In this way, through the tree-shaped distribution network composed of the two-way power divider, the four-way power divider, and the isolator, the single RF local oscillator signal is distributed to eight test units without loss and with low phase noise.

[0100] The send / receive isolation function is as follows: One RF drive signal output from the two-way power divider 1001a enters the unidirectional electromagnetic wave transmitter 2001 through Port1, exits through Port2, passes through isolator 2002, and reaches any chip under test 400. The echo signal returned from any chip under test 400 enters through the second port 2 of the unidirectional electromagnetic wave transmitter 2001, exits through the third port 3, passes through attenuator 2003 and multiplexer 2004, and finally reaches the detection RX port of R10U1.

[0101] As can be seen from the RX signal flow of the RF link, the unidirectional transmission characteristic of the unidirectional electromagnetic wave transmitter can isolate the transmit and receive links and effectively block the reverse injection of the transmitted signal into the receive link.

[0102] It should be noted that, Figure 6 and Figure 7 The aforementioned four-way power divider is not shown; only the RF link at the output of the two-way power divider 1001a will be analyzed and explained.

[0103] In some alternative embodiments, combined with Figure 6 and Figure 7 As shown, the test unit 200a also includes a coupler 500.

[0104] The input terminal IN of coupler 500 is connected to one output terminal of two-way power divider 1001a. The DIR coupling terminal of coupler 500 is connected to the first terminal Port1 and the multiplexer 2004 respectively. Coupler 500 is used for power detection.

[0105] Combination Figure 6 and Figure 7 As shown, test unit 200a also includes a differential-to-single-ended conversion circuit. This circuit is used for differential-to-single-ended conversion. The ISO isolation terminal of coupler 500 is connected to the input terminal of the first balun 601 and then to the RX terminal of R10U1. The other output terminal of the two-way power divider 1001a is connected to the input terminal of the second balun 602 and then to the local oscillator input terminal LOIN of R10U1. The differential-to-single-ended conversion circuit includes the first balun 601 and the second balun 602.

[0106] The aforementioned frequency division isolation (FDI)-based testing method can be superimposed on the chip testing system described above. Each test unit includes a unidirectional electromagnetic wave transmitter and an isolator to suppress reverse leakage from the transmit link to the receive link. Simultaneously, the main control module executes the FDI-based testing method during the test initialization phase. Thus, hardware isolation and FDI work together: hardware isolation blocks large signal leakage paths, while FDI avoids residual crosstalk at the same frequency, jointly ensuring high parallelism and high stability for mass production testing of all test units.

[0107] Table 3 shows the performance comparison data between this application and existing solutions.

[0108]

[0109] In Table 3, the traditional same-frequency scheme indicates a parallel test scheme that does not use frequency division isolation and hardware isolation; hardware isolation only indicates the test scheme used by the chip test system mentioned above; frequency division isolation only indicates the parallel test scheme based on the frequency division isolation mechanism mentioned above, and the center frequency is arranged by alternating high and low frequencies; hardware isolation + frequency division isolation indicates a parallel test scheme that combines the chip test system mentioned above with the frequency division isolation mechanism mentioned above.

[0110] As shown in Table 3, compared to the hardware isolation only solution, the hardware isolation + frequency division isolation scheme significantly improves the ACLR (Adjacent Channel Leakage Ratio) from -55dBc (decibels relative to carrier) to -65dBc, and the test yield from 94% to 99.2%. The frequency division isolation only solution can also achieve an isolation level of -40dBc, a 15dBc improvement over traditional same-frequency solutions, making it the preferred solution for sacrificing availability for zero cost.

[0111] In practical applications, the main control module is equipped with test programs. The test method based on the frequency division isolation mechanism specifically executes the following steps: S101, Initialization phase: The test program reads the frequency division isolation enable flag from the configuration file.

[0112] S102, after the frequency division isolation enable flag is enabled, the test program obtains the number of test units N as 8, and the frequency step size. The frequency is set at 10MHz, with the lower frequency threshold as the starting center frequency of 860MHz, and the frequency step size is successively added based on the starting center frequency. Different center frequencies are obtained and a sequence of center frequencies is generated. The center frequencies are then written to the register of the local oscillator signal source.

[0113] S103, the test program responds to the test enable signal, and eight test units work simultaneously, each using a pre-assigned center frequency.

[0114] S104, the receiver distinguishes the echo signals of each test unit based on the center frequency difference and calculates the test results.

[0115] S105 If a test unit fails three times in a row, the test program will automatically offset the center frequency of the test unit by ±5MHz and retest it based on the offset center frequency.

[0116] This disclosure provides a computer-readable storage medium storing computer-executable instructions configured to execute the above-described test method based on a frequency division isolation mechanism.

[0117] The technical solutions of this disclosure can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes one or more instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the method described in this disclosure. The aforementioned storage medium can be a non-transitory storage medium, such as a USB flash drive, external hard drive, read-only memory (ROM), random access memory (RAM), magnetic disk, or optical disk, etc., and other media capable of storing program code.

[0118] The foregoing description and accompanying drawings fully illustrate embodiments of this disclosure to enable those skilled in the art to practice them. Other embodiments may include structural, logical, electrical, procedural, and other changes. The embodiments represent only possible variations. Individual components and functions are optional unless explicitly required, and the order of operation may vary. Parts and features of some embodiments may be included in or replace parts and features of other embodiments. Moreover, the terminology used in this application is for describing embodiments only and is not intended to limit the claims. As used in the description of embodiments and claims, the singular forms “a,” “an,” and “the” are intended to equally include the plural forms unless the context clearly indicates otherwise. Similarly, the term “and / or” as used in this application means including one or more of the associated listed items and all possible combinations thereof. Additionally, when used in this application, the term "comprise" and its variations "comprises" and / or "comprising" refer to the presence of stated features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof. Without further limitations, an element defined by the phrase "comprises a..." does not exclude the presence of other identical elements in the process, method, or apparatus that includes said element. In this document, each embodiment may focus on the differences from other embodiments, and similar or identical parts between embodiments can be referred to mutually. For methods, products, etc., disclosed in the embodiments, if they correspond to the method section disclosed in the embodiments, the relevant parts can be referred to the description of the method section.

[0119] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the embodiments of this disclosure. Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0120] The methods and products disclosed in the embodiments herein (including but not limited to devices and equipment) can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For instance, the division of units may be merely a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. In addition, the mutual coupling or direct coupling or communication connection shown or discussed may be through some interfaces, and the indirect coupling or communication connection of devices or units may be electrical, mechanical, or other forms. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to implement this embodiment according to actual needs. In addition, the functional units in the embodiments of this disclosure may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0121] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to embodiments of this disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a different order than that shown in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. In the descriptions corresponding to the flowcharts and block diagrams in the accompanying drawings, the operations or steps corresponding to different blocks may also occur in a different order than disclosed in the description, and sometimes there is no specific order between different operations or steps. For example, two consecutive operations or steps may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. Each block in a block diagram and / or flowchart, and combinations of blocks in a block diagram and / or flowchart, can be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

Claims

1. A test method based on frequency division isolation mechanism, characterized in that, It is used in chip testing systems, which include an RF generation module and multiple test units. The RF generation module is used to generate multiple RF drive signals. The input of each test unit is connected to the RF generation module, and the output of each test unit is connected to a chip under test; the test method includes: Based on the operating frequency band of the chip under test and the number of test units, a center frequency sequence is constructed; wherein, the center frequency sequence includes mutually distinct center frequencies; The center frequency is allocated to each test unit according to the frequency division isolation mechanism; wherein the frequency division isolation mechanism satisfies that the center frequency interval between any two physically adjacent test units is not less than the preset frequency domain isolation threshold. In response to the test enable signal, multiple RF drive signals are configured according to the center frequency allocated to each test unit to drive all chips under test to perform parallel tests.

2. The test method according to claim 1, characterized in that, Based on the operating frequency band compatible with the chip under test and the number of test units, a center frequency sequence is constructed, including: Determine the bandwidth of the operating frequency band; The frequency step size is determined based on the bandwidth and the number of test units; Starting with the lower frequency threshold as the initial center frequency, frequency steps are successively added to obtain different center frequencies, and a sequence of generated center frequencies is constructed.

3. The test method according to claim 2, characterized in that, The frequency step size is determined based on the bandwidth and the number of test units, including: The frequency step size is determined based on the ratio of bandwidth to the number of test units.

4. The test method according to claim 1, characterized in that, The absolute value of the center frequency difference between test units that are physically adjacent is greater than the absolute value of the center frequency difference between test units that are not physically adjacent.

5. The test method according to claim 1, characterized in that, The center frequency is allocated to each test unit according to the frequency division isolation mechanism, including: Based on the physical location of the test units, a corresponding center frequency is assigned to each test unit using an alternating arrangement of high and low frequencies.

6. The test method according to claim 1, characterized in that, The center frequency is allocated to each test unit according to the frequency division isolation mechanism, including: According to the physical location of the test units, the corresponding center frequencies are assigned to each test unit in sequence according to the center frequency sequence number.

7. The test method according to any one of claims 1 to 6, characterized in that, Also includes: In response to the test enable signal, multiple radio frequency drive signals are configured according to the center frequency allocated to each test unit to drive all chips under test to perform parallel tests and obtain the test results corresponding to each chip under test. If the test result indicates that the test has failed, the current center frequency of the test unit corresponding to the test result is adjusted according to the preset frequency offset to obtain the RF drive offset frequency. The RF drive signal of the corresponding test unit is reconfigured according to the RF drive offset frequency.

8. A test device based on a frequency division isolation mechanism, comprising a processor and a memory storing program instructions, characterized in that, The processor is configured to execute the test method based on the frequency division isolation mechanism as described in any one of claims 1 to 7 when running the program instructions.

9. A chip testing system, characterized in that, include: The radio frequency generation module is used to generate multiple radio frequency drive signals; The test channel includes multiple test units. The input of each test unit is connected to the RF generation module, and the output of each test unit is connected to a chip under test. The main control module is connected to multiple test units, including the test device based on the frequency division isolation mechanism as described in claim 8.

10. A computer-readable storage medium storing program instructions, characterized in that, When the program instructions are executed, they cause the computer to perform the test method based on the frequency division isolation mechanism as described in any one of claims 1 to 7.

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