Design device and method for dynamic allocation of read-write rate of spaceborne solid-state memory

Abstract

The application belongs to the technical field of satellite data transmission, and provides a kind of on-board solid-state memory read-write rate dynamic allocation design device and method thereof, including storage module, high-capacity high-speed DDR and FPGA for storing read-write control;High-capacity high-speed DDR cooperates with read-write control FPGA, according to the rate of load writing into storage module, and the priority sorting processing strategy of read-write cache data stream, dynamically controls the read-write of storage module.This application realizes the current data writing while reading under the high peak rate of satellite load, and also can realize non-overflow real-time data processing and transmission to the earth under the high-speed condition of writing rate close to throughput rate;Through the priority sorting processing strategy of read-write cache data stream, ensure that the load data of high peak rate is completely written into the storage module, and realize dynamic allocation of read rate resource according to the remaining processing capacity of throughput rate.

Description

Technical Field

[0001] This invention belongs to the field of satellite data transmission technology, specifically relating to a device and method for dynamically allocating read / write rates of a spaceborne solid-state memory. Background Technology

[0002] In the field of remote sensing satellite data transmission, to meet the demand for high-speed storage of remote sensing payload data, multiple high-reliability memory chips are typically used in parallel processing and control to expand and improve the read and write speeds of satellite storage modules. However, considering factors such as the maximum storage capacity of payload data, the cost of memory chips, read / write control design resources, and system reliability, the read and write speeds of satellite storage modules cannot be expanded indefinitely. Therefore, given the fixed hardware resources of onboard solid-state storage, its total data throughput for read and write operations is a predetermined design value.

[0003] Onboard solid-state storage (SSD) operates in three modes for data transmission: write mode, read mode, and simultaneous read / write mode. Since the storage module only supports read or write operations at a time, simultaneous read / write functionality is achieved by allocating fixed time slots for high-speed read or write operations. In simultaneous read / write mode, the storage module allocates fixed read and write bandwidths, ensuring the sum of these two bandwidths does not exceed the total throughput. The peak write rate cannot exceed the write bandwidth; exceeding this limit will result in data loss. This prevents near real-time data transfer, thus limiting the data transmission efficiency and overall performance of the payload in near real-time mode.

[0004] In the field of satellite solid-state memory read / write applications, based on the retrieved patents, there are currently no patents that feature a dynamic adaptive adjustment design for read / write rates. Patent document "A Storage Device" (CN106508056B) addresses the problem that large-capacity spaceborne storage chips cannot simultaneously perform read / write operations and partitioned random operations. In simultaneous read / write operation mode, when the amount of input data (i.e., the amount of data written to storage) is less than the amount of output data for an extended period, the read operation is automatically paused, entering a timed wait. After the wait ends, subsequent operations are executed again based on the relationship between the input and output data amounts. While it solves the problem of simultaneous read / write operations when the sum of the write rate and peak read rate is not greater than the throughput, it fails to implement a design that prioritizes write operations and automatically reduces the read rate when the sum of the write rate and peak read rate exceeds the throughput, thus imposing a narrower limit on the upper limit of the write rate.

[0005] Patent application document "Read / Write Method Based on SDRAM Solid State Memory" (CN102831089A) provides a read / write method based on SDRAM solid state memory, including a memory recording step and a memory playback step. When the read pointer exceeds the write pointer, it is a read overflow, but the previously recorded data that has not been overwritten can still be played back. After any read operation, the read and write pointers will return to the memory's starting address. Patent application document "File-based Read / Write Design Method Based on SDRAM Onboard Memory" (CN102779016A) provides a file-based read / write design method based on SDRAM onboard memory. The write pointer is not constrained by the read pointer; recording will only automatically stop when the payload data is full of memory. When the read pointer exceeds the write pointer, it is a read loop, and playback continues repeatedly. Patent application document "A Spaceborne High-Speed ​​Switching and Storage Integrated Cache Control Method and Device" (CN115766627A) discloses a spaceborne high-speed switching and storage integrated cache control method, including: dividing the cache into multiple blocks using a preset minimum unit or an integer multiple of the minimum unit, wherein each block consists of a meta area and a data area; receiving data packets from the input port and storing the received data into the corresponding cache; and, if, after each block has received its corresponding data, there is still a cache address larger than the minimum unit that is empty, dividing the empty cache address into independent blocks using a preset minimum unit or an integer multiple of the minimum unit. Patent application document "A Method for Accelerating the Storage of Multiple-Way Satellite Payload Files" (CN111209228A) provides a method for accelerating the storage of multiple-way satellite payload files by employing a two-level cache and a multi-threaded pipelined processing method.

[0006] While the aforementioned existing technologies have each solved related problems in the field, none of them involve the design of dynamic adaptive adjustment of read and write speeds of solid-state storage modules. The real-time performance and timeliness of satellite payload data downlink are among the key factors for improving the effectiveness of satellite applications.

[0007] The patent application document "High-speed, high-capacity dual-channel, dual-buffered memory system based on DDR3" (CN116414732A) designs a high-speed, high-capacity dual-channel, dual-buffered memory system in an embedded system. It utilizes FPGA and DDR3 memory to achieve parallel processing of dual-channel data streams. It adopts a dual-buffered design and a cache module composed of FIFO to optimize the read and write operation order and address pointer management. Combining the advantages of high speed and high capacity of DDR3, it solves the problems of low efficiency and high hardware overhead, and achieves high throughput and reliable data storage.

[0008] In general, existing onboard memory typically employs a fixed allocation strategy for read / write bandwidth in simultaneous read / write mode. Under this framework, if the read rate accounts for a large proportion, the peak write rate allowed for the payload will be constrained to a low level. However, satellite payloads often experience short-duration, high-rate bursts. If the sudden write rate exceeds the fixed write bandwidth, it can easily lead to data overflow and data loss, or even cause system crashes, thus limiting the payload's transmission performance in near real-time mode.

[0009] Therefore, it is necessary to address the limitation imposed by the storage module on the peak load rate in write-while-read mode. On the one hand, the load and data transmission operating modes can be decoupled to make the application more flexible; on the other hand, near real-time downlink of high peak load data can be achieved. Summary of the Invention

[0010] To address the shortcomings of existing technologies, the present invention aims to provide a dynamic allocation design device and method for read / write rates of spaceborne solid-state storage, which solves the problem of data loss caused by read / write rate conflicts when the sum of the peak write rate of the payload and the transmission rate to ground exceeds the total throughput of the storage module but the write rate does not exceed the total throughput of the storage module. By prioritizing the write rate when there is a conflict between the payload write and read rates, and adaptively reducing the read rate, near real-time transmission of satellite payload data to ground while writing and reading data simultaneously is achieved.

[0011] According to the present invention, a dynamic allocation design device for read and write rates of a spaceborne solid-state memory includes a storage module, a DDR chip and an FPGA module. The DDR chip connects the FPGA module and the storage module to perform interactive caching of written and read data.

[0012] The DDR chip includes a write cache and a read cache.

[0013] The FPGA module monitors the status of the write buffer and read buffer in real time, sorts the multi-channel data time-sharing processing according to the set priority, controls the timing of the DDR chip and storage module in a time-sharing manner, and dynamically allocates the real-time read and write rates of the storage module according to the changes in the load write rate.

[0014] Preferably, the maximum throughput of the storage module is determined according to the hardware configuration.

[0015] The internal scheduling control rate of the DDR chip is not less than twice the maximum throughput of the storage module.

[0016] At the data interaction interface between the FPGA module, DDR chip, and storage module, the rate is smoothed through multiple balanced rate-controlled first-in-first-out queues, ensuring that the interface rate between the FIFO and the onboard solid-state memory is equal to the maximum throughput, and the interface rate of the DDR chip's read buffer does not exceed the maximum read rate.

[0017] Preferably, the priority sorting of multi-channel data time-sharing processing includes multiple time-sharing processing requests.

[0018] The time-sharing processing request includes: Request 1: When the amount of data cached in the write cache of the DDR chip reaches the set threshold for a single write to the storage module, a write cache output request is triggered.

[0019] Request 2: The storage module is in read mode and the data in the read buffer of the DDR chip is not empty. At the same time, the second buffer FIFO at the output end of the read buffer of the DDR chip is empty, triggering a read buffer output request.

[0020] Request 3: When the storage module is in read mode and the data in the read cache of the DDR chip is below the set threshold, a read cache input request is triggered.

[0021] Request 4: Satellite payload data is continuously written to the first buffer FIFO of the FPGA module and accumulates to fill a fixed frame length of data, triggering a write buffer input request.

[0022] Preferably, the four time-sharing requests are ordered from highest to lowest priority as request one, request two, request three, and request four.

[0023] When in write-read-while-read mode, and the sum of the instantaneous write rate and the maximum read rate exceeds the maximum throughput of the storage module, the FPGA module prioritizes responding to request one and adaptively reduces the response frequency of request three.

[0024] When in write-read-read mode, and the sum of the payload write rate and the maximum read rate does not exceed the maximum throughput, the FPGA module increases the response frequency of request three, and the read rate returns to the constant rate read state constrained by the ground transmission code rate.

[0025] Preferably, the FPGA module reads data from the second buffer FIFO at the highest read rate. When the amount of data read from the second buffer FIFO is lower than the first set threshold, it sends a request for supplementary data to the read buffer of the DDR chip.

[0026] When the amount of remaining data in the read cache of the DDR chip is lower than the second set threshold, a request is sent to the storage module. When the storage module detects that there is no write operation, it reads the data to the third buffer FIFO of the DDR chip at the maximum throughput.

[0027] When the DDR chip's read buffer receives input, the read buffer maintains continuous data output until it is completely empty, at which point the data output is interrupted.

[0028] A method for dynamically allocating read / write rates for a spaceborne solid-state memory according to the present invention includes: The status of the write buffer and read buffer of the DDR chip is monitored in real time through the FPGA module; Based on the set priority of multi-channel data time-sharing processing, the FPGA module performs time-sharing timing control on the DDR chip and memory module. The real-time read and write rates of the storage modules are dynamically allocated based on changes in the load write rate.

[0029] Preferably, the maximum throughput of the storage module is determined according to the hardware configuration.

[0030] The internal scheduling control rate of the DDR chip is not less than twice the maximum throughput of the storage module.

[0031] At the data interaction interface between the FPGA module, DDR chip, and storage module, the rate is smoothed through multiple balanced rate-controlled first-in-first-out queues, ensuring that the interface rate between the FIFO and the onboard solid-state memory is equal to the maximum throughput, and the interface rate of the DDR chip's read buffer does not exceed the maximum read rate.

[0032] Preferably, the priority sorting of multi-channel data time-sharing processing includes multiple time-sharing processing requests.

[0033] The time-sharing processing request includes: Request 1: When the amount of data cached in the write cache of the DDR chip reaches the set threshold for a single write to the storage module, a write cache output request is triggered.

[0034] Request 2: The storage module is in read mode and the data in the read buffer of the DDR chip is not empty. At the same time, the second buffer FIFO at the output end of the read buffer of the DDR chip is empty, triggering a read buffer output request.

[0035] Request 3: When the storage module is in read mode and the data in the read cache of the DDR chip is below the set threshold, a read cache input request is triggered.

[0036] Request 4: Satellite payload data is continuously written to the first buffer FIFO of the FPGA module and accumulates to fill a fixed frame length of data, triggering a write buffer input request.

[0037] Preferably, the four time-sharing requests are ordered from highest to lowest priority as request one, request two, request three, and request four.

[0038] When in write-read-while-read mode, and the sum of the instantaneous write rate and the maximum read rate exceeds the maximum throughput of the storage module, the FPGA module prioritizes responding to request one and adaptively reduces the response frequency of request three.

[0039] When in write-read-read mode, and the sum of the payload write rate and the maximum read rate does not exceed the maximum throughput, the FPGA module increases the response frequency of request three, and the read rate returns to the constant rate read state constrained by the ground transmission code rate.

[0040] Preferably, the FPGA module reads data from the second buffer FIFO at the highest read rate. When the amount of data read from the second buffer FIFO is lower than the first set threshold, it sends a request for supplementary data to the read buffer of the DDR chip.

[0041] When the amount of remaining data in the read cache of the DDR chip is lower than the second set threshold, a request is sent to the storage module. When the storage module detects that there is no write operation, it reads the data to the third buffer FIFO of the DDR chip at the maximum throughput.

[0042] When the DDR chip's read buffer receives input, the read buffer maintains continuous data output until it is completely empty, at which point the data output is interrupted.

[0043] Compared with the prior art, the present invention has the following beneficial effects: 1. Under the near real-time transmission condition of simultaneous recording and reading, the peak rate of reading and writing exceeds the total throughput rate of the storage module, and the peak rate of the payload being written to the storage module does not exceed the total throughput rate of the storage module, thereby realizing the near real-time transmission function of satellite payload data to the ground with simultaneous writing and reading and no overflow.

[0044] 2. This invention opens up more application bandwidth to the payload under near real-time transmission conditions. The payload's working mode and parameter settings are not limited by the fixed large data playback rate of the memory, ensuring the working capability under different modes.

[0045] 3. This invention uses a priority sorting strategy for read and write cached data streams to ensure that high peak rate load data is completely written to the storage module. It dynamically allocates read rate resources based on the remaining processing capacity of the throughput, ensuring that the total read and write rate is never greater than the throughput of the storage module. Under the condition that the ground playback rate does not exceed the required rate according to the mode setting, it maximizes the use of the read rate allocated by the storage module to play back the data. Attached Figure Description

[0046] Other features, objects, and advantages of the invention will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings: Figure 1 A schematic diagram of the design method for dynamic allocation of read and write rates for spaceborne solid-state storage. Detailed Implementation

[0047] The present invention will now be described in detail with reference to specific embodiments. These embodiments will help those skilled in the art to further understand the present invention, but do not limit the invention in any way. It should be noted that those skilled in the art can make several changes and improvements without departing from the concept of the present invention. These all fall within the protection scope of the present invention.

[0048] The present invention provides a design device for dynamic allocation of read and write rates of spaceborne solid-state memory. By configuring an FPGA (Field Programmable Gate Array) and a high-speed, high-capacity DDR (Double Data Rate Synchronous Dynamic Random Memory) chip for read and write control through a storage module, and combining it with FIFO (First-In-First-Out) balanced rate control, the device enables simultaneous writing and reading of current data at high peak rates of the satellite payload, while prioritizing the data write rate, and provides near real-time transmission to Earth, provided that the peak rate of the payload does not exceed the total throughput rate of the memory.

[0049] The spaceborne high-reliability solid-state memory (SSD) uses multiple NAND flash memory chips interacting in parallel with an FPGA to achieve data read and write storage functions. However, each NAND flash memory chip can only read or write at any given time, and is constrained by hardware resources. Once the hardware design is complete, the peak instantaneous read or write rate capability of the storage module is determined. This capability is defined as the throughput of the storage module, that is, the sum of the read and write rates of the storage module.

[0050] Spaceborne data transmission requires simultaneous read and write operations, meaning that while recording and storing satellite payload data, it is also necessary to read and replay the stored data. Therefore, the storage module uses DDR cache in conjunction with a high-speed clock, dividing time into small time slots. Write or read operations are performed step-by-step according to these time slots, achieving simultaneous read and write functionality and enabling near real-time transmission of payload data to Earth while it is being written and read simultaneously. Figure 1 For example, including: The read and write rates of the storage module are dynamically allocated based on the rate at which the load is written to the memory. DDR is used as a read and write cache, and the read and write control FPGA is used to control the write or read of the storage module. The priority sorting processing strategy of the read and write cache data stream ensures that the load data at high peak rates is completely written to the storage module. The read rate resources are dynamically allocated based on the remaining processing capacity of the throughput.

[0051] Specifically, the storage module can only write or read at any given time, and does not have the function of simultaneous read and write. DDR is configured as the read and write cache of the storage module, and the read and write control FPGA is configured to perform read and write operations on the storage module. DDR notifies the read and write control FPGA whether it is in write or read state according to the current busy / idle state of the cache. The read and write rate of the storage module is dynamically allocated according to the write rate change. The control rate of the write or read of the storage module is the throughput. The maximum write or read rate is constrained from not exceeding the throughput of the storage module.

[0052] In traditional modes, when the read rate accounts for a large proportion of the throughput, the peak write rate in the record-and-playback mode will be constrained to a relatively low level. For example, with a throughput of 4Gbps, a read rate of 1.5Gbps is required, allowing a write rate exceeding 2.5Gbps. If the load write rate to memory exceeds this limit, it will cause data overflow, data loss, or even program crashes. If the load exhibits short bursts of low duty cycles, such as a burst rate of 3Gbps, working for 5 seconds and stopping for 45 seconds, lasting for 6 hours, the actual working time accounts for 10% of the total working time. In this case, the data must be recorded into solid-state storage first, and then stored and played back after the 6-hour work period ends.

[0053] Therefore, in the recording-while-playing mode, the read rate is no longer fixed, but the data write rate is prioritized. When the read plus write rate does not exceed the throughput, the data is read from the memory according to the playback rate requirement. If the read plus write rate exceeds the throughput and the write rate is less than the throughput, the write rate is prioritized, and the payload data is completely written into the memory. The throughput minus the write rate is the currently dynamically allocated read rate.

[0054] By dynamically releasing the fixed percentage of the read rate in the throughput, even when the load experiences occasional large data rates (less than the throughput) under certain specific conditions, near real-time transmission with simultaneous recording and playback can still be achieved. This reduces the load rate constraint in the near real-time mode and improves the load application efficiency.

[0055] Meanwhile, the load rate constraint is not mandatory to the ground transmission rate, which allows for the application of the highest transmission rate for the load.

[0056] In more preferred embodiments, the solid-state storage operates in read-only or write-only mode at the same time. By increasing the read and write rates, read and write operations are dynamically divided into time slots according to the read and write rate requirements, satisfying the simultaneous read and write application under the original rate conditions. The highest processing rate of read or write is the maximum throughput of the solid-state storage module, realizing near real-time data processing and transmission to ground while recording and playing back.

[0057] The storage module configuration and read / write control FPGA and DDR chip work together to realize the simultaneous read / write function of the storage module. Among them, the read / write control FPGA controls the reading or writing of the storage module; the DDR chip is divided into a read buffer and a write buffer, and the read or write speed is accelerated by increasing the clock speed or expanding the parallel transmission bit width; the simultaneous read / write function of the storage module is realized by high-speed scheduling of the read / write buffer in conjunction with the read / write FPGA.

[0058] In both read and write modes, high-speed data writing is prioritized, while the read rate automatically decreases. DDR employs a processing method that combines non-fixed time slot read and write requests with the read and write status of the storage module. The peak effective read rate is constrained by the transfer code rate to ground.

[0059] When the peak combined read and write rate exceeds the storage module's maximum data processing capacity (maximum throughput), data writing is prioritized, and the read rate is automatically reduced to match the peak combined read and write rate with the storage module's maximum data processing capacity (maximum throughput).

[0060] Specifically, high-speed, high-capacity DDR is divided into a read cache and a write cache. The read and write cache data streams are uniformly scheduled, and four data streams are processed in a time-sharing manner according to their priority from high to low: write cache output, read cache output, read cache input, and write cache input. Write cache output has a higher priority than read cache input, enabling priority data writing.

[0061] The first priority is write cache output, which is triggered when the DDR chip's write cache is filled with the set amount of data for a single page / block operation (preferably 64Kb). A write operation request is sent to the storage module, and the highest priority response is given to prevent data loss.

[0062] The second priority is read buffer output, which is triggered when the read buffer is not empty in playback mode and the read buffer output rate is smoothly output when the FIFO is empty. This ensures that the data stream transmitted to ground is continuously and at a constant speed within the physical pipeline, without interruption due to internal replenishment.

[0063] The third priority is read cache input, which is triggered when the storage module is in read mode (including read-only or read-while-write) and the data in the read cache is below a set threshold. It requests new data from the storage module and moves the data at maximum throughput when the storage module is not in write mode.

[0064] The fourth priority is the write buffer input, which is triggered when external payload data is written to the first-level FIFO inside the FPGA and accumulates to fill a fixed frame length of data (usually a few KB). Due to the extremely high DDR scheduling rate, it can be processed quickly after one read / write poll, without causing FIFO overflow.

[0065] In more specific preferred examples, when the write rate to the storage module is not high and the total peak rate of read and write does not exceed the maximum throughput, the effective read rate is constant and read according to the ground transmission code rate constraint.

[0066] When the peak write rate is less than the maximum throughput of the storage module but the sum of the write rate and the read rate exceeds the maximum throughput of the storage module, data writing is prioritized and the read rate is automatically reduced. This ensures that the load data is not lost and can automatically match the data processing capability of the storage module, achieving the goal of simultaneous reading and writing and dynamic allocation of throughput resources at the peak load rate.

[0067] Because the DDR scheduling rate is much higher than the storage module throughput, for example, the DDR scheduling rate is 20Gbps, the input and output rates of the DDR cache are 20Gbps respectively; the storage module throughput is 6Gbps, that is, the peak write and read rates of the storage module do not exceed 6Gbps, the input of the DDR cache, that is, the DDR read cache area, is 20Gbps, and the output rate is 1.5Gbps. The DDR scheduling rate can meet the four-way data processing requirements.

[0068] When the DDR write cache is full of a certain amount of data, the DDR notifies the read / write control FPGA write cache that it can write to the storage module. The storage module sends a write request to the DDR, and after receiving the write request, the DDR sends the data to the storage module.

[0069] Specifically, the payload data is input at high speed to the write DDR, i.e., the DDR write buffer, in units of frames. When the buffer is full of a certain amount of data (e.g., 64Kb), the write DDR notifies the read / write control FPGA that the write DDR buffer can be written to the storage module. The storage module sends a storage write request to the write DDR. After receiving the write request, the write DDR sends the data to the FIFO buffer through a high-speed interface, smooths the rate, and writes it to the storage module at a rate of 6Gbps.

[0070] After the DDR write cache is completed and output is finished, since the DDR scheduling rate is much higher than the smoothed rate of writing to storage, it can be polled to determine whether there is data output in the DDR read cache. If there is, the data read from the DDR cache is sent to the FIFO cache through the high-speed interface. After smoothing the rate, the data is output at 1.5Gbps (peak rate of transmission to ground), and the backend implements the transmission of the data to ground.

[0071] When the DDR is idle, the DDR notifies the read / write control FPGA that it can read data. If the storage module is still performing a write operation at this time, the data read operation will not be performed. When the storage module stops performing a write operation, a certain amount of data is sent to the DDR at once.

[0072] In more preferred embodiments, when the DDR is idle, that is, when there is no data input to write to the DDR cache in the current time slot and the read DDR cache is empty, the DDR notifies the read / write control FPGA that it can read the data in the memory. If the storage module is still performing a write operation from FIFO to the storage module at this time, the data read operation from the storage module will no longer be performed. When the storage module no longer performs a write operation, a certain amount of data (e.g., 64Kb) is sent to the read DDR cache at one time.

[0073] Because the read DDR cache output is constrained by a read rate of 1.5Gbps, the read DDR cache cannot continuously write at 20Gbps. Therefore, after the read DDR cache has written a certain amount of data (e.g., 64Kb), it needs to wait for a smooth output time of 1.5Gbps. At this time, the write DDR cache operation can be performed.

[0074] The processing speed of the four channels—write DDR cache output, read DDR cache output, read DDR cache input, and write DDR cache input—is much higher than the throughput of the storage module. The input of the read cache has a short scheduling time, and the write cache will not overflow when the DDR read cache is input. With the help of interface interaction priority, the data write and read can be adaptively adjusted.

[0075] This invention provides a method for dynamically allocating read / write rates for spaceborne solid-state storage. The method dynamically allocates the read / write rates of storage modules based on changes in write rate, achieving near real-time data transmission to ground under peak load write rates with simultaneous writing and reading and no overflow. Specifically, it includes the following steps: The status of the write buffer and read buffer of the DDR chip is monitored in real time through the FPGA module; Based on the set priority of multi-channel data time-sharing processing, the FPGA module performs time-sharing timing control on the DDR chip and memory module. The real-time read and write rates of the storage modules are dynamically allocated based on changes in the load write rate.

[0076] In more preferred embodiments, the maximum throughput of the storage module is determined based on the hardware configuration.

[0077] The internal scheduling control rate of the DDR chip is not less than twice the maximum throughput of the storage module.

[0078] At the data interaction interface between the FPGA module, DDR chip, and storage module, the rate is smoothed through multiple balanced rate-controlled first-in-first-out queues, ensuring that the interface rate between the FIFO and the onboard solid-state memory is equal to the maximum throughput, and the interface rate of the DDR chip's read buffer does not exceed the maximum read rate.

[0079] In more preferred embodiments, the multi-channel data time-sharing processing priority sorting includes multiple time-sharing processing requests.

[0080] The time-sharing processing request includes: Request 1: When the amount of data cached in the write cache of the DDR chip reaches the set threshold for a single write to the storage module, a write cache output request is triggered.

[0081] Request 2: The storage module is in read mode and the data in the read buffer of the DDR chip is not empty. At the same time, the second buffer FIFO at the output end of the read buffer of the DDR chip is empty, triggering a read buffer output request.

[0082] Request 3: When the storage module is in read mode and the data in the read cache of the DDR chip is below the set threshold, a read cache input request is triggered.

[0083] Request 4: Satellite payload data is continuously written to the first buffer FIFO of the FPGA module and accumulates to fill a fixed frame length of data, triggering a write buffer input request.

[0084] In more preferred embodiments, the four time-sharing requests are ordered from highest to lowest priority as request one, request two, request three, and request four.

[0085] When in write-read-while-read mode, and the sum of the instantaneous write rate and the maximum read rate exceeds the maximum throughput of the storage module, the FPGA module prioritizes responding to request one and adaptively reduces the response frequency of request three.

[0086] When in write-read-read mode, and the sum of the payload write rate and the maximum read rate does not exceed the maximum throughput, the FPGA module increases the response frequency of request three, and the read rate returns to the constant rate read state constrained by the ground transmission code rate.

[0087] In more preferred embodiments, the FPGA module reads data from the second buffer FIFO at the highest read rate, and when the amount of read data in the second buffer FIFO is lower than a first set threshold, it sends a request for supplementary data to the read buffer of the DDR chip.

[0088] When the amount of remaining data in the read cache of the DDR chip is lower than the second set threshold, a request is sent to the storage module. When the storage module detects that there is no write operation, it reads the data to the third buffer FIFO of the DDR chip at the maximum throughput.

[0089] When the DDR chip's read buffer receives input, the read buffer maintains continuous data output until it is completely empty, at which point the data output is interrupted.

[0090] Specific embodiments of the present invention have been described above. It should be understood that the present invention is not limited to the specific embodiments described above, and those skilled in the art can make various changes or modifications within the scope of the claims, which do not affect the essence of the present invention. Unless otherwise specified, the embodiments and features described in this application can be arbitrarily combined with each other.

Claims

1. A dynamic allocation design device for read / write rates of a spaceborne solid-state memory, comprising a storage module, a DDR chip, and an FPGA module, wherein the DDR chip connects the FPGA module and the storage module to perform interactive caching of write and read data, characterized in that: The DDR chip includes a write cache and a read cache; The FPGA module monitors the status of the write buffer and read buffer in real time, sorts the multi-channel data time-sharing processing according to the set priority, controls the timing of the DDR chip and storage module in a time-sharing manner, and dynamically allocates the real-time read and write rates of the storage module according to the changes in the load write rate.

2. The spaceborne solid-state memory read / write rate dynamic allocation design device according to claim 1, characterized in that, The maximum throughput of the storage module is determined based on the hardware configuration. The internal scheduling control rate of the DDR chip is not less than twice the maximum throughput of the storage module; The data interaction interface between the FPGA module, DDR chip and storage module is smoothed by multiple balanced rate-controlled FIFOs, so that the interface rate of the FIFO and the on-board solid-state memory is equal to the maximum throughput, and the interface rate of the DDR chip's read buffer does not exceed the maximum read rate.

3. The spaceborne solid-state memory read / write rate dynamic allocation design device according to claim 1, characterized in that, The priority sorting of multi-channel data time-sharing processing includes multiple time-sharing processing requests; The time-sharing processing request includes: Request 1: When the amount of data cached in the write cache of the DDR chip reaches the set threshold for a single write to the storage module, a write cache output request is triggered. Request 2: The storage module is in read mode and the data in the read buffer of the DDR chip is not empty. At the same time, the second buffer FIFO at the output end of the read buffer of the DDR chip is empty, triggering a read buffer output request. Request 3: When the storage module is in read mode and the data in the read cache of the DDR chip is lower than the set threshold, a read cache input request is triggered. Request 4: Satellite payload data is continuously written to the first buffer FIFO of the FPGA module and accumulates to fill a fixed frame length of data, triggering a write buffer input request.

4. The spaceborne solid-state memory read / write rate dynamic allocation design device according to claim 3, characterized in that, The four time-sharing requests are ordered from highest to lowest priority as request one, request two, request three, and request four. When in write-read-while-read mode, and the sum of the instantaneous write rate and the maximum read rate exceeds the maximum throughput of the storage module, the FPGA module prioritizes responding to request one and adaptively reduces the response frequency of request three. When in write-read-read mode, and the sum of the payload write rate and the maximum read rate does not exceed the maximum throughput, the FPGA module increases the response frequency of request three, and the read rate returns to the constant rate read state constrained by the ground transmission code rate.

5. The spaceborne solid-state memory read / write rate dynamic allocation design device according to claim 4, characterized in that, The FPGA module reads data from the second buffer FIFO at the highest read rate. When the amount of read data in the second buffer FIFO is lower than the first set threshold, it sends a request to the read buffer of the DDR chip to supplement data. When the amount of remaining data in the read buffer of the DDR chip is lower than the second set threshold, a request three is sent to the storage module. When the storage module detects that there is no write operation, it reads the data to the third buffer FIFO of the DDR chip at the maximum throughput. When the DDR chip's read buffer receives input, the read buffer maintains continuous data output until it is completely empty, at which point the data output is interrupted.

6. A method for dynamically allocating read / write rates for a spaceborne solid-state memory, characterized in that, include: The status of the write buffer and read buffer of the DDR chip is monitored in real time through the FPGA module; Based on the set priority of multi-channel data time-sharing processing, the FPGA module performs time-sharing timing control on the DDR chip and memory module. The real-time read and write rates of the storage modules are dynamically allocated based on changes in the load write rate.

7. The method for dynamically allocating read / write rates for spaceborne solid-state storage according to claim 6, characterized in that, The maximum throughput of the storage module is determined based on the hardware configuration. The internal scheduling control rate of the DDR chip is not less than twice the maximum throughput of the storage module; The data interaction interface between the FPGA module, DDR chip and storage module is smoothed by multiple balanced rate-controlled FIFOs, so that the interface rate of the FIFO and the on-board solid-state memory is equal to the maximum throughput, and the interface rate of the DDR chip's read buffer does not exceed the maximum read rate.

8. The method for dynamically allocating read / write rates for spaceborne solid-state storage according to claim 6, characterized in that, The priority sorting of multi-channel data time-sharing processing includes multiple time-sharing processing requests; The time-sharing processing request includes: Request 1: When the amount of data cached in the write cache of the DDR chip reaches the set threshold for a single write to the storage module, a write cache output request is triggered. Request 2: The storage module is in read mode and the data in the read buffer of the DDR chip is not empty. At the same time, the second buffer FIFO at the output end of the read buffer of the DDR chip is empty, triggering a read buffer output request. Request 3: When the storage module is in read mode and the data in the read cache of the DDR chip is lower than the set threshold, a read cache input request is triggered. Request 4: Satellite payload data is continuously written to the first buffer FIFO of the FPGA module and accumulates to fill a fixed frame length of data, triggering a write buffer input request.

9. The method for dynamically allocating read / write rates for spaceborne solid-state storage according to claim 8, characterized in that, The four time-sharing requests are ordered from highest to lowest priority as request one, request two, request three, and request four. When in write-read-while-read mode, and the sum of the instantaneous write rate and the maximum read rate exceeds the maximum throughput of the storage module, the FPGA module prioritizes responding to request one and adaptively reduces the response frequency of request three. When in write-read-read mode, and the sum of the payload write rate and the maximum read rate does not exceed the maximum throughput, the FPGA module increases the response frequency of request three, and the read rate returns to the constant rate read state constrained by the ground transmission code rate.

10. The method for dynamically allocating read / write rates for spaceborne solid-state memory according to claim 9, characterized in that, The FPGA module reads data from the second buffer FIFO at the highest read rate. When the amount of read data in the second buffer FIFO is lower than the first set threshold, it sends a request to the read buffer of the DDR chip to supplement data. When the amount of remaining data in the read buffer of the DDR chip is lower than the second set threshold, a request three is sent to the storage module. When the storage module detects that there is no write operation, it reads the data to the third buffer FIFO of the DDR chip at the maximum throughput. When the DDR chip's read buffer receives input, the read buffer maintains continuous data output until it is completely empty, at which point the data output is interrupted.

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