A synchronization control circuit, a synchronization control method, and a display device

Abstract

The application provides a synchronization control circuit, a synchronization control method and a display device. The synchronization control circuit is applied to the display device and comprises: a plurality of state counting modules corresponding to a plurality of data channels in a multi-channel data transmission system, configured to output corresponding state values under the driving of a link synchronization clock signal; and a synchronization correction module electrically connected with the plurality of state counting modules, configured to output a synchronization control signal to control the plurality of state counting modules to restore to a unified synchronization state. The synchronization control circuit provided by the application aligns the states between the state counting modules of the plurality of data channels, thereby improving the continuity and stability of multi-channel data transmission.

Description

Technical Field

[0001] This application relates to the field of display technology, and more specifically, to a synchronization control circuit, a synchronization control method, and a display device. Background Technology

[0002] With the rapid development of display technologies such as virtual reality (VR) and augmented reality (AR), terminal devices are placing increasingly stringent demands on the bandwidth and transmission rate of video data display. To meet the demands for high throughput and high frame rate data transmission, embedded DisplayPort (eDP) interfaces are being widely used and promoted in the display field (such as VR display modules), gradually replacing the traditional mobile industry processor interface (MIPI) interface.

[0003] However, a certain percentage of display devices using the eDP interface for multi-channel video data transmission exhibit abnormal display issues such as black lines on the screen during specific phases (e.g., power-on). Improving and eliminating these display defects, including black screens and black lines, is a pressing technical problem that needs to be solved. Summary of the Invention

[0004] This application provides a synchronization control circuit, a synchronization control method, and a display device. The synchronization control circuit features stable data transmission.

[0005] In a first aspect, a synchronization control circuit is provided for use in a display device, comprising: multiple state counting modules, each corresponding to multiple data channels in a multi-channel data transmission system, configured to output corresponding state values ​​under the drive of a link synchronization clock signal; and a synchronization correction module, electrically connected to the multiple state counting modules, configured to output a synchronization control signal to control the multiple state counting modules to restore to a unified synchronization state.

[0006] According to the embodiments provided in this application, by aligning the states between the state counting modules of multiple data channels, the continuity and stability of multi-channel data transmission are improved, avoiding the data frames from being misaligned due to misalignment of the state counting modules, which would cause frame loss of the external synchronization signal and the black line display problem.

[0007] In conjunction with the first aspect, some implementations of the first aspect further include: a state detection module electrically connected to multiple state counting modules for acquiring multiple state values ​​and determining whether the multiple state values ​​are consistent; and a synchronization correction module electrically connected to the state detection module, configured to output a synchronization control signal to control the multiple state counting modules to restore to a unified synchronization state when the state detection module detects inconsistency between the multiple state values.

[0008] According to the embodiments provided in this application, the state detection module can continuously detect the state value of the state counting module, and when it detects that multiple data channels have lost synchronization, it sends a synchronization control signal to the state counting module, thereby eliminating the counting misalignment caused by inconsistent states and ensuring the continuity and stability of multi-channel data transmission.

[0009] In conjunction with the first aspect, in some implementations of the first aspect, the multi-channel data transmission system includes an embedded display interface (eDP) transmission system; the multiple data channels include at least two Lane channels that transmit video data in parallel.

[0010] In conjunction with the first aspect, in some implementations of the first aspect, the state counting module includes a parity check marker (PM) counting module, which is configured to determine the forward error correction (FEC) frame sequence; the state value includes the binary value output by the PM counting module.

[0011] According to the embodiments provided in this application, by directly mapping the synchronization control to the forward error correction (FEC) decoding process, the FEC decoder is ensured to obtain an accurately aligned channel data frame sequence, thus guaranteeing the normal descrambling and restoration of the video data stream in the eDP multi-channel environment.

[0012] In conjunction with the first aspect, in some implementations of the first aspect, the state detection module includes: a comparison circuit configured to compare the corresponding binary bits of each state counting module in a plurality of data channels; the plurality of data channels include a first channel and a second channel, and the comparison circuit includes a two-bit comparator, used to compare the low bit of the state counting module corresponding to the first channel with the low bit of the state counting module corresponding to the second channel, and the high bit of the state counting module corresponding to the first channel with the high bit of the state counting module corresponding to the second channel.

[0013] According to the embodiments provided in this application, by using hardware binary bit comparison, the response delay of state inconsistency detection is shortened, and instantaneous and high-precision detection of out-of-step deviation between multiple data channels is achieved.

[0014] In conjunction with the first aspect, in some implementations of the first aspect, the synchronization correction module is further configured to: output a reset signal when the state detection module outputs a comparison signal representing a state inconsistency; the reset signal is used to reset the values ​​of multiple state counting modules to their initial states.

[0015] In conjunction with the first aspect, in some implementations of the first aspect, the synchronization correction module is further configured to: when an inconsistency is detected between multiple state values, modify the value output by the state counting module corresponding to the data channel that is interfered with to the value output by the state counting module corresponding to the data channel that is not interfered with; or, temporarily suspend the link synchronization clock signal corresponding to the channel with the leading count through the clock shielding unit until the state counting modules of multiple data channels are restored to alignment.

[0016] According to the embodiments provided in this application, by temporarily suspending the link clock corresponding to the leading channel, the leading channel is kept in a state while waiting for the lagging channel to catch up, thereby achieving dynamic smooth alignment between channels and reducing switching noise caused by level changes and power consumption of the multi-channel data transmission system.

[0017] In some possible implementations, when the multi-channel data transmission system includes a first channel and a second channel, the synchronization correction module is configured to: when the state values ​​of the first channel and the second channel are detected to be inconsistent, overwrite the state value of the first channel into the second channel by default; or, when the multi-channel data transmission system includes more than two channels, the synchronization correction module is configured to determine the data channel that is being interfered with through majority voting logic.

[0018] In some embodiments, the state value of the first channel can be considered as the state value corresponding to the data channel that is not disturbed.

[0019] In conjunction with the first aspect, in some implementations of the first aspect, the inconsistency in state values ​​is caused by the link synchronization clock signal being interfered with by coupled noise, resulting in at least one of the multiple state counting modules generating abnormal values.

[0020] In conjunction with the first aspect, in some implementations of the first aspect, the coupling noise includes the sleep wake-up SLPOUT signal.

[0021] According to the embodiments provided in this application, the anti-interference capability of the multi-channel data transmission system is improved during the specific working timing transition phase by suppressing the coupling noise interference caused by high-frequency level flipping at the moment of switching between sleep and wake-up SLPOUT states.

[0022] In some possible implementations, the state detection module is also electrically connected to the control line that receives the sleep wake-up SLPOUT signal; the state detection module is configured to initiate consistency detection of multiple state values ​​within a preset time window after the transient level flip of the SLPOUT signal.

[0023] Secondly, a synchronization control method is provided, the method comprising: acquiring the current state values ​​of multiple state counting modules corresponding to multiple data channels under the drive of a link synchronization clock signal; determining whether the multiple state values ​​are consistent; and, if inconsistency is detected between the state values, outputting a synchronization control signal to control the multiple state counting modules to restore to a unified synchronization state.

[0024] In conjunction with the second aspect, in some implementations of the second aspect, multiple data channels include a first channel and a second channel. Determining whether multiple state values ​​are consistent includes: comparing the low-order binary bits of the state counting module corresponding to the first channel with the low-order binary bits of the state counting module corresponding to the second channel, and comparing the high-order binary bits of the state counting module corresponding to the first channel with the high-order binary bits of the state counting module corresponding to the second channel.

[0025] In conjunction with the second aspect, in some implementations of the second aspect, controlling multiple state counting modules to return to a unified synchronous state includes: generating a reset signal to reset the multiple state counting modules that have experienced counting misalignment, so as to resynchronize counting after the interference is eliminated.

[0026] Thirdly, a display driver chip is provided for use in a display device. The display driver chip includes a synchronization control circuit, which includes: multiple state counting modules, each corresponding to multiple data channels in a multi-channel data transmission system, configured to output corresponding state values ​​under the drive of a link synchronization clock signal; and a synchronization correction module, each electrically connected to the multiple state counting modules, configured to output a synchronization control signal to control the multiple state counting modules to restore to a unified synchronization state.

[0027] Fourthly, a display device is provided, including a display driver chip. The display driver chip is applied to the display device and includes a synchronization control circuit. The synchronization control circuit includes: multiple state counting modules, each corresponding to multiple data channels in a multi-channel data transmission system, configured to output corresponding state values ​​under the drive of a link synchronization clock signal; and a synchronization correction module, each electrically connected to the multiple state counting modules, configured to output a synchronization control signal to control the multiple state counting modules to restore to a unified synchronization state.

[0028] Fifthly, a computer-readable storage medium is provided having computer program instructions stored thereon, which, when executed by a processor, implement the methods of the second aspect and any of its implementations.

[0029] In a sixth aspect, a computer program product is provided, comprising a computer program whose instructions, when executed by a processor, implement the methods as described in the second aspect and any of its implementations.

[0030] In a seventh aspect, a multi-channel data receiver is provided for use in an embedded display interface eDP transmission system, including a synchronization control circuit as described in the first aspect and any of its implementations. Attached Figure Description

[0031] Figure 1 This is a schematic diagram of a control circuit; Figure 2 This is a schematic diagram of a control circuit that experiences abnormal operating conditions due to coupling noise. Figure 3 This is a schematic diagram of the structure of a synchronization control circuit provided in an embodiment of this application; Figure 4 This is a schematic diagram of another synchronous control circuit provided in an embodiment of this application; Figure 5 This is a schematic diagram of another synchronous control circuit provided in an embodiment of this application; Figure 6 This is a waveform diagram of a synchronization control circuit provided in an embodiment of this application; Figure 7 This is a schematic diagram of another synchronous control circuit provided in an embodiment of this application; Figure 8 This is a flowchart illustrating a synchronization control method provided in an embodiment of this application. Detailed Implementation

[0032] The technical solutions in this application will now be described with reference to the accompanying drawings.

[0033] This application will present various aspects, embodiments, or features relating to a system comprising multiple devices, components, modules, etc. It should be understood and appreciated that individual systems may include additional devices, components, modules, etc., and / or may not include all the devices, components, modules, etc. discussed in conjunction with the accompanying drawings. Furthermore, combinations of these approaches are also possible.

[0034] Furthermore, in the embodiments of this application, the words "exemplary," "for example," etc., are used to indicate that they are examples, illustrations, or descriptions. Any embodiment or design scheme described as "exemplary" in the embodiments of this application should not be construed as being better or more advantageous than other embodiments or design schemes. Specifically, the use of the term "exemplary" is intended to present the concept in a concrete manner.

[0035] The business scenarios described in the embodiments of this application are for the purpose of more clearly illustrating the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions provided in the embodiments of this application. As those skilled in the art will know, with the evolution of technology and the emergence of new business scenarios, the technical solutions provided in the embodiments of this application are also applicable to similar technical problems.

[0036] References to "one embodiment" or "some embodiments" as described in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.

[0037] In this application embodiment, "at least one" refers to one or more, and "more than one" refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, and B alone, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can represent: a, b, c, ab, ac, bc, or abc, where a, b, and c can be single or multiple.

[0038] In the description of the embodiments of this application, the terms "upper," "lower," "left," "right," "inner," "outer," "vertical," and "horizontal," etc., indicate the orientation or positional relationship relative to the orientation or position of the components shown in the accompanying drawings. It should be understood that these directional terms are relative concepts, used for relative description and clarification, and not to indicate or imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. They can change accordingly depending on the orientation of the components in the accompanying drawings, and therefore should not be construed as limiting this application.

[0039] In the embodiments of this application, the same reference numerals are used to denote the same component or part. For the same part in the embodiments of this application, only one part or component may be labeled with reference numerals in the figures. It should be understood that the reference numerals also apply to other identical parts or components. In addition, the various parts in the figures are not drawn to scale, and the dimensions and sizes of the parts shown in the figures are only exemplary and should not be construed as limiting this application.

[0040] The following describes the technical content related to the embodiments of this application.

[0041] As clients of virtual reality (VR) or augmented reality (AR) devices have increasingly demanding requirements for data transmission (e.g., increased data bandwidth, increased transmission distance, low latency, or high resolution), the MIPI interface cannot meet the data transmission needs of VR devices. Therefore, the eDP interface is adopted in VR devices to meet these data transmission requirements.

[0042] This eDP transmission system typically employs a multi-lane parallel transmission architecture. To improve the anti-interference capability of data transmission, a forward error correction (FEC) module is integrated into the transmission system.

[0043] However, some display devices using eDP exhibit abnormal display problems such as black lines on the screen during certain stages (e.g., power-on). Testing and analysis revealed that these abnormal display problems are usually accompanied by frame loss or dropped frames in the external vertical synchronization (V-sync) signal.

[0044] How to effectively avoid the loss of the external field synchronization signal (Vsync) in the eDP multi-channel transmission system, thereby completely improving and eliminating display defects such as black screen and black line abnormal display, is an urgent problem to be solved.

[0045] Figure 1 This is a schematic diagram of a control circuit.

[0046] Figure 1 The parity marker output generator (PM OutputGen) is shown. PM OutputGen is part of the forward error correction (FEC) protocol. PMOutputGen is used to indicate the frame position of the FEC structure. Figure 1 A counter is also shown, which is used to display a count value (e.g., 2'b00 or 2'b01). The counter can be a state counter used to track the current FEC frame sequence. Figure 1 The link speed clock (LSCLK) signal is also shown; LSCLK is a signal used to drive the counter. Figure 1 The channel enable signals (e.g., L0 enable signal, or L1 enable signal (L0 / L1_Lane_en)) are also shown, indicating that Lane 0 and Lane 1 are in the working state. Figure 1The parity input signal (PM input) for generating the parity signal (e.g., L0_PM or L1_PM) is also shown. Coupling noise is an external source of interference that can cause faults.

[0047] refer to Figure 1 The transmitting end is equipped with a PM Output Gen and a PM input. The PM Output Gen, as part of the FEC protocol, is used to generate PM markers based on the PM input signal to indicate the frame position in the FEC structure. The transmission system contains multiple data channels that transmit video data in parallel, such as the first channel (Lane 0) and the second channel (Lane 1). Each channel is enabled via channel enable signals (L0_Lane_en, L1_Lane_en).

[0048] At the receiving end (such as within a display driver chip), there is a forward error correction decoder (FEC Decoder) and a status counter (hereinafter referred to as PM counter) corresponding to each data channel.

[0049] Each state counter increments and flips under the drive of the link speed clock (LSCLK) signal to track the current FEC frame sequence locally. During normal operation and interference-free initialization or data transmission phases, since the first and second channels receive the enable signal synchronously and the LSCLK signal is undisturbed, the state value (L0 Cnt) output by the PM counter corresponding to the first channel remains synchronized with the state value (L1 Cnt) output by the PM counter corresponding to the second channel. For example, if both output the binary value 2'b00 within the same clock cycle, they will both flip to 2'b01 in the next clock cycle, and their corresponding PM markers will remain completely equal (i.e., L0_PM = L1_PM). At this time, the receiver FEC Decoder can accurately align the data frames of the two channels, descrambling and reassembly are completely normal, the module display shows no abnormalities, and the external field synchronization signal (ExternalVsync) is output stably.

[0050] However, during the actual operation of a multi-channel data transmission system or during specific state switching phases, external interference may occur due to the limitations of timing and spatial routing in the multi-channel data transmission system.

[0051] Figure 2 This is a schematic diagram of a control circuit that is in an abnormal operating state due to coupling noise.

[0052] refer to Figure 2When the system performs level toggling operations such as sleep-out (SLPOUT), due to the distributed capacitance and inductance effects between physical lines, the coupling noise generated by the SLPOUT signal can electromagnetically interfere into the transmission path of the link synchronization clock signal (LSCLK). The injection of this external coupling noise causes fluctuations in the physical level of the LSCLK signal, thereby introducing unexpected glitches into its clock signal line.

[0053] As a result, for example at time 1, the LSCLK corresponding to the first channel is not affected by glitches, and its PM counter (L0Cnt) remains normally at 2'b00; however, the LSCLK corresponding to the second channel is triggered by a glitch pulse generated by coupling noise, which is mistakenly identified by the receiver as a valid clock trigger edge, causing the PM counter (L1Cnt) corresponding to the second channel to make an abnormal lead jump, incorrectly jumping to 2'b01. At this time, the values ​​of the two counters deviate (L0Cnt ≠ L1Cnt), which in turn causes the parity markers of the two channels to be unequal (L0_PM ≠ L1_PM). At the subsequent time 2, even if the coupling noise disappears and the clock waveform of the LSCLK signal is repaired and restored to normal by the equalizer, the state counters corresponding to the two channels will maintain a fixed phase deviation and continue to run in subsequent increments (i.e., "always one step behind," for example, the counter corresponding to one channel is counting 1, 2, 3, and the counter corresponding to the other channel is counting 2, 3, 4), thus falling into a permanent phase out-of-sync state. This long-term counter desynchronization causes the FEC Decoder to be unable to properly align the data frames of the two channels, resulting in continuous descrambling failures (FEC module error), causing external Vsync to lose frames or drop frames, and ultimately manifesting as obvious black lines on the display screen.

[0054] In view of this, embodiments of this application provide a synchronization control circuit, a control method, a display driver chip, and a display device.

[0055] Figure 3 This is a schematic diagram of a synchronous control circuit provided in an embodiment of this application.

[0056] refer to Figure 3 The synchronization control circuit 100 provided in this application embodiment includes: Multiple state counting modules 10 correspond to multiple data channels (e.g., at least two Lane channels for parallel transmission of video data, including the first channel Lane 0 and the second channel Lane 1) in a multi-channel data transmission system (e.g., an eDP transmission system).

[0057] Each state counting module 10 is configured to output a corresponding state value under the drive of the link synchronization clock signal (LSCLK).

[0058] In some embodiments, the state counting module 10 can be a parity check marker PM counter module (PMCounter) used to track the current FEC frame sequence at the receiving end. The state value output by the state counting module 10 is the current binary count value of the PM counter module.

[0059] The synchronization correction module 30 is electrically connected to multiple state counting modules 10. The synchronization correction module 30 is configured to output synchronization control signals to the multiple state counting modules 10 to control the multiple state counting modules 10 to restore to a unified synchronization state.

[0060] Figure 4 This is a schematic diagram of another synchronous control circuit provided in an embodiment of this application.

[0061] refer to Figure 4 The control circuit also includes: The status detection module 20 is electrically connected to multiple status counting modules 10 and a synchronization correction module 30. The status detection module 20 is configured to acquire the current output status value of each status counting module 10 and determine whether the multiple status values ​​are consistent (i.e., whether there is a loss of synchronization between channels). Loss of synchronization: that is, loss of synchronization.

[0062] The status detection module 20 can acquire the status value output by each status counting module 10 in real time during each cycle.

[0063] Figure 5 This is a schematic diagram of another synchronous control circuit provided in an embodiment of this application.

[0064] Reference Figures 3-5 The system has multiple data channels, including a first channel (Lane 0) and a second channel (Lane 1). The first channel corresponds to a first state counter module (L0 Counter), whose current output state value includes the high-order binary byte A1 and the low-order binary byte A0; the second channel corresponds to a second state counter module (L1 Counter), whose current output state value includes the high-order binary byte B1 and the low-order binary byte B0.

[0065] The comparison circuit in the status detection module 20 includes a 2-bit comparator 200. This 2-bit comparator is configured to perform parallel comparisons of each bit of the binary value of any one of the status counting modules in the multiple data channels.

[0066] The two-bit comparator 200 includes a first comparison unit 210 and a second comparison unit 220.

[0067] The two input terminals of the first comparison unit 210 are connected to the binary low-order bit A0 of L0 Counter and the binary low-order bit B0 of L1 Counter, respectively, and are used to compare whether the low-order bit values ​​of the corresponding counting modules of the first channel and the second channel are consistent.

[0068] The two input terminals of the second comparison unit 220 are connected to the high-order binary bits A1 of L0 Counter and B1 of L1 Counter, respectively, to compare whether the high-order bit values ​​of the corresponding counting modules of the first channel and the second channel are consistent.

[0069] The outputs of the first comparison unit 210 and the second comparison unit 220 are both connected to the synchronization correction module 30. When A0 and B0 are inconsistent, or A1 and B1 are inconsistent, the comparison circuit generates a comparison signal representing the inconsistency of state values ​​(e.g., outputting a high-level pulse) and outputs it to the synchronization correction module 30.

[0070] After receiving the "state value inconsistency" comparison signal sent by the state detection module 20, the synchronization correction module 30 can restore the state counting modules 10 corresponding to each channel to a unified alignment state in various ways.

[0071] In some embodiments, a global reset (Reset reset to zero) can be performed based on a reset signal.

[0072] Figure 6 This is a waveform diagram of a synchronization control circuit provided in an embodiment of this application.

[0073] refer to Figure 6 The synchronization correction module 30 is configured to output a reset signal when the state detection module 20 outputs a comparison signal representing a state inconsistency.

[0074] The specific reset process and timing coordination are as follows: Figure 6 The waveform diagram is shown below: Normal counting phase: Driven by the LSCLK signal, the first channel counter (L0_PM) and the second channel counter (L1_PM) synchronously toggle and count (e.g., synchronously changing from 00 to 01). At this time, the two-bit comparator detects that the two channels are consistent, and the Reset signal remains low (does not reset).

[0075] Noise interference and loss of synchronization: At certain stages (e.g., when the SLPOUT signal level flips), high-frequency glitches are generated on the transmission path of coupled noise to LSCLK, causing the second channel counter (L1_PM) to jump to 01 prematurely, while the first channel counter (L0_PM) remains at 00.

[0076] Deviation detection: The two-bit comparator of the status detection module 20 finds that the lower bit A0(0) is not equal to B0(1), and outputs an abnormal trigger signal to the synchronization correction module 30.

[0077] Reset process: In response to the abnormal trigger signal, the synchronous correction module 30 pulls the Reset signal high (switching from low level to high level). This high-level reset signal is simultaneously applied to the clear reset terminal (Rst terminal) of L0 Counter and L1 Counter, resetting the values ​​of these two state counting modules to the initial zero state (e.g., resetting to 2'b00).

[0078] When the comparison result Y equals 0, it indicates that the channel is in an abnormal synchronization state (Fec_abnormal_pm). The comparison results between multiple channels are inconsistent, and multiple channels have lost synchronization, requiring a reset or resetting.

[0079] When the comparison result Y equals 1, it indicates that the channel is in a normal synchronization state (Fec_normal_pm). If the comparison results of multiple channels are consistent, the channels are synchronized and no reset or resetting is required.

[0080] Realignment Startup: After the reset action is completed, the Reset signal is pulled low to release. With the subsequent disappearance of coupling noise and the recovery of the LSCLK waveform, the two state counting modules synchronously restart counting from the same zero reference point under clean clock drive (synchronous toggling to 01, 10, 11, etc.). In this way, the FEC Decoder can seamlessly restore the alignment of data frames in each channel and successfully decode them, thereby preventing frame loss from external Vsync and eliminating black lines.

[0081] In some embodiments, the first channel and the second channel can be directly aligned based on value overwriting.

[0082] In some embodiments, the synchronization correction module 30 is configured to output a numerical overwrite signal when an inconsistency is detected between multiple state values.

[0083] The specific working logic is as follows: When the first channel counter and the second channel counter are misaligned (for example, L0Cnt = 2'b00, L1Cnt = 2'b01), the synchronization correction module 30 determines that the data channel affected by coupling noise is the second channel, while the data channel that is not affected by noise is the first channel.

[0084] Subsequently, the synchronization correction module 30 uses the current state value (2'b00) of the unaffected first channel counter as a reference to overwrite the distorted second channel counter, changing the output value of the second channel counter from 2'b01 to 2'b00. In other words, the value output of the distorted second channel counter is modified to the value output of the unaffected first channel counter.

[0085] According to the embodiments provided in this application, by overwriting the values, the counting states of the two channels can be aligned instantly without undergoing a global hardware reset, thereby reducing the power consumption fluctuations and potential timing overhead caused by the global reset.

[0086] In some embodiments, the first channel and the second channel can be aligned based on a clock shielding unit delay.

[0087] In some embodiments, the synchronization correction module 30 may integrate a clock shielding unit (e.g., a clock gating cell (CGC)). This clock shielding unit can distribute the LSCLK signal to the transmission paths of each state counting module 10.

[0088] When the status detection module 20 detects inconsistencies in status values, the synchronization correction module 30 temporarily suspends (intercepts) the link synchronization clock signal corresponding to the channel with an advanced count through the clock shielding unit, while maintaining the normal transmission of the link synchronization clock signal corresponding to the channel with a lagging count, until the status counting modules of multiple channels are re-aligned. Alternatively, the opposite can be true.

[0089] The specific control logic is as follows: Assume that noise interference causes the second channel counter to jump ahead (L1 Cnt = 2'b01, L0 Cnt = 2'b00). The synchronization correction module 30 identifies the second channel's count as ahead and controls the clock masking unit corresponding to the second channel to pull down the clock enable signal, thereby temporarily intercepting and suspending the LSCLK clock signal input to L1 Counter for one cycle. During this suspension period, L1 Counter does not receive the trigger clock edge, and its count value remains unchanged at 2'b01. At the same time, the clock masking unit of the first channel remains open, and L0 Counter normally receives the LSCLK clock pulse and counts forward one step, its value changing from 2'b00 to 2'b01.

[0090] When the status detection module 20 detects that L0 Cnt and L1 Cnt have become equal again (e.g., both are 2'b01), the synchronization correction module 30 removes the clock gating restriction on the second channel, causing the clock masking unit to release LSCLK again. The two counters then continue to count synchronously in a fully aligned state.

[0091] According to the embodiments provided in this application, the advantage of this solution is that it achieves completely lossless state recovery, avoids instantaneous interruption of data stream, and greatly improves the continuity of video display and the stability of image quality.

[0092] Figure 7 This is a schematic diagram of another synchronous control circuit provided in an embodiment of this application.

[0093] refer to Figure 7 The system has multiple data channels, including a first channel (Lane 0), a second channel (Lane 1), a third channel (Lane 2), and a fourth channel (Lane 3). The first channel corresponds to a first state counter module (L0 Counter), whose current output state value includes the high-order binary byte A1 and the low-order binary byte A0. The second channel corresponds to a second state counter module (L1 Counter), whose current output state value includes the high-order binary byte B1 and the low-order binary byte B0. The third channel corresponds to a third state counter module (L2 Counter), whose current output state value includes the high-order binary byte C1 and the low-order binary byte C0. The fourth channel corresponds to a fourth state counter module (L3 Counter), whose current output state value includes the high-order binary byte D1 and the low-order binary byte D0.

[0094] The comparison circuit in the status detection module 20 includes a two-bit comparator 200. This two-bit comparator is configured to perform parallel comparisons of each bit of the binary value of any one of the status counting modules in the multiple data channels.

[0095] The two-bit comparator 200 includes a first-stage comparator unit 200A and a second-stage comparator unit 200B.

[0096] The first-level comparison unit 200A includes a first sub-comparison unit 201A, a second sub-comparison unit 202A, a third sub-comparison unit 203A, a fourth sub-comparison unit 204A, a fifth sub-comparison unit 205A, a sixth sub-comparison unit 206A, a seventh sub-comparison unit 207A, an eighth sub-comparison unit 208A, a ninth sub-comparison unit 209A, a tenth sub-comparison unit 210A, an eleventh sub-comparison unit 211A, and a twelfth sub-comparison unit 212A.

[0097] The second-level comparison unit 200B includes a low-order comparator 210B and a high-order comparator 220B.

[0098] The two input terminals of the first sub-comparison unit 201A are connected to the binary low-order bit A0 of L0 Counter and the binary low-order bit B0 of L1 Counter, respectively, and are used to compare whether the low-order values ​​of the corresponding counting modules of the first channel and the second channel are consistent.

[0099] The two inputs of the second sub-comparison unit 202A are connected to the high-order binary bits A1 of L0 Counter and B1 of L1Counter, respectively, to compare whether the high-order values ​​of the corresponding counting modules of the first and second channels are consistent. The two inputs of the third sub-comparison unit 203A are connected to the low-order binary bits A0 of L0 Counter and C0 of L2Counter, respectively, to compare whether the low-order values ​​of the corresponding counting modules of the first and third channels are consistent.

[0100] The two input terminals of the fourth sub-comparison unit 204A are connected to the high binary bit A1 of L0 Counter and the high binary bit C1 of L2Counter, respectively, to compare whether the high bit values ​​of the corresponding counting modules of the first channel and the third channel are consistent.

[0101] The two input terminals of the fifth sub-comparison unit 205A are connected to the binary low-order bits C0 of L2 Counter and D0 of L3 Counter, respectively, to compare whether the low-order values ​​of the corresponding counting modules of the third and fourth channels are consistent.

[0102] The two input terminals of the sixth sub-comparison unit 206A are connected to the high binary bit C1 of L2 Counter and the high binary bit D1 of L3 Counter, respectively, to compare whether the high bit values ​​of the corresponding counting modules of the third channel and the fourth channel are consistent.

[0103] The two input terminals of the seventh sub-comparison unit 207A are connected to the binary low-order bit A0 of L0 Counter and the binary low-order bit D0 of L3 Counter, respectively, to compare whether the low-order values ​​of the corresponding counting modules of the first channel and the fourth channel are consistent.

[0104] The two input terminals of the eighth sub-comparison unit 208A are connected to the high binary bit A1 of L0 Counter and the high binary bit D1 of L3 Counter, respectively, to compare whether the high bit values ​​of the corresponding counting modules of the first channel and the fourth channel are consistent.

[0105] The two input terminals of the ninth sub-comparison unit 209A are connected to the binary low-order bit B0 of L1 Counter and the binary low-order bit C0 of L2 Counter, respectively, to compare whether the low-order values ​​of the corresponding counting modules of the second channel and the third channel are consistent.

[0106] The two input terminals of the tenth sub-comparison unit 210A are connected to the high-order binary bits B1 of L1 Counter and C1 of L2 Counter, respectively, to compare whether the high-order values ​​of the corresponding counting modules of the second and third channels are consistent.

[0107] The two input terminals of the eleventh sub-comparison unit 211A are connected to the binary low-order bit B0 of L1 Counter and the binary low-order bit D0 of L3 Counter, respectively, and are used to compare whether the low-order values ​​of the corresponding counting modules of the second channel and the fourth channel are consistent.

[0108] The two inputs of the twelfth sub-comparison unit 212A are connected to the high-order binary bits B1 of L1 Counter and D1 of L3 Counter, respectively, to compare whether the high-order values ​​of the corresponding counting modules of the second and fourth channels are consistent.

[0109] The input terminals of the low-order comparator 210B are connected to the output terminals of the first sub-comparison unit 201A, the third sub-comparison unit 203A, the fifth sub-comparison unit 205A, the seventh sub-comparison unit 207A, the ninth sub-comparison unit 209A, and the eleventh sub-comparison unit 211A, respectively. The low-order comparator 210B is used to determine whether the low-order values ​​of multiple channels are consistent.

[0110] As an example, the low-order bit comparator 210B can determine whether the low-order bit values ​​are consistent between any two channels among the first, second, third, and fourth channels. The low-order bit comparator 210B can further determine which specific channels have inconsistent low-order bit values.

[0111] The input terminals of the high-order comparator 220B are connected to the output terminals of the second sub-comparison unit 202A, the fourth sub-comparison unit 204A, the sixth sub-comparison unit 206A, the eighth sub-comparison unit 208A, the tenth sub-comparison unit 210A, and the twelfth sub-comparison unit 212A, respectively. The high-order comparator 220B is used to determine whether the high-order values ​​of multiple channels are consistent.

[0112] As an example, the high-order bit comparator 220B can determine whether the high-order bit values ​​are consistent between any two channels among the first, second, third, and fourth channels. The high-order bit comparator 220B can further determine which specific channels have inconsistent high-order bit values.

[0113] The outputs of the low-order comparator 210B and the high-order comparator 220B are both connected to the synchronization correction module 30. When any two of A0, B0, C0, and D0 are inconsistent, or any two of A1, B1, C1, and D1 are inconsistent, the comparator circuit generates a comparison signal representing the inconsistency of state values ​​(e.g., outputting a high-level pulse) and outputs it to the synchronization correction module 30.

[0114] This application also provides a synchronization control method. This synchronization control method can be applied to multi-channel data transmission systems.

[0115] Figure 8 This is a flowchart illustrating a synchronization control method provided in an embodiment of this application. (Reference) Figure 8 The synchronization control method includes the following steps: S710: Obtain the current status values ​​of multiple status counting modules corresponding to multiple data channels.

[0116] Driven by the link synchronization clock signal, the current status values ​​of multiple status counting modules (such as L0 Counter and L1 Counter) corresponding to multiple data channels can be obtained.

[0117] Alternatively, driven by the link synchronization clock signal, the current status values ​​of multiple status counting modules (such as L0 Counter, L1 Counter, L2 Counter and L3 Counter) corresponding to multiple data channels can be obtained.

[0118] S720 determines whether multiple state values ​​are consistent.

[0119] A state detection module (such as a comparison circuit containing a two-bit hardware comparator) can be used to compare whether the low-order binary bit A0 of the state counting module corresponding to the first channel is equal to the low-order binary bit B0 of the state counting module corresponding to the second channel, and whether the high-order binary bit A1 of the state counting module corresponding to the first channel is equal to the high-order binary bit B1 of the state counting module corresponding to the second channel. This determines whether the multiple state values ​​are consistent.

[0120] Alternatively, a state detection module (such as a comparison circuit containing a two-bit hardware comparator) can be used to compare whether the binary low-order bits A0, B0, C0, and D0 of the state counting module corresponding to the first channel, the second channel, and the third channel are equal, and whether the binary high-order bits A1, B1, C1, and D1 of the state counting module corresponding to the first, second, and third channels are equal. This determines whether multiple state values ​​are consistent.

[0121] When multiple state values ​​are inconsistent, the S730 outputs a synchronization control signal to control multiple state counting modules to restore them to a unified synchronization state.

[0122] If an inconsistency is detected between state values ​​in step S720, the synchronization correction module immediately outputs a synchronization control signal (e.g., a Reset signal, a value overwrite control signal, or a clock mask enable signal) to control multiple state counting modules to restore to a unified synchronization state (e.g., global zeroing, value copying, or clock gating suspension alignment).

[0123] Once the state is restored to consistency, the system continues to synchronously increment the count, thereby eliminating the phenomenon of loss of synchronization between channels caused by external interference at the hardware level.

[0124] Embodiments of this application also provide a display driver IC (DDIC) that integrates the synchronous control circuit 100 of the aforementioned multi-channel data transmission system.

[0125] This display driver chip can achieve counter alignment at its receiving end (such as in the eDP receiver physical layer and FEC decoding logic), thereby greatly improving the chip's anti-electromagnetic crosstalk and anti-noise capabilities, and ensuring the timing and frame integrity of the video data output by the chip to the display screen.

[0126] Embodiments of this application also provide a display device. The display device may include a synchronization control circuit 100, or may directly incorporate a display driver chip integrating the synchronization control circuit 100.

[0127] The display device provided in this application can be a virtual reality (VR) device or an augmented reality (AR) device (such as a VR head-mounted display, AR smart glasses, etc.).

[0128] In VR / AR devices, due to the compact structure of the headset and the dense internal high-frequency digital traces (e.g., the physical distance between control lines such as SLPOUT and eDP clock lines is extremely close), spatial electromagnetic crosstalk can occur. VR / AR devices equipped with the synchronization control circuit or display driver chip provided in the embodiments of this application can solve the clock distortion and counting synchronization problems caused by sleep wake-up or other electromagnetic noise coupling, resolve external Vsync frame loss faults, and provide a stable, smooth display without black line abnormalities.

[0129] Embodiments of this application also provide a computer-readable storage medium having computer program instructions stored thereon, which, when executed by a processor, implement the control method as described in any embodiment of this application.

[0130] Embodiments of this application also provide a computer program product, including a computer program that, when executed by a processor, implements the control method as described in any embodiment of this application.

[0131] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed in this application can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0132] Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0133] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0134] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0135] In addition, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0136] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0137] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A synchronous control circuit, characterized in that, Applied to display devices, including: Multiple status counting modules, each corresponding to a data channel in a multi-channel data transmission system, are configured to output corresponding status values ​​under the drive of a link synchronization clock signal. The synchronization correction module is electrically connected to the plurality of state counting modules and is configured to output a synchronization control signal to control the plurality of state counting modules to restore to a unified synchronization state.

2. The synchronous control circuit according to claim 1, characterized in that, Also includes: A state detection module, electrically connected to the plurality of state counting modules, is used to acquire the plurality of state values ​​and determine whether the plurality of state values ​​are consistent. The synchronization correction module is also electrically connected to the state detection module and is configured to output the synchronization control signal to control the multiple state counting modules to restore to a unified synchronization state when the state detection module detects inconsistencies among the multiple state values.

3. The synchronous control circuit according to claim 1 or 2, characterized in that, The multi-channel data transmission system includes an embedded display interface (eDP) transmission system. The multiple data channels include at least two Lane channels that transmit video data in parallel.

4. The synchronous control circuit according to claim 1 or 2, characterized in that, The state counting module includes a parity check marker (PM) counting module, which is configured to determine the forward error correction (FEC) frame sequence. The status value includes the binary value output by the PM counting module.

5. The synchronous control circuit according to claim 2, characterized in that, The status detection module includes: The comparison circuit is configured to compare the corresponding binary bits of each state counting module in the plurality of data channels; The plurality of data channels include a first channel and a second channel. The comparison circuit includes a two-bit comparator, which is used to compare the low bit of the state counting module corresponding to the first channel with the low bit of the state counting module corresponding to the second channel, and the high bit of the state counting module corresponding to the first channel with the high bit of the state counting module corresponding to the second channel.

6. The synchronous control circuit according to claim 2, characterized in that, The synchronization correction module is also configured to: When the state detection module outputs a comparison signal representing a state inconsistency, a reset signal is output. The reset signal is used to reset the values ​​of the plurality of state counting modules to their initial state.

7. The synchronous control circuit according to claim 1 or 2, characterized in that, The synchronization correction module is also configured to: When inconsistencies are detected among multiple state values, the value output by the state counting module corresponding to the interfered data channel is modified to the value output by the state counting module corresponding to the undisturbed data channel; or, The link synchronization clock signal corresponding to the channel with the advanced count is temporarily suspended by the clock shielding unit until the status counting modules of the multiple data channels are restored to alignment.

8. The synchronous control circuit according to claim 1 or 2, characterized in that, The inconsistency in the status values ​​is caused by the link synchronization clock signal being interfered with by coupling noise, resulting in at least one of the multiple status counting modules generating abnormal values.

9. The synchronous control circuit according to claim 8, characterized in that, The coupling noise includes the sleep wake-up SLPOUT signal.

10. A synchronization control method, characterized in that, The method includes: Driven by the link synchronization clock signal, the current status values ​​of multiple status counting modules corresponding to multiple data channels are acquired; Determine whether the multiple state values ​​are consistent; and, If an inconsistency is detected between the state values, a synchronization control signal is output to control the multiple state counting modules to restore to a unified synchronization state.

11. The synchronization control method according to claim 10, characterized in that, The plurality of data channels includes a first channel and a second channel, and determining whether the plurality of state values ​​are consistent includes: Compare the low-order binary bits of the state counting module corresponding to the first channel with the low-order binary bits of the state counting module corresponding to the second channel, and compare the high-order binary bits of the state counting module corresponding to the first channel with the high-order binary bits of the state counting module corresponding to the second channel.

12. The synchronization control method according to claim 10 or 11, characterized in that, Controlling the multiple state counting modules to restore to a unified synchronization state includes: A reset signal is generated to reset the multiple state counting modules that have experienced counting misalignment, so that the counting can be resynchronized after the interference is eliminated.

13. A display driver chip, characterized in that, The display driver chip, applied to a display device, includes a synchronization control circuit, which comprises: Multiple status counting modules, each corresponding to a data channel in a multi-channel data transmission system, are configured to output corresponding status values ​​under the drive of a link synchronization clock signal. The synchronization correction module is electrically connected to the plurality of state counting modules and is configured to output a synchronization control signal to control the plurality of state counting modules to restore to a unified synchronization state.

14. A display device, characterized in that, The display driver chip is used in the display device. The display driver chip includes a synchronization control circuit, which includes: Multiple status counting modules, each corresponding to a data channel in a multi-channel data transmission system, are configured to output corresponding status values ​​under the drive of a link synchronization clock signal. The synchronization correction module is electrically connected to the plurality of state counting modules and is configured to output a synchronization control signal to control the plurality of state counting modules to restore to a unified synchronization state.

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