Test method, device and equipment for CPU card chip and storage medium

Abstract

The invention relates to the technical field of CPU card chips, and discloses a CPU card chip test method, device and equipment and a storage medium, and the method comprises the steps: carrying out the data collection of a CPU card chip, and obtaining an initial test data matrix; constructing a test parameter association diagram of the initial test data matrix and predicting missing data to obtain a complete test data matrix; performing principal component analysis on the complete test data matrix to obtain an effective test data set; constructing a multi-level fuzzy set according to the effective test data set to obtain fusion test data; and inputting the fusion test data into a variational auto-encoder for self-supervised pre-training, executing conditional interpolation by using a diffusion state space model to obtain a defect detection result and an uncertainty estimation value, and realizing optimal fusion of electrical characteristics and functional test data by using a multi-stage fuzzy set and an adaptive weight adjustment mechanism. Complementary advantages of dual-channel data are fully utilized, and a more comprehensive and accurate test result is provided.

Description

Technical Field

[0001] The present invention relates to the technical field of CPU card chips, and in particular to a testing method, device, equipment and storage medium for a CPU card chip. Background Art

[0002] The traditional CPU card chip testing method mainly relies on a single test channel to collect data for analysis. This method has problems such as large test data errors and possible data missing during the actual test process, which seriously affects the accuracy and reliability of the test. When the test data is missing or the collection is incomplete, the traditional data filling method often uses simple mean replacement or linear interpolation, which is difficult to reflect the complex correlation between parameters, resulting in inaccurate test results or even misjudgment, affecting product quality and test efficiency.

[0003] With the rapid development of smart card manufacturing technology, the defect types of CPU card chips are becoming increasingly complex and hidden, and traditional closed-set classification algorithms face severe challenges in the testing process. Existing defect identification methods usually treat chip testing as a typical closed-set classification problem, pre-defining a limited number of defect types, but new types of defects that are unknown in advance often appear in actual production environments. Data imbalance and missing values ​​caused by test equipment failures and communication problems further increase the difficulty of testing, making existing deep learning models perform poorly in CPU card chip testing and unable to effectively cope with complex situations in actual production environments. Summary of the invention

[0004] The present invention provides a testing method, device, equipment and storage medium for a CPU card chip. The present invention adopts a multi-level fuzzy set and an adaptive weight adjustment mechanism to achieve the optimal fusion of electrical characteristics and functional test data, fully utilizes the complementary advantages of dual-channel data, and provides more comprehensive and accurate test results.

[0005] In a first aspect, the present invention provides a method for testing a CPU card chip, the method comprising: Collect data on the CPU card chip to obtain an initial test data matrix including electrical parameter vectors and functional parameter vectors; Constructing a test parameter association diagram of the initial test data matrix and predicting missing data to obtain a complete test data matrix; Performing principal component analysis on the complete test data matrix to obtain a valid test data set; Constructing a multi-level fuzzy set according to the effective test data set, and calculating the cosine similarity with the calibration reference model to obtain fused test data; The fused test data is input into a variational autoencoder for self-supervised pre-training, and a diffusion state space model is used to perform conditional interpolation to obtain defect detection results and uncertainty estimates.

[0006] In a second aspect, the present invention provides a test device for a CPU card chip, the test device for the CPU card chip comprising: The data acquisition module is used to collect data from the CPU card chip to obtain an initial test data matrix including an electrical parameter vector and a functional parameter vector; A construction module is used to construct a test parameter association diagram of the initial test data matrix and predict missing data to obtain a complete test data matrix; A principal component analysis module, used for performing principal component analysis on the complete test data matrix to obtain a valid test data set; A calculation module, used for constructing a multi-level fuzzy set according to the effective test data set, and calculating the cosine similarity with the calibration reference model to obtain fused test data; The defect detection module is used to input the fusion test data into a variational autoencoder for self-supervised pre-training, and use a diffusion state space model to perform conditional interpolation to obtain defect detection results and uncertainty estimates.

[0007] The third aspect of the present invention provides a test device for a CPU card chip, comprising: a memory and at least one processor, wherein instructions are stored in the memory; the at least one processor calls the instructions in the memory so that the test device for the CPU card chip executes the above-mentioned test method for the CPU card chip.

[0008] A fourth aspect of the present invention provides a computer-readable storage medium, wherein the computer-readable storage medium stores instructions, which, when executed on a computer, enable the computer to execute the above-mentioned CPU card chip testing method.

[0009] In the technical solution provided by the present invention, the integrity and reliability of test data are significantly improved through a dual-channel synchronous test system, and the missing data prediction method constructed based on fuzzy mathematics theory can accurately quantify the correlation between test parameters and effectively fill in the missing information in the test data set; the combination of principal component analysis technology and outlier detection mechanism effectively screens out real and reliable test data, thereby improving the quality and credibility of test data; multi-level fuzzy sets and adaptive weight adjustment mechanism realize the optimal fusion of electrical characteristics and functional test data, fully utilizing the complementary advantages of dual-channel data to provide more comprehensive and accurate test results; the CCTT multi-step training framework effectively solves the problems of test data imbalance and missingness through data enhancement, self-supervised pre-training and conditional interpolation, thereby improving the performance of defect detection models; the combination of open set recognition method and decoupled federal expert model system realizes the automatic discovery and continuous learning recognition of unknown defect types, while overcoming the catastrophic forgetting problem of traditional models during the updating process, so that the CPU card chip test system can continuously adapt to new defects appearing in the production environment and maintain a high test accuracy and reliability.

[0010] Other features and advantages of the present invention will be described in the following description, and partly become apparent from the description, or understood by practicing the present invention. The purpose and other advantages of the present invention are realized and obtained by the structures particularly pointed out in the description, claims and drawings.

[0011] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, preferred embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 A schematic diagram of an embodiment of a method for testing a CPU card chip in an embodiment of the present invention; Figure 2 A schematic diagram of an embodiment of a test device for a CPU card chip in an embodiment of the present invention; Figure 3 The figure is a schematic diagram of an embodiment of a testing device for a CPU card chip in an embodiment of the present invention. DETAILED DESCRIPTION

[0013] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0014] The terms "including" and "having" and any variations thereof mentioned in the embodiments of the present invention are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device end including a series of steps or units is not limited to the listed steps or units, but may optionally include other steps or units that are not listed, or may optionally include other steps or units that are inherent to these processes, methods, products or device ends.

[0015] To facilitate understanding of this embodiment, a method for testing a CPU card chip disclosed in an embodiment of the present invention is first described in detail. Figure 1 As shown, the method comprises the following steps: 101. Collect data on the CPU card chip to obtain an initial test data matrix including an electrical parameter vector and a functional parameter vector; It is understandable that the execution subject of the present invention may be a test device for a CPU card chip, or a terminal or a server, which is not limited here. The embodiment of the present invention is described by taking a server as the execution subject as an example.

[0016] Specifically, an electrical characteristic test channel including a voltage test unit, a current test unit and an impedance test unit is constructed. The voltage test unit collects the operating voltage, reference voltage and voltage data of the input / output port of the CPU card chip. The current test unit is used to monitor the operating current, standby current and peak current of the CPU card chip, and the power consumption and efficiency of the chip under different load conditions are evaluated through these data. The impedance test unit collects the impedance data of the input and output ports of the CPU card chip. At the same time, in order to evaluate the functional performance of the CPU card chip, the functional test channel includes a logic test unit, a timing test unit and a communication test unit. The logic test unit is used to collect the logic gate circuit response data and state transition data of the CPU card chip. By testing the response time and logic accuracy of the logic gate circuit, the processing capacity and stability of the chip when performing different operations are evaluated. The timing test unit specifically tests the timing characteristics of the CPU card chip such as the clock frequency, response time and delay time. The communication test unit is used to collect the data transmission rate, signal integrity and communication protocol consistency data of the CPU card chip. Through these data, it is analyzed whether the chip has problems such as packet loss, delay or protocol mismatch during data transmission, so as to evaluate the communication performance of the chip in actual use. In terms of hardware architecture, the electrical characteristics test channel and the functional test channel are connected through precise hardware interfaces and data acquisition cards. These interfaces ensure that data can be transmitted from the test unit to the data acquisition system stably and at high speed. The test system adopts a synchronous trigger mechanism to ensure that the acquisition of electrical parameter vectors and functional parameter vectors is synchronized in time so as to accurately associate the electrical and functional data in each test cycle. When testing, the CPU card chip interacts with the test system through a preset test sequence, which includes different excitation signals, such as voltage fluctuations, current pulses, and various timing changes. These excitation signals simulate different load conditions in actual applications and reflect the performance of the chip under various working conditions. The system measures the chip based on these excitation signals and records the changes in electrical parameters and functional parameters in real time. By recording these data as electrical parameter vectors and functional parameter vectors respectively, an initial test data matrix is ​​formed.

[0017] 102. Construct a test parameter association diagram of the initial test data matrix and predict missing data to obtain a complete test data matrix; Specifically, the initial test data matrix is ​​standardized to eliminate the dimensional differences between different test parameters and make each parameter comparable. During the standardization process, the values ​​of all electrical parameter vectors and functional parameter vectors are adjusted to the same scale range to ensure that the relationship between the parameters will not be affected by different units or value ranges during subsequent analysis, and a standardized test data matrix is ​​obtained. The Pearson correlation coefficient is calculated for the parameters in the standardized test data matrix to obtain the quantitative results of the correlation strength between the parameters. Based on the quantitative results of the correlation strength between the parameters, a test parameter association graph is constructed, which consists of a set of nodes and edges connecting these nodes, where each node represents a test parameter, and the weight of the edge represents the correlation strength between the parameters. According to the test parameter association graph, a membership function in the form of a normal distribution is established for each test parameter in the standardized test data matrix to predict missing data. Fuzzy set representation is a description method based on membership function, which gives each parameter a possibility distribution under different states. The membership function in the form of a normal distribution is used to describe the fuzzy set representation of the test parameter. The fuzzy set representation of each parameter is used to characterize the possibility of the parameter in different numerical ranges, thereby providing richer information when predicting missing data. Fuzzy set representation can combine the distribution characteristics of historical test data to ensure that the prediction results are as close to the true value as possible. Based on the fuzzy set representation of parameters, weighted fuzzy reasoning is performed on the missing parameter values ​​in the initial test data matrix to obtain the predicted value of the missing data. Missing data prediction adopts the weighted fuzzy reasoning method. By analyzing the relationship between known data and missing data in the test parameter association diagram, combined with the fuzzy set representation of parameters, the most likely missing data value is calculated. In this process, each missing parameter is inferred using parameters with a high correlation with it. The higher the correlation, the greater the impact of the parameter on the missing data. When calculating the predicted value of missing data, all test parameters related to the parameter are comprehensively considered, and reasoning is performed according to their fuzzy rules to obtain a predicted value that best meets the characteristics of the test data. The existing data in the standardized test data matrix is ​​merged with the predicted value of the missing data to form a complete test data matrix.

[0018] 103. Perform principal component analysis on the complete test data matrix to obtain a valid test data set; Specifically, the covariance matrix is ​​calculated based on the complete test data matrix to quantify the statistical relationship between each test parameter, reflect the degree of correlation between different test parameters, and thus reveal the main direction of data change. The characteristic equation is solved for the covariance matrix to obtain the principal component direction of the test data. The determination of the principal component direction depends on the eigenvalues ​​and eigenvectors of the covariance matrix, where the size of the eigenvalue reflects the importance of the direction represented by the corresponding eigenvector in the data. By calculating and sorting these eigenvalues, the distribution characteristics of the test data in different directions are determined, and the principal component direction that best represents the data structure is extracted. The cumulative variance contribution rate is calculated based on the principal component direction to determine how many principal components should be selected to construct the main feature space. The cumulative variance contribution rate is used to measure the amount of data variance information that can be explained by the first few principal components. In order to ensure that the main information of the data is not lost, a preset threshold is set, and the first k principal components that meet the cumulative variance contribution rate greater than or equal to the threshold are selected as the main feature directions of the test data. After the principal component is selected, the main feature space is constructed so that all test data are mapped to this new space in order to analyze the validity of the sample and the quality of the data. For each test sample in the complete test data matrix, the similarity with the i-th principal component in the main feature space is calculated to measure the adaptability of each test sample in the new feature space, that is, whether the sample is consistent with the main feature direction, and the overall similarity is calculated to obtain the feature space similarity of the test sample. The data support of each test sample is calculated based on the feature space similarity of the test sample to quantify the credibility and validity of each test sample. The calculation method of data support comprehensively considers the matching degree between the test sample and the main feature space, and combines the contribution of the test data in different feature directions to ensure that the screened data can exist stably in the main feature space. The test samples are screened according to the data support threshold to obtain preliminary valid test data. Outlier detection is performed on the preliminary valid test data to eliminate abnormal samples. In the outlier detection process, the projection distance and Mahalanobis distance of each test sample are calculated to quantify its deviation in the main feature space. The calculation of projection distance is used to judge the projection deviation of the sample in the main feature space, that is, whether the test sample strictly falls in the main feature direction, while the calculation of Mahalanobis distance is used to measure the deviation of the sample from the center of the entire data distribution to ensure that the data conforms to the overall statistical distribution characteristics. Through the comprehensive analysis of these two distances, samples that are significantly different from the overall data distribution are identified and marked as outliers. All test samples that are judged as outliers are eliminated to form a valid test data set.

[0019] 104. Construct a multi-level fuzzy set based on the valid test data set, and calculate the cosine similarity with the calibration reference model to obtain fused test data; Specifically, multiple first-state fuzzy sets based on the trapezoidal membership function are constructed according to the electrical characteristic test parameters in the effective test data set. The specific parameters of the trapezoidal membership function are determined in combination with the distribution characteristics of the historical test data to ensure that it can accurately describe the different state ranges of the electrical characteristic test parameters. The construction of the trapezoidal membership function is to establish the attribution relationship of the electrical characteristic parameters under different states, and to describe the change trend of different electrical parameters by setting different state ranges. After mapping each electrical characteristic test parameter to these state fuzzy sets, the first fuzzy representation of the parameter is obtained, so that it has better interpretability and flexibility under the framework of fuzzy mathematics. At the same time, for the functional test parameters, multiple second-state fuzzy sets based on the Gaussian membership function are constructed to reflect the fuzzy representation of the functional test parameters. The Gaussian membership function determines the center value and width parameters based on the distribution characteristics of the historical test data, forming a continuous and smooth membership distribution, so that the transition of the functional parameters under different states is more natural. In this way, the functional test parameters are classified, and each functional test parameter is mapped to multiple Gaussian fuzzy sets to obtain the second fuzzy representation of the parameter. Based on expert knowledge and historical calibration data, a calibration reference model of real test data is constructed. This model is used as a benchmark to evaluate the degree of match between the current test data and the ideal data. The construction of the calibration reference model combines high-quality test samples in historical data and is fine-tuned in combination with expert experience to ensure that it is sufficiently representative. By calculating the cosine similarity between the first fuzzy representation and the calibration reference model, the closeness of the electrical characteristic test parameters to the benchmark data is obtained, while by calculating the cosine similarity between the second fuzzy representation and the calibration reference model, the closeness of the functional test parameters is obtained. The goal of this process is to measure the similarity between the current test data and the ideal data, ensuring that high-quality data is given a higher weight during the fusion process to enhance the accuracy and stability of the final fused data. According to the closeness of the dual-channel data to the calibration reference model, the target fusion weights of the electrical characteristic test parameters in the effective test data set and the functional test parameters in the effective test data set are calculated. The calculation of the fusion weight is adjusted according to the closeness of the dual-channel data to the calibration reference model, so that the test data with higher quality occupies a larger proportion in the final fusion process. If the electrical characteristic test parameters are close, the corresponding fusion weight will be increased to ensure that the data of this channel dominates the final fusion result; on the contrary, if the functional test parameters are close, the corresponding fusion weight will be increased. In order to improve the adaptability of the fusion model, adaptive adjustments are made based on the quality indicators such as the signal-to-noise ratio and data integrity of the test data to obtain the optimal fusion weight allocation scheme. The electrical characteristic test parameters in the effective test data set and the functional test parameters in the effective test data set are weighted and combined according to the target fusion weight to obtain the fused test data.

[0020] 105. The fused test data is input into the variational autoencoder for self-supervised pre-training, and the diffusion state space model is used to perform conditional interpolation to obtain the defect detection results and uncertainty estimates.

[0021] Specifically, the fused test data is input into a variational autoencoder containing an encoder and a decoder for self-supervised pre-training. The fused test data is mapped to a latent space, which is a low-dimensional representation space that can capture the high-dimensional features of the data. By adding controlled noise to the latent space, the variational autoencoder can generate new samples that expand the original dataset to form an enhanced dataset. The role of the enhanced dataset is to improve the robustness and generalization ability of the model by artificially increasing the diversity of the data, ensuring that the model can better handle various test data encountered in the future. The enhanced dataset is input into a self-supervised model based on the Transformer architecture for training. Self-supervised learning reconstructs masked features through contextual information. At this stage, the model randomly masks some features in the enhanced dataset and predicts the masked feature values ​​through the information of the rest. In this way, the model can learn the deep structure inside the data and extract a common feature representation. Through training, the model can automatically identify and extract key features related to defects in chip performance. A diffusion state space model is constructed based on the pre-trained feature encoder to improve the accuracy and integrity of the data. The key to the diffusion state space model is to gradually convert data into noise through a random diffusion process, which can effectively simulate the uncertainty and noise factors in the data. Simple noise generation is not enough to effectively restore the original data, so the model gradually reconstructs the data through the reverse diffusion process. This process uses the features extracted by the encoder as conditions to guide the reconstruction process, thereby ensuring that the generated data not only has high-quality structural features but also retains the key information in the original data. The conditional data interpolation model is obtained to process test samples containing missing values. This model accurately fills in the missing data and obtains a complete test feature representation. The enhanced data set and the complete test feature representation are fine-tuned in a balanced manner. A combination of cross entropy loss and focal loss is used to train the defect detection classifier. Cross entropy loss is used to deal with conventional classification problems, while focal loss enhances the model's attention to samples that are difficult to classify, especially in the case of unbalanced data. Focal loss helps improve the model's ability to identify rare defects. Through this fine-tuning process, the model can be trained on more diverse test data, gradually improve its detection accuracy, and form a classifier that can efficiently identify CPU card chip defects. After the training of the defect detection classifier is completed, the uncertainty estimate is calculated based on the test results. The uncertainty estimate reflects the degree of confidence the model has in the prediction results. When the confidence level of the test results is low, the uncertainty estimate of the model is high, which means that there is a large uncertainty in the classification result of the model for the sample, and further verification or manual intervention is required. When the confidence level is high, the uncertainty estimate is low, and the model is more reliable in identifying defects.Through uncertainty estimation, the test system can dynamically adjust its processing strategy and, for samples with high uncertainty, perform manual inspection or use other supplementary models to assist in decision-making, thereby ensuring the accuracy and reliability of defect detection results.

[0022] For the test samples whose uncertainty estimation value exceeds the second preset threshold, the representation in the deep feature space is extracted, and the Mahalanobis distance with the center of each known defect category is calculated to measure the statistical difference between the sample and different defect categories, so as to effectively distinguish known defects from unknown defects. For each sample, if its minimum Mahalanobis distance with the center of the known defect category exceeds the third preset threshold, the test sample is determined to be an unknown defect type. In this way, all samples identified as unknown defects are collected into an unknown defect sample set, and these samples will be further processed as candidates for new defect types. The Euclidean distance between samples is calculated based on the unknown defect sample set to reflect the similarity of the samples in the feature space. By calculating the Euclidean distance, the density of each sample in its local area and the relationship between the sample and its nearest neighbor sample are evaluated. According to the product of the local density of each sample and its minimum distance value, the clustering decision index is calculated, and the test samples whose clustering decision index exceeds the fourth preset threshold are selected as cluster centers. These cluster centers represent the core samples of the new defect type, which have higher feature concentration and lower noise influence. Other test samples are assigned to the nearest cluster center according to the Euclidean distance to complete the clustering of samples. Through this process, new defect types are automatically identified. Based on the new defect types automatically clustered, an independent sample library is built for each cluster. When building the sample library, data feature normalization and data expansion are performed to ensure the balance and sufficiency of the samples. Data expansion is achieved by adding noise, data transformation, etc., so that the number of samples for each defect category is more balanced. Each sample also needs to add a unique identifier and category label to make the data in the sample library more traceable and effectively support subsequent model training and defect analysis. Through this process, a standardized sample library is formed. For each defect category in the standardized sample library, a dual attention network structure containing a channel attention module and a spatial attention module is constructed to enhance the model's ability to extract specific defect features and improve its recognition accuracy of defect types. The channel attention module can automatically adjust the weights of different channels to improve the expression of important features, while the spatial attention module improves attention to local information by focusing on features at different spatial locations. Through the dual attention mechanism, the model can understand the data at a more fine-grained level, thereby improving the accuracy of defect classification. During the training process, the class-balanced focal loss is used to deal with the sample imbalance problem. The focal loss helps the model pay more attention to the defect categories that are difficult to classify by amplifying the loss of difficult-to-classify samples. And through comparative learning, the model's ability to distinguish between different defect categories is enhanced, further improving the accuracy and robustness of the defect analysis model. For the constructed defect analysis expert model, the knowledge distillation mechanism is implemented to optimize the model performance.The knowledge distillation mechanism trains the student model (i.e., the model that needs to be optimized) by taking the soft label distribution of the teacher model (i.e., a mature model with high accuracy) as the target. The difference between the teacher model and the student model is measured by calculating the KL divergence of the outputs, and the student model is enabled to better learn the knowledge of the teacher model by minimizing this divergence. Decoupled representations are constructed at the feature level so that different expert models can share knowledge while maintaining independence, ensuring that the model can continue to learn and improve the accuracy and stability of its defect detection. Through the decoupled federated learning mechanism, multiple independent expert models are combined into a model-decoupled federated expert model set.

[0023] In the embodiment of the present invention, the integrity and reliability of the test data are significantly improved through the dual-channel synchronous test system, and the missing data prediction method constructed based on fuzzy mathematics theory can accurately quantify the correlation between test parameters and effectively fill in the missing information in the test data set; the combination of principal component analysis technology and outlier detection mechanism effectively screens out real and reliable test data, and improves the quality and credibility of the test data; the multi-level fuzzy set and adaptive weight adjustment mechanism realize the optimal fusion of electrical characteristics and functional test data, and make full use of the complementary advantages of dual-channel data to provide more comprehensive and accurate test results; the CCTT multi-step training framework effectively solves the problems of test data imbalance and missingness through data enhancement, self-supervised pre-training and conditional interpolation, and improves the performance of the defect detection model; the combination of the open set recognition method and the decoupled federal expert model system realizes the automatic discovery and continuous learning recognition of unknown defect types, and overcomes the catastrophic forgetting problem of the traditional model during the updating process, so that the CPU card chip test system can continuously adapt to new defects appearing in the production environment and maintain a high test accuracy and reliability.

[0024] In a specific embodiment, the process of executing step 101 may specifically include the following steps: Construct an electrical characteristic test channel including a voltage test unit, a current test unit and an impedance test unit, wherein the voltage test unit collects the working voltage, the reference voltage and the input / output port voltage, the current test unit collects the working current, the standby current and the peak current, and the impedance test unit collects the input impedance and the output impedance; Construct a functional test channel including a logic test unit, a timing test unit and a communication test unit, wherein the logic test unit collects logic gate circuit response and state transition data, the timing test unit collects clock frequency, response time and delay time, and the communication test unit collects data transmission rate, signal integrity and communication protocol consistency data; The CPU card chip is connected to the electrical characteristic test channel and the functional test channel, a test excitation signal is applied to the CPU card chip according to a preset test sequence, and the electrical parameter vector and the functional parameter vector are recorded synchronously to obtain an initial test data matrix.

[0025] Specifically, an electrical characteristic test channel including a voltage test unit, a current test unit and an impedance test unit is constructed to measure the voltage, current and impedance of the CPU card chip under different conditions, thereby providing electrical characteristic data. The voltage test unit collects the working voltage, the reference voltage and the voltage of the input / output port, wherein the working voltage is used to characterize the power supply stability of the chip under normal working conditions, the reference voltage is the voltage reference for the internal circuit, and the input / output port voltage can reflect the signal level of the chip when communicating with an external device. The current test unit is responsible for collecting the working current, the standby current and the peak current. The peak current can characterize the instantaneous power consumption of the chip under high load conditions, while the standby current reflects the energy consumption level of the chip in low power consumption mode. The impedance test unit is used to measure the input impedance and output impedance. These parameters are related to the signal integrity of the chip, and can reflect the matching of the input and output ends, as well as the stability of the chip under different load conditions. At the same time, in order to ensure that the functional characteristics of the CPU card chip meet the design requirements, a functional test channel is constructed, which includes a logic test unit, a timing test unit and a communication test unit. The logic test unit is used to collect the response and state transition data of the logic gate circuit. Its core goal is to verify whether the logic circuit inside the chip operates as expected. For example, when executing a certain operation task, the logic test unit will analyze whether the input and output of the chip conform to the logic rules to ensure the correctness of the calculation result. The timing test unit focuses on the timing characteristics of the chip, including parameters such as clock frequency, response time and delay time. The clock frequency determines the working rate of the chip, while the response time and delay time affect the speed performance of the chip when processing tasks. The communication test unit is used to measure the data transmission rate, signal integrity and consistency of the communication protocol of the CPU card chip to ensure that the chip can operate stably when interacting with other devices. Connect the CPU card chip to the electrical characteristics test channel and the functional test channel, and apply the test excitation signal to the chip according to the preset test sequence to simulate the working state of the chip in actual application, so as to collect more realistic test data. The design of the test sequence needs to cover multiple working modes, such as normal working mode, low power mode, high load mode, etc., so as to comprehensively evaluate the performance of the chip under different working conditions. For example, when testing the working current, different workloads are applied at different supply voltages and the instantaneous current changes of the chip are measured, while when testing the clock frequency, different clock signals are applied and the synchronization error of the chip is analyzed. In order to ensure the synchronization of electrical parameters and functional parameters, the test system uses a high-precision data acquisition module and synchronously records the electrical parameter vector and the functional parameter vector when the test signal is triggered to obtain the initial test data matrix.

[0026] In a specific embodiment, the process of executing step 102 may specifically include the following steps: Performing standardization processing on the electrical parameter vector and the functional parameter vector in the initial test data matrix respectively to obtain a standardized test data matrix; Calculate the Pearson correlation coefficient for the parameters in the standardized test data matrix to obtain the quantitative results of the correlation strength between the parameters, and construct a test parameter correlation diagram based on the quantitative results of the correlation strength between the parameters; According to the test parameter association diagram, a membership function in the form of normal distribution is established for each test parameter in the standardized test data matrix to obtain a fuzzy set representation of the parameter; Based on the fuzzy set representation of parameters, weighted fuzzy reasoning is performed on the missing parameter values ​​in the initial test data matrix to obtain the predicted values ​​of the missing data, and the existing data in the standardized test data matrix are merged with the predicted values ​​of the missing data to obtain the complete test data matrix.

[0027] Specifically, the electrical parameter vector and the functional parameter vector are standardized to ensure that the test parameters of different dimensions are analyzed on a unified scale. and function parameters , using the mean-standard deviation normalization method, it is standardized as follows: in, and Respectively represent electrical parameters The mean and standard deviation of and Respectively represent the function parameters The mean and standard deviation of the test parameters are calculated. With this transformation, all test parameters have a mean of zero and the same variance, allowing for direct correlation analysis between parameters without imbalanced weights due to different numerical ranges. The Pearson correlation coefficient is calculated between each parameter in the standardized test data matrix to quantify the strength of association between the test parameters. The Pearson correlation coefficient is calculated as follows: in, Represents standardized parameters and parameters The Pearson correlation coefficient between and The test samples are In the parameters and parameters Normalized values ​​on the dimension, and The parameters are and parameters is the mean value over the entire test data set, and Represents the total number of test samples. The value of the Pearson correlation coefficient is between -1 and 1, where values ​​close to 1 indicate a strong positive correlation between the two parameters, values ​​close to -1 indicate a strong negative correlation, and values ​​close to 0 indicate almost no linear relationship between the two. By calculating the correlation coefficient matrix, the quantitative results of the association strength between all test parameters are obtained, thereby constructing a test parameter association graph, in which the nodes represent the test parameters and the edge weights are determined by the Pearson correlation coefficient. According to the test parameter association graph, a membership function in the form of a normal distribution is established for each test parameter in the standardized test data matrix to obtain a fuzzy set representation of the parameter. For a certain test parameter , use Gaussian distribution function to define its membership function: in, Represents test parameters In the parameters The fuzzy membership of is the mean center of the normal distribution, indicating the most typical value of the parameter, is the width parameter, which determines the distribution range of the data. Through this membership function, each test parameter is mapped to a fuzzy set, which has the ability to describe uncertainty. The parameter-based fuzzy set representation performs weighted fuzzy reasoning on the missing parameters in the initial test data matrix to predict the value of the missing data. The weight between each missing parameter and the known parameter is calculated. : in, Represents known parameters For missing parameters The contribution weight of is the set of all known parameters, is a parameter With parameters Pearson correlation coefficient between . Use these weights to make weighted predictions for missing values: in, Is a missing parameter The predicted value of is a known parameter The corresponding fuzzy membership function. Through this weighted fuzzy reasoning method, the missing data can be completed without losing the relationship between the data, making the test data more complete. The existing data in the standardized test data matrix is ​​combined with the predicted values ​​of the missing data to obtain a complete test data matrix.

[0028] In a specific embodiment, the process of executing step 103 may specifically include the following steps: Calculate the covariance matrix based on the complete test data matrix, and solve the characteristic equation for the covariance matrix to obtain the principal component direction of the test data; Calculate the cumulative variance contribution rate based on the principal component direction, select the first k principal components whose cumulative variance contribution rate is greater than or equal to a first preset threshold, and construct the main feature space; For each test sample in the complete test data matrix, the similarity with the i-th principal component in the main feature space is calculated, and the overall similarity is calculated to obtain the feature space similarity of the test sample; The data support of each test sample is calculated based on the feature space similarity of the test samples, and the test samples are screened according to the data support threshold to obtain preliminary valid test data; The projection distance and Mahalanobis distance are calculated for each test sample in the preliminary valid test data, and outliers are removed to obtain a valid test data set.

[0029] Specifically, the covariance matrix of the complete test data matrix is ​​calculated to measure the statistical correlation between the various test parameters. Assume that the complete test data matrix is ​​expressed as , where each row represents a test sample and each column represents a test parameter, then the covariance matrix The calculation method is as follows: in, is the number of test samples, is the transpose of the test data matrix. The covariance matrix Elements Reflects the test parameters and The correlation between them, a larger value indicates that they have a stronger linear dependence in the sample, while a smaller value indicates that the linear relationship between them is weaker. After obtaining the covariance matrix, solve the characteristic equation to obtain the principal component direction of the test data. The characteristic equation is in the following form: in, are the eigenvalues ​​of the covariance matrix, is the identity matrix. Solve for all eigenvalues And arrange them in descending order, and find the corresponding eigenvectors , these eigenvectors are the principal component directions of the data. The size of the eigenvalue determines the contribution of the principal component to the data variance, so the principal component direction can characterize the main change pattern of the test data. In order to screen out the most important principal components, the cumulative variance contribution rate is calculated to determine how many principal components to select to construct the main feature space. The calculation of the cumulative variance contribution rate is as follows: in, Before The variance contribution of the principal components is It is eigenvalues, is the total number of all principal components. Select the value that satisfies the cumulative variance contribution rate greater than or equal to the first preset threshold Before principal components, namely: Thus, a main feature space is constructed, which is composed of the previous eigenvectors, denoted as a matrix : For each test sample in the complete test data matrix, calculate its projection in the principal feature space and evaluate its similarity with each principal component. The standardized representation of , then it is the same as principal components The similarity is defined as follows: in, Representative samples With principal component The cosine similarity between and Represents the Euclidean norm of the sample and the principal component respectively. Calculate the test sample The overall similarity with the main feature space: in, is the weight of the principal component, which is determined by the eigenvalue After normalization, we get: Through this step, the fitness of the test sample in the main feature space is determined, and whether it is consistent with the main data pattern is evaluated. Based on the feature space similarity of the test samples, the data support of each sample is calculated to further screen the effective test data. Data support The calculation of is as follows: in, Represents the test sample The measurement error is measured by experiment. Above a certain threshold When , the test sample is determined to be preliminary valid test data, otherwise it is eliminated. After obtaining preliminary valid test data, outlier detection is performed to ensure that there are no abnormal samples in the data set. Calculate the projection distance of each test sample: in, It represents the projection error of the test sample on the main feature space. A larger projection distance means that the distribution of the sample deviates greatly from the overall data pattern. Secondly, the Mahalanobis distance of each test sample is calculated: in, is the mean vector of the data, is the inverse matrix of the covariance matrix. The Mahalanobis distance is used to evaluate the degree of deviation of the sample from the center of the data. If the sample exceeds a certain set threshold, it will be judged as an outlier and removed, thus obtaining a high-quality and effective test data set.

[0030] In a specific embodiment, the process of executing step 104 may specifically include the following steps: Constructing a plurality of first-state fuzzy sets based on a trapezoidal membership function according to the electrical characteristic test parameters in the effective test data set, determining the parameters of the trapezoidal membership function according to the distribution characteristics of the historical test data, and mapping each electrical characteristic test parameter to the plurality of first-state fuzzy sets to obtain a first fuzzy representation; Constructing multiple second-state fuzzy sets based on Gaussian membership function according to the functional test parameters in the effective test data set, determining the center and width parameters of the Gaussian membership function according to the distribution characteristics of the historical test data, mapping each functional test parameter to the multiple second-state fuzzy sets, and obtaining a second fuzzy representation; Based on expert knowledge and historical calibration data, a calibration reference model of real test data is constructed, and the cosine similarity between the first fuzzy representation and the calibration reference model is calculated, and the cosine similarity between the second fuzzy representation and the calibration reference model is calculated to obtain the closeness between the dual-channel data and the calibration reference model; According to the closeness between the dual-channel data and the calibration reference model, the target fusion weights of the electrical characteristic test parameters in the effective test data set and the functional test parameters in the effective test data set are calculated; The electrical characteristic test parameters in the effective test data set and the functional test parameters in the effective test data set are weighted and combined according to the target fusion weight to obtain fused test data.

[0031] Specifically, a fuzzy representation based on a trapezoidal membership function is established for the electrical characteristic test parameters. The electrical characteristic parameters include operating voltage, reference voltage, input / output port voltage, operating current, standby current, peak current, input impedance and output impedance. These parameters have certain fluctuations in different chip test samples, so fuzzy sets are used to describe their state range. For each electrical characteristic test parameter By analyzing the distribution characteristics of historical test data, the four key parameters of the trapezoidal membership function are determined, namely the lower limit , go down the stairs , Go up the stairs and upper limit , the trapezoidal membership function is defined as follows: in, Represents electrical characteristics test parameters The fuzzy membership of In arrive When it is between , its membership is 1, indicating that it fully conforms to the fuzzy set, and arrive Between or arrive The membership changes gradually between them, reflecting the fuzziness of the test data. By constructing multiple trapezoidal membership functions, multiple first-state fuzzy sets are established for each electrical characteristic parameter, and the test parameters are mapped to these fuzzy sets by calculating the membership values ​​to obtain the first fuzzy representation. At the same time, for functional test parameters, such as logic gate circuit response, state transition data, clock frequency, response time, delay time, data transmission rate, signal integrity and communication protocol consistency, Gaussian membership function is used to describe its fuzzy state. Gaussian function can describe the distribution of parameters more smoothly and is suitable for modeling continuously changing functional characteristics. Suppose the functional test parameters The Gaussian membership function of is defined as follows: in, Indicates functional test parameters In the The membership degree in a Gaussian fuzzy set is is the center of the fuzzy set, i.e., the typical value of the function parameter. is the width parameter, which determines the tolerance of the fuzzy set to different values. and , each functional test parameter is mapped to multiple second-state fuzzy sets to obtain a second fuzzy representation. After obtaining the first fuzzy representation and the second fuzzy representation, a calibration reference model of real test data is constructed based on expert knowledge and historical calibration data. The model consists of test data under ideal conditions and is used to measure the similarity between current test data and standard data. In order to calculate the similarity between the fuzzy representation of electrical characteristic test parameters and the calibration reference model, cosine similarity is used for calculation: in, Indicates the similarity between the electrical characteristics test data and the calibration reference model, is the fuzzy representation of the current test data, is the corresponding membership value in the calibration reference model. Similarly, the similarity of the functional test parameters is calculated as follows: in, Represents the similarity between the functional test data and the calibration reference model, is a fuzzy representation of the current function parameters, is the corresponding membership value in the calibration reference model. These two similarities measure the degree of match between the test data and the standard data. Based on the similarity of the electrical characteristics and functional test data, the target fusion weight of the effective test data set is calculated. The calculation of the fusion weight is based on the closeness of the test data to the calibration model and is defined as follows: in, and are the target fusion weights of the electrical characteristics test parameters and the functional test parameters, respectively. This weight distribution mechanism ensures that when the final data is fused, the contribution of the test data is determined by the degree of matching with the calibration reference model, thereby enhancing the rationality and reliability of data fusion. According to the calculated fusion weights, the electrical characteristics test parameters and functional test parameters in the effective test data set are weighted and combined to form the final fused test data: ; in, is the fused test data, It is the standardized electrical characteristics test data. It is the standardized functional test data.

[0032] Among them, after constructing a multi-level fuzzy set of trapezoidal membership function and Gaussian membership function for the test parameters in the effective test data set, calculating and calibrating the cosine similarity of the reference model, and introducing an adaptive weight adjustment mechanism, after obtaining the fusion test data and before inputting the fusion test data into the CCTT multi-step training framework, it also includes the step of conducting a security performance test on the CPU card chip. The security performance test includes: applying an electromagnetic interference pulse signal to the CPU card chip, monitoring the chip working status and data integrity under interference conditions of different intensities, frequencies and positions, recording the chip crash threshold and data error rate, generating an electromagnetic anti-interference performance index matrix, and obtaining the anti-interference characteristic data of the CPU card chip; inputting the standard cryptographic algorithm test vector into the cryptographic processing unit of the CPU card chip, performing cryptographic operations including symmetric encryption, asymmetric encryption and hash algorithm, comparing the operation results with the expected output of the standard test vector, analyzing the operation time and power consumption fluctuations, and obtaining the correctness and performance data of the cryptographic algorithm implementation; triggering the random number generator of the CPU card chip to continuously generate a random number sequence of a fixed length, and applying NIST to the generated random number sequence SP800-22 randomness test suite, calculates entropy value, autocorrelation coefficient and statistical distribution characteristics, evaluates random number quality and prediction difficulty, and obtains random number generation quality evaluation results; implements boundary condition testing on the instruction system of the CPU card chip, including constructing illegal instruction sequences, parameter out-of-bounds operations and timing attack sequences, monitoring the response mode and recovery capability of the chip exception handling mechanism, recording security protection trigger conditions and exception handling time, and obtaining instruction execution security data under boundary conditions; uses high-precision probes to collect electromagnetic signals from the CPU card chip when performing key cryptographic operations, applies differential electromagnetic analysis technology to process the collected signals, calculates the amount of information leakage and the difficulty coefficient of key information extraction, evaluates the chip's ability to resist electromagnetic side channel attacks, and obtains electromagnetic leakage analysis results; implements power supply fluctuation attacks and clock interference on the CPU card chip Interference attack, monitor the triggering of the chip's protection mechanism under different voltage, temperature and clock frequency conditions, record the success rate of fault injection and the protection effect of sensitive data, analyze the response characteristics of the security monitoring circuit, and obtain the side channel attack protection evaluation data; according to the security protocol specifications of application fields such as financial payment, mobile communication and identity recognition, verify the protocol implementation consistency of the CPU card chip, test the protocol functions including handshake process, key negotiation, session management and secure communication, record the protocol interaction timing and resource occupancy, and obtain the security protocol consistency test results; simulate abnormal situations such as power failure, communication interruption and physical tampering, trigger the abnormal response mechanism of the CPU card chip, evaluate the automatic protection effect and security status recovery capability of sensitive data, analyze the integrity and traceability of the abnormal record log, and obtain the abnormal response processing evaluation data;Based on anti-interference characteristic data, cryptographic algorithm implementation correctness and performance data, random number generation quality assessment results, instruction execution security data under boundary conditions, electromagnetic leakage analysis results, side channel attack protection assessment data, security protocol consistency test results and abnormal response processing assessment data, a CPU card chip security performance scoring model is constructed, the comprehensive security level score is calculated and a detailed security feature report is generated to obtain the security performance test results of the CPU card chip; the security performance test results are combined with the fusion test data, security-related features are extracted and fused into the test feature vector, and enhanced fusion test data is constructed for subsequent defect detection analysis. ;

[0033] In a specific embodiment, the process of executing step 105 may specifically include the following steps: Input the fused test data into a variational autoencoder including an encoder and a decoder, map the fused test data to a latent space, and generate new samples by adding controlled noise to the latent space to obtain an enhanced dataset; The augmented dataset is input into a self-supervised model based on the Transformer architecture, the masked features are reconstructed through contextual information, and the common feature representation is extracted to obtain a pre-trained feature encoder. A diffusion state space model is constructed based on the pre-trained feature encoder. The augmented data set is gradually converted into noise through a random diffusion process. The data is then reconstructed through an inverse diffusion process. The features extracted by the encoder are used as conditions to guide the reconstruction process, thus obtaining a conditional data interpolation model. Apply the conditional data interpolation model to the test samples with missing values, complete the data based on the existing features and the feature representation extracted by the encoder, and perform consistency verification on the interpolation results to obtain a complete test feature representation; Balanced fine-tuning is performed on the enhanced dataset and the complete test feature representation, and a defect detection classifier is trained using a combination of cross entropy loss and focal loss to obtain the defect detection results of the CPU card chip, and the uncertainty estimation value is calculated based on the defect detection results.

[0034] Specifically, the fused test data is input into a variational autoencoder containing an encoder and a decoder to learn the latent structure of the data and generate an enhanced dataset. The core goal of the variational autoencoder is to map the input data into a continuous low-dimensional latent space, so as to generate data and extract features in this space. Given the input data , which the encoder transforms into the mean and variance parameters of the latent variable: in, and They are respectively the neural network mapping function of the encoder, is the mean of the latent variable, is the variance. In the latent space, these parameters are resampled to generate new latent variables: in, is the final potential representation, is a noise term sampled from a standard normal distribution. By adding controlled noise to the latent space, new data samples are generated, making the augmented dataset more generalizable and robust. The decoder converts the latent variable Map back to the data space to generate new test samples , thus constructing a diverse augmented dataset. The augmented dataset is input into a self-supervised model based on the Transformer architecture to reconstruct the masked features through contextual information and extract common feature representations to obtain a pre-trained feature encoder. In this process, the input data is masked, and some features in the data matrix are randomly selected and set to missing values ​​to train the model to learn how to recover the original data from the contextual information. The self-supervised learning objective is used to optimize the mask reconstruction loss: in, is the set of masked feature indices, It is real data. is the feature value predicted by the Transformer model. By minimizing this loss function, a universal feature encoder is trained, which can extract the deep features of high-dimensional data and form a low-dimensional representation of the data. After obtaining the pre-trained feature encoder, a diffusion state space model is constructed based on the encoder to interpolate the data. The key to the diffusion state space model is to simulate the transformation process of data from a structured state to a completely noisy state and reconstruct the data in the reverse diffusion process. Indicates that at time step The data state of the forward diffusion process is defined as follows: in, is the preset noise coefficient, which controls the rate at which data is converted to Gaussian noise. Through this process, the data gradually evolves to uniformly distributed noise. The inverse diffusion process is used to recover the data, using conditional generation, that is, using the feature representation extracted by the feature encoder As conditions guide the refactoring process: in, is an inverse diffusion network, which is used to convert the completely noisy state Restore to structured data state . This model is used as a conditional data interpolation model to fill in missing values ​​in the test data and ensure the consistency of the interpolated data with the existing data. After completing the conditional data interpolation, the interpolation model is applied to the test samples with missing values. For each test sample, the data is completed using its existing feature information and the feature representation extracted by the feature encoder, and then consistency verification is performed to ensure that the completed data is reasonable in the entire data distribution. By calculating the cosine similarity between the interpolated data and the real data: like If the threshold is exceeded, the interpolated data is considered valid, otherwise recalculation or manual intervention is required. The augmented dataset and the complete test feature representation are fine-tuned to train the defect detection classifier. During the training of the classifier, a combination of cross entropy loss and focal loss is used to optimize the performance of the model on imbalanced data. Cross entropy loss is used to optimize the overall classification performance, while focal loss improves the recognition ability of the model on minority categories by adjusting the loss weights of difficult-to-classify samples. It is defined as follows: in, Yes Category The predicted probability of is the true category label, is the focus parameter, which is used to adjust the weight of difficult-to-classify samples. By optimizing this loss function, a robust defect detection model is trained. After the model training is completed, the uncertainty estimate of the defect detection result is finally calculated. The purpose of uncertainty estimation is to measure the confidence of the model in the classification result, which is estimated by calculating the entropy value of the predicted probability: in, Indicates uncertainty. When the predicted probability distribution is more uniform, the entropy value is higher, indicating that the model has greater uncertainty; when the predicted probability distribution is biased towards a certain category, the entropy value is lower, indicating that the model is more certain. If the uncertainty of a test sample exceeds the set threshold, further manual review or re-examination using a more complex model is required.

[0035] In a specific embodiment, the method for executing the test of the CPU card chip also includes the following steps: For the test samples whose uncertainty estimation value exceeds the second preset threshold, the representation in the deep feature space is extracted, and the Mahalanobis distance with the center of each known defect category is calculated. When the minimum distance value exceeds the third preset threshold, the test sample is determined to be an unknown defect type, and an unknown defect sample set is obtained; Calculate the Euclidean distance between samples according to the unknown defect sample set, and calculate the product of the local density and the minimum distance value for each sample as the clustering decision index, select the test sample whose clustering decision index exceeds the fourth preset threshold as the clustering center, and assign the remaining test samples to the nearest clustering center to obtain a new defect type of automatic clustering; Based on the new defect type automatically clustered, an independent sample library is built for each cluster. The data in the sample library is normalized and expanded, and a unique identifier and category label are added to obtain a standardized sample library. For each defect category in the standardized sample library, a dual attention network structure consisting of a channel attention module and a spatial attention module is constructed. An independent expert model is trained using a category-balanced focal loss, and feature discrimination is enhanced through contrastive learning to obtain a defect analysis expert model. A knowledge distillation mechanism is implemented on the defect analysis expert model to calculate the KL divergence between the soft label distribution of the teacher model and the output of the student model. A decoupled representation is constructed at the feature level to obtain a model-decoupled federated expert model set.

[0036] Specifically, for the test samples whose uncertainty estimation value exceeds the second preset threshold, the representation in the deep feature space is extracted, and their Mahalanobis distances with the centers of each known defect category are calculated to determine whether these samples belong to the known defect category or should be classified as unknown defect types. The representation in the deep feature space is , and the known defect categories The center of , then its Mahalanobis distance is calculated as follows: in, Representative test samples Related to known defect categories The Mahalanobis distance between Yes Category The inverse matrix of the covariance matrix. The minimum Mahalanobis distance Exceeding the third preset threshold , it means that the similarity between the sample and all known defect categories is low, so it is judged as an unknown defect type and added to the unknown defect sample set. The unknown defect sample set is automatically clustered to identify new defect types. The Euclidean distance between all unknown defect samples is calculated to measure their similarity. Assume that the unknown defect sample and The representation in feature space is and , then its Euclidean distance is calculated as follows: in, Representation sample and Based on these distances, the local density of each sample is calculated. and the minimum distance value : in, is the indicator function, when the sample With sample The Euclidean distance between hour, , otherwise 0; local density Reflects the sample The number of nearby samples, and the minimum distance Represents the minimum Euclidean distance between this sample and the sample with higher density. Calculate the clustering decision index: in, Representative test samples The importance of clustering. Select clustering decision indicators Exceeding the fourth preset threshold The sample of is taken as the cluster center, and the rest of the samples are assigned to the nearest cluster center, so as to obtain the new defect type of automatic clustering. After completing the automatic clustering, an independent sample library is built for each cluster based on these new defect types. The data in the sample library is feature normalized to ensure that the feature distribution of all samples is consistent and improve the training effect of the model. Assume that the original feature vector After normalization, we get : in, and are the mean and standard deviation of the features in the sample library, respectively. Perform data augmentation, such as using random noise perturbation or affine transformation, to increase data diversity, and add a unique identifier and category label to each sample to obtain a standardized sample library. After the standardized sample library is constructed, a dual attention network structure containing a channel attention module and a spatial attention module is constructed for each defect category to improve the classification ability of the model. The channel attention module adaptively adjusts the weights of different channels to highlight key features. Its calculation is as follows: in, is the channel attention weight, and is a trainable parameter, is the sigmoid activation function. The spatial attention module is used to focus on the features of different spatial positions, and the calculation method is: in, is the spatial attention weight, and is a trainable parameter. By combining channel attention and spatial attention, the model can capture defect features more accurately and is trained with category-balanced focal loss: in, Yes Category The predicted probability of is the real category, is the focus parameter, which can increase the attention to difficult-to-classify samples. By contrastive learning, the feature distinguishability is enhanced to ensure that the features between different categories are more separated, thereby improving the robustness of the defect analysis expert model. After the training of the defect analysis expert model is completed, the knowledge distillation mechanism is implemented to improve the adaptability and generalization ability of the model. Assume that the soft label distribution of the teacher model is , the output of the student model is , then the KL divergence between the two is calculated as follows: By minimizing the KL divergence, the knowledge of the teacher model is effectively transferred to the student model. In addition, a decoupled representation is constructed at the feature level to reduce the interference between different expert models, and finally a model-decoupled federated expert model set is formed. This federated model can maintain high accuracy in classification tasks of multiple different defect categories, and can continuously adapt to new defect categories, achieving efficient CPU card chip defect detection.

[0037] The above describes the testing method of the CPU card chip in the embodiment of the present invention. The following describes the testing device of the CPU card chip in the embodiment of the present invention. Figure 2 , an embodiment of the testing device of the CPU card chip in the embodiment of the present invention comprises: The data acquisition module 201 is used to collect data from the CPU card chip to obtain an initial test data matrix including an electrical parameter vector and a functional parameter vector; A construction module 202 is used to construct a test parameter association diagram of an initial test data matrix and predict missing data to obtain a complete test data matrix; A principal component analysis module 203 is used to perform principal component analysis on the complete test data matrix to obtain a valid test data set; The calculation module 204 is used to construct a multi-level fuzzy set according to the effective test data set, and calculate the cosine similarity with the calibration reference model to obtain fused test data; The defect detection module 205 is used to input the fused test data into the variational autoencoder for self-supervised pre-training, and use the diffusion state space model to perform conditional interpolation to obtain defect detection results and uncertainty estimates.

[0038] Through the coordinated cooperation of the above-mentioned components, the integrity and reliability of the test data are significantly improved through the dual-channel synchronous test system. The missing data prediction method based on fuzzy mathematics theory can accurately quantify the correlation between test parameters and effectively fill in the missing information in the test data set; the combination of principal component analysis technology and outlier detection mechanism can effectively screen out real and reliable test data, and improve the quality and credibility of test data; multi-level fuzzy sets and adaptive weight adjustment mechanism realize the optimal fusion of electrical characteristics and functional test data, and make full use of the complementary advantages of dual-channel data to provide more comprehensive and accurate test results; CCTT multi-step training framework effectively solves the problems of test data imbalance and missingness through data enhancement, self-supervised pre-training and conditional interpolation, and improves the performance of defect detection model; the combination of open set recognition method and decoupled federated expert model system realizes the automatic discovery and continuous learning recognition of unknown defect types, and overcomes the catastrophic forgetting problem of traditional models during the updating process, so that the CPU card chip test system can continuously adapt to new defects appearing in the production environment and maintain a high test accuracy and reliability.

[0039] above Figure 2 The testing device of the CPU card chip in the embodiment of the present invention is described in detail from the perspective of modular functional entities. The testing device of the CPU card chip in the embodiment of the present invention is described in detail from the perspective of hardware processing.

[0040] Figure 3It is a structural schematic diagram of a CPU card chip test device provided by an embodiment of the present invention. The CPU card chip test device 300 may have relatively large differences due to different configurations or performances, and may include one or more processors (central processing units, CPU) 310 (for example, one or more processors) and a memory 320, and one or more storage media 330 (for example, one or more mass storage device terminals) storing application programs 333 or data 332. Among them, the memory 320 and the storage medium 330 can be short-term storage or permanent storage. The program stored in the storage medium 330 may include one or more modules (not shown in the figure), and each module may include a series of instruction operations in the CPU card chip test device 300. Furthermore, the processor 310 can be configured to communicate with the storage medium 330, and execute a series of instruction operations in the storage medium 330 on the CPU card chip test device 300 to implement the steps of the above-mentioned CPU card chip test method.

[0041] The CPU card chip test device 300 may also include one or more power supplies 340, one or more wired or wireless network interfaces 350, one or more input and output interfaces 360, and / or one or more operating systems 331, such as Windows Serve, Mac OS X, Unix, Linux, FreeBSD, etc. Those skilled in the art will appreciate that Figure 3 The structure of the test device for the CPU card chip shown does not constitute a limitation on the test device for the CPU card chip provided by the present invention, and may include more or fewer components than shown in the figure, or a combination of certain components, or a different arrangement of components.

[0042] The present invention also provides a computer-readable storage medium, which may be a non-volatile computer-readable storage medium or a volatile computer-readable storage medium. Instructions are stored in the computer-readable storage medium. When the instructions are executed on a computer, the computer executes the steps of the CPU card chip testing method.

[0043] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the above-described systems, systems and units can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0044] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention is essentially or the part that contributes to the prior art or the whole or part of the technical solution can be embodied in the form of a software product. The computer software product is stored in a storage medium, including several instructions to enable a computer device (which can be a personal computer, server, or network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), disk or optical disk and other media that can store program code.

[0045] As described above, the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features thereof may be replaced by equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for testing a CPU card chip, characterized in that: The method comprises: Collect data on the CPU card chip to obtain an initial test data matrix including electrical parameter vectors and functional parameter vectors; Constructing a test parameter association diagram of the initial test data matrix and predicting missing data to obtain a complete test data matrix; Performing principal component analysis on the complete test data matrix to obtain a valid test data set; Constructing a multi-level fuzzy set according to the effective test data set, and calculating the cosine similarity with the calibration reference model to obtain fused test data; The fused test data is input into a variational autoencoder for self-supervised pre-training, and a diffusion state space model is used to perform conditional interpolation to obtain defect detection results and uncertainty estimates.

2. The method for testing a CPU card chip according to claim 1, wherein: The CPU card chip is subjected to data collection to obtain an initial test data matrix including an electrical parameter vector and a functional parameter vector, including: Construct an electrical characteristic test channel including a voltage test unit, a current test unit and an impedance test unit, wherein the voltage test unit collects the working voltage, the reference voltage and the input / output port voltage, the current test unit collects the working current, the standby current and the peak current, and the impedance test unit collects the input impedance and the output impedance; Construct a functional test channel including a logic test unit, a timing test unit and a communication test unit, wherein the logic test unit collects logic gate circuit response and state transition data, the timing test unit collects clock frequency, response time and delay time, and the communication test unit collects data transmission rate, signal integrity and communication protocol consistency data; The CPU card chip is connected to the electrical characteristic test channel and the functional test channel, a test excitation signal is applied to the CPU card chip according to a preset test sequence, and the electrical parameter vector and the functional parameter vector are synchronously recorded to obtain an initial test data matrix.

3. The method for testing a CPU card chip according to claim 1, wherein: The step of constructing a test parameter association diagram of the initial test data matrix and predicting missing data to obtain a complete test data matrix includes: Performing standardization processing on the electrical parameter vector and the functional parameter vector in the initial test data matrix respectively to obtain a standardized test data matrix; Calculating the Pearson correlation coefficient for the parameters in the standardized test data matrix to obtain a quantitative result of the correlation strength between the parameters, and constructing a test parameter association diagram based on the quantitative result of the correlation strength between the parameters; According to the test parameter association diagram, a membership function in the form of normal distribution is established for each test parameter in the standardized test data matrix to obtain a fuzzy set representation of the parameter; Based on the fuzzy set representation of the parameters, weighted fuzzy reasoning is performed on the missing parameter values ​​in the initial test data matrix to obtain the predicted values ​​of the missing data, and the existing data in the standardized test data matrix is ​​merged with the predicted values ​​of the missing data to obtain a complete test data matrix.

4. The method for testing a CPU card chip according to claim 1, wherein: The complete test data matrix is ​​subjected to principal component analysis to obtain a valid test data set, including: Calculating a covariance matrix according to the complete test data matrix, and solving a characteristic equation for the covariance matrix to obtain the principal component directions of the test data; Calculating the cumulative variance contribution rate based on the principal component direction, selecting the first k principal components satisfying the cumulative variance contribution rate greater than or equal to a first preset threshold, and constructing a principal feature space; Calculating the similarity between each test sample in the complete test data matrix and the i-th principal component in the main feature space, and calculating the overall similarity to obtain the feature space similarity of the test sample; Calculating the data support of each test sample based on the feature space similarity of the test samples, and screening the test samples according to the data support threshold to obtain preliminary valid test data; The projection distance and the Mahalanobis distance are calculated for each test sample in the preliminary valid test data, and outliers are removed to obtain a valid test data set.

5. The method for testing a CPU card chip according to claim 1, characterized in that: The step of constructing a multi-level fuzzy set according to the valid test data set and calculating the cosine similarity with the calibration reference model to obtain fused test data includes: Constructing a plurality of first-state fuzzy sets based on a trapezoidal membership function according to the electrical characteristic test parameters in the valid test data set, determining the parameters of the trapezoidal membership function according to the distribution characteristics of the historical test data, and mapping each electrical characteristic test parameter to the plurality of first-state fuzzy sets to obtain a first fuzzy representation; Constructing a plurality of second-state fuzzy sets based on a Gaussian membership function according to the functional test parameters in the effective test data set, determining the center and width parameters of the Gaussian membership function according to the distribution characteristics of the historical test data, and mapping each functional test parameter to a plurality of second-state fuzzy sets to obtain a second fuzzy representation; Based on expert knowledge and historical calibration data, a calibration reference model of real test data is constructed, and the cosine similarity between the first fuzzy representation and the calibration reference model is calculated, and the cosine similarity between the second fuzzy representation and the calibration reference model is calculated to obtain the closeness between the dual-channel data and the calibration reference model; Calculating target fusion weights of electrical characteristic test parameters in the effective test data set and functional test parameters in the effective test data set according to the closeness between the dual-channel data and the calibration reference model; The electrical characteristic test parameters in the valid test data set and the functional test parameters in the valid test data set are weighted and combined according to the target fusion weight to obtain fused test data.

6. The method for testing a CPU card chip according to claim 1, characterized in that: The fusion test data is input into the variational autoencoder for self-supervised pre-training, and conditional interpolation is performed using a diffusion state space model to obtain defect detection results and uncertainty estimates, including: Inputting the fused test data into a variational autoencoder including an encoder and a decoder, mapping the fused test data to a latent space, and generating new samples by adding controlled noise to the latent space to obtain an enhanced data set; Inputting the enhanced dataset into a self-supervised model based on a Transformer architecture, reconstructing masked features through context information, and extracting common feature representations to obtain a pre-trained feature encoder; Building a diffusion state space model based on the pre-trained feature encoder, gradually converting the enhanced data set into noise through a random diffusion process, reconstructing the data through an inverse diffusion process, and using the features extracted by the encoder as conditions to guide the reconstruction process, thereby obtaining a conditional data interpolation model; Applying the conditional data interpolation model to the test samples with missing values, completing the data according to the existing features and the feature representation extracted by the encoder, and performing consistency verification on the interpolation results to obtain a complete test feature representation; The enhanced data set and the complete test feature representation are fine-tuned in a balanced manner, a defect detection classifier is trained using a combination of cross entropy loss and focal loss, a defect detection result of the CPU card chip is obtained, and an uncertainty estimation value is calculated based on the defect detection result.

7. The method for testing a CPU card chip according to claim 1, characterized in that: The testing method of the CPU card chip also includes: For the test samples whose uncertainty estimation value exceeds the second preset threshold, extract the representation in the deep feature space, and calculate the Mahalanobis distance with the center of each known defect category, and when the minimum distance value exceeds the third preset threshold, judge the test sample as an unknown defect type, and obtain an unknown defect sample set; Calculating the Euclidean distance between samples according to the unknown defect sample set, and calculating the product of the local density and the minimum distance value for each sample as a clustering decision index, selecting the test sample whose clustering decision index exceeds a fourth preset threshold as the clustering center, and assigning the remaining test samples to the nearest clustering center to obtain a new defect type that is automatically clustered; Based on the new defect type automatically clustered, an independent sample library is constructed for each cluster, feature normalization and data expansion are performed on the data in the sample library, and a unique identifier and category label are added to obtain a standardized sample library; For each defect category in the standardized sample library, a dual attention network structure including a channel attention module and a spatial attention module is constructed, an independent expert model is trained using a category-balanced focal loss, and feature distinguishability is enhanced through contrastive learning to obtain a defect analysis expert model; A knowledge distillation mechanism is implemented on the defect analysis expert model, the KL divergence between the soft label distribution of the teacher model and the output of the student model is calculated, and a decoupled representation is constructed at the feature level to obtain a model-decoupled federated expert model set.

8. A CPU card chip testing device, characterized in that: A method for testing a CPU card chip according to any one of claims 1 to 7, wherein the testing device for the CPU card chip comprises: The data acquisition module is used to collect data from the CPU card chip to obtain an initial test data matrix including an electrical parameter vector and a functional parameter vector; A construction module is used to construct a test parameter association diagram of the initial test data matrix and predict missing data to obtain a complete test data matrix; A principal component analysis module, used for performing principal component analysis on the complete test data matrix to obtain a valid test data set; A calculation module, used for constructing a multi-level fuzzy set according to the effective test data set, and calculating the cosine similarity with the calibration reference model to obtain fused test data; The defect detection module is used to input the fusion test data into a variational autoencoder for self-supervised pre-training, and use a diffusion state space model to perform conditional interpolation to obtain defect detection results and uncertainty estimates.

9. A CPU card chip testing device, characterized in that: The CPU card chip test device comprises: a memory and at least one processor, wherein instructions are stored in the memory; The at least one processor calls the instruction in the memory so that the CPU card chip testing device executes the CPU card chip testing method according to any one of claims 1 to 7.

10. A computer-readable storage medium having instructions stored thereon, characterized in that: When the instructions are executed by the processor, the testing method for the CPU card chip according to any one of claims 1 to 7 is implemented.

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