A method for optical transceiver signal flow and control

Abstract

The application relates to the field of optical modules, and discloses a light transceiver signal flow and control method, which comprises the following steps: converting an optical signal into a photo-generated current based on an optical detector D1 and guiding the photo-generated current to a mainboard; converting the photo-generated current into an initial voltage signal based on a passive resistance conversion network arranged on the mainboard; converting the initial voltage signal into a digital logic level to generate an output electrical signal; capturing a driving electrical signal input via a second pin of a single-row 4-bit pin array; controlling a chip IC1A arranged on the mainboard to generate an alternating current modulation current according to the driving electrical signal; collecting an optical power monitoring signal in a laser LD1 power supply loop by using a closed-loop tracking circuit; controlling the closed-loop tracking circuit to calculate a corresponding compensation current according to the optical power monitoring signal; and superimposing the alternating current modulation current and the compensation current at a cathode node of the laser LD1 to form a total driving current to trigger the laser LD1 to emit a communication optical signal to the outside.

Description

Technical Field

[0001] This application relates to the field of optical communication, and in particular to a method for the flow and control of optical transceiver signals. Background Technology

[0002] With the widespread adoption of fiber optic communication technology, the demand for low-speed data transmission via fiber optics in specific industrial control and specialized equipment is constantly increasing. These applications impose significant space constraints on the size and installation density of the equipment.

[0003] In related technologies, low-speed optical modules with a 1*9 pin structure are often used to achieve photoelectric signal conversion and transmission. The printed circuit board of this 1*9 pin optical module is relatively large.

[0004] When facing special application environments with strict installation space constraints, the optical modules in related technologies have the disadvantage of being too large to be embedded in the restricted assembly compartment. If the area of ​​their printed circuit boards is reduced, the weak optical current link on the receiving side and the high current loop driving the laser on the transmitting side are prone to electromagnetic interference and signal crosstalk in the limited wiring space, which may lead to increased communication error rate or even link interruption.

[0005] Solving this technical problem is a technical challenge that needs to be overcome by those skilled in the art. Summary of the Invention

[0006] This application provides a method for the flow and control of optical transceiver signals, which at least partially solves the above-mentioned technical problems.

[0007] To achieve the above objectives, this application provides a method for the flow and control of optical transceiver signals, comprising: The optical signal input to the photodetector D1 is acquired; the optical signal is converted into a photocurrent based on the photodetector D1; the photocurrent is guided to the motherboard along the flexible PCB transmission path; and the photocurrent is converted into an initial voltage signal based on the passive resistor conversion network arranged on the motherboard. The initial voltage signal is controlled to be input to the integrated decision chip in open-loop operation. The initial voltage signal is converted into a digital logic level through open-loop level decision to generate an output electrical signal. The output electrical signal is then guided to the third pin of a single-row 4-pin header for output to an external terminal. The drive signal input via the second pin of the single-row 4-pin header is captured; the IC1A chip arranged on the motherboard is controlled to generate an AC modulation current according to the drive signal; the optical power monitoring signal in the power supply circuit of the laser LD1 is acquired using a closed-loop tracking circuit; the closed-loop tracking circuit includes an operational amplifier chip IC3. The closed-loop tracking circuit is controlled to calculate the corresponding compensation current based on the optical power monitoring signal; the AC modulation current and the compensation current are combined and superimposed at the cathode node of the laser LD1 to form a total driving current that triggers the laser LD1 to emit a communication optical signal to the outside; wherein, the swing of the AC modulation current independently determines the extinction ratio of the communication optical signal, and the compensation current is superimposed on the AC modulation current as a separate DC bias baseline.

[0008] In this embodiment, the above technical solution guides the photocurrent output by photodetector D1 to the motherboard along the flexible PCB transmission path, achieving spatial isolation between the microampere-level receiving link and the high-current transmitting circuit of laser LD1 in terms of topology, thus blocking electromagnetic radiation crosstalk. On the receiving side, the susceptible closed-loop transimpedance amplification circuit is abandoned, and an open-loop level decision mechanism combining a passive resistor conversion network and an integrated decision chip is used, improving the anti-interference capability on the small-size motherboard. On the transmitting side, a closed-loop tracking circuit is used to calculate an independent compensation current and uses it as a separate DC bias baseline to be superimposed in parallel with the AC modulation current at the cathode node of laser LD1. This maintains the stability of the average output power of the communication optical signal while ensuring that the extinction ratio of the communication optical signal is not degraded due to the adjustment of the DC bias baseline.

[0009] Other features and advantages of this application will be described in detail in the following detailed description section. Attached Figure Description

[0010] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0011] Figure 1 This is a circuit schematic provided in an exemplary embodiment of this application.

[0012] Figure 2 This is a circuit system architecture diagram provided in an exemplary embodiment of this application.

[0013] Figure 3 This is a flowchart illustrating the steps of a method for the flow and control of optical transceiver signals provided in an exemplary embodiment of this application. Detailed Implementation

[0014] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the protection scope of this application.

[0015] Reference Figure 1 This is a schematic diagram of the circuit principle of the transceiver module used in the method of this application. The receiving path of the transceiver module is based on photodetector D1, and the transmitting path is based on laser LD1. The two paths are connected to the main board via a flexible PCB to form a transceiver isolated layout. Photodetector D1 is deployed at the front end of the flexible PCB near the fiber optic interface, and laser LD1 is deployed on the main board near the fiber optic interface. The flexible PCB spatially separates the receiving front end where photodetector D1 is located from the transmitting path on the main board to block crosstalk caused by electromagnetic radiation generated by the transmitting circuit under high modulation current conditions to the microampere-level photocurrent. The main board is equipped with a passive resistor conversion network, an integrated decision chip, chip IC1A, and a closed-loop tracking circuit; the closed-loop tracking circuit includes operational amplifier chip IC3; the integrated decision chip is specifically a comparator chip IC4. The single-row 4-pin header is led out from the self-board, providing external interfaces for signal input, signal output, grounding, and power supply; the single-row 4-pin header is the Ming 1*4 pin optical module. The first pin of the single-row 4-pin header is the ground pin, the second pin is the transmit data input pin, the third pin is the receive data output pin, and the fourth pin is the power supply pin.

[0016] This application provides a method for the flow and control of optical transceiver signals. Please refer to [link to relevant documentation]. Figure 2 The method for the flow and control of optical transceiver signals provided in this application includes: S101. Acquire the optical signal input to photodetector D1, convert the optical signal into photocurrent based on photodetector D1, guide the photocurrent to the main board along the flexible PCB transmission path, and convert the photocurrent into an initial voltage signal based on the passive resistor conversion network arranged on the main board. Specifically, the communication optical signal from the fiber optic link is coupled to the photosensitive surface of photodetector D1 through the fiber optic interface; photodetector D1 operates under reverse bias voltage conditions, and its internal PN junction absorbs incident photons and excites electron-hole pairs to generate a photocurrent proportional to the incident light power; the photocurrent output by photodetector D1 is injected into the transmission trace arranged on the flexible PCB, and the photocurrent is transmitted across space to the receiving node on the main board using the transmission trace, restricting the photocurrent to only flow into the main board at the receiving node, forming spatial isolation from the transmitting circuit used to drive laser LD1; control the photocurrent output by photodetector D1 to flow through the passive resistor conversion network composed of resistors R14, R18 and R21 to convert it into an initial voltage signal of corresponding amplitude. This passive resistor conversion network replaces the closed-loop transimpedance amplifier topology commonly used in related technologies. It establishes the primary voltage level from current to voltage solely through a passive method of resistor voltage division and biasing, avoiding the introduction of feedback loop noise from active devices. The optical signal referred to here is a modulated optical pulse sequence transmitted via single-mode fiber from a remote optical transmitter; the aforementioned flexible PCB transmission path refers to the conductive wiring path connecting the flexible circuit board containing photodetector D1 to the main board; the aforementioned receiving node refers to the electrical connection point on the main board that receives the photogenerated current; and the aforementioned initial voltage signal refers to the original voltage quantity that is linearly related to the photogenerated current and has not been actively amplified.

[0017] S102. The initial voltage signal is input to the integrated decision chip in open-loop operation. The initial voltage signal is converted to a digital logic level through open-loop level decision to generate an output signal. This output signal is then guided to pin 3 of a single-row 4-pin header for output to an external terminal. Specifically, the initial voltage signal is input to the non-inverting input of the comparator chip IC4 (which is the integrated decision chip) via resistor R14. A set decision threshold voltage is injected into the inverting input of the comparator chip IC4 based on a bias network including resistor R11. The comparator chip IC4, operating without a closed-loop feedback loop, compares the initial voltage signal with the decision threshold voltage, and outputs the analog initial voltage signal as a digital logic level from its output. The digital logic level signal output by the comparator chip IC4 flows through the motherboard's signal transmission traces to pin 3 of the single-row 4-pin header. This pin provides received data output to the external terminal. The external terminal can reconstruct the original data sequence transmitted by the remote optical transmitter by sampling the level on pin 3. The aforementioned integrated decision chip refers to an integrated circuit with level comparison function, used to binarize continuously changing analog voltages into high and low logic levels; the aforementioned open-loop level decision refers to the working mode of the comparator, which outputs the decision result directly based solely on the relative magnitude of the input signal and the threshold, under the condition that there is no feedback path between the output and input terminals.

[0018] S103. The drive signal input via pin 2 of a single-row 4-pin header is captured. The IC1A chip on the motherboard is controlled to generate an AC modulation current based on the drive signal. A closed-loop tracking circuit is used to acquire the optical power monitoring signal in the power supply circuit of the laser LD1. Specifically, the external terminal injects the drive signal to be transmitted into pin 2 of the single-row 4-pin header. The motherboard captures the drive signal through the receiving trace located near pin 2 and guides it to the signal input terminal of the IC1A chip. The logic level state of the drive signal is obtained, and the drive signal is controlled to be input to the signal input terminal of the logic gate integrated chip IC1A. The switching transistor configured inside the logic gate integrated chip is triggered to switch between on and off according to the logic level state. Based on the on / off action of the switching transistor, the inverting output terminal of the logic gate integrated chip outputs the logic-flipped level signal. The level signal is controlled to flow through the first current-limiting resistor and injected into the cathode node of the laser LD1 to form an AC modulation current. The backlight monitoring diode arranged inside the laser LD1 cavity absorbs the backscattered photons and converts the absorbed photons into an optical power monitoring signal. The aforementioned driving electrical signal refers to a digital level sequence generated by an external terminal that carries the data to be transmitted; the aforementioned AC modulation current refers to a pulse current that alternately turns on and off as the driving electrical signal switches between high and low levels, and its swing determines the high-low power ratio, i.e., the extinction ratio, of the emitted optical signal from the laser LD1; the aforementioned closed-loop tracking circuit is composed of the operational amplifier chip IC3 and its peripheral resistor network; the aforementioned optical power monitoring signal refers to a current signal that is proportional to the current emitted optical power of the laser LD1.

[0019] S104. The control closed-loop tracking circuit calculates the corresponding compensation current based on the optical power monitoring signal. The AC modulation current and the compensation current are combined and superimposed at the cathode node of laser LD1 to form a total driving current that triggers laser LD1 to emit communication optical signals outward. Specifically, the control optical power monitoring signal is converted into a monitoring voltage via an input resistor and flows into the non-inverting input of operational amplifier chip IC3. A reference bias voltage is injected into the inverting input of operational amplifier chip IC3 via a voltage divider resistor network to set a safe reference voltage. The difference between the monitoring voltage and the safe reference voltage is calculated by operational amplifier chip IC3. An analog voltage containing the difference is generated at the output of operational amplifier chip IC3 as a compensation current and is independently injected into the cathode node of laser LD1 via a feedback resistor. The AC modulation current, representing the digital envelope, flows from the output path of chip IC1A into the cathode node of laser LD1. The compensation current, representing the basic luminous power, is independently injected into the same cathode node from the feedback path of operational amplifier chip IC3. The two currents form a parallel superimposed total driving current at the cathode node. This total driving current flows through the PN junction of laser LD1 and triggers the emitted light, forming a communication optical signal corresponding to the logic level of the driving electrical signal. The swing of the AC modulation current independently determines the extinction ratio of the communication optical signal. The compensation current, as a separate DC bias baseline, is superimposed on the AC modulation current. This ensures that when the compensation current raises the DC baseline to overcome laser LD1 aging or high-temperature threshold drift, it does not change the high and low level swing of the AC modulation current, maintaining the extinction ratio of the communication optical signal unaffected by DC bias baseline adjustment.

[0020] Based on the above scheme, by guiding the photocurrent output by photodetector D1 to the motherboard along the flexible PCB transmission path, spatial isolation between the microampere-level receiving link and the high-current transmitting circuit of laser LD1 is achieved in the topology, blocking electromagnetic radiation crosstalk. On the receiving side, the closed-loop transimpedance amplification circuit that is susceptible to interference is abandoned, and an open-loop level decision mechanism combining a passive resistor conversion network and an integrated decision chip is used instead, which improves the anti-interference capability on the small-size motherboard. On the transmitting side, a closed-loop tracking circuit is used to calculate an independent compensation current and use it as a separate DC bias baseline to be superimposed in parallel with the AC modulation current at the cathode node of laser LD1. While maintaining the stability of the average output power of the communication optical signal, it ensures that the extinction ratio of the communication optical signal is not degraded due to the adjustment of the DC bias baseline.

[0021] In some embodiments, guiding photocurrent to the motherboard along the arranged flexible PCB transmission path includes: S201. Inject the photocurrent output by photodetector D1 into the transmission traces arranged on the flexible PCB. Specifically, the cathode output terminal of photodetector D1 is electrically connected to the copper foil transmission traces on the surface of the flexible PCB through a pad, and the photocurrent is injected into the transmission traces from the cathode pin of photodetector D1.

[0022] S202. The photocurrent is transmitted across space to the receiving node on the motherboard using transmission traces. Specifically, the flexible PCB serves as a flexible interconnect carrier, bridging the spatial distance between the location of the photodetector D1 and the motherboard; the transmission traces carry the photocurrent in the inner wiring layer of the flexible PCB; the receiving node is located on the side of the motherboard away from the laser LD1 and its driving circuit.

[0023] S203. The photocurrent is limited to the receiving node, flowing into the motherboard only, creating spatial isolation from the transmitting circuit used to drive the LD1 laser. This prevents crosstalk caused by electromagnetic radiation generated by the transmitting circuit under high-current modulation. Specifically, the receiving node is designated as the sole electrical path for the photocurrent to enter the motherboard. During PCB routing, the current-carrying traces of the transmitting circuit around the receiving node are placed on another routing layer. The interlayer dielectric blocks the large-current pulse magnetic field generated by the transmitting circuit during the switching transistor's flip-flop, ensuring that the magnetic field at the moment of switching is attenuated by space and has insufficient to have an observable impact on the microampere-level photocurrent.

[0024] Based on the above scheme, the microampere-level photocurrent is confined to the transmission traces of the flexible PCB to flow across space. This spatially increases the distance between the receiving node and the high-current transmission circuit of the laser LD1, blocking the transmission of electromagnetic radiation generated by the transmission circuit in the modulation state to the receiving side, thus ensuring the signal-to-noise ratio of the weak photocurrent within the confined assembly chamber.

[0025] In some embodiments, the photogenerated current is converted into an initial voltage signal based on a passive resistor conversion network disposed on the motherboard, including: S301: The photocurrent output by the photodetector D1 flows through a passive resistor conversion network consisting of resistors R14, R18, and R21 to convert it into an initial voltage signal of corresponding amplitude. Specifically, after the photocurrent flows through resistor R14, a voltage drop is formed across it; resistors R18 and R21 form a voltage divider branch that works with resistor R14 to linearly map the amplitude change of the photocurrent into a voltage amplitude change, thus obtaining the initial voltage signal; the resistance value of resistor R14 is selected based on the output current range of the photodetector D1 at its rated receiving power to ensure that the amplitude of the initial voltage signal falls within the common-mode input voltage range of the comparator chip IC4.

[0026] The initial voltage signal is input to an integrated decision chip operating in an open-loop state. The initial voltage signal is converted into a digital logic level through open-loop level decision to generate an output electrical signal, including: S302. The initial control voltage signal is input to the non-inverting input of the comparator chip IC4, which is an integrated decision chip, via resistor R14. Specifically, one end of resistor R14 is connected to the cathode node of photodetector D1, and the other end is connected to the non-inverting input pin of comparator chip IC4; the initial voltage signal is directly fed into comparator chip IC4 via resistor R14 without going through an intermediate amplification stage.

[0027] S303. Based on the bias network including resistor R11, a set decision threshold voltage is injected into the inverting input terminal of comparator chip IC4. Specifically, resistor R11 and auxiliary voltage divider resistors form a bias network, which divides the power supply rail to obtain the decision threshold voltage and injects it into the inverting input terminal of comparator chip IC4; the set value of the decision threshold voltage is determined during the factory calibration stage based on the responsivity of photodetector D1 and the link budget of the fiber optic link.

[0028] S304. Using comparator chip IC4 in a non-closed-loop feedback state, the initial voltage signal is compared with a decision threshold voltage. The analog initial voltage signal is then converted into a digital logic level and output from the output terminal of comparator chip IC4. Specifically, no feedback resistor is set between the output and input terminals of comparator chip IC4, forming an open-loop comparator topology. When the initial voltage signal at the non-inverting input terminal is higher than the decision threshold voltage at the inverting input terminal, comparator chip IC4 outputs a high level; when the initial voltage signal is lower than the decision threshold voltage, comparator chip IC4 outputs a low level, thereby converting the analog initial voltage signal into a digital logic level.

[0029] Based on the above scheme, a passive resistor conversion network consisting of resistors R14, R18 and R21 is used to establish the primary level. Combined with the open-loop level decision mechanism of the comparator chip IC4, hardware threshold comparison is used to replace linear amplification, which suppresses the cascading amplification effect of spatial crosstalk noise on the small-size motherboard and improves the immunity of the output logic level.

[0030] In some embodiments, before guiding the output electrical signal to the third pin of a single-row 4-pin header for output to an external terminal, the method further includes: S401. Connect the first pin of the single-row 4-pin header to the motherboard's ground network to establish a reference ground potential. Specifically, the first pin is connected to the entire ground network through the ground copper area on the motherboard to achieve low impedance, providing a unified zero potential reference for the signal loops of the entire board; the ground network covers most of the bottom layer area of ​​the motherboard and is connected to the ground pins of each chip in a star or grid configuration through vias.

[0031] S402. Connect the fourth pin of the single-row 4-pin header to the motherboard's power network to obtain power supply voltage from the outside. Specifically, the fourth pin serves as the power input terminal, introducing the DC power supply voltage provided by the external terminal into the motherboard's power network. After being filtered by decoupling capacitors, it is distributed to the power supply pins of each chip. The power network is arranged in the form of a power plane on the inner layer of the motherboard, providing a low-impedance power supply path for each chip.

[0032] Based on the above scheme, a unified reference ground potential and power supply voltage input point are established by using specific pins of a single row of 4-pin headers, avoiding grounding loop interference caused by multiple grounding points, and providing an equipotential reference for high-frequency modulation and weak signal detection of the entire board.

[0033] In some embodiments, controlling the chip IC1A arranged on the motherboard to generate an AC modulated current according to a drive electrical signal includes: S501: Obtain the logic level state of the drive signal input via pin 2 of a single-row 4-pin header. Specifically, the motherboard's input buffer circuit samples the voltage on pin 2 and converts it into a logic state compatible with the input level of chip IC1A; the input buffer circuit includes pull-up or pull-down resistors to ensure that the input level is in a defined state when no external terminal is connected.

[0034] S502: The control drive electrical signal is input to the signal input terminal of the logic gate integrated chip IC1A. Specifically, the drive electrical signal is input to the input pin of the logic gate integrated chip via an impedance matching resistor; the resistance value of the impedance matching resistor is matched with the input impedance of the logic gate integrated chip to reduce signal reflection and overshoot.

[0035] S503 triggers the switching transistors configured inside the logic gate integrated chip, which toggle according to the logic level state to switch between on and off states. Specifically, the logic gate integrated chip integrates complementary P-channel and N-channel MOS transistor pairs; when the input is high, the P-channel transistor is off and the N-channel transistor is on, and the output is pulled down to a low level; when the input is low, the P-channel transistor is on and the N-channel transistor is off, and the output is pulled up to a high level.

[0036] S504. Based on the switching action of the switching transistor, the logic gate integrated chip outputs a logic-inverted level signal. Specifically, the logic gate integrated chip performs logic operations on the input signal and outputs a low level when the input signal is valid to drive the laser LD1, satisfying the level polarity requirements of the common cathode driving topology of the laser LD1.

[0037] S505: The control level signal flows through the first current-limiting resistor and is injected into the cathode node of the laser LD1 to form an AC modulated current. Specifically, the first current-limiting resistor is connected in series between the inverting output terminal of the logic gate integrated chip and the cathode node of the laser LD1, converting the output level signal into a current-limited pulse current. The peak value of this pulse current is determined by the resistance value of the first current-limiting resistor and the output voltage of the logic gate integrated chip. When the logic gate integrated chip outputs a low level, the current flows from the anode of the laser LD1 through the PN junction to the cathode node and then through the first current-limiting resistor into the chip output terminal, turning on the laser LD1 to emit light. When the output is high, the laser LD1 is turned off.

[0038] Based on the above scheme, a logic gate integrated chip containing internal switching transistors is selected as the driving source. The switching action of the transistor is used to replace the linear current source modulation, providing steeper rising and falling edges for the AC modulation current, reducing the pulse jitter of the communication optical signal and improving the quality of the optical eye diagram.

[0039] In some embodiments, the control closed-loop tracking circuit calculates the corresponding compensation current based on the optical power monitoring signal, including: S601. A backlight monitoring diode arranged inside the cavity of the laser LD1 absorbs backscattered photons and converts the absorbed photons into an optical power monitoring signal. Specifically, the backlight monitoring diode is integrated inside the laser LD1 package, with its photosensitive surface facing the rear end of the laser LD1 to receive the back-emitted laser component; the backlight monitoring diode operates in photovoltaic mode, generating a monitoring photocurrent that is linearly proportional to the emitted optical power of the laser LD1.

[0040] S602: The control optical power monitoring signal is converted into a monitoring voltage via an input resistor and flows into the non-inverting input of the operational amplifier chip IC3. Specifically, the monitoring photocurrent flows through the input resistor to form a voltage drop, and this voltage is fed into the non-inverting input pin of the operational amplifier chip IC3 as the monitoring voltage; the value of the input resistor is selected to balance the signal-to-noise ratio and the response bandwidth.

[0041] S603. A reference bias voltage is injected into the inverting input of the operational amplifier chip IC3 via a voltage divider resistor network using the power supply node to set a safety reference voltage. Specifically, the reference bias voltage obtained by voltage division from the power rail by a high-precision voltage divider resistor network is injected into the inverting input of the operational amplifier chip IC3; the set value of this safety reference voltage corresponds to the rated average output power of the laser LD1 during the factory calibration stage.

[0042] S604. The operational amplifier chip IC3 is used to calculate the difference between the monitoring voltage and the safety reference voltage. Specifically, the operational amplifier chip IC3 performs a subtraction operation on the monitoring voltage at the non-inverting input terminal and the safety reference voltage at the inverting input terminal in its internal differential input stage to obtain the difference voltage; the sign and amplitude of the difference voltage reflect the degree and direction of the deviation of the current average output power of the laser LD1 from the rated value.

[0043] S605. An analog voltage containing the difference is generated at the output of the operational amplifier chip IC3 as a compensation current and is independently injected into the cathode node of the laser LD1 via a feedback resistor. Specifically, the difference voltage is amplified by the operational amplifier chip IC3 to generate an analog output voltage at its output terminal. This output voltage is converted into a compensation current through the feedback resistor and injected into the cathode node of the laser LD1. When the average output power of the laser LD1 decreases due to temperature rise or aging, the monitoring voltage decreases, the difference voltage increases, the output voltage of the operational amplifier chip IC3 increases accordingly, the compensation current increases, and the DC bias baseline of the laser LD1 is raised so that its average output power returns to the rated range.

[0044] Based on the above scheme, a purely analog feedback loop is constructed using the operational amplifier chip IC3. The monitoring voltage captured by the backlight monitoring diode is hard-wired to calculate the difference between the monitoring voltage and the reference bias voltage, eliminating the sampling and instruction processing delay of the digital chip. This ensures that the generation of the compensation current has low control hysteresis and smooths out the optical power fluctuations caused by transient changes in ambient temperature.

[0045] In some embodiments, before acquiring the optical signal input to the photodetector D1, the method further includes: S701. High-frequency noise is filtered out using a first decoupling capacitor connected between the power input terminal of the photodetector D1 and the analog ground network. Specifically, the first decoupling capacitor is located close to the power supply pin of the photodetector D1 to provide a low-impedance bypass path for high-frequency ripple on the power bus, preventing power supply noise from coupling to the internal amplification stage of the photodetector D1 and raising the output noise floor.

[0046] When triggering laser LD1 to emit communication optical signals outward, the following is also included: S702. The second and third decoupling capacitors connected in parallel on the power supply branch of laser LD1 work together to provide transient current pulses to smooth out power bus voltage fluctuations caused by AC modulation current. Specifically, the second and third decoupling capacitors provide high-frequency and low-frequency decoupling characteristics, respectively; the second decoupling capacitor has a smaller capacitance value to filter out high-frequency noise spikes introduced by the switching transistor flip-flop; the third decoupling capacitor has a larger capacitance value to provide a large transient current at the moment laser LD1 is turned on to compensate for the voltage drop caused by the parasitic inductance of the power bus; the two capacitors are connected in parallel near the power supply pin of laser LD1 between the power supply pin and the ground network. At the moment laser LD1 emits, the stored charge is released by the capacitors, reducing transient voltage fluctuations on the power supply network and preventing conductive interference from the large current switching action on the bias circuit of photodetector D1.

[0047] Based on the above solution, to address the limitation of large parasitic inductance of the power bus under the single-row pin power supply architecture, two sets of decoupling capacitors are connected in parallel near the power supply branch of the laser LD1. The capacitors provide transient current pulses nearby at the moment the laser LD1 is turned on, which reduces the voltage drop on the power supply network and prevents the high-current switching action from causing conductive pull on the power supply of other modules on the motherboard.

[0048] In some embodiments, the AC modulation current and the compensation current are combined and superimposed at the cathode node of the laser LD1, including: S801. When the optical power monitoring signal indicates that the average output power of laser LD1 has attenuated, the closed-loop tracking circuit is controlled to increase the output amplitude of the compensation current. Specifically, when the monitoring photocurrent output by the backlight monitoring diode is lower than the reference value corresponding to the rated average output power, the voltage at the non-inverting input terminal of the operational amplifier chip IC3 decreases, the voltage difference between it and the safety reference voltage at the inverting input terminal increases, the output voltage of the operational amplifier chip IC3 increases, and the compensation current flowing through the feedback resistor increases accordingly.

[0049] S802. The increased compensation current is directed to the cathode node of laser LD1, causing the DC bias baseline in the total drive current to shift upwards to counteract the threshold drift of laser LD1, forcing the average output power of the communication optical signal back to the stable range. Specifically, the increased compensation current raises the DC operating point at the cathode node of laser LD1, causing the AC modulation current to be superimposed on a higher DC bias baseline, thus raising the lower limit of the total drive current and restoring the average output power of laser LD1 to its rated value. During this process, the high and low level swings of the AC modulation current remain unchanged, and the extinction ratio of the communication optical signal is unaffected.

[0050] Based on the above scheme, a dual-path independent injection topology is adopted at the cathode node of the laser LD1, so that the AC swing and the DC baseline are decoupled at this node. When the DC baseline is raised by the compensation current to overcome the aging of the laser LD1 or the high temperature threshold drift, the peak-to-peak value of the AC modulation current remains constant, maintaining the stability of the high and low power ratio of the optical signal and preventing communication errors caused by the deterioration of the extinction ratio.

[0051] In some embodiments, after connecting the fourth pin of a single-row 4-pin header to the motherboard's power network to obtain power supply voltage from an external source, the method further includes: S901 detects the actual supply voltage connected through pin 4. Specifically, a voltage detection divider network is arranged on the motherboard to proportionally attenuate the supply voltage at pin 4 before sending it to the auxiliary input of the comparator, where it is compared with the built-in reference voltage source to determine the range of the actual supply voltage.

[0052] S902. When it is determined that the actual supply voltage falls into the first range, the integrated decision chip and chip IC1A are configured to operate in the first bias state. Specifically, when the supply voltage is detected to be approximately 3.3V, the voltage divider resistor network of the decision threshold voltage is switched to the first voltage division ratio, and the first current limiting resistor of chip IC1A is switched to the first resistance value range. The first voltage division ratio and the first resistance value range make the decision threshold voltage fall within the optimal switching range of the comparator chip IC4 under the 3.3V supply condition, so that the swing of the AC modulation current is adapted to the modulation characteristics of the laser LD1 under the 3.3V supply condition.

[0053] S903. When the actual supply voltage falls into the second interval, the distribution ratio of the decision threshold voltage and the safety reference voltage of the operational amplifier chip IC3 are simultaneously adjusted to configure the transceiver bias of the entire link into the second bias state. Specifically, when the supply voltage is detected to be approximately 5V, the voltage divider resistor network of the decision threshold voltage is switched to the second voltage division ratio, the safety reference voltage of the operational amplifier chip IC3 is adjusted to the voltage division value corresponding to the 5V supply, and the first current limiting resistor of the chip IC1A is switched to the second resistance value level, so that the drive current of the laser LD1 is adapted to the 5V supply environment. The detection thresholds and corresponding resistor voltage division ratios of the first and second intervals mentioned above are preset in the parameter storage area of ​​the motherboard during the factory calibration stage to ensure that the transceiver module can operate within the safe bias range when connected to external terminals with different power supply specifications.

[0054] Based on the above scheme, by configuring multi-level voltage detection and bias switching intervals, the underlying circuit has hardware-level compatibility with external power supply standards; when connected to power supply terminals of different specifications, it switches to the corresponding resistor voltage division ratio and safety reference voltage, avoiding the risk of breakdown of the laser LD1 and photodetector D1 caused by external voltage overshoot, and improving the versatility of the transceiver module.

[0055] In some embodiments, the photocurrent is transmitted across space to a receiving node on the motherboard using transmission traces, including: S1001. Obtain the shielding potential of the grounding layer surrounding the transmission path of the flexible PCB. Specifically, the flexible PCB adopts a multi-layer structure, and the upper and lower surfaces of the inner wiring layer where the transmission trace is located are covered with a grounding copper layer; the shielding potential of this grounding layer is connected to the grounding network of the motherboard through vias, forming a conductive shielding cavity surrounding the transmission trace.

[0056] S1002. Interconnect the shielding potential with the motherboard's grounding network. Specifically, the grounding layer of the flexible PCB is connected to the grounding copper area of ​​the motherboard at multiple points through connectors or pads to ensure that there is no potential difference between the shielding potential and the motherboard's reference ground potential, thus avoiding a decrease in shielding effectiveness due to the shielding layer being suspended or poorly grounded.

[0057] S1003. When the photocurrent flows along the transmission line, the grounding layer is used to intercept the electromagnetic radiation energy injected from the external space to maintain the waveform of the photocurrent without distortion. Specifically, the conductive shielding cavity formed by the grounding layer encloses the transmission line; when stray electromagnetic waves in the external space are incident on the surface of the grounding layer, a surface current is induced on the metal surface and a reverse reflection field is generated. Most of the electromagnetic energy is reflected or absorbed, and only a small amount of attenuation margin penetrates into the internal space where the transmission line is located. In this way, the electromagnetic interference experienced by the microampere-level photocurrent during transmission is reduced to an order of magnitude that does not affect the accuracy of digital decision-making, and the integrity of the photocurrent waveform is maintained.

[0058] Based on the above scheme, the grounding layer wrapped around the outside of the flexible PCB forms a shielding effect, and the shielding potential is forced to be equipotentially interconnected with the motherboard reference ground. This intercepts and absorbs stray space radiation energy injected by the external equipment environment and discharges it to the grounding network, maintaining the integrity of the microampere-level photocurrent waveform.

[0059] The embodiments, implementation methods, and related technical features of this application can be combined and substituted for each other without conflict.

[0060] The above are merely preferred embodiments of this application and are not intended to limit this application in any way. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of this application without departing from the scope of the technical solution of this application shall still fall within the scope of the technical solution of this application.

Claims

1. A method for the flow and control of optical transceiver signals, characterized in that, include: Acquire the optical signal input to photodetector D1; The photodetector D1 converts the optical signal into a photocurrent; the photocurrent is then guided to the motherboard along the flexible PCB transmission path. The photogenerated current is converted into an initial voltage signal based on a passive resistor conversion network arranged on the motherboard; The initial voltage signal is controlled to be input to an integrated decision chip in an open-loop operating state. The initial voltage signal is converted into a digital logic level through open-loop level decision to generate an output electrical signal. The output electrical signal is guided to the third pin of a single row of 4-pin headers to be output to an external terminal. The drive signal input via the second pin of the single-row 4-pin header is captured; the IC1A chip arranged on the motherboard is controlled to generate an AC modulation current according to the drive signal; the optical power monitoring signal in the power supply circuit of the laser LD1 is acquired using a closed-loop tracking circuit; the closed-loop tracking circuit includes an operational amplifier chip IC3. The closed-loop tracking circuit is controlled to calculate the corresponding compensation current based on the optical power monitoring signal; the AC modulation current and the compensation current are combined and superimposed at the cathode node of the laser LD1 to form a total driving current that triggers the laser LD1 to emit a communication optical signal to the outside; wherein, the swing of the AC modulation current independently determines the extinction ratio of the communication optical signal, and the compensation current is superimposed on the AC modulation current as a separate DC bias baseline.

2. The method according to claim 1, characterized in that, The photocurrent is guided to the motherboard along the flexible PCB transmission path, including: The photocurrent output by the photodetector D1 is injected into the transmission traces arranged on the flexible PCB. The photocurrent is transmitted across space to the receiving node on the motherboard using transmission lines; The photocurrent is limited to flowing into the motherboard only at the receiving node, forming spatial isolation from the transmitting circuit used to drive the laser LD1, so as to block the crosstalk caused by the electromagnetic radiation generated by the transmitting circuit under the modulation of high current to the photocurrent.

3. The method according to claim 2, characterized in that, The passive resistor conversion network arranged on the motherboard converts the photogenerated current into an initial voltage signal, including: The photocurrent output by the photodetector D1 is controlled to flow through the passive resistor conversion network composed of resistors R14, R18 and R21, so as to be converted into the initial voltage signal with the corresponding amplitude; The initial voltage signal is controlled to be input to an integrated decision chip operating in an open-loop state. The initial voltage signal is converted into a digital logic level through open-loop level decision to generate an output electrical signal, including: The initial voltage signal is controlled to be input to the non-inverting input terminal of the comparator chip IC4, which is the integrated decision chip, via the resistor R14; A set decision threshold voltage is injected into the inverting input of the comparator chip IC4 based on a bias network containing resistor R11. When the comparator chip IC4 is operating without a closed-loop feedback loop, it compares the initial voltage signal with the decision threshold voltage, and outputs the simulated initial voltage signal as the digital logic level from the output terminal of the comparator chip IC4.

4. The method according to claim 3, characterized in that, Before guiding the output electrical signal to pin 3 of a single-row 4-pin header for output to an external terminal, the method further includes: Connect the first pin of the single-row 4-pin header to the ground network of the motherboard to establish a reference ground potential; Connect the fourth pin of the single-row 4-pin header to the motherboard's power network to obtain power supply voltage from the outside.

5. The method according to claim 4, characterized in that, The control chip IC1A, located on the motherboard, generates an AC modulated current based on a drive signal, including: Obtain the logic level state of the drive electrical signal input via the second pin of the single row of 4-pin header; The drive electrical signal is controlled to be input to the signal input terminal of the logic gate integrated chip IC1A; The switching transistors configured inside the logic gate integrated chip are triggered to perform a toggling action according to the logic level state to achieve switching between conduction and cutoff; Based on the switching action of the switching transistor, the logic gate integrated chip outputs a logic-flipped level signal from its inverting output terminal. The controlled level signal flows through the first current-limiting resistor and is injected into the cathode node of the laser LD1 to form the AC modulation current.

6. The method according to claim 5, characterized in that, The control of the closed-loop tracking circuit to calculate the corresponding compensation current based on the optical power monitoring signal includes: The backlight monitoring diode arranged inside the cavity of the laser LD1 absorbs backscattered photons and converts the absorbed photons into the optical power monitoring signal; The optical power monitoring signal is converted into a monitoring voltage via an input resistor and flows into the non-inverting input of the operational amplifier chip IC3; A reference bias voltage is injected into the inverting input terminal of the operational amplifier chip IC3 via a voltage divider resistor network using a power supply node to set a safe reference voltage; The operational amplifier chip IC3 is used to calculate the difference between the monitoring voltage and the safety reference voltage; An analog voltage containing the difference is generated from the output of the operational amplifier chip IC3 as the compensation current and is independently injected into the cathode node of the laser LD1 via the feedback resistor.

7. The method according to claim 6, characterized in that, Before acquiring the optical signal input to the photodetector D1, the method further includes: High-frequency noise is filtered out using a first decoupling capacitor connected between the power input terminal of the photodetector D1 and the analog ground network. When triggering the laser LD1 to emit a communication optical signal to the outside, the method further includes: using a second decoupling capacitor and a third decoupling capacitor connected in parallel on the power supply branch of the laser LD1 to provide a transient current pulse in order to smooth out the power bus voltage fluctuations caused by the AC modulation current.

8. The method according to claim 7, characterized in that, The step of combining and superimposing the AC modulation current and the compensation current at the cathode node of the laser LD1 includes: When the optical power monitoring signal indicates that the average output power of the laser LD1 has attenuated, the closed-loop tracking circuit is controlled to increase the output amplitude of the compensation current. The increased compensation current is directed to the cathode node of the laser LD1, causing the DC bias baseline in the total drive current to shift upward to counteract the threshold drift of the laser LD1, thereby forcing the average output power of the communication optical signal back to the stable range.

9. The method according to claim 8, characterized in that, After connecting the fourth pin of the single-row 4-pin header to the motherboard's power network to obtain power supply voltage from an external source, the method further includes: Detect the actual power supply voltage connected through the fourth pin; When it is determined that the actual power supply voltage falls into the first range, the integrated decision chip and the chip IC1A are configured to operate in the first bias state. When it is determined that the actual power supply voltage falls into the second range, the distribution ratio of the decision threshold voltage and the safety reference voltage of the operational amplifier chip IC3 are adjusted synchronously to configure the full-link transmit and receive bias to enter the second bias state.

10. The method according to claim 9, characterized in that, The method of transmitting photocurrent across space to the receiving node on the motherboard using transmission lines includes: Obtain the shielding potential of the ground layer that wraps around the transmission path of the flexible PCB; The shielding potential is interconnected with the motherboard's ground network; As the photocurrent flows along the transmission line, the grounding layer intercepts electromagnetic radiation energy injected from the external space to maintain the waveform of the photocurrent without distortion.

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