Chip, method for heterogeneous time synchronization and communication system supporting the same
Patent Information
- Application Number
- CN202611155938.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-07-31
- Publication Date
- 2026-11-03
Smart Images
Figure CN123034907A_ABST
Abstract
Description
Technical Field
[0001] This disclosure belongs to the field of communication technology, and specifically relates to a chip, a method for heterogeneous time synchronization, and a communication system that support heterogeneous time synchronization. Background Technology
[0002] With the evolution of 6G communication technology, optical transmission networks (SPN / MTN / OTN / fgOTN / OSU) carry a wide variety of service interfaces, and different types of service interfaces generate high-precision heterogeneous time synchronization requirements.
[0003] Meanwhile, the increasing integration of chips and the wide variety of compatible service interfaces, along with the need for extensive adaptation to service interfaces with different rates, have continuously increased the difficulty of implementing the internal time synchronization system of optical transmission chips. When chips need to adapt to multiple service interfaces and implement heterogeneous time synchronization functions, deficiencies in areas such as whether the time sources are the same, time expression accuracy, and synchronization convergence efficiency become increasingly prominent.
[0004] Existing technical solutions have several shortcomings: First, most chips cannot achieve time synchronization from different sources; second, in the case of time synchronization from the same source, if IEEE1588 synchronization and delay measurement synchronization are enabled at the same time, the IEEE1588 synchronization process must be completed first before delay measurement synchronization can be performed, resulting in a long overall synchronization cycle. Fluctuations in the synchronization source can also cause interference superposition. In addition, different synchronization services will introduce jitter interference to each other during operation, and in severe cases, the synchronization cannot converge, becoming a performance bottleneck for the practical application of existing time synchronization systems. Summary of the Invention
[0005] To address the aforementioned issues, this disclosure provides a chip that supports heterogeneous time synchronization. This chip has the advantage of being able to quickly and accurately synchronize heterogeneous time systems within the chip itself. The chip is equipped with at least two time engines and a fast time interface corresponding to each time engine. Each time engine generates an independent global timestamp. The chip is configured as follows: Receive fast time frames sent by external devices through the fast time interface; Extract time information within a fast time frame and compare it with the global timestamp of the corresponding time engine. Then, calibrate the global timestamp of the corresponding time engine based on the difference in the comparison. The global timestamp calibrated by the time engine is encapsulated to generate a processed fast time frame; The processed fast time frame is output through the fast time interface.
[0006] Furthermore, the fast time frame and the processed fast time frame have a unified fixed-length frame structure, which includes: a frame header, a state byte, a payload field carrying time information, a check field, and reserved bits; wherein, the check field is used to check all contents from the state byte to the payload field.
[0007] Furthermore, the state byte is configured with multiple sets of bit flags, which are used to identify the synchronization status of time information at each level and the synchronization status of frame valid pulses, respectively. When the time information of the corresponding level is matched, the corresponding bit is set. The chip is configured to determine whether synchronization is completed based on preset bit conditions.
[0008] Furthermore, the chip is configured as follows: Receive configuration commands from outside the chip; The chip parameters of the chip are adjusted according to the configuration instructions.
[0009] Furthermore, the chip is configured as follows: According to the received configuration instructions, the fast time interface parameters are adjusted to adjust the fast time frame transmission and reception frequency; the fast time interface parameters include: clock and baud rate.
[0010] Furthermore, the chip is configured as follows: Based on the received configuration instructions, control the opening and closing of any number of time engines and the opening and closing of any number of fast time interfaces.
[0011] Furthermore, the chip is configured as follows: Configure the global timestamp for any time engine based on the received configuration instructions.
[0012] Furthermore, the chip is configured as follows: Before encapsulating the global timestamp calibrated by the time engine into a processed fast time frame, the calibrated global timestamp is compensated and its format converted according to business requirements.
[0013] This disclosure also proposes a heterogeneous time synchronization method, which is implemented based on the chip that supports heterogeneous time synchronization described above.
[0014] This disclosure also proposes a communication system that performs heterogeneous time synchronization based on the aforementioned chip that supports heterogeneous time synchronization.
[0015] Compared with the prior art, this disclosure has the following advantages: (1) The chip disclosed herein has at least two independent time engines, each paired with a corresponding fast time interface. The fast time frame sent by the external device can be compared and calibrated with the global timestamp of the corresponding time engine. The calibrated global timestamp is then encapsulated into a processed fast time frame for external output. Multiple independent time engines and paired fast time interfaces can process external heterogeneous time information respectively, realizing multi-path independent time interaction and calibration. The chip natively supports heterogeneous time synchronization scenarios, solving the defect that existing chips cannot adapt to heterogeneous time synchronization. (2) This disclosure generates uncoupled global timestamps by using multiple independently running time engines. Different synchronization services can work in parallel with the time information output by different time engines, without waiting for one type of synchronization process to complete before starting another type of synchronization. At least two types of service time synchronization can be achieved at the same time, which greatly shortens the overall synchronization time and avoids the waiting delay problem caused by serial synchronization. (3) Each time engine and fast time interface form an independent time processing link. Fluctuations generated by a single synchronization source only affect the corresponding link and will not cause interference to other synchronization links. The synchronization convergence process of each service is isolated from each other. The jitter generated by one service synchronization will not be transmitted to other synchronization services, effectively avoiding the system bottleneck of jitter interference and synchronization failure. (4) The chip can receive external configuration instructions, flexibly control the start and stop of the time engine and fast time interface, customize the global timestamp, interface clock and baud rate and other parameters, adapt to different rates and multiple types of SPN / MTN / OTN / fgOTN / OSU optical transmission service interfaces, with a wide range of adaptability, reducing the implementation complexity of time synchronization system in multi-interface compatibility scenarios. (5) The fast time frame with uniform specifications has a built-in state byte after processing. It accurately identifies the time synchronization status of each level by relying on the bit flag. The chip determines the synchronization completion status according to the preset bit conditions. The time synchronization status identification logic is clear and the synchronization judgment is highly reliable. (6) Before the global time frame is packaged after calibration, the chip can complete time compensation and format conversion as needed, adapt to the time data output standards of different services, and can be widely used in 6G bearer optical transmission communication systems to meet the needs of time synchronization of multiple scenarios with the same source and different sources.
[0016] Other features and advantages of this disclosure will be set forth in the following description and will be apparent in part from the description or may be learned by practicing the disclosure. The objects and other advantages of this disclosure may be realized and obtained by means of the structures pointed out in the description, claims and drawings. Attached Figure Description
[0017] To more clearly illustrate the technical solutions in the embodiments of this disclosure or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0018] Figure 1 A chip architecture supporting heterogeneous time synchronization according to an embodiment is shown; Figure 2 A chip architecture supporting heterogeneous time synchronization according to another embodiment is shown; Figure 3 The frame structure of a fast time frame according to an embodiment is shown. Detailed Implementation
[0019] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.
[0020] To achieve heterogeneous time synchronization within a chip, this disclosure proposes a chip that supports heterogeneous time synchronization, such as... Figure 1 As shown, the chip has at least two time engines and a fast time interface corresponding to each time engine; wherein, different time engines generate independent global timestamps. The chip is configured as follows: Receive fast time frames sent by external devices through the fast time interface; Extract time information within a fast time frame and compare it with the global timestamp of the corresponding time engine. Then, calibrate the global timestamp of the corresponding time engine based on the difference in the comparison. The global timestamp calibrated by the time engine is encapsulated to generate a processed fast time frame; The processed fast time frame is output through the fast time interface.
[0021] According to some embodiments of this disclosure, the chip supporting heterogeneous time synchronization proposed in this disclosure includes at least two time engines and a fast time interface corresponding to each time engine. The chip receives fast time frames sent by external devices through the fast time interface, extracts the time information in the fast time frame and compares it with the global timestamp of the corresponding time engine, calibrates the global timestamp of the corresponding time engine based on the comparison difference, encapsulates the calibrated global timestamp of the time engine to generate a processed fast time frame, and outputs the processed fast time frame through the corresponding fast time interface. Different paired links independently complete the entire process of receiving external fast time frames, calibrating local timestamps, and outputting processed fast time frames. Different time engines and their global timestamps are independent of each other and are not affected by the synchronization fluctuations of the other link. Multiple sets of independent time processing links can simultaneously process multiple external heterogeneous time bases, realizing multi-channel parallel heterogeneous time synchronization.
[0022] Furthermore, the fast time frame and the processed fast time frame have a unified fixed-length frame structure, which includes: a frame header, a state byte, a payload field carrying time information, a check field, and reserved bits; wherein, the check field is used to check all contents from the state byte to the payload field.
[0023] According to some embodiments of this disclosure, the fast time frame is 16 bytes in total. First, there is a two-byte frame header, and the third byte is the state byte. The fourth to fifteenth bytes are the payload field responsible for carrying time information. The time information consists of a 4-byte second field, a 4-byte nano second field, and a 30-bit fraction nano second field. The last byte is a CRC8 check field byte, used to verify the information content from the state byte to the entire payload field. The high 4 bits of the state byte and the low 2 bits of the last byte of the payload field information are defined as reserved information.
[0024] Furthermore, the state byte is configured with multiple sets of bit flags, which are used to identify the synchronization status of time information at each level and the synchronization status of frame valid pulses, respectively. When the time information of the corresponding level is matched, the corresponding bit is set. The chip is configured to determine whether synchronization is completed based on preset bit conditions.
[0025] According to some embodiments of this disclosure, the fast time frame format is characterized by a 16-byte frame structure, which must contain a frame header byte, a state indication byte, and must include a time second field, a nano second field, a 30-bit fraction nano second field, and a CRC field for verification. The time information in its payload field is derived from the time engine and has undergone synchronization processing.
[0026] Furthermore, each bit of the state byte corresponds to the synchronization status of different time domains of the fast time frame and the frame's valid pulse; the chip is configured to: set the corresponding bit when the received frame time information matches the local global timestamp, or when the pulse marker edge is aligned, and determine the time synchronization status of the corresponding link by monitoring the set state combination of the specified bit bits.
[0027] According to some embodiments of this disclosure, in the state byte of the custom fast time frame, the state[2:0] bits correspond to the synchronization indicator flags that identify the time synchronization status of the second field, nano second field, and fraction nanosecond field in the fast time frame information, respectively. state[3] indicates the synchronization status of the fast time frame valid indicator pulse flag. That is, when the second value of the i-th received channel is the same as the second value of the local synchronized Global Timestamp, the corresponding state[2] indicator flag is set; when the comparison values of the corresponding nano second are the same, the corresponding state[1] indicator flag is set; when the comparison values of the corresponding fraction nano second are the same, the corresponding state[0] indicator flag is set; when the rising edge of the fast time frame valid indicator pulse flag is aligned, the corresponding state[3] indicator flag is set. The specific application of the state byte is as follows: the state[2] and state[1] of the m-th fast time interface are monitored, and the synchronization processing of the time information of the corresponding time engine and the second and nano second fields of the fast time interface received information is executed. When it is detected that both the received state[2:1] and the state[2:1] bits to be sent are set, it indicates that the time system of the service corresponding to the m-th fast time interface has been synchronized.
[0028] Furthermore, the chip is configured as follows: Receive configuration commands from outside the chip; The chip parameters of the chip are adjusted according to the configuration instructions.
[0029] According to some embodiments of this disclosure, the chip supporting heterogeneous time synchronization proposed in this disclosure also has a receiving module for receiving external configuration instructions. The chip can receive external configuration instructions through the receiving module and adjust its own parameters through the external configuration instructions.
[0030] Furthermore, the chip is configured as follows: According to the received configuration instructions, the fast time interface parameters are adjusted to adjust the fast time frame transmission and reception frequency; the fast time interface parameters include: clock and baud rate.
[0031] According to some embodiments of this disclosure, the chip defaults to transmitting and receiving fast time frames at 50 times per second, which is equivalent to a frequency of 20ms interval. To achieve different synchronization applications, the transmission and reception frequency can be configured by sending configuration commands to the chip to set parameters such as the clock and baud rate of the fast time interface.
[0032] Furthermore, the chip is configured as follows: Based on the received configuration instructions, control the opening and closing of any number of time engines and the opening and closing of any number of fast time interfaces.
[0033] According to some embodiments of this disclosure, the chip that supports heterogeneous time synchronization proposed in this disclosure enables one time engine and its corresponding fast time interface among all time engines by default. It can control the opening and closing of any time engine and its corresponding fast time interface by sending configuration instructions to the chip.
[0034] Furthermore, the chip is configured as follows: Configure the global timestamp for any time engine based on the received configuration instructions.
[0035] According to some embodiments of this disclosure, after an external configuration command is sent to the chip, the chip can independently assign initial time values and configure time offsets for the global timestamps corresponding to different time engines. The global timestamp configurations of the two time engines are independent of each other and do not affect each other. The time base of any time engine can be modified as needed to adapt to the initial time requirements of different services in multi-source / heterogeneous time synchronization scenarios.
[0036] Furthermore, the chip is configured as follows: Before encapsulating the global timestamp calibrated by the time engine into a processed fast time frame, the calibrated global timestamp is compensated and its format converted according to business requirements.
[0037] According to some embodiments of this disclosure, before encapsulating the global timestamp calibrated by the time engine to generate a processed fast time frame, the calibrated global timestamp is compensated and its format is converted according to business requirements to meet the time data output requirements of different synchronization services.
[0038] The above solution will be further explained below with reference to the embodiments.
[0039] Figure 2 The chip architecture corresponding to a preferred embodiment employing a dual-time engine and a fast time interface is shown. Figure 2The chip shown includes a time generation module (containing two time engines, Global-1 and Global-2) and a fast time interface module (containing two fast time interfaces, namely the first fast time interface and the second fast time interface). Global-1 is used to generate a global timestamp, Global Timestamp-1, and Global-2 is used to generate a global timestamp, Global Timestamp-2. Global Timestamp-1 and Global Timestamp-2 do not interfere with each other. The chip receives fast time frames sent by external devices through the fast time interface; extracts the time information within the fast time frame and compares it with the global timestamp of the corresponding time engine; calibrates the global timestamp of the corresponding time engine based on the comparison difference; encapsulates the calibrated global timestamp to generate a processed fast time frame; and outputs the processed fast time frame through the fast time interface. Taking the pairing of the first fast time interface with Global-1 and the second fast time interface with Global-2 as an example, after receiving the fast time frame sent from the outside, the first fast time interface extracts the time information within the frame and compares it with Global Timestamp-1. Based on the comparison difference, it completes the calibration of Global Timestamp-1 and encapsulates it to generate a processed fast time frame, which is then output by the first fast time interface. The second fast time interface synchronously and independently executes the entire time synchronization process, completing the comparison, calibration, and frame output operations with Global Timestamp-2 for the external fast time frame. The two paired links independently complete the entire process of receiving external frames, calibrating local timestamps, and outputting processed frames. Global Timestamp-1 and Global Timestamp-2 are independent of each other and are not affected by the synchronization fluctuations of the other link.
[0040] In this embodiment, the time source of the IEEE 1588 system is connected to the first fast time interface, and the time source of the delay measurement system is connected to the second fast time interface. The two time sources are different. It should be understood that this connection method does not constitute a limitation on the scheme disclosed herein. After the chip starts working, the circuit that enables the i-th (i∈[1,2]) fast time interface is enabled by default. Related control modules inside the chip (such as...) Figure 2 When the global management module (as shown) detects that IEEE1588 and delay measurement are connected to different fast time interfaces or that the control module is enabled by configuring the heterogeneous time mode, the control module controls the activation of the second fast time interface function. At the same time, the control module enables the dual-source indicator flag two_src_ind control signal to be valid and sends it to the relevant module.
[0041] Accordingly, when the time generation module receives and detects that the dual-source indicator flag two_src_ind signal from the control module is valid, it activates the dual-time engine function, thereby generating a global timestamp for each time engine. The internal structure of the dual-time engine time information is as follows: Global Timestamp-1 is a 94-bit structure consisting of 32-bit second, 32-bit nano second, and 30-bit fraction nano second; Global Timestamp-2 is also a 94-bit structure consisting of 32-bit second, 32-bit nano second, and 30-bit fraction nano second.
[0042] Accordingly, the time generation module will start running with the Global Timestamp-1 time value generated by the time engine of the first fast time interface it uses, starting from the preset initial time As.B-ns.C-fraction_ns. The time generation module will also start running with the Global Timestamp-2 time value generated by the time engine of the second fast time interface, starting from the preset initial time Ds.E-ns.F-fraction_ns. The preset values for A and D, B and E, C and F for the time information generated by each time engine can be the same or all different.
[0043] Accordingly, the fast time interface modules of the first and second channels perform their respective receiving and sending of fast time frame information according to the fast time frame format defined in this disclosure.
[0044] The content definitions of the second, nano second, and fraction nano second fields in the custom fast time frame format payload field information are consistent with the information structure of the time information Global Timestamp-1 and Global Timestamp-2.
[0045] Correspondingly, the frame structure of the custom fast time frame is as follows: Figure 3As shown, the overall 16-byte fast time frame format structure begins with a two-byte frame header. In this embodiment, the values of the two-byte frame header configured in the first and second fast time frames are 0x46 and 0x48, respectively. The third byte is the state byte, and the fourth to fifteenth bytes are the payload field responsible for carrying the time information for synchronization processing. The time information consists of a 4-byte second field, a 4-byte nano second field, and a 30-bit fraction nano second field. The last byte is a CRC8 checksum byte, used to verify the information content from the state byte to the entire payload field. The high 4 bits of the state byte and the low 2 bits of the last byte of the payload field information are defined as Reserved information, where the Reserved value is 0.
[0046] Among them, in the state byte of the custom fast time frame, the state[2:0] bits correspond to the synchronization indicator flags that identify the time synchronization status of the second field, nano second field, and fraction nano second field in the fast time frame information, respectively. state[3] indicates the synchronization status of the valid indicator pulse flag of the fast time frame. That is, when the second value of the i-th (i ∈ [1, 2]) received channel is the same as the second value of the Global Timestamp after local synchronization processing, the corresponding state[2] indicator flag is set; when the comparison values of the corresponding nano second are the same, the corresponding state[1] indicator flag is set; when the comparison values of the corresponding fraction nano second are the same, the corresponding state[0] indicator flag is set; when the rising edge of the valid indicator pulse flag of the fast time frame is aligned, the corresponding state[3] indicator flag is set.
[0047] Correspondingly, the fast time interface modules of channels 1 and 2 on the receiving side each execute the receiving frame header byte under the fast time frame valid indication pulse. When all received frame header bytes match, they continue to receive and detect the state status byte indication of the frame and sequentially receive all time information in the payload field of their respective fast time frames. The state status and related information are then sent to the fast time adaptation module.
[0048] Correspondingly, the fast time adaptation module receives the time information from the corresponding engine of the time generation module, and uses the receiving timing pulse edges of the two fast time frame valid indicator pulses to obtain their respective internal real-time Global Timestamp-1 and Global Timestamp-2 times. Simultaneously, it matches these times with the frame time information received from the two fast time interfaces, performing a comparison of the second, nano second, and fraction nano second fields for each field. The comparison difference for each field is fed back to the global management module. The global management module, based on the delay introduced by each fast time interface, uses a compensation configuration value to superimpose the corresponding time information difference, and reports the final comparison difference information to the external main control CPU, while simultaneously sending it to the time generation module. The time generation module receives all compensation and comparison difference values and control information from the global management module. After matching to its respective time engine according to the valid dual-source indicator flag two_src_ind signal, it performs synchronization processing on the matched time information according to its respective compensation and comparison difference information, and sends the processed Global Timestamp-1 and Global Timestamp-2 time values to the fast time adaptation module and the time distribution module. It should be noted that the global management module's functions include: receiving relevant CPU configuration and control information, reporting relevant monitoring information and alarms as needed, and completing the monitoring and control of the overall synchronization application scenario's time engine and synchronization time source operations. Based on the time synchronization system's application scenario, the global management module flexibly manages the synchronization sources used by each module, specifying Global-1 source or / and Global-2 source information, and flexibly manages the enabling and disabling of the fast time interface and dual time engines. It manages and monitors the fast time adaptation module's time information, compares differences, and reports state status; manages and controls the time information preset of the time generation module, and compares and reports, and overlays compensation of the engine's real-time time information. It also manages and controls the time distribution module to perform compensation operations according to its respective time source, and to perform time conversion and distribution to the PTP synchronization module and / or the DM delay measurement module.
[0049] Correspondingly, when the fast time adaptation module detects that the comparison difference value of the corresponding time information field is 0, it sets the state status bit of the corresponding fast time interface. When it detects that the corresponding bits of both the received state status and the state status to be sent are set, it indicates that the field has been synchronized. When it detects that all bits of both the received state status and the state status to be sent are set, it indicates that synchronization has been achieved. The time information and state are then reported externally, such as to an external main control CPU.
[0050] Among them, the synchronization method determined by the fast time adaptation module is primarily controlled by the synchronization application requirements. For example, if the application configures the second and nano second fields in the delay measurement system to be synchronized, while the nano second field in the PTP synchronization system is synchronized, then in this embodiment, the fast time adaptation module monitors the state[2] and state[1] received by the second fast time interface, and performs the synchronization processing of the time information of the time engine corresponding to the delay measurement system and the second and nano second fields of the information received by the fast time interface. When it is detected that the received state[2:1] and the state[2:1] to be sent are both set, it indicates that the time system of delay measurement has been synchronized; the fast time adaptation module also monitors the state[1] received by the first fast time interface, and performs the synchronization processing of the time information of the time engine corresponding to the PTP synchronization system and the nano second field of the information received by the corresponding fast time interface. When it is detected that the received state[1] and the state[1] to be sent are both set, it indicates that the time system of PTP synchronization has been synchronized, thereby completing the heterogeneous time synchronization.
[0051] Correspondingly, the fast time adaptation module matches all the synchronized second, nano second, and fraction nano second information to the corresponding two fast time interfaces, and generates their respective fast time frame valid indication pulse signals according to the time information. Simultaneously, the fast time adaptation module detects all transmitted state values and the synchronized transmission of Global Timestamp-1 and Global Timestamp-2 time information, and sends them along with the fast time frame valid indication pulse signals to the matched fast time interface modules. The first and second fast time interface modules first send the frame header bytes of the fast time frame, configuring both headers to send corresponding header byte values of 0x46 and 0x48 respectively. Then, they sequentially send the state bytes received from the fast time adaptation module and the payload field time information, and generate the corresponding CRC8 checksum bytes to form a complete fast time frame, which is then sent from their respective fast time interfaces. The second, nano second, and fraction nano second fields of the payload field time information sent by each channel are all derived from the synchronized Global Timestamp-1 and Global Timestamp-2 time information from the corresponding time engine of the time generation module.
[0052] Accordingly, the clock and baud rate parameters of each fast time interface are configured to make the fast time frame 50 times per second, which is a frequency of 20ms interval. To achieve different synchronization applications, a higher frequency can be achieved by configuring different clock and baud rate parameters of the fast time interface.
[0053] Accordingly, the time distribution module receives the time information of Global Timestamp-1 and Global Timestamp-2 after synchronization processing by the time generation module. Simultaneously, it monitors and receives the two_src_ind dual-source indicator flag from the global management module. If the two_src_ind indicator flag is valid or the heterogeneous time mode is enabled, the module sequentially completes the matching and compensation operations of Global Timestamp-1 and Global Timestamp-2 according to the control information configured for each of the two synchronous applications. Then, the Global Timestamp-1 time information is further converted to the IEEE 1588 system time and distributed to the PTP synchronization module, while the Global Timestamp-2 time information is converted to the delay measurement system time and distributed to the delay measurement module. Thus, the technical solution proposed in this disclosure can complete the time synchronization process of heterogeneous time sources.
[0054] Based on the same technical concept, this disclosure also proposes a heterogeneous time synchronization method, which is implemented based on the chip that supports heterogeneous time synchronization described above.
[0055] Based on the same technical concept, this disclosure also proposes a communication system that performs heterogeneous time synchronization based on the aforementioned chip that supports heterogeneous time synchronization.
[0056] Although the present disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present disclosure.
Claims
1. A chip supporting heterogeneous time synchronization, characterized in that: The chip has at least two time engines and a fast time interface corresponding to each time engine; wherein, different time engines generate independent global timestamps. The chip is configured as follows: Receive fast time frames sent by external devices through the fast time interface; Extract time information within a fast time frame and compare it with the global timestamp of the corresponding time engine. Then, calibrate the global timestamp of the corresponding time engine based on the difference in the comparison. The global timestamp calibrated by the time engine is encapsulated to generate a processed fast time frame; The processed fast time frame is output through the fast time interface.
2. The chip as described in claim 1, characterized in that, The fast time frame and the processed fast time frame share a unified fixed-length frame structure, comprising: a frame header, a state byte, a payload field carrying time information, a checksum field, and reserved bits; wherein... The verification field is used to verify all contents from the state byte to the payload field.
3. The chip as described in claim 2, characterized in that, The state byte sets multiple sets of bit flags, which are used to identify the synchronization status of time information at each level and the frame valid pulse synchronization status, respectively. When the time information of the corresponding level is matched, the corresponding bit is set. The chip is configured to determine whether synchronization is complete based on preset bit conditions.
4. The chip as described in claim 1, characterized in that, The chip is configured as follows: Receive configuration commands from outside the chip; The chip parameters of the chip are adjusted according to the configuration instructions.
5. The chip as described in claim 4, characterized in that, The chip is configured as follows: According to the received configuration instructions, the fast time interface parameters are adjusted to adjust the fast time frame transmission and reception frequency; the fast time interface parameters include: clock and baud rate.
6. The chip as described in claim 4, characterized in that, The chip is configured as follows: Based on the received configuration instructions, control the opening and closing of any number of time engines and the opening and closing of any number of fast time interfaces.
7. The chip as described in claim 4, characterized in that, The chip is configured as follows: Configure the global timestamp for any time engine based on the received configuration instructions.
8. The chip as described in claim 4, characterized in that, The chip is configured as follows: Before encapsulating the global timestamp calibrated by the time engine into a processed fast time frame, the calibrated global timestamp is compensated and its format converted according to business requirements.
9. A heterogeneous time synchronization method, characterized in that, The heterogeneous time synchronization method is implemented based on the chip supporting heterogeneous time synchronization as described in any one of claims 1-8.
10. A communication system, characterized in that, The communication system performs heterogeneous time synchronization based on the chip supporting heterogeneous time synchronization as described in any one of claims 1-8.