A method of carrier and timing synchronization for a multi-rate receiver and related apparatus

Abstract

The application discloses a carrier and timing synchronization method of a multi-rate receiver and a related device, relates to the technical field of digital communication, and is used for carrier and symbol timing recovery, solves the problems that matching filter group delay and low-rate residual frequency offset cannot be compatible, and timing phase discrimination is interfered by data symbol amplitude. The method determines extraction parameters according to a symbol rate and completes coarse carrier frequency offset capture; the integral component of a carrier loop filter is used to update a first local oscillator phase sample by sample, first-stage digital down conversion and matching filtering are sequentially performed on an input signal; the variation of the first local oscillator phase within the matching filter group delay is taken as a group delay feedforward amount, and the sum of the group delay feedforward amount and a proportional component is taken as a second-stage rotation angle symbol rotation; the difference between the energy of a leading sample and the energy of a lagging sample is normalized according to the energy of a quasi-time sample to obtain a timing error amount, and the symbol timing step is corrected according to the timing error amount. The application has the advantages of rate grade multiplexing configuration, decision point phase deviation cancellation and phase discrimination without a symbol amplitude factor.

Description

Technical Field

[0001] This application relates to the field of digital communication technology, and in particular to a carrier and timing synchronization method and related apparatus for a multi-rate receiver. Background Technology

[0002] In satellite communication, telemetry, remote control, and data relay links, the same receiver often needs to operate at multiple symbol rates, with the rate span reaching an order of magnitude. The signal at the receiving end is superimposed with the local oscillator frequency deviation and the Doppler frequency offset caused by carrier motion. The sampling time is also not aligned with the symbol beat at the transmitting end. The receiver must first restore the carrier frequency and phase to the accuracy usable for decision-making, and then align the decision time with the point of highest signal-to-noise ratio on the symbol waveform in order to correctly decode the data. The carrier synchronization loop and the symbol timing synchronization loop share the same digital baseband processing chain. The matched filter in the link not only provides the maximum signal-to-noise ratio for decision-making but also determines the bandwidth within which the signal is restricted before entering the decision stage.

[0003] Low symbol rate settings are typically used in long-distance applications with limited transmit power. The link margin is already insufficient, and if synchronization fails to be established or tracking is lost midway, the entire link is interrupted, and all data during reacquisition is lost. Furthermore, the entire system is usually required to be implemented in a fixed-point manner on a single programmable logic device. If a separate set of decimation ratios, transformation points, detection thresholds, and loop coefficients is configured for each symbol rate setting, the on-chip resources and debugging workload increase with the number of supported rates.

[0004] Existing carrier and timing synchronization schemes treat each link as an independent module and tune them separately. The criteria required for each link can only be estimated or assumed to be ideal. However, these criteria are actually scattered in other links of the link as intermediate quantities and are not used. Therefore, the position and parameter selection of each part of the link become a trade-off that cannot be satisfied. The passband width of the matched filter is proportional to the symbol rate, while the carrier frequency offset is an absolute quantity independent of the symbol rate. When the symbol rate decreases, the passband narrows accordingly. The same amount of residual frequency offsets outside the passband. Placing the entire carrier correction after the matched filter will cause the signal to be filtered out as an out-of-band component before reaching the correction stage. Placing the entire carrier correction before the matched filter will cause the group delay to fall into the feedback loop. The open-loop phase will be additionally lost at the gain crossing point by the product of the group delay and the crossing frequency. When the phase margin is insufficient, phase sway will occur until the lock is lost. In order to maintain stability, the loop bandwidth must be reduced, and the acquisition time will be lengthened accordingly, and the tracking ability of Doppler changes will decrease. The group delay is originally a quantity determined in the design stage, but because it is not used, it can only be regarded as an obstacle that must be avoided.

[0005] The same situation occurs during the synchronization establishment process. The initial estimation of the carrier frequency offset requires integrating and accumulating the signal before eliminating the modulation phase. The integration window must not cross the symbol boundary to avoid cancellation due to data phase jumps, thus relying on the established symbol timing. The leading and lagging samples used for symbol timing are taken from the neighborhood of the decision time, relying on the converged carrier phase. The phase error of carrier fine tracking is taken from the decision result, relying on the aligned decision time. The three are interdependent and none can be closed first. The timing criterion itself is also not clean. The energy difference between the leading and lagging samples is proportional to both the timing deviation and the current symbol energy. After the random data is shaped and filtered, the amplitude of the neighborhood of the decision time fluctuates with the data pattern, while the current symbol energy has been calculated at the same time but has not participated in the construction of the criterion. Summary of the Invention

[0006] In order to enable the criteria required by each link in the synchronization link to be taken from the intermediate values ​​that already exist in the link, and to alleviate the trade-offs in the selection of the matched filter position and parameter tuning, this application provides a carrier and timing synchronization method and related apparatus for a multi-rate receiver.

[0007] Firstly, this application provides a carrier and timing synchronization method for a multi-rate receiver, employing the following technical solution:

[0008] A carrier and timing synchronization method for a multi-rate receiver includes the following steps:

[0009] S1. Determine the decimation parameters based on the symbol rate, so that the decimated sampling rate is a preset multiple of the symbol rate;

[0010] S2. Perform coarse carrier frequency offset acquisition on the input signal according to the extraction parameters to obtain the estimated carrier frequency offset value, and load it into the first-stage local oscillator;

[0011] S3. The carrier phase error is filtered by the carrier loop filter to obtain the integral component and the proportional component. The first-stage local oscillator phase is updated with the integral component at each sampling point. The first-stage digital down-conversion and matched filtering are performed on the input signal in sequence to obtain the first-stage down-converted signal and the matched filtered signal, respectively.

[0012] S4. The change in the phase of the first-stage local oscillator within the group delay of the matched filter is taken as the group delay feedforward.

[0013] S5. Using the sum of the proportional component and the group delay feedforward as the second-stage rotation angle, perform phase rotation of the matched filter signal symbol by symbol using the second-stage rotation angle to obtain the second-stage down-conversion signal;

[0014] S6. Perform carrier phase detection on the second-stage down-conversion signal to obtain the carrier phase error;

[0015] S7. At the decision time, take the punctual sample, leading sample and lagging sample of the second-level down-conversion signal, and normalize the difference between the energy of the leading sample and the lagging sample with the energy of the punctual sample to obtain the timing error.

[0016] S8. The timing error is corrected by the proportional branch of the timing loop filter to advance the symbol timing step, and the subsequent decision time is determined according to the symbol timing step. S3 to S8 are executed cyclically.

[0017] By adopting the above technical solution, the decimation parameters normalize the sampling rate after decimation with the symbol rate, and the criterion of the acquisition stage no longer drifts with the rate; the integral component of the carrier loop filter is a slow variable, which is not attenuated after the group delay of the matched filter, so the first stage responsible for frequency offset correction can be placed before the matched filter, and the residual frequency offset at low symbol rates is eliminated before the frequency band is limited by the matched filter; the change of the local oscillator phase in the group delay of the first stage is a definite quantity that already exists in the link and can be directly used. Adding it to the proportional component constitutes the second stage rotation angle, so that the phase lag caused by the matched filter is canceled before the decision, while the fast-changing proportional component is applied after the matched filter, and its feedback path does not contain a finite impulse response filter.

[0018] Optionally, in S4, the first-stage local oscillator phase is delayed by a delay line, the depth of the delay line is equal to the group delay beat number of the matched filter, and the group delay feedforward measures the difference between the current value of the first-stage local oscillator phase and the output value of the delay line.

[0019] By adopting the above technical solution, the feedforward quantity is taken from the difference between the current value and the delay value of the first-stage local oscillator phase. This difference is always equal to the actual cumulative phase within the lag interval. This also holds true in the stage where the carrier loop is drawn in and the integral component is still changing, without relying on assumptions about the phase change law.

[0020] Optionally, in S1, the symbol rate range is divided into multiple rate levels, and the rate level to which the symbol rate belongs is determined as the current rate level.

[0021] The depth of the delay line is taken as the number of group delay cycles of the matched filter at the current rate level;

[0022] The loop gain of the carrier loop filter decreases as the ratio of the depth of the delay line to the number of input samples per symbol at the current rate setting increases, where the number of input samples per symbol is the ratio of the sampling rate of the input signal to the symbol rate.

[0023] By adopting the above technical solution, the delay line depth and loop gain switch synchronously with the current rate setting, and the change in group delay converted to symbol number is compensated by the loop gain, so that the same set of loop parameters maintains similar phase margins at multiple rate settings.

[0024] Optionally, during the execution of S3 to S8, an enable determination operation is also performed, which includes carrier frequency offset convergence determination and timing lock determination performed sequentially.

[0025] The carrier frequency offset convergence determination is made when the change of the integral component within the preset observation window is lower than the preset convergence threshold. The preset observation window is counted based on the update sampling points of the first-level local oscillator phase.

[0026] The timing lock determination is determined when the sliding variance of the timing error is lower than a preset lock threshold and remains no less than a preset number of symbols after the carrier frequency offset convergence determination is established.

[0027] S7 and S8 are executed from the moment the carrier frequency offset convergence determination is established.

[0028] The proportional gain of the carrier loop filter is reduced to a value lower than the nominal value before the timing lock determination is made.

[0029] The carrier phase detection is achieved by performing a demodulation transformation to eliminate the modulation phase on the second-level downconversion signal before the timing lock determination is established, and by the decision result of the second-level downconversion signal after the timing lock determination is established.

[0030] By adopting the above technical solution, the carrier loop is closed from the first downconversion stage, and the timing loop is engaged and the proportional gain is restored sequentially according to whether the prior is available. The carrier phase detection before timing lock does not depend on the decision result, and the phase error can still be extracted when the decision time is not yet aligned.

[0031] Optionally, in S8, the correction of the symbol timing step is performed in parallel as S8a and S8b:

[0032] S8a. In response to the correction interval of the symbol timing step being greater than one symbol, the correction time of the symbol timing step is staggered from the update time of the second-level rotation angle by different symbols;

[0033] S8b. In response to the symbol timing step-by-symbol correction, the product of the residual frequency offset after the first-level digital down-conversion and the correction amount of the current symbol timing step is used as the phase reference offset. The carrier phase error is offset compensated according to the phase reference offset. The residual frequency offset after the first-level digital down-conversion is calculated from the difference of the second-level rotation angle between two adjacent symbols.

[0034] By adopting the above technical solution, the symbol timing step and the second-level rotation angle act at the same decision time, and their updates are staggered to avoid mutual injection of disturbances; when symbol-by-symbol correction cannot be staggered, the product of the residual frequency deviation after the first-level digital downconversion and the step correction amount is used to compensate for the movement of the phase reference.

[0035] Optionally, in S2, the carrier frequency offset coarse acquisition includes integral accumulation decimation performed on the input signal according to the decimation parameters, demodulation transformation to eliminate the modulation phase performed on the decimation result, and frequency domain transformation and spectral peak retrieval performed on the transformation result;

[0036] In step S1, the extraction parameters also satisfy the following extraction constraints:

[0037] The extracted sampling rate is greater than twice the product of the order of the demodulation transform and the preset maximum carrier frequency offset;

[0038] The ratio of the extracted sampling rate to the number of points in the frequency domain transformation is not greater than the preset frequency resolution;

[0039] The extraction parameter is not greater than the number of samples per symbol and is divisible by the number of samples per symbol, where the number of samples per symbol is the ratio of the sampling rate of the input signal to the symbol rate.

[0040] By adopting the above technical solution, the extraction parameters are simultaneously constrained by three factors: non-aliasing, frequency resolution, and no crossing of symbols. The values ​​are determined by the symbol rate and the preset maximum carrier frequency offset. The integral accumulation window does not cross the symbol boundary, and the cancellation loss when the symbol timing has not yet been established is limited to within one symbol.

[0041] Optionally, during the execution of S3, a fine capture operation is also performed, which includes the following steps in sequence:

[0042] The preset frequency resolution serves as the residual upper bound of the carrier frequency offset estimate.

[0043] The fine acquisition decimation parameters are determined by replacing the preset maximum carrier frequency offset with the residual upper bound, and the fine acquisition decimation parameters are greater than the decimation parameters.

[0044] The first-stage downconversion signal is subjected to integral accumulation decimation and demodulation transformation according to the fine capture decimation parameters. The residual frequency offset estimate is obtained by frequency domain transformation and spectral peak retrieval.

[0045] The residual frequency offset estimate is superimposed on the frequency of the first-stage local oscillator.

[0046] By adopting the above technical solution, the residual frequency offset after coarse acquisition is compressed to within the preset frequency resolution, and fine acquisition can use larger decimation parameters to obtain finer frequency resolution without aliasing. The frequency offset estimation accuracy is no longer limited by the frequency resolution of a single transformation.

[0047] Optionally, in step S7, the sign of the punctual sample point whose energy is not lower than a preset energy threshold is determined as a valid sign, and the signal-to-noise ratio estimate is obtained by the ratio of the square of the mean to the variance of the energy of the punctual sample point within a preset statistical window.

[0048] In step S8, only the timing error at the effective symbol is used to correct the symbol timing step. The effective symbol is corrected once for each accumulated effective symbol number. The effective symbol number is determined according to the signal-to-noise ratio estimate based on a preset mapping relationship. The preset mapping relationship causes the effective symbol number to decrease as the signal-to-noise ratio estimate increases.

[0049] By adopting the above technical solution, symbols with low energy at the timed sampling points do not participate in the step correction, thus avoiding the injection of spurious measurements with zero timing error into the loop; the number of effective symbols required for updating changes with the signal-to-noise ratio estimate, and the equivalent loop bandwidth automatically shrinks with the signal quality.

[0050] Optionally, in S5, the phase rotation is performed at each sampling point within each symbol by a linear interpolation between the second-level rotation angle of the current symbol and the second-level rotation angle of the previous symbol; in response to the symbol rate being lower than a preset rate threshold, the linear interpolation is enabled; in response to the symbol rate being not lower than the preset rate threshold, each sampling point performs the phase rotation by the second-level rotation angle of the current symbol.

[0051] By adopting the above technical solution, each sampling point within the symbol obtains a rotation amount that varies with the phase ramp, and the phase accumulated within the symbol period at low symbol rates is no longer approximated by a single value.

[0052] Optionally, the method is applied to a receiver whose symbol clock is obtained by frequency division of the local oscillator clock of the first-stage local oscillator. In S8, the symbol timing step includes a nominal step, a frequency difference feedforward amount, and a correction amount of the proportional branch. The frequency difference feedforward amount is calculated by multiplying the ratio of the integral component to the nominal carrier frequency by the nominal symbol rate.

[0053] By adopting the above technical solution, the symbol clock frequency difference is eliminated outside the loop after being converted by the carrier frequency, and the proportional branch does not need to bear the responsibility of clearing the steady-state error.

[0054] Optionally, in step S2, the integral accumulation decimation, the demodulation transform, and the frequency domain transform are performed again according to the auxiliary decimation parameters to obtain the auxiliary spectral peak frequency. The auxiliary decimation parameters satisfy the decimation constraints and are coprime with the decimation parameters. The carrier frequency offset estimate is the only frequency within the joint unambiguous range that matches both the result of the spectral peak retrieval and the auxiliary spectral peak frequency. The joint unambiguous range is the least common multiple of the ambiguity period corresponding to the decimation parameters and the ambiguity period corresponding to the auxiliary decimation parameters.

[0055] By adopting the above technical solution, the least common multiple of the two estimated fuzzy periods is taken, and the fuzz-free range is expanded without reducing the frequency resolution.

[0056] Optionally, in S3, the integral component further includes a frequency ramp term, which is obtained by second-order integration of the carrier phase error; the frequency ramp term is calculated by superimposing the ratio of the nominal symbol rate to the nominal carrier frequency onto the rate of change of the symbol timing step.

[0057] By adopting the above technical solution, the integral component can obtain the ability to track the frequency ramp, and the Doppler change rate caused by the acceleration of the carrier no longer manifests as a steady-state frequency difference.

[0058] Optionally, in S7, in response to the signal-to-noise ratio estimate being lower than a preset signal-to-noise ratio threshold, the denominator of the normalization is taken as the sliding average of the energy of the punctual sample points within a preset average window, and the numerator of the normalization is taken as the difference between the energy of the leading sample point and the lagging sample point of the current symbol.

[0059] By adopting the above technical solution, the normalized denominator in the low signal-to-noise ratio range is taken from the average of multiple symbols, and the fluctuations of the denominator itself no longer enter the phase detection output.

[0060] Optionally, in S8, the timing loop filter further includes an integration branch, which is enabled in response to the sliding variance of the timing error being lower than a preset activation threshold and continuously not less than a preset number of activation symbols. The integration branch is configured with an integral limit value and a leakage coefficient.

[0061] By adopting the above technical solution, when the transmitting and receiving clocks are from different sources, the integration branch is responsible for clearing the steady-state timing error, and the accumulation of integral limiting and leakage suppression stages is taken into account.

[0062] Optionally, in S7, in response to the energy difference between the leading and lagging samples of the valid symbols for a consecutive number of not less than a preset run-length symbols being lower than a preset difference threshold, and the energy of the punctual sample not being lower than the preset energy threshold, it is determined that the data pattern is degraded, and the symbol timing step maintains the value after the previous correction during the duration of the data pattern degradation.

[0063] By adopting the above technical solution, the long run data pattern enables the identification of the interval where the slope of the phase detection curve collapses, and the symbol timing step is not driven by invalid phase detection output within this interval.

[0064] Optionally, in S2, in response to the result of the spectral peak retrieval falling into a preset neighborhood without ambiguity boundaries, it is determined that the carrier frequency offset estimate has folding, the carrier frequency offset coarse acquisition is re-executed after reducing the decimation parameter, and the reduced decimation parameter still satisfies the decimation constraint. The unambiguous boundary is half the ratio of the decimated sampling rate to the order of the demodulation transform.

[0065] By adopting the above technical solution, spectral peaks falling near unambiguous boundaries are identified as potentially folded, and recapture after reducing the extraction parameters can eliminate erroneous estimates of mirror positions.

[0066] Optionally, the method is applied to burst communication, storing the integral component and the symbol timing step at the end of the previous burst as a binding value; in the subsequent burst, S3 and S8 respectively use the binding value as the initial value of the integral component and the symbol timing step, and the carrier frequency offset coarse acquisition in S2 of the subsequent burst is performed according to a preset amortization search range centered on the binding value; in response to the carrier frequency offset convergence determination not being established within a preset amortization symbol number, the carrier frequency offset coarse acquisition is re-executed according to the full frequency search range.

[0067] By adopting the above technical solution, the convergence state of the previous burst becomes the starting point of the next burst, the search range required for capture is shortened accordingly, and the effective payload ratio under short bursts is increased.

[0068] Secondly, the computer device provided in this application adopts the following technical solution:

[0069] A computer device comprising:

[0070] One or more processors;

[0071] Memory;

[0072] One or more applications, wherein the one or more applications are stored in the memory and configured to be executed by the one or more processors, the one or more applications being configured to:

[0073] Perform the carrier and timing synchronization method for the multi-rate receiver described above.

[0074] Thirdly, this application provides a computer-readable storage medium that adopts the following technical solution:

[0075] A computer-readable storage medium storing at least one instruction, at least one program, a code set, or an instruction set, wherein the at least one instruction, the at least one program, the code set, or the instruction set is loaded and executed by a processor to implement the following:

[0076] The above-mentioned carrier and timing synchronization method for multi-rate receivers.

[0077] In summary, this application includes at least one of the following beneficial technical effects:

[0078] 1. The slow-changing component and the fast-changing component of the carrier loop are placed on both sides of the matched filter. The phase lag caused by the group delay is canceled out by the feedforward amount taken from the phase of the first-stage local oscillator before the decision. The decision point no longer has a residual phase deviation due to the group delay. The residual frequency offset at low symbol rate is eliminated before the frequency band is restricted.

[0079] 2. Timing error is normalized to the energy of the punctual sample points. The amplitude factor of the current symbol that is not related to the timing deviation in the phase detection output is canceled out. Symbols with low energy of punctual sample points are not included in the update. The equivalent loop bandwidth automatically shrinks with the signal quality.

[0080] 3. Acquisition, carrier tracking, and symbol timing are sequentially implemented based on whether the priors they depend on are available, thus breaking the cold start deadlock where the three are interdependent; the extraction parameters are jointly determined by the constraints of non-aliasing and frequency resolution, and the same set of configurations is reused according to the rate level, and the subsequent criteria remain uniform within the feasible region. Attached Figure Description

[0081] Figure 1 This is a flowchart of a carrier and timing synchronization method for a multi-rate receiver in one embodiment of this application.

[0082] Figure 2 This is a schematic block diagram of the synchronization architecture of a multi-rate receiver in one embodiment of this application.

[0083] Figure 3 This is a state transition diagram of a synchronization state machine in one embodiment of this application.

[0084] Figure 4 This is a block diagram illustrating the principle of combining the group delay feedforward quantity with the second-stage rotation angle in one embodiment of this application.

[0085] Figure 5 This is a schematic diagram of a computer device according to an embodiment of this application. Detailed Implementation

[0086] The present application will be further described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are merely illustrative of the application and are not intended to limit the scope of the application.

[0087] This application discloses a carrier and timing synchronization method for a multi-rate receiver. First, several technical terms involved in this application's embodiments are explained. The first-stage digital down-conversion and the second-stage digital down-conversion refer to two complex multiplication operations on the same digital baseband processing chain, located on either side of the matched filter. The former operates on the input signal before narrowbanding, updating the local oscillator phase point by point, while the latter operates on the signal after matched filtering, updating the rotation angle symbol by symbol.

[0088] The carrier loop and timing loop refer to two closed loops, respectively, consisting of a phase detection or error detection stage, a loop filter, and an execution stage. In contrast, the carrier loop filter and timing loop filter are components within their respective loops, only responsible for converting error quantities into control quantities, and do not include phase detection or execution stages.

[0089] The group delay feedforward refers to the change in the phase of the first-stage local oscillator within the group delay interval of the matched filter. The matched filter delays the correction applied by the first stage by a fixed time before reaching the decision time. During this time, the signal carries a phase that has not yet been corrected. This phase is not a random quantity, but a definite quantity determined by the phase advance of the first-stage local oscillator itself, and therefore can be calculated and canceled in the second stage.

[0090] A rate range refers to several intervals into which the range of symbol rates supported by this method is divided based on the reusability of the decimation parameters and matched filter coefficients; the rate range into which the symbol rate falls is called the current rate range. Rates within the same range share the same set of configurations, and configurations are switched only when crossing ranges.

[0091] Extraction constraints refer to the set of three inequalities and one divisibility condition that the values ​​of the extracted parameters must simultaneously satisfy, corresponding to the three requirements of non-aliasing, frequency resolution, and accumulation window not crossing signs; the integer solution of the four conditions constitutes the feasible region of the extracted parameters.

[0092] Timely samples, leading samples, and lagging samples refer to three samples taken at the same decision time and at each of the half-preset intervals before and after it. Timely samples serve two functions: decision and amplitude reference. Leading and lagging samples, on the other hand, use the difference in their energy to represent the direction of the offset of the sampling time relative to the symbol waveform.

[0093] A valid symbol is a symbol whose energy at the precise sampling point is not lower than a preset energy threshold. In contrast, valid symbols are not discarded, but rather do not participate in the symbol timing step correction, nor do they occupy the counter bits required for correction.

[0094] The core idea of ​​this application is to extract the criteria required by each link in the synchronization chain from the existing intermediate quantities within the link, rather than having each link estimate or assume ideal values. The main method is as follows: First, the decimation parameters are normalized according to the symbol rate, ensuring that the criteria for the acquisition link do not drift with the rate. Then, the two outputs of the carrier loop filter are placed on either side of the matched filter according to their speed; the slowly varying integral component eliminates frequency offset before matched filtering, while the rapidly varying proportional component corrects the phase after matched filtering. Finally, the energy difference between the leading and lagging samples is normalized using the energy of the punctual sample to obtain a timing error unaffected by the data pattern. This allows for the coverage of multiple symbol rates differing by an order of magnitude under a single set of parameters, ensuring that the group delay of the matched filter neither causes loop oscillations nor results in the filtering out of residual frequency offsets at lower rates.

[0095] The examples below all follow the same baseline scenario: the receiver's input sampling rate is fixed, and the supported symbol rate range is divided into high and low levels, with the high level's symbol rate being approximately 10 times that of the low level. The number of taps in the matched filter is configured according to the rate level, and the number of taps in the two levels does not change proportionally with the number of samples per symbol. If carrier correction is placed entirely before matched filtering, in this scenario, at the high level, the group delay of the matched filter, when converted to a symbol, can reach several symbols. The loop experiences a wait of several symbols between acquiring the phase error and the correction taking effect. When the loop bandwidth is increased to the order of magnitude sufficient to meet the acquisition time requirements, the constellation phase begins to swing back and forth, and the lock indicator repeatedly sets and resets. If carrier correction is moved entirely after matched filtering, in the low level, the passband of the matched filter narrows by approximately 10 times with the symbol rate. The same amount of residual frequency offset falls outside the passband, and the signal is filtered out as an out-of-band component before reaching the correction stage. Both methods fail, which is the reason why this application places the two control variables on opposite sides. (Refer to...) Figure 1 The following sections will explain in detail the determination of extraction parameters, carrier frequency offset acquisition, two-stage downconversion and group delay cancellation, carrier phase detection, symbol timing error detection and step correction, and the mapping between computer equipment and storage media.

[0096] S1. Determine the decimation parameters based on the symbol rate to ensure that the decimated sampling rate is a preset multiple of the symbol rate. The purpose of the decimation parameters is to convert the absolute bandwidth that varies with the rate into a relative bandwidth that is normalized with the rate: the input sampling rate is fixed, but the symbol rate changes. By allowing the decimation parameters to change synchronously with the symbol rate, the ratio of the decimated sampling rate to the symbol rate will always remain at the preset multiple. Therefore, the number of transformation points, peak detection threshold, and loop coefficients of subsequent stages do not need to be tuned step by step. The preset multiple is generally set to 2 to 4. A value of 2 minimizes the computational load of subsequent stages, while a value of 3 to 4 provides more margin for peak retrieval. In engineering practice, the value is selected within this range based on the resources of subsequent stages and the required capture range. Alternatively, the decimation parameters can be used without integer multiples, instead employing fractional multiple interpolation resampling to normalize the decimated sampling rate. This alternative method also achieves the goal of decoupling subsequent stage parameters from the rate.

[0097] In some embodiments, S1 divides the symbol rate range into multiple rate levels, and the rate level to which the symbol rate belongs is determined as the current rate level. The basis for level division is whether the decimation parameters and matched filter coefficients can be reused within the level: the decimation parameters and filter coefficients required for each rate within the same level are the same or differ by only one integer factor, and configuration changes are only required when crossing levels. Level boundaries are usually taken at the point where the decimation parameters undergo integer transitions, so that configuration switching within a level is reduced to reloading the parameter register rather than changing the coefficient table. The high and low levels in the baseline scenario are divided in this way. Rate level switching should preferably be completed during gaps when there is no data reception. The loop state variables that have converged at the moment of switching are inherited after being converted according to the dimensions of the new level, avoiding loss of lock caused by the switching itself.

[0098] Optionally, the decimation parameters in S1 are determined according to the following decimation constraints. Let the sampling rate of the input signal be... Symbol rate is Extraction parameters are The order of the demodulation transform is The number of points in the frequency domain transform is The preset maximum carrier frequency offset is The preset frequency resolution is Input number of samples per symbol Then the three inequalities are as follows:

[0099]

[0100]

[0101]

[0102] in, To determine the maximum carrier frequency offset given by the local oscillator deviation and the expected Doppler range, To capture the minimum resolvable frequency interval required. In addition to the three equations mentioned above, It must be divided. The first equation represents the upper limit of non-aliasing; demodulation transformation will amplify the carrier frequency deviation to [a certain extent]. The first equation is the amplification factor, which must be accommodated by the decimated sampling rate. The second equation is the lower bound of the frequency resolution, where the decimated sampling rate divided by the number of transform points gives the minimum resolvable frequency interval. The third equation, together with the divisibility condition, is called the accumulation window non-cross-symbol constraint, which restricts the decimation parameter to an integer that is no greater than the number of samples per symbol of the input and can divide it.

[0103] The four conditions together define the feasible region for the extraction parameters, while the preset multiple in S1 gives the target value, that is, the target value of the extraction parameters is equal to the quotient of the number of samples per symbol and the preset multiple. The actual value is the one that falls within the feasible region and is closest to the target value; if the target value itself falls outside the feasible region, the feasible region takes precedence, that is, the requirements for capture range and frequency resolution take precedence over the preference for computational complexity. Taking the high-end of the benchmark scene as an example, let... If the preset multiple is 2, then the candidates that satisfy the third equation and the divisibility condition are 1, 2, and 4. The target value is 2, which is among the candidates and has passed the verification of the first two equations, so we take it. Low-end When the preset multiple is 2, the target value is 20, and the candidates are all divisors of 40. Because... , and All three are independent of the rate setting. The non-aliasing upper bound of the first equation is the same across all rates. A decrease in the sign rate causes the target value to increase accordingly. When the target value collides with this fixed upper bound, the upper bound is used as the standard, i.e., the largest divisor below the upper bound is taken. In this case, the decimated sampling rate is higher than the value corresponding to the preset multiple, and the frequency resolution becomes correspondingly coarser. The second equation is used to verify whether the requirements are still met. The decimation parameter can also be limited to an integer power of 2, allowing integration and shifting to achieve the desired result without a divider. This alternative method also satisfies the above four conditions.

[0104] The necessity of limiting the accumulation window to within one symbol constraint lies in the execution order of the acquisition phase. The initial estimation of the carrier frequency offset occurs before symbol timing is established, at which point the alignment between the accumulation window and the symbol boundary is random. If the window length exceeds one symbol, it will inevitably cross at least one symbol boundary. The modulation phases on both sides of the boundary are uncorrelated and cancel each other out during accumulation, thus weakening the signal energy before the demodulation transformation. By limiting the window length to within one symbol, even in the worst-case scenario, cancellation only occurs at one boundary, resulting in bounded loss.

[0105] S2. Perform coarse carrier frequency offset acquisition on the input signal according to the extraction parameters to obtain the estimated carrier frequency offset value and load it into the first-stage local oscillator. The product of coarse acquisition is a frequency value, which needs to be converted into the frequency control word of the first-stage local oscillator before being written. The writing timing is arranged after the acquisition decision is completed and before the tracking loop closes. The purpose of loading is to compress the residual frequency offset into the passband of the matched filter. The passband width is proportional to the symbol rate and is especially narrow at low rates. If it is not loaded in advance, the signal will have been largely cut off by the matched filter when the tracking loop closes, and the loop will not be able to converge.

[0106] Specifically, carrier frequency offset coarse acquisition includes integral accumulation decimation of the input signal according to the decimation parameters, demodulation transformation to eliminate the modulation phase of the decimation result, and frequency domain transformation and spectral peak retrieval of the transformation result. The data format changes sequentially in these three stages: integral accumulation decimation transforms the continuous... The summation of each input sample point outputs a single point, which reduces the computational load of subsequent stages and suppresses out-of-band noise using a rectangular window. The demodulation transform performs a fourth-order operation on the decimation result. In a quadrature phase-shift keying (QPSK) system, the four constellations are phase-differentiated by a quarter cycle. After being folded to the fourth power, they converge to the same position, thus eliminating the modulation phase and leaving a single-frequency component with a frequency offset of four times the original frequency. Frequency domain transformation and spectral peak retrieval locate the peak value on this single-frequency component. The peak position is then divided by... This restores the carrier frequency offset estimate. The fourth power, while eliminating the modulation phase, also amplifies the frequency offset by a factor of four, which is precisely the aforementioned upper bound for non-aliasing. The origin of the term "multiplier".

[0107] As an optional implementation, S2 further performs an integral-cumulative decimation, demodulation transform, and frequency domain transform based on the auxiliary decimation parameters to obtain the auxiliary spectral peak frequency. The auxiliary decimation parameters satisfy the decimation constraints and are coprime with the decimation parameters. The carrier frequency offset estimate is the unique frequency within the joint unambiguous range that matches both the spectral peak retrieval result and the auxiliary spectral peak frequency. The joint unambiguous range is the least common multiple of the ambiguity period corresponding to the decimation parameters and the ambiguity period corresponding to the auxiliary decimation parameters. In a single acquisition, the spectral peak position can only determine the remainder of the frequency offset within one ambiguity period, which is equal to the decimated sampling rate divided by... The decimation parameters used in the two captures are different, resulting in different fuzzy periods. The range that can be uniquely determined by combining the two remainders extends to the least common multiple of the two periods. When the two remainders are coprime, this range can be extended to the entire range allowed by the sampling rate before decimation. The two transformations are performed sequentially in time, sharing the same set of memory and butterfly computing resources, without increasing the on-chip area.

[0108] In other embodiments, in S2, in response to the result of spectral peak retrieval falling into a preset neighborhood without ambiguity boundaries, it is determined that the carrier frequency offset estimate has folding. The carrier frequency offset coarse acquisition is then re-executed after reducing the decimation parameters, and the reduced decimation parameters still satisfy the decimation constraints. (Unambiguous boundaries) for

[0109]

[0110] When the amplified frequency offset exceeds At this point, the spectral peak no longer appears at its true location, but rather folds to a mirror image on the other side of the boundary, making it impossible to distinguish between the true peak and the folded peak in a single peak detection. The preset neighborhood is typically taken as a width of several frequency resolutions; if it is too narrow, it will result in missed detections, while if it is too wide, it will frequently trigger re-acquisition. Reducing... It will increase the sampling rate after extraction, thereby increasing This causes the frequency offset that was originally out of bounds to fall back within the boundary; an upper limit is set for the number of recaptures, and if the frequency still falls within the neighborhood after reaching the upper limit, it is determined to be outside the capture range of this method and reported.

[0111] In one optional implementation, this method is applied to burst communication. The integral component and symbol timing step at the end of the previous burst are stored as a binding value. In the subsequent burst, S3 and S8 use the binding value as the initial value for the integral component and symbol timing step, respectively. In S2 of the subsequent burst, coarse carrier frequency offset acquisition is performed according to a preset amortized search range centered on the binding value. In response to the carrier frequency offset convergence determination not being established within a preset amortized symbol number, coarse carrier frequency offset acquisition is re-executed according to the full frequency search range, which is the complete acquisition range allowed by the extraction constraints. The frequency drift of the local oscillator between bursts is much smaller than its absolute deviation; therefore, the convergence state of the previous burst still has reference value for the subsequent burst. The amortized search range can be determined by taking a multiple of the short-term drift of the local oscillator within the burst interval. The determination of binding value failure is based on the burst interval. If the interval exceeds the duration corresponding to the short-term stability of the local oscillator, it is no longer used, and full-range acquisition is directly performed.

[0112] S3. The carrier phase error is filtered by the carrier loop filter to obtain the integral component and the proportional component. The phase of the first-stage local oscillator is updated point by point with the integral component. The first-stage digital down-conversion and matched filtering are then performed on the input signal sequentially to obtain the first-stage down-converted signal and the matched-filtered signal, respectively. (Refer to...) Figure 2The carrier loop filter employs a proportional-integral (PI) structure. The integrator branch accumulates the phase error, and its output represents the frequency deviation that needs to be maintained over a long period, making it a slow variable. The proportional branch amplifies the phase error by a fixed multiple, and its output represents the instantaneous phase error, making it a fast variable. The figure also shows the loading path from the acquisition branch to the first-stage digital downconversion, and the path of the timing branch reconnecting from the decision time. The first stage only takes the integral component and is located before the matched filter. The spectrum of the slow variable is concentrated at very low frequencies, far below the passband edge of the matched filter, and is only delayed, not attenuated, when passing through the matched filter; the group delay of the matched filter is denoted as . The loop gain crossover frequency is Therefore, the additional phase shift introduced at the crossing point is:

[0113]

[0114] in, This is a fixed time delay from input to output for matched filtering. At very low levels, this loss is negligible. Although the group delay is inside the feedback loop, it does not push the loop towards instability. This is precisely the basis for prioritizing the first stage: prioritization ensures that the residual frequency offset is eliminated before the matched filter limits the bandwidth, and the resulting phase margin cost becomes acceptable due to the slow change in the control quantity. As an alternative, a phase lead network can be inserted into the loop to compensate for the phase shift caused by the group delay. This alternative method can also restore the phase margin, but it requires additional multipliers and the compensation amount is less than that of the previous stage. Binding, When changes occur, readjustment is required.

[0115] In some embodiments, during the execution of S3 to S8, an enable determination operation is also performed, which includes carrier frequency offset convergence determination and timing lock determination executed sequentially. The carrier frequency offset convergence determination is performed when the change in the integral component within a preset observation window is lower than a preset convergence threshold, and the preset observation window is counted based on the update sampling points of the first-level local oscillator phase. The timing lock determination is performed when, after the carrier frequency offset convergence determination is successful, the sliding variance of the timing error is lower than a preset lock threshold and remains at least a preset number of symbols, and the determination is successful. (Refer to...) Figure 3The two determinations each have specific observable meanings: the integral component represents the steady-state frequency difference, and its change tends to zero, indicating that the frequency has caught up; the sliding variance of the timing error characterizes the jitter at the sampling moment, and the variance falling below the threshold indicates that the timing is aligned. The preset observation window is generally on the order of 100 to 1000 sampling points. Too short a window will lead to misjudgment of convergence due to noise, while too long a window will delay the input of subsequent stages. The preset convergence threshold is determined by a multiple of the frequency control word change corresponding to the short-term frequency stability of the local oscillator. The preset locking threshold and the preset number of symbols are determined in the same way. The former is based on a multiple of the typical magnitude of timing jitter after locking, while the latter is a number of symbols sufficient to overcome one deep fading. The results of the two determinations, along with the enable signals of each loop and the update of the mistime, are uniformly output and distributed by a synchronous state machine, and each loop itself no longer makes repeated determinations. If a false trigger occurs, subsequent steps will be activated without the necessary conditions, resulting in an increase in the variance of the timing error instead of a decrease. Therefore, a fallback window can be set after activation; if the variance does not decrease within the window, activation is revoked and the loop waits again. Alternatively, a timer of fixed duration can be used, waiting a fixed number of symbols after acquisition before activating each loop sequentially. This alternative method also achieves sequential activation of each loop, but the waiting time must be set based on the worst-case signal-to-noise ratio, which tends to be conservative in most cases.

[0116] Optionally, during the execution of S3, a fine acquisition operation is also performed. This fine acquisition operation includes: using a preset frequency resolution as the residual upper bound of the carrier frequency offset estimate; determining fine acquisition decimation parameters based on the decimation constraint obtained by replacing the preset maximum carrier frequency offset with the residual upper bound, where the fine acquisition decimation parameters are greater than the decimation parameters; performing integral accumulation decimation and demodulation transformation on the first-stage down-conversion signal according to the fine acquisition decimation parameters, and obtaining the residual frequency offset estimate through frequency domain transformation and spectral peak retrieval; and superimposing the residual frequency offset estimate onto the frequency of the first-stage local oscillator. The estimation error of coarse acquisition will not exceed one... Therefore, The upper bound of the residue is justified; since the residue is already greater than... The difference is much smaller, and the upper bound for non-aliasing in the first equation is thus widened. Fine capture can use larger decimation parameters to achieve finer frequency resolution without aliasing. Fine capture targets the first-stage down-converted signal, not the original input signal, because the coarse estimate has already been applied, and the frequency offset on the original input signal has not yet been eliminated. The residual value is obtained by performing a second estimate on the down-converted signal. The residual frequency offset estimate is written to the frequency of the first-stage local oscillator in a superimposed manner, without overwriting the result of the coarse capture. Alternatively, a second capture stage can be omitted. Instead, a three-point interpolation can be performed using the amplitudes of the peak sample and its left and right adjacent samples to solve for the peak offset within the sample interval. This alternative method also improves the frequency offset estimation accuracy to better than one... The level.

[0117] As an optional implementation, the integral component in S3 also includes a frequency ramp term, which is obtained by second-order integration of the carrier phase error. The first-order integral can be zeroed out for constant frequency deviations, but leaves an unavoidable steady-state error for frequency deviations that vary linearly with time. The Doppler frequency offset during carrier acceleration is precisely such a time-varying quantity, hence the need to add a second-order integral term specifically to track its rate of change. The gain of the second-order term is usually taken to be much smaller than the gain of the first-order term. Taking it too large will further reduce the loop's phase margin and approach the stability boundary. In engineering, the overshoot under a step frequency offset is used as the tuning basis. It should be noted that the specific value of the loop gain in this step also depends on the explanation of delay line depth later in the text; see the description below for the value of delay line depth and loop gain normalization under multiple rates.

[0118] S4. The change in the phase of the first-stage local oscillator within the group delay of the matched filter is taken as the group delay feedforward. Let the change in the phase of the first-stage local oscillator within the group delay of the matched filter be... The value at time is Then the group delay feedforward quantity for

[0119]

[0120] in, This refers to the portion of the phase for which the first-level correction has not yet been reflected at the decision time. (Refer to...) Figure 4 The output of the matched filter is at The sample points at time t correspond to The input samples at time 1 and 2 are different, and the phase of the first-stage local oscillator at these two time points is not the same. The difference is the quantity given by the above formula. This difference does not depend on the channel or the data; it is determined solely by the phase advance of the first-stage local oscillator itself. It is a definite quantity that can be calculated clearly during the design phase. Calculating it and subtracting it before the decision ensures that the hysteresis of the matched filter does not enter the phase of the decision point. In the high-end scenario of the reference, Converted to symbols, this amounts to several symbols. The residual frequency offset advances by a phase on the order of one-tenth of a cycle during this period, resulting in a considerable difference in phase between the decision points for cancellation and non-cancellation. When the frequency control word of the first-stage local oscillator is essentially constant, It can also be approximated as the product of the frequency control word and the group delay beat number. This approximation is equivalent to the precise form in steady state and is simpler to implement.

[0121] In some embodiments, in S4, the phase of the first-stage local oscillator is delayed by a delay line. The depth of the delay line is equal to the number of group delay beats in the matched filter. The group delay feedforward is the difference between the current value of the first-stage local oscillator phase and the output value of the delay line. The delay line is implemented using a shift register, and its depth is set to half the number of taps in the matched filter. Automatic matching, no further tuning required. The difference between the current value and the delayed value is always equal to the actual accumulated phase within that interval, regardless of whether the frequency control word changes within the interval. This is the key difference between it and the constant approximation form: the approximation form implies a constant frequency within the interval, while the pull-in stage is precisely the stage where the frequency control word changes most drastically and needs to be canceled out the most. At this time, the value given by the approximation form does not match the actual accumulated amount. The bit width and truncation of the phase accumulation value determine the quantization error of the difference. If the bit width is insufficient, this error will enter the second-stage rotation angle in the form of spurious signals. Therefore, the bit width is made with a margin according to the required phase resolution. As an alternative, two sets of parallel phase accumulators can be used to accumulate at the current frequency and the delayed frequency respectively, and the difference can be taken. This alternative method also obtains the phase accumulation within the interval, but requires twice the accumulator resources.

[0122] Accordingly, the delay line depth is taken as the group delay beat number of the matched filter at the current rate setting. The number of taps for the matched filter at multiple rates is configured according to the rate setting. The number of beats, measured in sampling points, varies depending on the gear. Since this number of beats does not change proportionally with the number of samples per symbol, the value converted to a symbol can differ by an order of magnitude between the two gears. The group delay beat count for each gear is given in the configuration table along with the other parameters for that gear. The depth and parameters are updated synchronously when the gear is switched. The switch occurs when there is no data gap, and the historical phase values ​​within the delay line have not yet been filled within a few beats after the switch. During this period, the feedforward is output as a zero value, and it is put into use after it is filled.

[0123] Based on this, the loop gain of the carrier loop filter decreases as the ratio of the delay line depth to the number of input samples per symbol at the current rate setting increases. The delay line depth is measured in sampling points and divided by... This yields the group delay value referred to the symbol; the larger this value, the greater the lag experienced by the loop within one symbol. The larger the value, the greater the phase margin loss; therefore, the gain should be reduced accordingly to compensate. Push back to the safe range. The normalization coefficient is determined in reverse according to the proportional relationship of the converted values ​​of each range, so that the two ranges have similar phase margins after tuning, so that the same set of loop parameters can be used between each range without having to be retuned for each range.

[0124] S5. Using the sum of the proportional component and the group delay feedforward as the second-stage rotation angle, perform phase rotation of the matched filter signal symbol by symbol to obtain the second-stage down-converted signal. The second-stage rotation angle consists of two components from different sources: the proportional component comes from the carrier loop filter and is responsible for correcting the instantaneous phase error; the group delay feedforward comes from the phase advance of the first-stage local oscillator and is responsible for the portion of the phase that has not yet been reflected in the decision time after the first-stage correction. The former is the feedback quantity, and the latter is the feedforward quantity; the two are added together and then applied at once. In some embodiments, the second-stage rotation angle only takes the proportional component; in this case, the lag phase caused by the group delay is not canceled out and must be indirectly tolerated by reducing the loop bandwidth. In other embodiments, the second-stage rotation angle takes the sum of the proportional component and the group delay feedforward. The sum of the phases, the lagging phase is directly subtracted before the decision, and the decision point no longer has a residual phase deviation due to group delay. Phase rotation can be implemented using coordinate rotation digital calculation method or lookup table. The former approximates the target angle through shift and addition iteration without occupying a multiplier, while the latter directly reads the pre-stored sine and cosine values, which is fast but requires storage. In engineering, one method is chosen based on the multiplier margin of the target device and the required angle resolution. Both implementation methods can also complete the symbol-by-symbol phase rotation of the matched filter signal. The second stage is located after the matched filter. The loop from the second stage through decision, phase detection, loop filtering and back to the second stage does not contain a finite impulse response filter. The group delay of the feedback path is zero, and the correction of the proportional component takes effect immediately.

[0125] Accordingly, the proportional gain of the carrier loop filter is reduced to a value lower than the nominal value before the timing lock determination is established. The phase error on which the proportional component depends is taken from the decision point. However, the decision time is not yet aligned before timing lock. The phase error taken from this point contains a large number of components coupled with timing deviation. If the full value is used, timing jitter will be introduced into the carrier loop. The reason for taking a reduced value instead of zero is that in the implementation of the integration branch working continuously in this stage, the phase accumulator of the first-stage local oscillator and the integration branch of the loop filter constitute a double integral. Once the proportional term is completely removed, the open-loop phase lag is always 180 degrees and the phase margin is zero, and the loop will lose stability. Retaining a reduced proportional term can maintain the phase margin while suppressing timing jitter crosstalk. In some other embodiments, after coarse acquisition, the frequency control word of the first-stage local oscillator remains unchanged in this stage. Only its phase is advanced by the integral component sampling point by point. At this time, only the phase accumulator is left as a single integral in the open-loop chain. The open-loop phase lag is 90 degrees and the phase margin is sufficient. The proportional gain can also be zero in this stage without instability. The difference between the two implementations lies in whether the integration branch continuously updates the frequency control word during the pull-in phase; in engineering, this is chosen based on the drift rate of capturing residual frequency offset. The second-stage rotation angle in this phase is determined by the reduced proportional component and... Together, they form a single structure, and the feedforward path remains unaffected. When the gain switches from a decreasing value to the nominal value, a gradual change within several symbols is adopted to avoid a step change in the rotation angle that would cause a phase jump at the decision point.

[0126] In other embodiments, the phase rotation in S5 is performed at each sampling point within each symbol by linear interpolation between the second-order rotation angle of the current symbol and the second-order rotation angle of the previous symbol; linear interpolation is enabled in response to the symbol rate being lower than a preset rate threshold; and phase rotation is performed at each sampling point by the second-order rotation angle of the current symbol in response to the symbol rate not being lower than the preset rate threshold. The second-order rotation angle of each symbol is Then the phase step per sample point within the symbol is

[0127]

[0128] Updating the rotation angle once per symbol is equivalent to approximating a continuously changing phase ramp with a single value throughout the entire symbol period. The approximation error increases with the length of the symbol period. At lower symbol rates, the symbol period is longer, and the same residual frequency offset propagates through more phases within a single symbol, resulting in a more significant error. Linear interpolation only requires obtaining the step size using the above formula and then accumulating it point-by-point, without additional angle calculations. The preset rate threshold is derived by back-calculating the maximum allowable approximate phase error within the symbol period. When the rate is below this threshold, interpolation is enabled; when it is above, it degenerates into maintaining a single value per symbol. These two approaches coexist, forming two parallel implementation paths within the same step.

[0129] S6. Carrier phase detection is performed on the second-stage down-conversion signal to obtain the carrier phase error. After locking, the carrier phase detection adopts a decision-guided method, that is, the cross product or phase difference between the decision result and the received sample is used as the error quantity. Its output is sent to the carrier loop filter, which separates the integral component and the proportional component to drive the two-stage down-conversion, thus closing the loop. The phase detection output is limited and quantized according to the required loop resolution before being sent to the loop filter. The limiting threshold is set as a multiple of the typical error amplitude during normal operation to prevent individual erroneous decisions from introducing large errors into the loop. As the decision accuracy decreases with the decrease of the signal-to-noise ratio, the slope of the decision-guided phase detection curve decreases accordingly until it is reversed. This is the inherent boundary of this method.

[0130] Following the previous explanation of carrier phase detection, before the timing lock determination is established, carrier phase detection is achieved by performing a demodulation transformation on the second-stage down-converted signal to eliminate the modulation phase. From the moment the timing lock determination is established, it is achieved by the decision result of the second-stage down-converted signal. The physical quantities output by the same demodulation transformation unit are not the same in the two stages: in the acquisition stage, its output, after frequency domain transformation, gives the position of the frequency domain peak; in the pull-in stage, its output, after angle taking, gives the phase error in the time domain. The reason for using this method before locking is that decision-guided phase detection relies on the alignment of the decision time, which is not the case before timing lock. The demodulation transformation does not depend on the decision time, but only on the modulation structure of the signal itself, thus still providing a usable phase error at this stage. The switching point between the two methods is tied to the timing lock determination. At the moment of switching, the output dimensions of both are aligned after being converted according to their respective phase detection gains, avoiding step disturbances to the loop during switching. As an alternative, a known symbol sequence can be used as an auxiliary phase detector in the burst preamble segment. This alternative method also provides a phase error when the decision timing is not aligned, but it requires that a preamble is available in the signal format.

[0131] S7. At the decision time, take the punctual, leading, and lagging samples of the second-stage down-conversion signal. Normalize the difference between the energy of the leading and lagging samples using the energy of the punctual sample to obtain the timing error. Let the punctual sample be denoted as... The lead-lag interval is Then the leading and lagging samples are respectively and Timing error for

[0132]

[0133] in, For the energy of the leading sample points, The energy of the lagging sample points, The energy of the timely sample points. Typically, half a symbol period is taken. At this point, the leading and lagging samples are located at quarter-symbol periods before and after the decision time. The values ​​must ensure that the matched filter output has samples available at these positions. Therefore, the matched filter output has no less than 4 sampling points per symbol. If the number of output sampling points is insufficient, interpolation is used to obtain intermediate samples at the required positions. The numerator is proportional to two quantities: the offset of the sampling time relative to the symbol waveform, and the energy of the current symbol itself. The data of four-phase phase shift keying is random. After shaping filtering, adjacent symbols are superimposed, and the amplitude of the neighborhood at the decision time fluctuates with the data pattern. If the numerator is directly used as the error, the phase detection output will be mixed with amplitude components unrelated to timing, which will manifest as the zero-crossing slope of the phase detection curve fluctuating greatly. After using the energy of the punctual sample as the denominator, the energy factor of the symbol itself appears in both the numerator and denominator and is canceled out. The remaining ratio only reflects the offset direction and magnitude. Therefore, the amplitude factor of the current symbol, which is unrelated to timing deviation, no longer enters the error in the phase detection output. It should be noted that normalization eliminates the amplitude factor of the current symbol; the phase detection curve distortion caused by the tailing of adjacent symbols in long-run conditions is not included. This residual effect will be identified and addressed in the data pattern degradation determination section below. The denominator can also be changed to the sum of the energies of the leading and lagging samples, making the numerator and denominator homologous and synchronously approaching zero during deep fading. Furthermore, to prevent the denominator from approaching zero during deep fading or at fixed cutoff points, [further details are needed]. To achieve divergence, a lower limit can be set for the denominator; if the value is below this limit, it can be substituted into the denominator. This substitution method also yields a timing error that does not fluctuate with the sign amplitude.

[0134] Correspondingly, S7 and S8 are executed from the moment the carrier frequency offset convergence determination is established. If the timing loop is activated before the carrier frequency offset has converged, the samples near the decision time will still have a large amount of unresolved frequency offset. The energy difference of the three samples mainly reflects the phase rotation rather than the timing deviation, and the obtained error is invalid for timing. Before enabling, the symbol timing step maintains its nominal step, that is, it runs freely at the nominal symbol rate; at the moment of enabling, the nominal step is used as the initial value of the loop, the accumulated state of the filter is cleared to zero, and thereafter it is gradually driven by the error.

[0135] In some embodiments, in S7, signs whose energy at the precise time of the sample is not lower than a preset energy threshold are identified as valid signs, and the signal-to-noise ratio estimate is obtained by the ratio of the square of the mean to the variance of the energy of the precise time of the sample within a preset statistical window. The difference between a valid sign and a total sign lies in whether there is a reliable amplitude benchmark: when the energy of the precise time of the sample is too low, its own noise as the denominator accounts for a large proportion, and the obtained error is unreliable. Such signs should be identified rather than accepted indiscriminately. There are two ways to determine the preset energy threshold: one is to take a fixed proportion based on the average energy after automatic gain control convergence, and the other is to take the value based on the minimum effective denominator that the fixed-point divider can withstand. The former is suitable for fading-dominated situations, and the latter is suitable for quantization noise-dominated situations. Signal-to-noise ratio (SNR) estimation utilizes the same set of calculated, timely sample energy points without additional acquisition steps. The signal component dominates in the mean, while the noise component dominates in the variance. The ratio of the square of the mean to the variance is the dimensionless SNR estimate, which monotonically changes with the SNR. The square of the mean is used to ensure the numerator and denominator have consistent dimensions; directly taking the ratio of the mean to the variance results in a quantity with the reciprocal of energy and cannot be used as the SNR. A preset statistical window is used to cover the number of symbols over several fading cycles. During deep fading, effective symbols become sparse, the number of samples falling into the statistical window decreases, and the confidence level of the estimate decreases accordingly. In this case, the estimate remains the previous result until the sample number recovers. The SNR can also be estimated from the error vector magnitude between the decision result and the received sample points; this alternative method also provides a usable SNR estimate.

[0136] In other embodiments, in S7, in response to the signal-to-noise ratio estimate being lower than a preset signal-to-noise ratio threshold, the normalized denominator is the moving average of the energy of the punctual samples within a preset averaging window, and the normalized numerator is the difference between the energy of the leading and lagging samples of the current symbol. At low signal-to-noise ratios, the instantaneous energy in the denominator itself carries considerable noise, which is incorporated into the division. This becomes another source of disturbance unrelated to timing. By changing the denominator to a moving average of multiple symbols, the noise is averaged out, and the amplitude reference becomes stable. The numerator still takes the instantaneous value because the timing sensitivity comes from the numerator's response to the current sampling offset; averaging it would also flatten the sensitivity. The preset averaging window takes a number of symbols much shorter than the channel coherence time to prevent the averaged reference from failing to keep up with the actual amplitude changes. Two denominator forms coexist: the instantaneous denominator cancels out amplitude fluctuations symbol by symbol under high signal-to-noise ratio, while the moving average denominator provides a stable reference under low signal-to-noise ratio.

[0137] As an optional implementation, in S7, if the energy difference between the leading and lagging samples of valid symbols with a consecutive run number not less than a preset number of symbols is lower than a preset difference threshold, while the energy of the punctual sample is not lower than a preset energy threshold, then data pattern degradation is determined. Long run strings of the same symbol cause the shaping filter output to flatten in the neighborhood at the decision time, and the energy difference between the leading and lagging samples subsequently approaches zero. The energy difference approaching zero is not due to accurate sampling timing, but rather to the collapse of the phase detection curve's slope. The criterion is the combination of an energy difference below the difference threshold and normal energy at the time of sampling: normal energy at the time of sampling indicates the signal itself has not decayed, yet the energy difference continues to approach zero, which can only be attributed to the collapse of the phase detection curve; in true alignment, the energy difference also approaches zero, but random data causes its duration to fall short of the preset run length symbol count. The judgment applies to valid symbols; invalid symbols are neither included in the run length nor participate in the comparison. The preset difference threshold is determined based on the typical residual of the energy difference after locking, and its magnitude is more than one order of magnitude lower than the preset energy threshold; the preset run length symbol count is determined based on the statistical length of the same symbol string under the modulation scheme used; if it is too short, normal alignment will be misjudged as degradation. Degradation judgment is lifted when any condition is no longer met.

[0138] S8. The timing error is corrected by the proportional branch of the timing loop filter to adjust the symbol timing step, and the subsequent decision time is determined according to the symbol timing step; S3 to S8 are executed cyclically. The error is amplified by a fixed multiple by the proportional branch and then superimposed on the symbol timing step. The step determines the interval between the next decision time and the current time, and the decision time in turn determines the sampling position of the three samples in the next round. The loop is thus closed and iterates symbol by symbol. The timing loop filter uses pure proportional control and disables integration to prevent saturation: the integration branch will continue to accumulate under small errors over a long period of time. If the correction fails to take effect within a certain period of time, the accumulated value will grow to a level far exceeding the actual requirement. When recovering, an excessively large correction is applied to the step, which will push the already aligned timing away. The cost of disabling integration is that there is an uneliminable steady-state error left for the fixed symbol clock frequency difference. In addition, under the condition of a fixed sampling rate, the reduction of the symbol rate makes... As the sampling position is increased, the resolution of the sampling position is improved, which helps to reduce the self-noise of timing error detection, thus making timing tracking at low speeds easier.

[0139] In an optional implementation, the symbol timing step correction in S8 is performed in parallel as S8a and S8b. S8a. In response to a symbol timing step correction interval greater than one symbol, the symbol timing step correction time and the second-level rotation angle update time are staggered in different symbols. S8b. In response to symbol-by-symbol correction of the symbol timing step, the product of the integral component and the correction amount of the current symbol timing step is used as the phase reference offset, and offset compensation is performed on the current carrier phase error according to the phase reference offset. The timing loop and the carrier loop are not independent: the symbol timing step correction shifts the decision time, and the second-level rotation angle update changes the phase reference at that time; both act on the same sampling point. When both operate simultaneously on the same symbol, the phase error obtained by the carrier loop contains components caused by the shift in the decision time, and the sample point obtained by the timing loop falls on the changed phase reference, injecting disturbances into each other. By staggering their operations to different symbols, there is at most one change within the same symbol, thus breaking the coupling. Since there are no symbols to err on during symbol-by-symbol correction, a compensation method is used instead: the amount of shift at the decision time is given by the step correction amount, and the phase offset corresponding to this shift is equal to the product of the residual frequency offset after the first-stage digital down-conversion and the shift amount. The residual frequency offset is used here instead of the integral component because the integral component represents the frequency difference that has been tracked by the first-stage local oscillator; when the decision time shifts, the phases of the input signal and the first-stage local oscillator advance synchronously at their respective frequencies, and after down-conversion, only the difference between the two, i.e., the residual frequency offset, is effective. This residual frequency offset can be calculated from the difference in the second-stage rotation angle between two adjacent symbols. The symbol-by-symbol increment of the proportional component is proportional to the residual frequency offset, eliminating the need for a separate measurement step. Therefore, the product of this residual frequency offset and the step correction amount is used as the phase reference offset, which can be subtracted from the carrier phase error of the current cycle. After compensation, the residual coupling only comes from the error of this calculation itself, and its magnitude is much smaller than before compensation. Alternatively, the update rate of the timing loop can be reduced so that it is naturally staggered from the update of the second stage on most symbols. This alternative also reduces the simultaneous actions of the two, but sacrifices the tracking speed of the timing loop.

[0140] Correspondingly, in S8, only the timing error at the valid symbol level is used to correct the symbol timing step. The symbol timing step is corrected once for each valid symbol accumulated. The number of valid symbols is determined according to a preset mapping relationship based on the signal-to-noise ratio (SNR) estimate. This preset mapping relationship causes the number of valid symbols to decrease as the SNR estimate increases. Counting by total symbols includes the error of treating invalid symbols as zero, which is equivalent to sending a pseudo-measurement with zero timing error to the loop. When deep fading persists for multiple symbols, the loop determines that the timing is aligned and stops correcting, while the actual timing is drifting. Counting by valid symbols is different; invalid symbols neither participate in the correction nor occupy a counting bit. The loop is only paused during this period, not misled, and the consequences of the two are opposite. The preset mapping relationship is given in the form of a segmented lookup table from the SNR interval to the number of valid symbols. A smaller number of valid symbols is used in the high SNR interval to improve tracking speed, while a larger value is used in the low SNR interval to improve smoothness. Since the correction interval is calculated based on the number of effective symbols rather than the total number of symbols, effective symbols become sparse during deep fading, and the actual correction interval automatically lengthens, thereby shrinking the equivalent loop bandwidth, eliminating the need for a separate bandwidth adjustment mechanism.

[0141] Optionally, this method is applied to a receiver whose symbol clock is obtained by frequency division of the local oscillator clock of the first-stage local oscillator. In this case, the symbol timing step in S8 includes three terms: nominal step, frequency difference feedforward, and correction amount of the proportional branch. The nominal step is the step corresponding to the nominal symbol rate; the carrier frequency difference represented by the integral component is denoted as... The nominal carrier frequency is Frequency difference feedforward quantity is ,but

[0142]

[0143] in, This is a correction to the nominal step, and its magnitude is much smaller than the nominal step itself. If the symbol clocks at both ends are obtained by frequency division of each carrier local oscillator, then the relative frequency difference of the symbol clock is equal to the relative frequency offset of the carrier, and the proportionality coefficient is... and The ratio. This represents the converged carrier frequency difference. After being converted according to the above formula and superimposed on the nominal step, the symbol clock frequency difference is eliminated outside the loop, leaving only the random disturbance that needs to be processed by proportional control inside the loop. The feedforward takes the convergence of the integral component as the effective condition; if it does not converge... The original statement is inaccurate. This process transforms disabling integration from a costly trade-off into a costless one. When the transmit and receive clocks originate from different sources, this proportional relationship does not hold, and the feedforward value becomes irrelevant to the true frequency difference. In this case, the integration branch described below should be used instead.

[0144] Correspondingly, the frequency ramp term is calculated by subtracting the ratio of the nominal symbol rate to the nominal carrier frequency and then superimposed on the rate of change of the symbol timing step. During carrier acceleration, the Doppler effect manifests simultaneously as the ramp of the carrier frequency and the ramp of the symbol clock frequency difference, with the same proportional relationship as in the above formula. Subtracting the frequency ramp term obtained from the second-order integral at the same ratio and superimposing it on the rate of change of the symbol timing step, the symbol timing step changes linearly with time to keep up with the drift of the clock frequency difference. In practice, this is represented by a second-order accumulation of the step of the numerically controlled symbol oscillator. Although this feedforward is small in high-dynamic platforms, its cumulative effect is sufficient to cause considerable timing drift over a relatively long reception period.

[0145] In other embodiments, the timing loop filter in S8 also includes an integration branch, which is enabled in response to the sliding variance of the timing error being lower than a preset activation threshold and continuously not less than a preset number of activation symbols. The integration branch is configured with an integral limit value and a leakage coefficient. This is another path parallel to disabling integration: disabling integration sacrifices clearing capability in exchange for unsaturated conditions, while conditional activation involves inputting integration only after the input is complete and the error has stabilized, suppressing accumulation through both limiting and leakage. The integral limit value is set at several times the expected magnitude of the steady-state error, and the leakage coefficient causes the accumulated value to decay exponentially when there is no error input, with the decay time constant being much longer than the loop response time. The activation condition and timing lock determination share the same observation, only the threshold is more stringent. Saturation is caused by the continuous accumulation of the same sign when the correction fails to take effect. Limiting caps the magnitude, and leakage forgets the time; using both together can prevent overshoot while retaining clearing capability.

[0146] Accordingly, the symbol timing step maintains the value of the previous correction during the duration of data pattern degradation. During degradation, the phase detection output of all symbols is unreliable, and the loop averaging cannot be diluted; averaging is only effective when invalid samples are in the minority. Maintaining the previous value means that the timing continues to extrapolate based on the last reliable correction, at the cost of the transmit / receive clock frequency difference not being tracked during this period, and the timing drifting slowly. The drift amount is proportional to the product of the relative clock frequency difference and the hold duration, from which the maximum tolerable hold duration can be deduced. If the degradation is not resolved after this duration, reacquisition is initiated. After degradation is resolved, the loop does not immediately engage full gain but recovers gradually over several symbols to avoid overshoot caused by a one-time correction of accumulated drift.

[0147] The aforementioned computer device includes one or more processors, memory, and one or more application programs. The one or more application programs are stored in memory and configured to be executed by the one or more processors, and are configured to perform the carrier and timing synchronization method for the aforementioned multi-rate receiver. The aforementioned computer-readable storage medium stores at least one instruction, at least one program, code set, or instruction set, which is loaded and executed by the processor to implement the carrier and timing synchronization method for the aforementioned multi-rate receiver. In addition to being implemented in a fixed-point manner using a programmable logic device, each step of this method can also be executed by a digital signal processor, a general-purpose processor, or a software radio platform. Each module can be implemented wholly or partially in software, hardware, or a combination thereof. When implemented in a fixed-point manner, the bit width of each intermediate quantity is set according to its dynamic range and the required resolution, and the entire device can be carried within a single chip.

[0148] In one embodiment, a computer device is provided, which may be a server, and its internal structure diagram may be as follows: Figure 5 As shown, the computer device includes a processor, memory, network interface, and database connected via a system bus. The processor provides computational and control capabilities. The memory includes a non-volatile storage medium and internal memory. The non-volatile storage medium stores the operating system, computer programs, and the database. The internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage medium. The database stores data related to the carrier and timing synchronization method of a multi-rate receiver. The network interface communicates with external terminals via a network connection. When the processor executes the computer program, it implements a carrier and timing synchronization method for a multi-rate receiver.

[0149] In one embodiment, a computer device is provided, including a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, it implements the carrier and timing synchronization method of the multi-rate receiver described in the above embodiments, for example... Figure 1 Steps S1 to S8 are shown.

[0150] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When executed by a processor, the computer program implements the carrier and timing synchronization method of the multi-rate receiver described in the above embodiments, for example... Figure 1 Steps S1 to S8 are shown.

[0151] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. This computer program can be stored in a non-volatile computer-readable storage medium. When executed, the computer program can include the processes of the embodiments of the above methods. Any references to memory, storage, databases, or other media used in the embodiments of this application can include non-volatile and / or volatile memory. Non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory may include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in various forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), dual data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), etc.

[0152] The above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A carrier and timing synchronization method for a multi-rate receiver, characterized in that, The steps are as follows: S1. Determine the decimation parameters based on the symbol rate, so that the decimated sampling rate is a preset multiple of the symbol rate; S2. Perform coarse carrier frequency offset acquisition on the input signal according to the extraction parameters to obtain the estimated carrier frequency offset value, and load it into the first-stage local oscillator; S3. The carrier phase error is filtered by the carrier loop filter to obtain the integral component and the proportional component. The first-stage local oscillator phase is updated by sampling point by sampling using the integral component. The first-stage digital down-conversion and matched filtering are performed on the input signal in sequence to obtain the first-stage down-converted signal and the matched filtered signal, respectively. S4. The change in the phase of the first-stage local oscillator within the group delay of the matched filter is taken as the group delay feedforward. S5. Using the sum of the proportional component and the group delay feedforward as the second-stage rotation angle, perform phase rotation of the matched filter signal symbol by symbol using the second-stage rotation angle to obtain the second-stage down-conversion signal; S6. Perform carrier phase detection on the second-stage down-conversion signal to obtain the carrier phase error; S7. At the decision time, take the punctual sample, leading sample and lagging sample of the second-level down-conversion signal, and normalize the difference between the energy of the leading sample and the lagging sample with the energy of the punctual sample to obtain the timing error. S8. The timing error is corrected by the proportional branch of the timing loop filter to advance the symbol timing step, and the subsequent decision time is determined according to the symbol timing step. S3 to S8 are executed cyclically.

2. The carrier and timing synchronization method for a multi-rate receiver according to claim 1, characterized in that, In step S4, the phase of the first-stage local oscillator is delayed by a delay line. The depth of the delay line is equal to the group delay beat number of the matched filter. The group delay feedforward measures the difference between the current value of the phase of the first-stage local oscillator and the output value of the delay line.

3. The carrier and timing synchronization method for a multi-rate receiver according to claim 2, characterized in that, In S1, the symbol rate range is divided into multiple rate levels, and the rate level to which the symbol rate belongs is determined as the current rate level. The depth of the delay line is taken as the number of group delay cycles of the matched filter at the current rate level; The loop gain of the carrier loop filter decreases as the ratio of the depth of the delay line to the number of input samples per symbol at the current rate setting increases, where the number of input samples per symbol is the ratio of the sampling rate of the input signal to the symbol rate.

4. The carrier and timing synchronization method for a multi-rate receiver according to claim 1, characterized in that, During the execution of S3 to S8, an enable determination operation is also performed, which includes carrier frequency offset convergence determination and timing lock determination performed sequentially: The carrier frequency offset convergence determination is made when the change of the integral component within the preset observation window is lower than the preset convergence threshold. The preset observation window is counted based on the update sampling points of the first-level local oscillator phase. The timing lock determination is determined when the sliding variance of the timing error is lower than a preset lock threshold and remains no less than a preset number of symbols after the carrier frequency offset convergence determination is established. S7 and S8 are executed from the moment the carrier frequency offset convergence determination is established. The proportional gain of the carrier loop filter is reduced to a value lower than the nominal value before the timing lock determination is made. The carrier phase detection is achieved by performing a demodulation transformation to eliminate the modulation phase on the second-level downconversion signal before the timing lock determination is established, and by the decision result of the second-level downconversion signal after the timing lock determination is established.

5. The carrier and timing synchronization method for a multi-rate receiver according to claim 4, characterized in that, In step S8, the correction of the symbol timing step is performed in parallel as steps S8a and S8b: S8a. In response to the correction interval of the symbol timing step being greater than one symbol, the correction time of the symbol timing step is staggered from the update time of the second-level rotation angle by different symbols; S8b. In response to the symbol timing step-by-symbol correction, the product of the residual frequency offset after the first-level digital down-conversion and the correction amount of the current symbol timing step is used as the phase reference offset. The carrier phase error is offset compensated according to the phase reference offset. The residual frequency offset after the first-level digital down-conversion is calculated from the difference of the second-level rotation angle between two adjacent symbols.

6. The carrier and timing synchronization method for a multi-rate receiver according to claim 1, characterized in that, In S2, the carrier frequency offset coarse acquisition includes integral accumulation decimation performed on the input signal according to the decimation parameters, demodulation transformation to eliminate the modulation phase performed on the decimation result, and frequency domain transformation and spectral peak retrieval performed on the transformation result. In step S1, the extraction parameters also satisfy the following extraction constraints: The extracted sampling rate is greater than twice the product of the order of the demodulation transform and the preset maximum carrier frequency offset; The ratio of the extracted sampling rate to the number of points in the frequency domain transformation is not greater than the preset frequency resolution; The extraction parameter is not greater than the number of samples per symbol and is divisible by the number of samples per symbol, where the number of samples per symbol is the ratio of the sampling rate of the input signal to the symbol rate.

7. The carrier and timing synchronization method for a multi-rate receiver according to claim 6, characterized in that, During the execution of S3, a fine capture operation is also performed, which includes the following steps in sequence: The preset frequency resolution serves as the residual upper bound of the carrier frequency offset estimate. The fine acquisition decimation parameters are determined by replacing the preset maximum carrier frequency offset with the residual upper bound, and the fine acquisition decimation parameters are greater than the decimation parameters. The first-stage downconversion signal is subjected to integral accumulation decimation and demodulation transformation according to the fine capture decimation parameters, and the residual frequency offset estimate is obtained by frequency domain transformation and spectral peak retrieval. The residual frequency offset estimate is superimposed on the frequency of the first-stage local oscillator.

8. The carrier and timing synchronization method for a multi-rate receiver according to claim 1, characterized in that, In step S7, the sign of the punctual sample point whose energy is not lower than a preset energy threshold is determined as a valid sign, and the signal-to-noise ratio estimate is obtained by the ratio of the square of the mean to the variance of the energy of the punctual sample point within a preset statistical window. In step S8, only the timing error at the effective symbol is used to correct the symbol timing step. The effective symbol is corrected once for each accumulated effective symbol number. The effective symbol number is determined according to the signal-to-noise ratio estimate based on a preset mapping relationship. The preset mapping relationship causes the effective symbol number to decrease as the signal-to-noise ratio estimate increases.

9. A computer device, characterized in that, It includes: One or more processors; Memory; One or more applications, wherein the one or more applications are stored in the memory and configured to be executed by the one or more processors, the one or more applications being configured to: perform a carrier and timing synchronization method for a multi-rate receiver according to any one of claims 1 to 8.

10. A computer-readable storage medium, characterized in that, The storage medium stores at least one instruction, at least one program, code set, or instruction set, wherein the at least one instruction, the at least one program, the code set, or the instruction set is loaded and executed by a processor to implement: the carrier and timing synchronization method for a multi-rate receiver according to any one of claims 1 to 8.

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