Screenless compliance assessment method and system, storage medium and computer program product
By using FPGA chips for screenless compliance testing of circuit boards, the problem of low efficiency in traditional testing methods is solved, and automated, rapid multi-interface compatibility compliance testing is achieved.
Patent Information
- Application Number
- CN202611195895.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-08-07
- Publication Date
- 2026-11-03
AI Technical Summary
Traditional testing of high-speed digital video output interfaces on circuit boards relies on manual visual observation, which suffers from high subjectivity, low efficiency, and inability to quantify and record data.
The screenless compliance assessment is performed using an FPGA chip. By receiving high-speed differential serial signals and auxiliary signals from the circuit board under test, a standardized parallel pixel evaluation stream is reconstructed. Automated testing is performed using an MCU core and FPGA logic test circuit, including timing signal and power supply measurements, to achieve multi-interface compatibility.
It enables automated, screenless testing of circuit boards, improving testing efficiency, reducing subjective judgment, and providing quantitative recording and support for rapid compliance assessment of multiple interfaces.
Smart Images
Figure CN123035295A_ABST
Abstract
Description
Technical Field
[0001] This application relates to automated mass production testing technology for digital video interfaces, and in particular to a multi-interface compatibility rapid compliance evaluation method and related equipment based on programmable logic devices and independent of external display devices. Background Technology
[0002] When mass-producing circuit boards with high-speed digital video output interfaces, each board needs to undergo functional screening. Traditional testing methods rely on manual visual observation of the image displayed on an external screen, which has drawbacks such as high subjectivity, low efficiency, and inability to quantify and record data. Summary of the Invention
[0003] According to a first aspect of the present invention, embodiments of this application provide a screenless compliance evaluation method for evaluating the compliance of a circuit board with a high-speed digital video output interface, characterized in that it is applied to an FPGA chip; the method includes: receiving a high-speed differential serial signal and an auxiliary signal output by the circuit board under test through a physical transceiver interface, wherein the number of channels and compliance mode of the physical transceiver interface are set by a configuration register according to the parameters of the circuit board under test; reconstructing a normalized parallel pixel evaluation stream based on the high-speed differential serial signal and the auxiliary signal through parameter mapping, wherein the normalized parallel pixel evaluation stream carries parameters such as line labels and field labels; and determining whether the pixel evaluation stream passes the test based on a threshold. In the implementation process, the FPGA chip is configured as an MCU core and an FPGA logic test circuit; the MCU core interacts with a host computer, and the host computer sends commands to start the FPGA logic test circuit to complete the test process through a control flow method.
[0004] The method includes: the FPGA chip performing timing signal measurements and / or power supply measurements in parallel; conditioning the high-voltage timing control signals and / or low-voltage control signals of the circuit board under test to a level range that the FPGA chip can receive and process via an adapter board; and processing the power supply or positive and negative high-voltage tests related to the board under test via the adapter board.
[0005] In a preferred embodiment of the first aspect, the method includes: reconstructing a parallel pixel evaluation stream in the video stream time sequence using an FPGA and writing it to on-chip RAM storage.
[0006] According to a second aspect of the present invention, a screenless compliance evaluation system is provided for performing compliance evaluation on circuit boards containing high-speed digital video output interfaces. The system includes an FPGA chip; the FPGA chip is configured to perform the following functions: the MCU core interacts with a host computer, the host computer issues commands through an agreed serial protocol, receives configurations such as the standard evaluation stream sequence number, starts the FPGA logic test circuit, receives high-speed video signals to reconstruct the evaluation stream, the FPGA extracts corresponding parameters according to the evaluation stream sequence number, and generates a standard evaluation stream consistent with the original data; the FPGA compares the results with pre-stored parameters for compliance, and sends the test results to the host computer, completing the test process for the output video stream of the board under test.
[0007] The FPGA performs timing signal measurements, power supply measurements, and voltage measurements on the circuit board under test. These parameters need to be consistent with the relevant parameters stored in the FPGA; otherwise, the test will fail.
[0008] According to a third aspect, a computer-readable storage medium is provided, characterized in that it includes computer program instructions, which, when executed by a computing device, perform the method described in the first aspect.
[0009] According to a fourth aspect, a computer program product is provided, comprising a computer program, characterized in that, when the computer program is executed by a processor, it implements the method described in the first aspect. Attached Figure Description
[0010] Figure 1 This is a schematic diagram of a compliance assessment system according to an embodiment of this application;
[0011] Figure 2 This is a schematic diagram of the evaluation method flow according to an embodiment of this application;
[0012] Figure 3 This is a schematic diagram illustrating configurable link compliance determination.
[0013] Figure 4 This is a schematic diagram illustrating the interactive communication processing status between the host computer and the MCU core inside the FPGA.
[0014] Figure 5 A schematic diagram illustrating the implementation of video extraction buffer (logical parallelism) and video algorithm recognition;
[0015] Figure 6 This is a grayscale test diagram involved in the logic test circuit;
[0016] Figure 7 This is a color bar test diagram involved in the logic test circuit.
[0017] The solution provided in this application will now be described with reference to the accompanying drawings. In this application, "multiple" refers to two or more objects, and "various kinds" refers to two or more types. Terms such as "first," "second," etc., are used only to distinguish similar objects and are not necessarily used to describe a specific order or number of objects.
[0018] Figure 1 This is a schematic diagram of a compliance assessment system according to an embodiment of this application. Figure 1 As shown, the compliance assessment system may include: a host computer 10, a signal excitation source 12, a board under test 14, and an FPGA chip 18. In some cases, the system may also include an adapter board 16.
[0019] The host computer 10 includes communication and interaction between the signal excitation source 12 and the FPAG chip 18, and completes the coordinated control of the entire system.
[0020] The signal excitation source 12 includes a specific screen output for the graphics testing process. For example, the signal excitation source 12 can receive a test file based on RGB data from the host computer 10, generate a first image signal corresponding to the target image screen based on the test file, and periodically send the first image signal to the board under test 14 according to the frame rate.
[0021] The board under test 14 is the object under test, and its loading and switching can be achieved by a tooling fixture. The board under test 14 generates a second image signal in the same RGB format based on the first image signal. The second image signal has second RGB data, while the first image signal has first RGB data.
[0022] The adapter board 16 can perform signal conversion between the board under test 14 and the FPGA chip 18 when needed. During power supply measurement, the high voltage and positive and negative high voltage signals output by the board under test need to undergo high-low voltage conversion processing such as voltage division attenuation, level boosting, and electrical isolation by the adapter board. After being converted into a low-voltage analog signal adapted to the ADC input range, it can be sent to the FPGA chip to complete the power supply sampling measurement. The MCU core of the FPGA chip reverse-calculates the sampled data based on the gain and voltage division coefficient of the high-low voltage conversion circuit to obtain the actual power supply voltage value, thereby completing the power supply parameter compliance verification.
[0023] Different circuit boards may have high-voltage signals such as STV, CPV, CLK, POL, LC, POL, and RST. These can be converted to low-voltage signals using an external adapter board. Different circuit boards may also have different power supplies or gamma power supplies. These can be acquired using the ADC of an external adapter board, and the driver interface can use the universal SPI interface.
[0024] The FPGA chip 18 performs functional testing and image algorithm recognition and extraction for the board under test. Functional testing includes timing signal measurement and power supply measurement. Image algorithm recognition involves identifying / comparing and recording image features (e.g., red, green, and blue monochrome detection, color bar detection).
[0025] The FPGA chip 18 may contain: an interface module 180, an MCU core 182, a configuration register 184, an FPGA logic test circuit 186, and a communication IP 188.
[0026] [1] Interface module 180
[0027] The interface module 180 can receive high-speed differential serial signals output from the circuit board under test. The interface module 180 can be parameterized, meaning that the electrical characteristics, link rate, equalization, and timing control conditions of the underlying physical transceiver hardware such as SerDes and LVDS are all designed with configurable parameters and have no fixed hardware coding. The on-chip MCU core can read different versions of the configuration BIN in RAM and switch the interface working mode by updating the FPGA configuration file.
[0028] Through the parameterized interface module 180, a single hardware circuit can be compatible with multiple video transceiver standards such as eDP, VBO, and LVDS, enabling adaptive matching with various types of boards under test. In other words, different configuration files will be configured to use different standard interfaces.
[0029] In some cases, interface module 180 also needs to receive auxiliary signals. For example, the auxiliary channel aux is needed for video boards in the EDP because different video sources have different interfaces. This demonstrates the flexibility of the FPGA, allowing for quick switching between different solutions.
[0030] [2] MCU core 182
[0031] The MCU core 182 can be equipped with a configuration register set, communication interface IP, and on-chip RAM. The MCU core reads and writes registers via address mapping to control the FPGA logic test circuit and communication IP module. The MCU core can act as a bus master, actively reading and writing to external slave devices. Therefore, the FPGA logic test circuit, communication IP module, and register array can all upload data processing status, communication interrupts, and buffer full flags to the host computer MCU core.
[0032] The MCU core 182 can interact with the host computer 10 via, for example, serial communication; it executes the test process according to the issued commands and records and transmits the screen feature recognition measurement results. The recognition measurement includes, but is not limited to, screen parameter information, control timing information, screen recognition judgment information, and measurement information of different power supplies.
[0033] The MCU core 182 can control local logic test circuits, communicate and interact with external host computers, receive and execute instructions, and configure local parameters at any time, making it quite flexible.
[0034] Because different video protocols differ, the MCU core 182 can be configured through parameterization in terms of judgment conditions to meet the needs of different test items.
[0035] For example, depending on the differences between EDP and VBO, the information obtained by the host computer will be different, and the MCU core will provide different feedback.
[0036] [3] Configuration register 184 (control / status register group)
[0037] Configuration register 184 may include configuration registers for different protocol interfaces and control / status register groups.
[0038] [4] Logic test circuit 186
[0039] The logic test circuit 186 can detect the STV timing trigger signal to initiate the test, and then can initiate all timing signal measurements and power measurements in parallel. For example, the logic test circuit 186 can receive external timing signals through an I / O buffer; it can use a high-frequency reference clock counter to measure timing parameters such as line period, vertical period, and effective data window width; all timing measurement values can be stored in a register set and read and converted by the on-chip MCU core to complete the video timing compliance verification.
[0040] The logic test circuit 186 can buffer the standardized RGB data rows according to the video stream timing and write them to the on-chip RAM for storage; the logic test circuit 186 can buffer the standardized RGB data rows according to the video stream timing and perform frame buffering according to different subsequent test conditions.
[0041] The on-chip RAM, acting as a row-level cache, can support real-time pipelined processing, simultaneously completing timing parsing, pixel preprocessing, single-frame pixel counting and checksum real-time statistics.
[0042] The MCU core can uniformly read all detection indicators and combine them with preset parameter configuration files to achieve comprehensive compliance judgment of video streams.
[0043] [5] Communication IP188
[0044] The IP188 communication module can include a UART communication module to enable interactive communication between the MCU core and the host computer.
[0045] The MCU core interacts with the host computer via the UART communication module, initiating the test process through control flow by receiving commands from the host computer, parsing the received signals according to the protocol, and unifying them into standard RGB pixel data. The MCU core allows for rapid configuration of parameters and definition of test items for different boards under test, and enables the entire test process to be carried out according to the instructions from the host computer.
[0046] The MCU core completes the image feature recognition, comparison, and recording (e.g., red, green, and blue monochrome detection, color bar detection) and feeds back to the host computer according to the instructions issued by the host computer. These instructions can be defined or configured at the software development level; they can perform status queries, read the test data results, etc. Different boards under test have different functions, and the corresponding instructions will vary.
[0047] The host computer reads the measurement results through the UART communication module to determine whether the board under test has passed the verification.
[0048] The above system requires only a single chip to achieve multi-interface adaptation; real-time evaluation can be completed based on row-level pipeline processing and hardware accumulators; simple legends can be accessed without ROM, and complex legends can be looked up on demand, balancing speed and accuracy; if an anomaly is detected, the system will stop immediately, providing strong support for production line cycle time; batch fault statistics and trend warnings are independently completed within the FPGA, making single-board testing a closed loop of process quality.
[0049] The following is combined with Figure 2 explain Figure 1 The system's working process. Figure 2 This is a schematic diagram of the evaluation method flow according to an embodiment of this application. Figure 2 The evaluation workflow is described below.
[0050] like Figure 2 As shown, the workflow includes six steps: FPGA power-on, excitation source output, board under test power-on, test start, measurement results, and test completion.
[0051] [1] FPGA power-on
[0052] The host computer controls the FPGA system to power on and loads an external BIN file to map functional logic circuits. The mapped functional modules can include an MCU core and logic test circuits. The file can be loaded via online programming by the host computer or by reading from local flash memory. After the FPGA system completes loading, the MCU core will complete the parameterization configuration of the test system registers.
[0053] A BIN file is a binary format FPGA configuration bitstream file. This file is generated by FPGA development tools after compiling, synthesizing, and placing and routing a complete system design, including the core MCU, logic test circuits, and on-chip memory. It is used to configure the FPGA chip during the power-on phase, mapping the system's hardware logic functions.
[0054] The BIN file contains FPGA configuration bitstream and memory initialization data. The memory initialization data is used to initialize the on-chip ROM and RAM. The on-chip ROM stores the startup program and algorithm feature data of the core MCU.
[0055] After the system is powered on, the BIN file is read from the local Flash memory via online programming on the host computer or by writing the configuration bit stream in the BIN file into the configuration storage unit of the FPGA. This completes the configuration of programmable logic resources and interconnection resources, realizing the hardware mapping between the MCU core and the logic test circuit. At the same time, the memory initialization data in the BIN file is written into the on-chip ROM and RAM, enabling the core MCU to read and execute the startup program from the on-chip ROM after power-on reset, and to read algorithm feature data from the on-chip RAM or ROM to complete the predetermined algorithm function.
[0056] [2] Excitation source output
[0057] The excitation source output is controlled by the host computer through communication, and the signal excitation is connected to the input terminal of the board under test.
[0058] [3] Powering on the board under test
[0059] The tooling fixture is used to import the new board under test (DUT). After the DUT is powered on, it will output relevant power and timing control signals, as well as video stream signals, in the order of system power-on. The electrical outputs of the DUT after normal power-on operation will include high-voltage power supply, low-voltage power supply, high-voltage timing signals, low-voltage timing signals, and high-speed video signals, depending on the video board.
[0060] [4] Test started
[0061] The FPGA chip will be powered on in advance, so that the MCU core can start the program and initialize the system through the preset boot ROM file.
[0062] The MCU core can load algorithm feature data that matches the function of the board under test through RAM resources, and initialize different operating frequencies output by the external clock chip through the interface based on the algorithm feature data.
[0063] Different bin files can be loaded for different test boards, such as EDP / VBO / MINI-LVDS, so the solution in this application is flexible and has low implementation cost.
[0064] Based on the power-on timing signals of the board under test, the logic test circuit will initiate automatic testing and record the corresponding test results to the corresponding registers according to the configuration information. Pattern switching will be performed according to the test steps. Switching can be controlled by a host computer, and the FPGA system will identify and judge the changes based on the received instructions.
[0065] The FPGA logic test circuit detects the STV timing trigger signal to start the test and records the current test start position information, which the MCU core can query at any time.
[0066] [5] Measurement results
[0067] The FPGA logic test circuit will initiate various timing signal measurements and power supply measurements.
[0068] Some boards under test, such as MINI-LVDS, have high-voltage timing control signals related to the gate driver, such as STV, CPV, CLK, POL, LC, POL, RST, etc. These high-voltage signals are converted to low-voltage signals through an external adapter board.
[0069] Some boards under test include low-voltage control signals, which are all sent to an external adapter board and conditioned to a level range that the FPGA can receive and process.
[0070] Some boards under test require power supply, positive and negative high voltage tests, and all related test signals are processed by an external adapter board. The adapter board also has a reserved communication interface, such as an SPI interface, to enable data interaction with the FPGA.
[0071] For example, the board under test has positive and negative power supplies, gamma power supply, and can perform AD sampling through an external adapter board, while the FPGA obtains data through the SPI interface.
[0072] For example, the board under test has high-voltage timing signals (STV, CPV, CLK, POL, LC, POL, RST, etc. depending on the screen), which are converted to low-voltage signals by an external adapter board, and then received and acquired by the FPGA.
[0073] Basic screen parameter identification and control logic timing signals are automatically measured and recorded in local registers after the board under test starts working, which can be read at any time, thus fully demonstrating the parallelism of FPGA.
[0074] FPGA logic test circuits can achieve multi-channel parallel driving to complete various measurement tasks in parallel.
[0075] The host computer provides a final judgment based on the measurement data. The status of the board under test is recorded according to the ID information of the board under test.
[0076] After timing control, power supply testing, and video stream testing, the verification results of each channel can be used to determine configurable link compliance. If all enabled items pass, the link is considered compliant; otherwise, abnormal channels are recorded and the test is terminated. All measurement information matches the design specifications of the board under test, and any abnormal results are recorded. The host computer can issue commands to read the status and results at any time.
[0077] [6] Test completed
[0078] The host computer determines whether the board under test has passed verification by reading the results of the measurement items.
[0079] If the results of each item are valid, the verification is successful; if the verification fails, the item is removed and recorded, and the problem is recorded by scanning the code on the board being tested, and then the next step of screening is carried out.
[0080] The control power supply system and fixture system switch to the next board under test. The power supply to the board under test is cut off and it is removed. The process jumps back to stage 3 to test the new board under test.
[0081] The embodiments of this application can use an FPGA to receive video streams instead of directly connecting the board under test (DUT) to a screen, and process the streams in real time through internal logic circuits. This eliminates the need for the DUT to connect to different types of screens, thus truly achieving screenless testing. The embodiments of this application can also reduce the space occupied by different types of screens, thus reducing the space required for the testing station. Furthermore, the automated testing process avoids subjective judgment and improves testing efficiency. The embodiments of this application are very convenient when switching between different DUT testing schemes; only the FPGA configuration file needs to be updated.
[0082] The following describes several aspects of the embodiments of this application, including configurable link compliance determination, interaction between the host computer and the MCU core inside the FPGA chip, and video extraction buffer (logical parallelism) and video algorithm recognition implementation.
[0083] Figure 3 This is a diagram illustrating configurable link compliance determination. For example... Figure 3 As shown, after power-on initialization, the FPGA loads the values of m, n, and k, as well as the link compliance mode, through the configuration register. It receives high-speed serial / differential signals and auxiliary signals from the board under test. Taking the SerDes channel as an example, only its clock recovery lock flag and encoded symbol alignment flag need to be checked; for the source synchronization channel, the period and pulse width of the synchronization signal are statistically analyzed through oversampling. The verification results of all channels are used to determine configurable link compliance. If all enabled items pass, the link is considered compliant; otherwise, abnormal channels are recorded and the test is terminated.
[0084] Figure 4is a schematic diagram of the interactive communication between the host computer and the MCU core inside the FPGA chip. As shown in Figure 4 , the host computer realizes communication interaction with the MCU inside the FPGA chip through the communication IP, completing instruction issuance, status query, and data acquisition. The MCU core completes logical judgment through the FPGA locally solidified ROM program.
[0085] After the evaluation is completed, the result code is sent to the host computer through the UART interface. The host computer only receives the single-board conclusion and fault code, and does not participate in or control the evaluation process.
[0086] At the same time, the batch fault summary module inside the FPGA continuously counts the occurrence frequency and trend of various faults in the current batch. When the same type of fault continuously exceeds the preset red line, it actively sends out an early warning signal and uploads the packaged batch report, realizing closed-loop quality control without host intervention.
[0087] Figure 5 is the implementation of video extraction buffering (logical parallel) and video algorithm recognition involved in the aforementioned logic test circuit.
[0088] The high-speed differential video signal output by the tested circuit board card is received through the interface module. According to the display specification of the tested circuit board card, the MCU sets the number of channels of the physical transceiver interface, screen parameters, image algorithm and its feature values, test thresholds, corresponding configuration registers, etc.; according to the high-speed differential serial video stream signal, a standardized parallel pixel evaluation stream is obtained through parameter mapping reconstruction; the mean square error between the evaluation stream output by the tested circuit board card and the original standard evaluation stream is calculated, and the evaluation stream reconstructed by the FPGA is compared with the set standard evaluation stream; the mean square error threshold corresponding to the known standard test stream and other related electrical signal parameters are obtained from the reference parameter source pre-set inside the programmable logic device; if the mean square error is less than the set threshold and the relevant electrical signal parameters are consistent, it is determined that the tested circuit board card meets the specification test, otherwise it does not meet the specification test.
[0089] The generation of the standard test stream is described below. Figure 6 is a schematic diagram of the horizontal grayscale test stream. In one embodiment, the standard horizontal grayscale test stream can be generated using the following generation rules.
[0090] First, in step 61, the width of the image is divided by 256 to obtain the grayscale step step (which may be a decimal); then, in step 62, x=0 is initialized; then, in step 63, i=floor(x / step) is set, red R=i, green G=i, blue B=i; where floor represents the rounding down operation; in step 64, x=x+1, if x<width, the calculation of step 63 is continued; otherwise, the calculation is ended, and the image generation is completed.
[0091] Figure 7 This is a schematic diagram of a vertical strip test flow. In one implementation, a standard vertical strip test flow can be generated using the following generation rules.
[0092] In step 71, divide the image width by 8 and round down, i.e., x = floor(width / 8); the remainder rem = mod(width, 8). In step 72, the width of the left 7 bars is x, and the height of the 8th bar is x + rem. In step 73, the first bar is black, i.e., red R = 0x00, green G = 0x00, and blue B = 0x00. In step 74, the second bar is blue, i.e., red R = 0x00, green G = 0x00, and blue B = 0xFF. In step 75, the third bar is green, meaning red R=0x00, green G=0xFF, and blue B=0x00. In step 76, the fourth bar is cyan, meaning red R=0x00, green G=0xFF, and blue B=0xFF. In step 77, the fifth bar is red, meaning red R=0xFF, green G=0x00, and blue B=0x00. In step 78, the sixth bar is purple, meaning red R=0xFF, green G=0x00, and blue B=0xFF. In step 79, the seventh bar is yellow, meaning red R=0xFF, green G=0xFF, and blue B=0x00. In step 80, the eighth bar is white, meaning red R=0xFF, green G=0xFF, and blue B=0xFF.
[0093] The testing process for the test flow is as follows:
[0094] S501, The host computer sends the specification evaluation stream sequence number to the FPGA system that is yet to be sent.
[0095] S502, The host computer sends the first signal of the FPGA system specification test stream;
[0096] S503, the first signal outputs the corresponding pixel stream second signal through the circuit board under test;
[0097] While detecting the second signal, the S504 and FPGA systems generate corresponding standard test flow third signals line by line according to the test flow sequence number. The third signal is consistent with the first signal.
[0098] S505. Compare the second signal with the third signal pixel by pixel to obtain the mean square error;
[0099] S506. If the mean square error is within the set threshold range (the closer to zero the better), the specification evaluation flow passes the test; otherwise, the specification evaluation flow test fails.
[0100] The formula for calculating the mean square error is:
[0101] ,in It is the third signal pixel. is the second signal pixel; n is the total number of pixels.
[0102] Based on the high-speed differential serial signal, a normalized pixel evaluation stream is reconstructed via parameter mapping. A histogram is calculated for the reconstructed normalized pixel evaluation stream. The mean square error between the reconstructed normalized pixel evaluation stream and the corresponding original evaluation stream is calculated. From the reference parameter source pre-embedded inside the programmable logic device, the histogram of the corresponding evaluation stream, the judgment threshold, and the mean square error threshold are obtained. If the difference between the histograms of the reconstructed evaluation stream and the original evaluation stream is less than the set threshold, and the mean square error between the reconstructed evaluation stream and the original evaluation stream is also less than the set threshold, a test pass signal is issued; otherwise, a test failure signal is issued.
[0103] Provide standardized test flows with a certain test coverage, such as grayscale images or bar charts. These standardized test flows do not require additional memory storage and can be generated according to rules, covering the test pixels. Calculate the histogram for each standardized test flow and store the image feature value parameters, including the histogram, and the sequence number in the relevant memory of the FPGA.
[0104] In various embodiments, the operations discussed herein (e.g., with reference to the accompanying drawings described herein) can be implemented as hardware (e.g., logic test circuitry), software, firmware, or a combination thereof, which can be provided as a computer program product, for example, including a tangible (e.g., non-transitory) machine-readable or computer-readable medium on which instructions (or software processes) are stored for programming a computer to perform the processes discussed herein. Machine-readable media can include storage devices such as those discussed with respect to the accompanying drawings.
[0105] Furthermore, such computer-readable medium can be downloaded as a computer program product, wherein the program can be provided via a communication link (e.g., bus, modem, or network connection) in a carrier or other propagation medium, transmitted from a remote computer (e.g., server) to a requesting computer (e.g., client) via data signals.
[0106] The reference to "an embodiment" or "an embodiment" in the specification means that a particular feature, structure, and / or characteristic described in connection with that embodiment may be included in at least one implementation. The phrase "in an embodiment" appearing in various places in the specification may or may not refer to the same embodiment.
[0107] Furthermore, the terms “coupled” and “connected”, and their derivatives, may be used in the description and claims. In some embodiments, “connected” may be used to indicate that two or more elements are in direct physical or electrical contact with each other. “Coupled” may mean that two or more elements are in direct physical or electrical contact. However, “coupled” may also mean that two or more elements may not be in direct contact with each other, but may still cooperate or interact with each other.
[0108] Therefore, although the embodiments have been described in language specific to structural features and / or method actions, it should be understood that the claimed subject matter may not be limited to the specific features or actions described. Instead, specific features and actions are disclosed as exemplary forms for implementing the claimed subject matter.
Claims
1. A screenless compliance evaluation method for evaluating the compliance of circuit boards containing high-speed digital video output interfaces, characterized in that, Applied to FPGA chips; the method includes: The high-speed differential serial signal output by the circuit board under test is received through the physical transceiver interface. The number of channels and compliance mode of the physical transceiver interface are set by the configuration register according to the parameters of the circuit board under test. The pixel evaluation stream is reconstructed based on the high-speed differential serial signal via parameter mapping. The pixel evaluation stream and the standard evaluation stream set by the FPGA test system are compared, and the mean square error between the standard evaluation stream and the reconstruction evaluation stream is calculated. If the mean square error is less than the given threshold, a test pass signal is given; otherwise, a test failure signal is given.
2. The method as described in claim 1, characterized in that: The method includes: Receive test stream sequence number; The specification evaluation stream is generated based on the test stream sequence number, and the specification evaluation stream is the test data covering the pixels.
3. The method as described in claim 1, characterized in that: Configure the FPGA chip as an MCU core and logic test circuit; The MCU core interacts with the host computer, receives commands issued by the host computer through the agreed serial protocol, receives the standard evaluation stream configuration information, starts the FPGA logic test circuit, receives high-speed video signals to reconstruct the evaluation stream, and the FPGA extracts the corresponding parameters according to the evaluation stream sequence number and generates a standard evaluation stream consistent with the original data. The test results are compared with the pre-stored parameters for compliance and sent to the host computer to complete the test process of the video stream output by the board under test.
4. The method as described in claim 1, characterized in that: The method includes: the FPGA chip performing one or more of timing signal measurement, power supply measurement, and voltage measurement on the circuit board under test; if the measured parameters are not consistent with the relevant parameters stored in the FPGA, the circuit board under test is determined to have failed the test.
5. The method as described in claim 1, characterized in that: The FPGA chip includes a hardware logic threshold memory that stores thresholds used for judging pixel evaluation streams. The method includes determining whether a pixel evaluation stream passes the test based on the threshold.
6. A screenless compliance evaluation system for evaluating the compliance of circuit boards containing high-speed digital video output interfaces, characterized in that, The system includes an FPGA chip configured to perform the following functions: The high-speed differential serial video signal output by the circuit board under test is received through the physical transceiver interface; wherein, the number of channels of the physical transceiver interface and the corresponding configuration register are set according to the parameters of the circuit board under test. The pixel evaluation stream is reconstructed based on the high-speed differential serial video signal via parameter mapping; The pixel evaluation stream is compared with the corresponding standard evaluation stream set by the FPGA test system, and the mean square error between the standard evaluation stream and the reconstruction evaluation stream is calculated. If the mean square error is less than the given threshold and consistent with the reference parameter set inside the programmable logic device, a test pass signal is given; otherwise, a test failure signal is issued.
7. The screenless compliance evaluation system as described in claim 6, wherein the system further includes an adapter board, the adapter board conditioning the high voltage timing control signal and / or low voltage control signal of the circuit board under test to a level range that the FPGA chip can receive and process, and / or processing the power supply or positive and negative high voltage tests related to the circuit board under test.
8. A computer-readable storage medium, characterized in that, It includes computer program instructions, which, when executed by a computing device, cause the computing device to perform the method of any one of claims 1-5.
9. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by a processor, it implements the method as described in any one of claims 1-5.