Semiconductor package and method of forming the same

Abstract

A semiconductor package and a method of forming the same are disclosed. The semiconductor package includes a redistribution layer structure having a first surface and a second surface opposite the first surface; a first die disposed on the first surface of the redistribution layer structure; a stress buffer structure disposed on the second surface of the redistribution layer structure, wherein the stress buffer structure includes a stress buffer layer and a conductive stud passing through the stress buffer layer; and a conductive bump structure disposed on the conductive stud and opposite the first die, wherein the conductive bump structure is electrically coupled to the first die through the stress buffer structure and the redistribution layer structure. When the semiconductor package is joined with a printed circuit board, the additional stress buffer structure can release stress from the printed circuit board during the joining process, thereby preventing damage to the redistribution layer structure and the first die.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to semiconductor packaging and its formation methods. Background Technology

[0002] To meet the growing demands of data centers, networking, and artificial intelligence, the ongoing pursuit of higher computing power and data bandwidth has driven the development of advanced packaging solutions for higher-performance devices.

[0003] In advanced packaging technologies, wafer-level fan-out has emerged as a highly attractive heterogeneous integration packaging solution. Wafer-level fan-out utilizes fine-pitch redistribution layer (RDL) technology for die interconnection, enabling the development of high-performance products with large package sizes and high interconnect densities. However, as networking and high-performance applications require the integration of more dies, the overall die size and package size continue to increase, making package reliability a critical issue. With increasing die size, packaging stress from the printed circuit board (PCB) can damage the die. Furthermore, the mismatch in the coefficient of thermal expansion (CTE) between the die and the interposer increases the risk of package failure and RDL failure in fan-out packages.

[0004] Therefore, a new type of semiconductor packaging structure is needed. Summary of the Invention

[0005] In view of this, the present invention provides a semiconductor package and a method for forming the same, to provide a more reliable semiconductor package and reduce the risk of RDL damage in the package.

[0006] An embodiment of the present invention provides a semiconductor package including a redistribution layer structure having a first surface and a second surface opposite to the first surface; a first die disposed on the first surface of the redistribution layer structure; a stress buffer structure disposed on the second surface of the redistribution layer structure, wherein the stress buffer structure includes a stress buffer layer and a conductive post passing through the stress buffer layer; and a conductive bump structure disposed on the conductive post and opposite to the first die, wherein the conductive bump structure is electrically coupled to the first die through the stress buffer structure and the redistribution layer structure.

[0007] Furthermore, the redistribution layer structure includes conductive vias, the size of which is smaller than the size of the conductive post. The conductive post, with its larger size, resists stress, thereby effectively buffering stress transmission.

[0008] Furthermore, the sidewalls of the stress buffer structure protrude beyond the corresponding sidewalls of the redistribution layer structure, and the redistribution layer structure partially covers the stress buffer structure. This gives the stress buffer structure a large coverage area, allowing for comprehensive stress buffering of the redistribution layer structure and other components, thereby protecting other parts of the semiconductor package.

[0009] Furthermore, the coefficient of thermal expansion of this stress buffer layer is between 3.5 and 24 ppm / ℃. This can greatly reduce the CTE mismatch between the grain and the redistribution layer structure, thereby reducing warpage of the semiconductor package.

[0010] Furthermore, it also includes a molding compound disposed on the redistribution layer structure and surrounding the first grain, wherein the molding compound surrounds the redistribution layer structure and contacts the stress buffer layer. The molding compound can protect the first grain and the redistribution layer structure, and cover the rest of the stress buffer structure to maintain the integrity of the structure, thereby improving the stability of the stress buffer structure and the semiconductor package structure.

[0011] Furthermore, the sidewalls of the molding compound are flush with the corresponding sidewalls of the stress-relief structure. This ensures the flatness and stability of the semiconductor package structure.

[0012] Furthermore, the interface between the stress buffer layer and the redistribution layer structure is flush with the interface between the stress buffer layer and the molding compound. This facilitates the manufacturing and molding of the stress buffer layer, redistribution layer structure, and molding compound, and ensures a tight fit between the components, thereby improving structural stability.

[0013] Furthermore, the redistribution layer structure and the molding compound together cover the entire upper surface of the stress-relief structure. This maintains the integrity of the structure, thereby improving the stability of the stress-relief structure and the semiconductor package structure.

[0014] Furthermore, the redistribution layer structure is in contact with the stress buffer structure, and the molding compound is also in contact with the stress buffer structure. This maintains the integrity of the structure and ensures a tight fit between the components, thereby improving structural stability.

[0015] Furthermore, the material of this stress-relief layer is selected from polyimide (PI), polybenzoxazole (PBO), glass fiber, epoxy resin, FR4, molding compound, or combinations thereof, to meet different material requirements.

[0016] Furthermore, it also includes a passivation layer disposed on the stress buffer layer and surrounding a portion of the conductive post, wherein the conductive post passes through the passivation layer and contacts the conductive bump structure. The passivation layer can protect the conductive post and reduce stress on the conductive post.

[0017] Furthermore, the passivation layer forms the bottom surface of the stress buffer structure from the surface exposed by the stress buffer layer.

[0018] Furthermore, the passivation layer surrounds the portion of the conductive post near the bottom surface of the stress buffer structure.

[0019] Furthermore, the thickness of the conductive post is less than the thickness of the first die. This reduces the overall height of the semiconductor package structure, and the conductive post provides a shorter electrical connection path with lower impedance. In addition, the thinner conductive post can also prevent deformation or breakage when subjected to stress.

[0020] A method for forming a semiconductor package includes: forming a conductive pillar and a stress buffer layer surrounding the conductive pillar on a carrier, wherein the conductive pillar and the stress buffer layer form a stress buffer structure; forming a redistribution layer structure on the stress buffer structure; disposing a first grain on the redistribution layer structure; and forming a conductive bump structure on the conductive pillar of the stress buffer structure, the conductive bump structure being opposite to the first grain.

[0021] Furthermore, forming a conductive pillar and a stress buffer layer surrounding the conductive pillar on the carrier includes: sequentially forming a passivation layer and a seed layer on the carrier, wherein the passivation layer has an opening; forming a conductive pillar on the seed layer; forming a stress buffer layer covering the passivation layer and the conductive pillar; and removing a portion of the stress buffer layer until the conductive pillar is exposed.

[0022] Furthermore, forming a conductive pillar and a stress buffer layer surrounding the conductive pillar on the carrier includes: sequentially forming a seed layer and a passivation layer on the carrier, wherein the passivation layer has a first opening exposing a portion of the seed layer; forming a stress buffer layer covering the passivation layer and the seed layer exposed from the first opening of the passivation layer; forming a second opening through the stress buffer layer, wherein the second opening is aligned with the first opening; forming the conductive pillar on the seed layer in the first opening of the passivation layer and the second opening of the stress buffer layer; and removing a portion of the stress buffer layer and a portion of the conductive pillar, such that the surfaces of the stress buffer layer and the conductive pillar away from the carrier are flush with each other.

[0023] Furthermore, it also includes: forming a molding compound on the stress buffer structure, wherein the molding compound surrounds the redistribution layer structure and the first grain; and removing the carrier from the stress buffer structure.

[0024] Furthermore, it also includes cutting the molding compound and the stress buffer structure at the interface between the molding compound and the stress buffer layer of the stress buffer structure, along a direction substantially perpendicular to the interface between the molding compound and the stress buffer layer of the stress buffer structure.

[0025] Furthermore, forming the conductive bump structure also includes: forming a bump under metal layer on the conductive post at a position opposite to the redistribution layer structure; and forming a conductive ball structure on the bump under metal layer.

[0026] The semiconductor package of this invention includes a redistribution layer structure having a first surface and a second surface opposite to the first surface; a first die disposed on the first surface of the redistribution layer structure; a stress buffer structure disposed on the second surface of the redistribution layer structure, wherein the stress buffer structure includes a stress buffer layer and conductive pillars passing through the stress buffer layer; and a conductive bump structure disposed on the conductive pillars and opposite to the first die, wherein the conductive bump structure is electrically coupled to the first die through the stress buffer structure and the redistribution layer structure. Therefore, when the semiconductor package is bonded to a printed circuit board (PCB), the additional stress buffer structure can release (or buffer) stress from the PCB during the bonding process, thereby preventing damage to the redistribution layer structure and the first die. The conductive pillars of the metal in the stress buffer structure have high strength to resist stress, while the stress buffer layer surrounding the conductive pillars can effectively buffer stress. Therefore, the stress buffer structure used in this invention combines the advantages of both, thereby more effectively buffering stress and also reducing the warpage of the semiconductor package. Attached Figure Description

[0027] Figure 1 This is a schematic cross-sectional view of a semiconductor package according to some embodiments of the present invention;

[0028] Figure 2 This is a schematic cross-sectional view of a semiconductor package according to some embodiments of the present invention;

[0029] Figure 3 , 4 5, 6, 7 and 8 are embodiments of the present invention. Figure 1 The image shows a cross-sectional view of an intermediate stage in the formation of a semiconductor package.

[0030] Figure 9 , 10 11, 12, 13 and 14 are embodiments of the present invention. Figure 2 The image shows a cross-sectional view of an intermediate stage in the formation of a semiconductor package. Detailed Implementation

[0031] The following description is for illustrative purposes only and should not be construed as limiting. The scope of the invention is best determined by reference to the appended claims. In embodiments of the invention, when an element or layer is referred to as being “located,” “connected to,” or “coupled to” another element or layer, it may be directly located, connected to, or coupled to that other element or layer, or there may be intermediate elements or layers. Conversely, when an element is referred to as being “directly located,” “directly connected to,” or “directly coupled to” another element or layer, there are no intermediate elements or layers. The same numbers always refer to the same element. The term “and / or” as used herein includes any and all combinations of one or more of the associated listed items. “Directly above” or “directly below” may indicate that the projections of two or more of them at least partially overlap, while “not directly above” or “directly below” may indicate that the projections of two or more of them do not overlap at all.

[0032] In traditional 2.5D (side-by-side) semiconductor packaging, the redistribution layer (RDL) interposer is built directly onto the carrier. There is no robust material between the RDL interposer and the solder balls. When the semiconductor package is bonded to the printed circuit board (PCB), the (bonding) stress from the PCB cannot be effectively buffered by the RDL layer, potentially damaging the system-on-chip (SoC) die. Furthermore, due to the significant mismatch in coefficient of thermal expansion (CTE) between the RDL interposer and the die, traditional 2.5D semiconductor packages may suffer greater warpage. Therefore, a novel semiconductor packaging structure is needed to address these issues.

[0033] Figure 1 This is a schematic cross-sectional view of a semiconductor package 500A according to some embodiments of the present invention. In some embodiments, the semiconductor package 500A can be used to form a fan-out package, a two-dimensional (2D) package, a 2.5D package, a three-dimensional (3D) semiconductor package, or other suitable package. The semiconductor package 500A may be mounted on a base 100. In some embodiments, the semiconductor package 500A may not include the base 100; that is, the base 100 is located outside the semiconductor package 500A. Figure 1 In the following figures, direction D10 is defined as the horizontal direction (also considered as the extension direction of the conductive layer and / or conductive trace of semiconductor package 500A), and direction D12 is defined as the vertical direction (also considered as the extension direction of the via and / or through-hole of semiconductor package 500A).

[0034] like Figure 1As shown, the base 100 can be a single-layer structure or a multi-layer structure. In some embodiments, the base 100 is, for example, a printed circuit board (PCB), an interposer, a packaging substrate, other semiconductor devices, or a semiconductor package. In some embodiments, the base 100 may be formed of a dielectric material (e.g., polypropylene (PP), epoxy resin, polyimide, or other suitable resin material) or a semiconductor material. The base 100 has an upper surface 100T and a bottom surface 100B opposite to the upper surface 100T. The base 100 is used for a semiconductor package 500A disposed on the upper surface 100T. A plurality of conductive traces (not shown), conductive vias, and / or conductive pads (not shown) are provided within the base 100. The conductive traces are electrically connected to the corresponding conductive vias and conductive pads. The conductive pads and / or conductive traces are exposed through openings in a solder mask layer (not shown) disposed near the upper surface 100T and the bottom surface 100B. In one embodiment, the conductive trace may include signal trace segments or ground trace segments for input / output (I / O) connections of the semiconductor package 500A. Furthermore, conductive pads are disposed on the upper surface 100T of the base 100 and connected to different terminals of the conductive traces. The conductive pads are used for direct mounting of the semiconductor package 500A thereon.

[0035] like Figure 1 As shown, the semiconductor package 500A is mounted on the substrate 100 using a bonding process with conductive bump structure 322. The semiconductor package 500A includes a first die 302, a second die 304 (the second die is optional, for example), a redistribution layer (RDL) structure 316-2, a stress buffer structure 316-1A, a molding compound 330, and a conductive bump structure 322.

[0036] The conductive bump structure 322 contacts and is electrically connected (or coupled) to the stress buffer structure 316-1A and the base 100. In some embodiments, the conductive bump structure 322 includes a conductive ball structure (e.g., a copper ball), a conductive bump structure (e.g., a copper bump), or a solder bump structure. For example, the conductive bump structure 322 may be a controlled collapse chip connection (C4) structure. In some embodiments, each conductive bump structure 322 may include an under bump metallurgy (UBM) 323 and a conductive ball structure 324 located on the under bump metallurgy (UBM) 323.

[0037] In some embodiments, the under bump metallurgy (UBM) 323 includes a seed layer (not shown), such as a pure copper (Cu) layer, a pure titanium (Ti) layer, a Ti / Cu layer, a TiW / Cu layer, any other metal layer, or combinations thereof. In some other embodiments, the under bump metallurgy (UBM) 323 includes a nickel (Ni) layer formed on the seed layer. In some embodiments, the under bump metallurgy (UBM) 323 is formed using a deposition method including physical vapor deposition (PVD), such as sputtering or electroplating.

[0038] In some embodiments, the conductive ball structure 324 is formed on the under-bump metallization (UBM) layer 323 using a solder plating process or a screen printing process, a photoresist stripping process, and a solder reflow process.

[0039] like Figure 1 As shown, stress buffer structure 316-1A is disposed on conductive bump structure 322, while RDL structure 316-2 is disposed on stress buffer structure 316-1A. RDL structure 316-2 is used to redistribute and fan out one or more die pads of first die 302 and second die 304 mounted thereon with small pitch.

[0040] In some embodiments, stress buffer structure 316-1A is located between conductive bump structure 322 and RDL structure 316-2. RDL structure 316-2 is located between first die 302 (and / or second die 304) and stress buffer structure 316-1A. Stress buffer structure 316-1A is used to release stress on substrate 100 during bonding processes, thereby preventing damage to RDL structure 316-2, first die 302, and second die 304. RDL structure 316-2 is used to redistribute the smaller-pitched die pads of first die 302 and second die 304 onto the conductive pads of RDL structure 316-2, which are connected to the corresponding larger-pitched conductive bump structure 322. In some embodiments, there is no specific limitation on the number of dies that may be included in semiconductor package 500A; semiconductor package 500A may include one, two, or more dies. In this embodiment, two dies are used as an example. For semiconductor packages with multiple dies, the structure described in this embodiment can provide enhanced buffering and protection.

[0041] The RDL structure 316-2 may have opposing surfaces 316TS and 316BS. Surface 316TS of the RDL structure 316-2 is used to directly set the first grain 302 and the second grain 304, also referred to as the grain attachment surface. Surface 316BS of the RDL structure 316-2 is used to directly set the stress buffer structure 316-1A, also referred to as the stress buffer attachment surface.

[0042] like Figure 1 As shown, the stress buffer structure 316-1A is located near the surface 316BS and conductive bump structure 322 of the RDL structure 316-2. The RDL structure 316-2 is disposed on the stress buffer structure 316-1A. Furthermore, the RDL structure 316-2 is located near the surface 316TS of the RDL structure 316-2. The stress buffer structure 316-1A may have a bottom surface 316-1BS and an upper surface 314T opposite to the bottom surface 316-1BS. The upper surface 314T of the stress buffer structure 316-1A may directly contact the surface 316BS of the RDL structure 316-2. The bottom surface 316-1BS of the stress buffer structure 316-1A is used to directly mount the conductive bump structure 322 (or UBM layer 323), also known as the solder ball attachment surface.

[0043] In some embodiments, the RDL structure 316-2 and the stress buffer structure 316-1A can form a mesa structure (a raised plateau-like structure). The RDL structure 316-2 is higher than the stress buffer structure 316-1A surrounding the RDL structure 316-2. Figure 1 As shown, RDL structure 316-2 partially covers stress buffer structure 316-1A. The peripheral region of the surface (upper surface) 314T of stress buffer structure 316-1A may be exposed from RDL structure 316-2. Furthermore, the sidewall E1A of stress buffer structure 316-1A is not flush with the corresponding sidewall E2 of RDL structure 316-2. In some embodiments, the sidewall E1A of stress buffer structure 316-1A may be higher than the corresponding sidewall E2 of RDL structure 316-2 in the D10 direction to provide sufficient protection for RDL structure 316-2 and the first grain 302 (and / or the second grain 304). Alternatively, the sidewall E1A of stress buffer structure 316-1A may protrude beyond the corresponding sidewall E2 of RDL structure 316-2 in the D10 direction. In some embodiments, in a plan view, the size (or area) of the stress buffer structure 316-1A is larger than the size (or area) of the RDL structure 316-2, the size (or area) of the RDL structure 316-2 is larger than the size (or area) of the first grain 302 or multiple grains, and the size (or area) of the molding compound 330 is equal to the size (or area) of the stress buffer structure 316-1A.

[0044] In some embodiments, the stress buffer structure 316-1A includes at least a stress buffer layer 314 and one or more conductive studs 312.

[0045] A stress-relief layer 314 is disposed between the RDL structure 316-2 and the conductive bump structure 322. In some embodiments, the stress-relief layer 314 may be formed of polyimide (PI), polybenzoxazole (PBO), glass fiber, epoxy resin, FR4, or molding compound. In some embodiments, the stress-relief layer 314 may be formed of molding compound to enhance mechanical strength and simplify the manufacturing process. In some embodiments, the coefficient of thermal expansion (CTE) of the stress-relief layer 314 may be between that of silicon (3.5–4.5 ppm / °C) and that of the molding compound. The coefficient of thermal expansion of the substrate (the coefficient of thermal expansion of the PCB is 12–24 ppm / °C). In other words, the coefficient of thermal expansion (CTE) of the stress-relief layer 314 may be between 3.5 and 24 ppm / °C.

[0046] Conductive posts 312 may be formed through stress buffer layer 314. Both ends of the conductive posts 312 may be exposed outside the stress buffer layer 314. In some embodiments, the conductive posts 312 may be formed of a conductive material, such as a metal including copper, gold, silver, or other suitable metals. In some embodiments, the stress buffer layer 314 may be free of other active devices (e.g., chips, dies, or functional circuits) to avoid damage to these active devices. In some embodiments, the stress buffer structure 316-1A may not include other connection structures (e.g., metal layers) to ensure adequate buffering and protection as well as stable electrical connections. However, the above description is not intended to limit the scope of the invention. Those skilled in the art can modify and adjust the described configurations as needed.

[0047] like Figure 1 As shown, the conductive pillar 312 has a thickness H1 and a diameter D1. In some embodiments, the thickness H1 is in the range of about 10 micrometers to about 220 micrometers. The diameter D1 is in the range of about 15 micrometers to about 300 micrometers. In some embodiments, the thickness H1 of the conductive pillar 312 may be less than the thickness T3 of the first die 302 and the thickness T4 of the second die 304. For example, the conductive pillar 312 is in the range of about 10 micrometers to about 60 micrometers. In some embodiments, the thickness H1 may be less than the thickness of the first die 302 (and / or the second die 304) to reduce the overall height of the semiconductor package and improve structural stability.

[0048] In some embodiments, the stress buffer structure 316-1A may further include a passivation layer 310. The passivation layer 310 is used to prevent oxidation of the conductive post 312. The passivation layer 310 is disposed on the stress buffer layer 314 and close to the conductive bump structure 322. The thickness T1 of the stress buffer layer 314 may be greater than the thickness T2 of the passivation layer 310. In some embodiments, the thickness T1 of the stress buffer layer 314 is greater than or equal to 10 μm. For example, the thickness T1 of the stress buffer layer 314 is in the range of about 10 μm to about 60 μm. The passivation layer 310 may surround the portion of the conductive post 312 close to the conductive bump structure 322. Furthermore, the outer sidewall 310E of the passivation layer 310 may be surrounded by the stress buffer layer 314. In some embodiments, the surface of the passivation layer 310 exposed from the stress buffer layer 314 constitutes the surface 316-1BS of the stress buffer structure 316-1A. In some embodiments, the passivation layer 310 may be formed of polyimide (PI) or other suitable passivating materials. In some embodiments, the conductive post 312 passes through the passivation layer 310 and contacts the conductive bump structure 322. In some embodiments, a seed layer 308 is disposed between the passivation layer 310 and the conductive post 312, and the conductive post 312 does not contact the passivation layer 310.

[0049] In some embodiments, RDL structure 316-2 may include one or more RDL layers (e.g., Figure 1 The RDL layers 316-2 (RDL1, RDL2, and RDL3) are shown, alternating with one or more dielectric layers 317. The RDL structure 316-2 also includes conductive pads 320. RDL layers 316-2 include conductive traces 319 and one or more conductive vias 318 disposed in one or more dielectric layers 317. The conductive vias 318 are electrically connected (or coupled) to conductive posts 312 and conductive traces 319 at different heights. The conductive traces 319 are electrically connected (or coupled) to corresponding conductive pads 320. The conductive pads 320 are exposed through openings in the solder mask layer (not shown) and are close to dies 302 and 304.

[0050] In some embodiments, a stress buffer layer 314 is disposed between RDL layers RDL1, RDL2, and RDL3 and the conductive bump structure 322. RDL layers RDL1, RDL2, and RDL3 are connected (or coupled) to the conductive bump structure 322 via conductive posts 312. In some embodiments, conductive vias 318 disposed in the dielectric layer 317 closest to the conductive post 312 can contact and be directly coupled to the corresponding conductive post 312. There are no conductive pads connecting the conductive posts 312 of the stress buffer structure 316-1A to the corresponding conductive vias 318. In other words, the conductive posts 312 of the stress buffer structure 316-1A do not contact any conductive pads of the RDL structure 316-2.

[0051] In some embodiments, the conductive via 318 of the RDL structure 316-2 is not larger than the conductive post 312. For example... Figure 1 As shown, the conductive post 312 and the conductive via 318 have a thickness H2 and a diameter D2. In some embodiments, the thickness H2 of the conductive via 318 is not greater than (or less than) the thickness H1 of the conductive post 312. For example, the thickness H2 can be in the range of about 5 micrometers to about 10 micrometers. In some embodiments, the diameter D2 of the conductive via 318 is not greater than (or less than) the diameter D1 of the conductive post 312. For example, the diameter D2 is in the range of about 5 micrometers to about 180 micrometers. The conductive post 312 has a larger size to resist stress, thereby effectively buffering stress transmission.

[0052] In some embodiments, the materials of the conductive vias 318, conductive traces 319, and conductive pads 320 of the RDL structure 316-2 may be the same as or similar to the material of the conductive pillars 312. In some embodiments, the material of the dielectric layer 317 may be the same as or similar to the material of the passivation layer 310. It should be noted that in the interposer layer 316, Figure 1 The number of conductive vias 318, conductive traces, conductive pads 320, and dielectric layers 317 shown are merely examples and are not intended to limit the scope of this invention.

[0053] like Figure 1 As shown, the first die 302 and the second die 304 are arranged side-by-side along direction D10. The first die 302 has an active surface 302a and a back surface 302b opposite to the active surface 302a. The second die 304 has an active surface 304a and a back surface 304b opposite to the active surface 304a. In some embodiments, the first die 302 and the second die 304 are manufactured using flip-chip technology and are flip-chip disposed on the RDL structure 316-2, opposite to the conductive bump structure 322. The active surfaces 302a and 304a may face the RDL structure 316-2. In other words, the conductive bump structure 322 is disposed on the conductive pillar 312 of the stress buffer structure 316-1A and opposite to the first die 302 and the second die 304. Furthermore, the RDL structure 316-2 and the stress buffer structure 316-1A are disposed between the first die 302, the second die 304, and the conductive bump structure 322. The conductive bump structure 322 is electrically connected to the first grain 302 and the second grain 304 through the conductive post 312 of the stress buffer structure 316-1A and the RDL structure 316-2.

[0054] In some embodiments, the first die 302 and the second die 304 have different functions. For example, the first die 302 includes a logic die, while the second die 304 includes a memory die. The logic die may include a system-on-chip (SoC), a central processing unit (CPU) die, a graphics processing unit (GPU) die, a radio frequency (RF) die, a micro control unit (MCU) die, a microprocessor unit (MPU) die, a power management integrated circuit (PMIC) die, a global positioning system (GPS) device, an application processor (AP) die, or any combination thereof. The memory die may include a dynamic random access memory (DRAM) die, a high bandwidth memory (HBM) die, or any combination thereof. For example, the second die 304 may be HBM2 or HBM3, but is not limited thereto. HBM is a low-power memory die with an ultra-wide communication channel. When a second grain 304 is present, the stress-buffering structure of this embodiment can more significantly reduce the negative impact of stress. Therefore, when multiple grains are arranged side by side, the structure of this embodiment has a more significant beneficial effect.

[0055] In some embodiments, the first die 302 can be mounted on the RDL structure 316-2 via a conductive bump structure 303. The second die 304 can be mounted on the RDL structure 316-2 via a conductive bump structure 305. The conductive bump structures 303 and 305 are in contact with and coupled to the conductive pads 320 of the RDL structure 316-2.

[0056] In some embodiments, conductive bump structures 303 and 305 may include microbumps. In some embodiments, each of conductive bump structures 303 and 305 may include an under-bump metallization (UBM) structure (not shown) and conductive ball structures (not shown) located on the UBM structure. In some embodiments, conductive bump structures 303 and 305 may include materials such as nickel, copper, gold, palladium, SnAg solder, or combinations thereof.

[0057] like Figure 1As shown, the semiconductor package 500A also includes an underfill material 315 that fills the gaps between the first die 302 and the RDL structure 316-2, and between the second die 304 and the RDL structure 316-2. The underfill material 315 may partially fill the gaps between the first die 302 and the second die 304. In some embodiments, the underfill material 315 surrounds a portion of the first die 302, a portion of the second die 304, and the conductive bump structures 303 and 305, and contacts a portion of the RDL structure 316-2 to further reduce the thermal resistance from the first die 302 and the second die 304 to the RDL structure 316-2. Furthermore, the underfill material 315 may be provided to compensate for the different coefficients of thermal expansion (CTE) among the first die 302, the second die 304, the conductive bump structures 303 and 305, and the RDL structure 316-2.

[0058] like Figure 1 As shown, molding compound 330 is disposed on stress buffer structure 316-1A and RDL structure 316-2. Furthermore, molding compound 330 surrounds and contacts the first grain 302 and the second grain 304. The active surface 302a of the first grain 302 and the active surface 304a of the second grain 304 can be covered or exposed by molding compound 330. In some embodiments, molding compound 330 contacts the surface 316TS of RDL structure 316-2 exposed from the first grain 302, the second grain 304, and the underfill material 315. Molding compound 330 surrounds and contacts the sidewall E2 of RDL structure 316-2. Furthermore, molding compound 330 contacts the surface (upper surface) 314T of stress buffer structure 316-1A not covered by RDL structure 316-2. Additionally, the sidewall E1A of stress buffer structure 316-1A can be exposed from molding compound 330. In some embodiments, the sidewall 330E of the molding compound 330 is flush with the corresponding sidewall E1A of the stress buffer structure 316-1A. In other words, the molding compound 330 does not surround the sidewall E1A of the stress buffer structure 316-1A. In some embodiments, the RDL structure 316-2 contacts the stress buffer structure 316-1A, while the molding compound 330 contacts the stress buffer structure 316-1A.

[0059] In some embodiments, the RDL structure 316-2 and the molding compound 330 are in contact with different portions of the surface 314T of the stress buffer structure 316-1A. In other words, the interface F1 between the RDL structure 316-2 and the stress buffer structure 316-1A is flush with the interface F2 between the molding compound 330 and the stress buffer structure 316-1A. In some embodiments, the RDL structure 316-2 and the stress buffer structure 316-1A are formed in different process steps, and the interface F1 is established between them. In some embodiments, the RDL structure 316-2 and the molding compound 330 are formed in different process steps, and the interface F2 is established between them. In some embodiments, the RDL structure 316-2, the stress buffer structure 316-1A, and the molding compound 330 are formed in different process steps. In some embodiments, the RDL structure 316-2 and the molding compound 330 together cover the entire upper surface 314T of the stress buffer structure 316-1A. Therefore, the semiconductor package 500A has better structural stability.

[0060] In some embodiments, molding compound 330 may be formed of a non-conductive material, such as epoxy resin, resin, moldable polymer, etc. Molding compound 330 may be applied in a substantially liquid state and then cured by a chemical reaction, for example, in an epoxy resin or resin. In some other embodiments, molding compound 330 may be an ultraviolet (UV) or thermosetting polymer, applied in the form of a gel or plastic solid, capable of being disposed around the first grain 302 and the second grain 304, and then cured using an ultraviolet or thermosetting process. Molding compound 330 may be cured using a mold (not shown).

[0061] In this embodiment, the stress buffer layer 314 and the molding compound 330 of the stress buffer structure 316-1A are formed of the same material, such as a molding substrate material. In some embodiments, the stress buffer layer 314 may contain glass fibers, while the molding compound 330 may not contain glass fibers.

[0062] In some embodiments, the semiconductor package 500A may include a stress buffer structure 316-1A located between the RDL structure 316-2 and the conductive bump structure 322. The stress buffer structure 316-1A includes a stress buffer layer 314 formed of a molding compound substrate material. The stress buffer layer 314 can release (or buffer) stress from the substrate 100 during the bonding process, thereby preventing damage to the first die 302 (and the second die 304). In some embodiments, the coefficient of thermal expansion (CTE) of the stress buffer layer 314 may be between that of silicon and the substrate. Therefore, warpage of the semiconductor package 500A can be reduced. In some embodiments, the stress buffer structure 316-1A also includes one or more conductive posts 312 passing through the stress buffer layer 314. The conductive posts 312 with stress buffering function also serve as electrical connections between smaller-pitch conductive vias 318 and larger-pitch conductive bump structures 322. The conductive posts 312 are larger than the conductive vias 318. For example, the thickness H1 and / or diameter D1 of the conductive post 312 is greater than the thickness H2 and / or diameter D2 of the conductive through hole 318.

[0063] Figure 2 This is a schematic cross-sectional view of a semiconductor package 500B according to some embodiments of the present invention. For the sake of brevity, the following embodiments are consistent with the previous references. Figure 1 Components that are identical or similar to those described will not be repeated. As shown in the figure... Figure 1 and Figure 2 In this context, the difference between semiconductor package 500A and semiconductor package 500B is at least that the stress buffer layer 414 of the stress buffer structure 316-1B of semiconductor package 500B is formed of a polymer base material. In addition, there is no seed layer 308 (or a residual portion of seed layer 308) between the conductive pillar 312 and the passivation layer 310 of semiconductor package 500B.

[0064] A stress-relief layer 414 is disposed between the RDL structure 316-2 and the conductive bump structure 322. In this embodiment, the stress-relief layer 414 and the molding compound 330 are formed of different materials. For example, the stress-relief layer 414 is formed of polyimide (PI), polybenzoxazole (PBO), glass fiber, epoxy resin, FR4, or other suitable materials. In some embodiments, the stress-relief layer 414 may be formed of a polymer substrate material to enhance its ability to buffer and protect the RDL structure 316-2 and the first grain 302 and / or the second grain 304. In some embodiments, the coefficient of thermal expansion (CTE) of the stress-relief layer 414 may be between the coefficient of thermal expansion of silicon (3.5 to 4.5 ppm / °C) and the coefficient of thermal expansion of the substrate (CTE of PCB is 12 to 24 ppm / °C). In other words, the coefficient of thermal expansion (CTE) of the stress-relief layer 414 may be between 3.5 and 24 ppm / °C.

[0065] In this embodiment, the outer sidewall 310E of the passivation layer 310 is flush with the corresponding sidewall E1B of the stress buffer structure 316-1B and the corresponding sidewall 330E of the molding compound 330. The outer sidewall 310E of the passivation layer 310 can be exposed from the stress buffer layer 414.

[0066] In some embodiments, the RDL structure 316-2 and the molding compound 330 are in contact with different portions of the surface 414T of the stress buffer structure 316-1B. In other words, the interface F3 between the RDL structure 316-2 and the stress buffer structure 316-1B is flush with the interface F4 between the molding compound 330 and the stress buffer structure 316-1B. In some embodiments, the RDL structure 316-2 and the molding compound 330 together cover the entire upper surface 414T of the stress buffer structure 316-1B. Therefore, the semiconductor package 500B has better structural stability.

[0067] In some embodiments, the semiconductor package 500B may include a stress buffer structure 316-1B located between the RDL structure 316-2 and the conductive bump structure 322. The stress buffer structure 316-1B includes a stress buffer layer 414 formed of a polymer substrate material. The stress buffer layer 414 can release stress from the substrate 100 during the bonding process, thereby preventing damage to the first die 302 and the second die 304. In some embodiments, the coefficient of thermal expansion (CTE) of the stress buffer layer 414 may be between that of silicon and the substrate. Therefore, warpage of the semiconductor package 500B can be reduced. In some embodiments, the stress buffer structure 316-1B further includes one or more through conductive posts 312. The conductive posts 312 are used to form an electrical connection between a narrowly spaced conductive via 318 and a wider-spaced conductive bump structure 322. The conductive posts 312 are larger than the conductive via 318.

[0068] Figure 3 , 4 5, 6, 7 and 8 are formed according to some embodiments of the present invention. Figure 1 A cross-sectional view of the intermediate stage of the 500A semiconductor package structure. The following embodiments are consistent with previous references. Figure 1 and 2 For the sake of brevity, components that are the same or similar to those described will not be repeated.

[0069] like Figure 3 As shown, a carrier 360 is provided. In some embodiments, the material of the carrier 360 includes glass. Next, a multi-deposition process is performed to sequentially form a passivation layer 310 and a seed layer 308 on the carrier 360. The passivation layer 310 has an opening OP1, and the seed layer 308 is compliantly formed on the passivation layer 310. Next, a photolithography process is performed to form a photoresist pattern (not shown) on the seed layer 308 to define the formation location of the subsequent conductive pillars 312. The conductive pillars 312 are formed on the seed layer 308 by an electroplating process. After the conductive pillars 312 are formed, the photoresist pattern is removed. Next, an etching process is performed to remove the exposed portion of the seed layer 308 around the conductive pillars 312. Therefore, residual portions of the seed layer 308 remain between the conductive pillars 312 and the carrier 306, and between the conductive pillars 312 and the passivation layer 310.

[0070] Next, as Figure 4 As shown, a molding process is performed to form a stress buffer layer 314 covering the passivation layer 310 and the conductive pillar 312. The stress buffer layer 314 may surround the sidewall 310E of the passivation layer 310. Next, a planarization process, such as grinding, is performed to remove part of the stress buffer layer 314 until the conductive pillar 312 is exposed. After the planarization process, the surface 312T of the conductive pillar 312 is flush with the surface 314T of the planarized stress buffer layer 314 away from the carrier 360. In this embodiment, the passivation layer 310, the conductive pillar 312, and the stress buffer layer 314 form a stress buffer structure 316-1A.

[0071] Next, as Figure 5 As shown, multiple deposition and patterning processes are performed to form an RDL structure 316-2 on the conductive pillar 312 and the stress buffer layer 314. In some embodiments, the RDL structure 316-2 and the stress buffer structure 316-1A are formed in separate process steps, and an interface F1 (e.g., ...) is established between them. Figure 1 (As shown).

[0072] Next, as Figure 6As shown, the first die 302 and the second die 304, along with conductive bump structures 303 and 305, are arranged side-by-side on the redistribution layer (RDL) structure 316-2. Next, a reflow soldering process is performed to couple the first die 302 and the second die 304 to the conductive pad 230 via the conductive bump structures 303 and 305. Next, an underfill adhesive 315 is introduced (distributed) into the gap between the first die 302, the second die 304, and the redistribution layer (RDL) structure 316-2 using an underfill process.

[0073] Next, as Figure 7 As shown, another molding process is performed to form molding compound 330 on stress buffer structure 316-1A and RDL structure 316-2. Molding compound 330 surrounds RDL structure 316-2, first grain 302 and second grain 304. Furthermore, molding compound 330 covers surface 314T of stress buffer structure 316-1A but is not covered by RDL structure 316-2. Next, carrier 360 is removed from RDL structure 316-2. In some embodiments, stress buffer structure 316-1A and molding compound 330 are formed in different process steps, establishing an interface F2 between them (e.g., Figure 1 (As shown).

[0074] In some embodiments of stress buffer structure 316-1A where the stress buffer layer 314 and molding compound 330 are formed of the same material, the interface F2 between the stress buffer layer 314 and molding compound 330 of stress buffer structure 316-1B is still visible because the surface 314T of the stress buffer layer 314 was planarized (e.g., ground) before the molding compound 330 was formed.

[0075] Next, as Figure 8 As shown, flip it again. Figure 7 The intermediate structure is shown. Next, a bumping process is performed to form a conductive bump structure 322, including an under-bump metal layer (UBM) 323 and a conductive ball structure 324, on the conductive pillars 312 of the stress buffer structure 316-1A, opposite to the first grain 302 and the second grain 304. In some embodiments, a residual portion of the seed layer 308 may be retained between the conductive pillars 312 and the passivation layer 310. In some embodiments, a residual portion of the seed layer 308 may also be retained between the conductive pillars 312 and the UBM layer 323.

[0076] In some embodiments, the bumping process includes forming an under-bump metallization (UBM) 323 on the conductive pillars 312 exposed from the openings in the passivation layer 310, opposite the RDL structure 316-2, using a deposition method. The under-bump metallization (UBM) 323 may also extend to the surface 316-1BS of the stress buffer structure 316-1A.

[0077] like Figure 8 As shown, the bumping process further includes forming a conductive ball structure 324 on the under-bump metal layer (UBM) 323 using a solder plating process, a photoresist stripping process, and a solder reflow process.

[0078] Next, a cutting process is performed. At the interface F2 between the molding compound 330 and the stress buffer layer 314 of the stress buffer structure 316-1A, the molding compound 330 and the stress buffer structure 316-1A are cut along a direction D12 that is substantially perpendicular to the interface F2 between the molding compound 330 and the stress buffer layer 314 of the stress buffer structure 316-1A. In some embodiments, the cutting process may not cut the RDL structure 316-2 and the passivation layer 310 of the stress buffer structure 316-1A. After performing the above process, a structure is formed as shown in the figure. Figure 1 The discrete semiconductor package 500A shown includes an RDL structure 316-2 and a stress buffer structure 316-1A.

[0079] Figure 9 , 10 11, 12, 13 and 14 are formed according to some embodiments of the present invention. Figure 2 A cross-sectional view of an intermediate stage of the semiconductor package 500B. The following embodiments are consistent with previous references. Figures 1 to 8 For the sake of brevity, components that are the same or similar to those described will not be repeated.

[0080] like Figure 9 As shown, a carrier 360 is provided. In some embodiments, the carrier 360 is made of glass, and a multi-deposition process is then performed to sequentially form a seed layer 308 and a passivation layer 310 on the carrier 360. Next, a photolithography process is performed to form a photoresist pattern (not shown) on the passivation layer 310 to define the formation location of subsequent conductive pillars 312. Next, an etching process is performed to form one or more openings OP1 through the passivation layer 310 to expose portions of the seed layer 308.

[0081] Next, a lamination process is performed to form a stress buffer layer 414 covering the passivation layer 310 and the seed layer 308 exposed from the opening OP1 of the passivation layer 310. The outer wall 310E of the passivation layer 310 can be exposed from the stress buffer layer 414.

[0082] like Figure 10 As shown, a patterning process is then performed to form one or more openings OP2 through the stress buffer layer 414. In some embodiments, the openings OP2 are aligned with the corresponding openings OP1 in the D12 direction.

[0083] Next, an electroplating process is performed to form one or more conductive pillars 312 on the seed layer 308 in the opening OP1 of the passivation layer 310 and the opening OP2 of the stress buffer layer 414. In some embodiments, the conductive pillars 312 completely fill the opening OP1 of the passivation layer 310. In addition, the opening OP1 of the passivation layer 310 may completely or partially fill the opening OP2 of the stress buffer layer 414.

[0084] like Figure 11 As shown, a planarization process, such as chemical mechanical polishing (CMP), is then performed to remove part of the stress buffer layer 414 and part of the conductive pillars 312, so that the surface 414T of the planarized stress buffer layer 414 and the surface 312T of the planarized conductive pillars are flush with each other away from the carrier 360. In this embodiment, the passivation layer 310, the conductive pillars 312, and the stress buffer layer 414 form a stress buffer structure 316-1B.

[0085] Next, as Figure 12 As shown, multiple deposition and patterning processes are performed to form an RDL structure 316-2 on the conductive pillar 312 and the stress buffer layer. In some embodiments, the RDL structure 316-2 and the stress buffer structure 316-1A are formed in separate process steps, and an interface F3 (such as...) is established between them. Figure 2 (As shown).

[0086] Next, as Figure 13 As shown, a first die 302 and a second die 304, as well as conductive bump structures 303 and 305, are disposed on the redistribution layer (RDL) structure 316-2. Next, a reflow soldering process is performed to couple the first die 302 and the second die 304 to the conductive pads 230 via the conductive bump structures 303 and 305. Next, an underfill process is used to introduce (distribute) underfill material 315 into the gaps between the first die 302, the second die 304, and the redistribution layer (RDL) structure 316-2.

[0087] Next, as Figure 13 As shown, a molding process is performed to form molding compound 330 on stress buffer structure 316-1B and RDL structure 316-2. Molding compound 330 surrounds RDL structure 316-2, first grain 302, and second grain 304. Furthermore, molding compound 330 covers surface 414T of stress buffer structure 316-1B but is not covered by RDL structure 316-2. Next, carrier 360 is removed from RDL structure 316B. In some embodiments, stress buffer structure 316-1A and molding compound 330 are formed in different process steps, with an interface F4 (e.g., ...) formed between them. Figure 2 (As shown).

[0088] In this embodiment, the stress buffer layer 414 and the molding compound 330 of the stress buffer structure 316-1B are formed of different materials. Furthermore, before forming the molding compound 330, the surface 414T of the stress buffer layer 414 is planarized (e.g., chemical mechanical polishing (CMP)), and the interface F3 between the stress buffer layer 414 and the molding compound 330 of the stress buffer structure 316-1B can be seen.

[0089] Next, as Figure 14 As shown, flip it again. Figure 13 The intermediate structure is shown. Next, a bumping process is performed to form a conductive bump structure 322, which includes a bottom metal layer (UBM) 323 and a conductive ball structure 324, on the conductive pillar 312 of the stress buffer structure 316-1B at a position opposite to the first grain 302 and the second grain 304.

[0090] In some embodiments, the bumping process includes forming an under-bump metallization (UBM) 323 on the conductive pillars 312 exposed from the openings in the passivation layer 310, at a location opposite to the RDL structure 316-2, using a deposition method. The under-bump metallization (UBM) 323 may also extend to the surface 416-1BS of the stress buffer structure 316-1B.

[0091] like Figure 14 As shown, the bumping process further includes forming a conductive ball structure by cutting the RDL structure 316-2 on the under-bump metal layer (UBM) 323 using solder plating, photoresist stripping, and solder reflow processes. In some embodiments, such as Figure 14 As shown, there is no residual seed layer 308.

[0092] Next, a cutting process is performed to cut the molding compound 330 and the stress buffer structure 316-1B at the interface F3 between the molding compound 330 and the stress buffer layer 414 of the stress buffer structure 316-1B, along a direction D12 substantially perpendicular to the interface F3 between the molding compound 330 and the stress buffer layer 414 of the stress buffer structure 316-1B. In some embodiments, the cutting process may not cut the RDL structure 316-2 and the passivation layer 310 of the stress buffer structure 316-1B. After performing the above process, a structure is formed as shown in the figure. Figure 2 The discrete semiconductor package 500B shown includes RDL structure 316-2 and stress buffer structure 316-1B.

[0093] This invention provides a semiconductor package and a method for forming the same. The semiconductor package includes a redistribution layer (RDL) structure (e.g., RDL structure 316-2), a first die (e.g., die 302 or 304), a stress buffer structure (e.g., stress buffer structure 316-1A or 316-1B), and a conductive bump structure (e.g., conductive bump structure 322). The RDL structure has a first surface (e.g., surface 316TS) and a second surface (e.g., surface 316BS). The first surface is opposite to the second surface. The first die is disposed on the first surface of the RDL structure. The stress buffer structure is disposed on the second surface of the RDL structure. The stress buffer structure includes a stress buffer layer (e.g., stress buffer layer 314 or 414) and conductive pillars (e.g., conductive pillars 312) passing through the stress buffer layer. The conductive bump structure is disposed on the conductive pillars and is opposite to the first die. The conductive bump structure is electrically coupled to the first die through the stress buffer structure and the RDL structure.

[0094] In some embodiments, the RDL structure includes conductive vias (e.g., conductive via 318) whose dimensions (e.g., thickness H2 and / or diameter D2) are smaller than the dimensions of the conductive posts (e.g., thickness H1 and / or diameter D1). The conductive posts, with their larger dimensions, resist stress, thereby effectively buffering stress transmission.

[0095] In some embodiments, the sidewalls of the stress buffer structure protrude beyond the corresponding sidewalls of the RDL structure, and the RDL structure partially covers the stress buffer structure.

[0096] In some embodiments, the sidewalls of the stress buffer structure are not flush with the corresponding sidewalls of the RDL structure.

[0097] In some embodiments, the coefficient of thermal expansion (CTE) of the stress buffer layer is between 3.5 and 24 ppm / °C. The thickness of the stress buffer layer is greater than or equal to 10 μm.

[0098] In some embodiments, the semiconductor package further includes a second die and a molding compound. The second die is disposed side-by-side with the first die. The molding compound is disposed on the stress buffer structure and the RDL structure and surrounds the first die.

[0099] In some embodiments, the molding compound surrounds the RDL structure and contacts the stress buffer layer.

[0100] In some embodiments, the sidewalls of the molding compound are flush with the corresponding sidewalls of the stress-relief structure.

[0101] In some embodiments, the stress-relief layer and the molding compound are formed of the same material.

[0102] In some embodiments, the stress-relief layer and the molding compound are formed of different materials.

[0103] In some embodiments, the stress buffer layer is formed of a molding compound or a polymer matrix. The stress buffer layer includes polyimide (PI), polybenzoxazole (PBO), glass fiber, epoxy resin, FR4, molding compound, or combinations thereof.

[0104] In some embodiments, the interface between the stress buffer layer and the RDL structure is flush with the interface between the stress buffer layer and the molding compound.

[0105] In some embodiments, the RDL structure and molding compound together cover the entire upper surface of the stress buffer structure.

[0106] In some embodiments, the RDL structure is in contact with the stress buffer structure, and the molding compound is in contact with the stress buffer structure.

[0107] In some embodiments, the material of the stress buffer layer is selected from polyimide (PI), polybenzoxazole (PBO), glass fiber, epoxy resin, FR4, molding compound, or a combination thereof.

[0108] In some embodiments, the semiconductor package further includes a passivation layer. The passivation layer is disposed on a stress buffer layer and surrounds a portion of the conductive pillars. The conductive pillars penetrate the passivation layer and contact the conductive bump structure.

[0109] In some embodiments, the conductive via is coupled to the conductive bump structure via a conductive post.

[0110] In some embodiments, the bottom surface of the stress buffer structure is formed from the surface of the passivation layer exposed from the stress buffer layer.

[0111] In some embodiments, a passivation layer surrounds a portion of the conductive post near the bottom surface of the stress-buffering structure.

[0112] In some embodiments, the thickness of the conductive post is less than the thickness of the first grain.

[0113] In some embodiments, the conductive layer of the RDL structure is coupled to the conductive bump structure via conductive pillars.

[0114] In some embodiments, the first die connector is connected to the RDL structure via another conductive bump structure.

[0115] In some embodiments, the semiconductor package further includes an underfill distribution below the first die region.

[0116] In some embodiments, molding compound surrounds the first die, optionally encapsulating the RDL structure.

[0117] This invention provides a method for forming a semiconductor package. The method includes forming conductive pillars and a stress buffer layer surrounding the conductive pillars on a carrier. The conductive pillars and the stress buffer layer form a stress buffer structure. The method further includes forming a redistribution layer (RDL) structure on the conductive pillars and the stress buffer layer. The method further includes distributing a first die on the redistribution layer (RDL) structure. The method further includes forming a conductive bump structure on the conductive pillars of the stress buffer structure, the bump structure being opposite to the first die.

[0118] In some embodiments, forming conductive pillars and a stress-buffered layer around the conductive pillars on a carrier includes sequentially forming a passivation layer and a seed layer on the carrier. The passivation layer has openings. The method further includes forming conductive pillars on the seed layer. The method further includes forming a stress-buffered layer covering the passivation layer and the conductive pillars. The method further includes removing a portion of the stress-buffered layer until the conductive pillars are exposed.

[0119] In some embodiments, forming conductive pillars and a stress-retaining layer surrounding the conductive pillars on a carrier includes sequentially forming a seed layer and a passivation layer on the carrier. The passivation layer has a first opening that exposes a portion of the seed layer. The method further includes forming a stress-retaining layer that covers the passivation layer and the seed layer exposed from the first opening in the passivation layer. The method further includes forming a second opening through the stress-retaining layer. The second opening is aligned with the first opening. The method further includes forming conductive pillars on the seed layer within the first opening in the passivation layer and the second opening in the stress-retaining layer. The method further includes removing portions of the stress-retaining layer and the conductive pillars such that the surfaces of the stress-retaining layer and the conductive pillars are flush with each other away from the carrier.

[0120] In some embodiments, the method further includes forming a molding compound on the stress-buffered structure. The molding compound surrounds the RDL structure and the first grain. The method further includes removing the carrier from the stress-buffered structure.

[0121] The method also includes cutting the molding compound and the stress buffer structure at the interface between the molding compound and the stress buffer layer of the stress buffer structure, in a direction substantially perpendicular to the interface between the molding compound and the stress buffer layer of the stress buffer structure.

[0122] In some embodiments, forming the conductive bump structure further includes forming a bottom bump metal layer (UBM) on the conductive post at a position opposite to the RDL structure. The method also includes forming a conductive ball structure on the bottom bump metal layer (UBM).

[0123] In semiconductor packaging, a stress-relief structure is located between the RDL structure and the conductive bump structure. The stress-relief structure includes a stress-relief layer and conductive pillars. In some embodiments, the stress-relief layer, formed from a molding compound or polymer substrate material, can release stress from the substrate material during bonding. This reduces damage to the die mounted on the RDL structure. In some embodiments, the coefficient of thermal expansion (CTE) of the stress-relief layer can be between the CTE of silicon (3.5–4.5 ppm / °C) and the CTE of the substrate (12–24 ppm / °C for PCBs). This minimizes CTE mismatch between the die and the RDL structure, thereby reducing warpage in the semiconductor package. Furthermore, in addition to stress relief, larger conductive pillars can be used to reduce the formation of electrical connections between conductive vias with smaller pitch and conductive bump structures with larger pitch.

[0124] While the invention has been described by way of example and according to preferred embodiments, it should be understood that the invention is not limited to the disclosed embodiments. Rather, it is intended to cover various modifications and similar arrangements (as will be apparent to those skilled in the art). Therefore, the scope of the appended claims should be given the broadest interpretation to cover all such modifications and similar arrangements.

Claims

1. A semiconductor package, characterized in that, include: A redistribution layer structure having a first surface and a second surface opposite to the first surface; A first grain is disposed on the first surface of the redistribution layer structure; A stress buffer structure is disposed on the second surface of the redistribution layer structure, wherein the stress buffer structure includes a stress buffer layer and a conductive post passing through the stress buffer layer. as well as A conductive bump structure is disposed on the conductive post and opposite to the first grain, wherein the conductive bump structure is electrically coupled to the first grain through the stress buffer structure and the redistribution layer structure.

2. The semiconductor package as described in claim 1, characterized in that, The redistribution layer structure includes conductive vias, the size of which is smaller than the size of the conductive post.

3. The semiconductor package as described in claim 1, characterized in that, The sidewall of the stress buffer structure protrudes from the corresponding sidewall of the redistribution layer structure, and the redistribution layer structure partially covers the stress buffer structure.

4. The semiconductor package as described in claim 1, characterized in that, The coefficient of thermal expansion of the stress buffer layer is between 3.5 and 24 ppm / ℃.

5. The semiconductor package as described in claim 1, characterized in that, Also includes: A molding compound is disposed on the redistribution layer structure and surrounds the first grain, wherein the molding compound surrounds the redistribution layer structure and contacts the stress buffer layer.

6. The semiconductor package as described in claim 5, characterized in that, The sidewall of the molding compound is flush with the corresponding sidewall of the stress-relief structure.

7. The semiconductor package as described in claim 5, characterized in that, The interface between the stress buffer layer and the redistribution layer structure is flush with the interface between the stress buffer layer and the molding compound.

8. The semiconductor package as described in claim 5, characterized in that, The redistribution layer structure and the molding compound together cover the entire upper surface of the stress buffer structure.

9. The semiconductor package as described in claim 5, characterized in that, The redistribution layer structure is in contact with the stress buffer structure, and the molding compound is in contact with the stress buffer structure.

10. The semiconductor package as claimed in claim 1, characterized in that, The stress buffer layer is made of polyimide (PI), polybenzoxazole (PBO), glass fiber, epoxy resin, FR4, molding compound, or a combination thereof.

11. The semiconductor package as claimed in claim 1, characterized in that, Also includes: A passivation layer is disposed on the stress buffer layer and surrounds a portion of the conductive post, wherein the conductive post passes through the passivation layer and contacts the conductive bump structure.

12. The semiconductor package as claimed in claim 1, characterized in that, The thickness of the conductive pillar is less than the thickness of the first grain.

13. A method for forming a semiconductor package, characterized in that, include: A conductive pillar and a stress buffer layer surrounding the conductive pillar are formed on the carrier, wherein the conductive pillar and the stress buffer layer form a stress buffer structure. A redistribution layer structure is formed on this stress buffer structure; A first grain is formed on this redistribution layer structure; as well as A conductive bump structure is formed on the conductive pillar of the stress buffer structure, and the conductive bump structure is opposite to the first grain.

14. The method for forming a semiconductor package as described in claim 13, characterized in that, The formation of conductive pillars on the carrier and a stress-buffered layer surrounding the conductive pillars includes: A passivation layer and a seed layer are sequentially formed on the carrier, wherein the passivation layer has an opening; Conductive pillars are formed on the seed layer; A stress buffer layer is formed covering the passivation layer and the conductive pillar; and Remove part of the stress buffer layer until the conductive post is exposed.

15. The method for forming a semiconductor package as described in claim 13, characterized in that, The formation of conductive pillars on the carrier and a stress-buffered layer surrounding the conductive pillars includes: A seed layer and a passivation layer are sequentially formed on a carrier, wherein the passivation layer has a first opening that exposes a portion of the seed layer; A stress buffer layer is formed that covers the passivation layer and exposes the seed layer from the first opening of the passivation layer; A second opening is formed through the stress buffer layer, wherein the second opening is aligned with the first opening; The conductive pillar is formed on the seed layer in the first opening of the passivation layer and the second opening of the stress buffer layer; and Remove part of the stress buffer layer and part of the conductive pillars so that the surfaces of the stress buffer layer and the conductive pillars away from the carrier are flush with each other.

16. The method for forming a semiconductor package as described in claim 13, characterized in that, Also includes: A molding compound is formed on a stress-buffering structure, wherein the molding compound surrounds a redistribution layer structure and a first grain; as well as Remove the carrier from the stress buffer structure.

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