Hybrid phy for flexible selection of operating mode

Abstract

A physical layer (PHY) device (100) includes an ingress transceiver (102), an egress transceiver (104), and a controller (118). The ingress and egress transceivers each include respective analog signal processing (ASP) circuitry (106, 110) and respective digital signal processing (DSP) circuitry (108, 112). The controller is configured to select, for one or both of the ingress and egress transceivers, an operating mode between (i) a digital mode in which both the ASP circuitry and the DSP circuitry are active, and (ii) an analog mode in which the ASP circuitry is active and the DSP circuitry is bypassed.

Description

Cross-references to related applications

[0001] This application claims the benefit of U.S. Provisional Patent Application 63 / 632,475, filed April 10, 2024, the disclosure of which is incorporated herein by reference. Technical Field

[0002] This disclosure relates generally to communication systems, and more specifically to transceiver systems with flexible operating modes. Background Technology

[0003] Physical layer (PHY) devices represent the lowest layer of the OSI 7-layer model and are essential components in modern communication systems. These devices facilitate the transmission and reception of data across various network interfaces by converting digital signals into formats suitable for transmission over physical media (such as fiber optics or copper cables) and vice versa. The PHY layer must be carefully designed to overcome media noise and adapt to varying channel conditions, ensuring reliable data delivery between network nodes. By addressing challenges such as latency, signal attenuation, interference, and distortion, well-designed PHY transceivers can significantly enhance the overall performance and reliability of communication systems across diverse operating environments.

[0004] The above description is presented as a general overview of the relevant technology in the art and should not be construed as an admission that any information contained herein constitutes prior art for this patent application. Summary of the Invention

[0005] The embodiments described herein provide a physical layer (PHY) device, which includes an ingress transceiver, an egress transceiver, and a controller. Each of the ingress and egress transceivers includes a corresponding analog signal processing (ASP) circuitry and a corresponding digital signal processing (DSP) circuitry. The controller is configured to select an operating mode for one or both of the ingress and egress transceivers between (i) a digital mode and (ii) an analog mode, in which both the ASP and DSP circuitry are active, and in the analog mode, the ASP circuitry is active and the DSP circuitry is bypassed.

[0006] In some embodiments, the controller is configured to independently select operating modes for the ingress and egress transceivers. In one embodiment, the ASP circuitry includes an analog repeater circuitry configured to amplify analog signals. In another embodiment, the DSP circuitry includes a digital retiming circuitry configured to digitally adjust the sampling timing of digital signals.

[0007] In the disclosed embodiments, the DSP circuitry has a first delay, and the ASP circuitry has a second delay less than the first delay. In an example embodiment, the DSP circuitry is bypassed but active when either or both of the ingress and egress transceivers are operating in analog mode, and is configured to collect telemetry information while bypassed.

[0008] In this embodiment, the ingress transceiver and the egress transceiver are configured to receive and transmit signals on the communication link, respectively; and the controller is configured to select an operating mode by comparing the channel conditions of the communication link with a defined level.

[0009] According to the embodiments described herein, a network device comprising multiple physical layer (PHY) devices and a controller is also provided. The multiple PHY devices are configured to communicate over respective network links. Each PHY device includes an ingress transceiver and an egress transceiver, each including a corresponding analog signal processing (ASP) circuitry and a corresponding digital signal processing (DSP) circuitry. The controller is configured to select an operating mode for one or both of the ingress and egress transceivers of each PHY device, the operating mode being selected between (i) a digital mode and (ii) an analog mode, in which both the ASP and DSP circuitry are active, and in the analog mode, the ASP circuitry is active and the DSP circuitry is bypassed.

[0010] In this embodiment, the controller is configured to select an operating mode independently for the first PHY device and the second PHY device.

[0011] According to the embodiments described herein, a method is also provided in a physical layer (PHY) device including an ingress transceiver and an egress transceiver, each including a corresponding analog signal processing (ASP) circuitry system and a corresponding digital signal processing (DSP) circuitry system. The method includes: selecting an operating mode for one or both of the ingress and egress transceivers between (i) a digital mode and (ii) an analog mode, wherein in the digital mode both the ASP and DSP circuitry systems are active, and in the analog mode the ASP circuitry system is active and the DSP circuitry system is bypassed. Communication is performed on a communication link according to the selected operating mode.

[0012] This disclosure will be more fully understood from the following detailed description of its embodiments, taken in conjunction with the accompanying drawings. Attached Figure Description

[0013] Figure 1This is a block diagram schematically illustrating a single-channel hybrid PHY device according to the embodiments disclosed herein;

[0014] Figure 2 This is a block diagram illustrating a network device including multiple dual-mode hybrid PHY devices, based on the embodiments disclosed herein.

[0015] Figure 3 This is a block diagram schematically illustrating a hybrid PHY device according to the embodiments disclosed herein;

[0016] Figure 4A This is a block diagram schematically illustrating an HDSP-LDSP mode hybrid PHY device coupled to an optical link (“line”) according to embodiments disclosed herein;

[0017] Figure 4B This is a block diagram schematically illustrating an HDSP-LANALOG mode hybrid PHY device coupled to an optical link according to embodiments disclosed herein;

[0018] Figure 4C This is a block diagram schematically illustrating a HANALOG-LDSP mode hybrid PHY device coupled to an optical link according to embodiments disclosed herein;

[0019] Figure 4D This is a block diagram schematically illustrating a HANALOG-LANALOG mode hybrid PHY device coupled to an optical link according to embodiments disclosed herein;

[0020] Figure 5 This is a block diagram schematically illustrating a hybrid PHY device configured to provide both rich telemetry information and low latency, according to embodiments disclosed herein.

[0021] Figures 6 to 8 This is a block diagram schematically illustrating the physical layout of an optical communication system according to embodiments disclosed herein; and

[0022] Figure 9 This is a flowchart illustrating, schematically, a method for configuring a hybrid transceiver according to embodiments disclosed herein. Detailed Implementation

[0023] Two main types of PHY devices can be used to address different application requirements and operating conditions. The first type includes low-cost, low-latency "eye openers," which primarily rely on analog circuitry to repeat signals over physical distances. These devices are useful in applications where minimal signal processing and low latency are desired.

[0024] The second type includes feature-rich, high-performance "DSP retimers" that utilize digital signal processing (DSP) technology to retime signals while covering physical distances. These devices offer advanced capabilities, including enhanced signal conditioning.

[0025] Each of the two types of PHY transceivers exhibits different characteristics in terms of performance, latency, and feature set. System designers can select a specific type of PHY device based on expected application requirements and operating conditions.

[0026] However, this approach can present challenges when the actual deployment environment differs from initial expectations or when requirements change over time. Furthermore, in some cases, different characteristics may be desired for the receiving and transmitting directions, or within different receiving or transmitting channels. This variability in requirements adds further complexity to the selection and deployment of PHY devices.

[0027] The embodiments described herein provide a PHY device that incorporates both analog and DSP technologies into the same device. Operating modes can be selectively configured at deployment time and / or at any time after the device has been put into use to achieve a desired mix of characteristics based on potentially changing application requirements and operating conditions.

[0028] In some embodiments, the disclosed hybrid physical layer (PHY) device supports multiple operating modes, including an analog “eye diagram opener” mode and a digital “DSP retimer” mode (for simplicity, the analog eye diagram opener mode and the DSP retimer mode are sometimes referred to as analog mode and DSP mode, respectively). The hybrid PHY architecture described herein provides flexibility to adapt to various deployment conditions and application requirements, offering advantages in system design and performance optimization.

[0029] In some embodiments, a hybrid PHY device incorporates both analog and digital signal processing circuitry, allowing for the selective activation or bypassing of certain components based on the chosen operating mode. This configurability enables the device to achieve different performance characteristics, such as latency, power consumption, and signal processing capabilities, depending on specific application requirements or operating environments.

[0030] The following detailed description presents various embodiments and implementations of a hybrid PHY device system, including its components, operating modes, and methods for mode selection and configuration. This disclosure also describes telemetry and diagnostic features that can enhance the functionality of the PHY device.

[0031] In some embodiments described below, the hybrid PHY device includes: a first PHY transceiver that receives input signals from a host ASIC and (e.g., via a laser) transmits output signals to an optical network; and a second PHY transceiver that receives input signals from an optical network (e.g., via a photodetector) and transmits output signals to the host ASIC. We refer to the first PHY transceiver as an exit transceiver and the second PHY transceiver as an ingress transceiver (the directions implied by the terms ingress and exit apply to line connections).

[0032] Figure 1 This is a block diagram schematically illustrating a single-channel hybrid PHY device 100 according to embodiments disclosed herein.

[0033] The hybrid PHY device 100 includes an ingress transceiver 102 and an egress transceiver 104. The ingress transceiver 102 receives signals from a communication channel (“line”) (e.g., an optical link), processes the received signals, and outputs the processed signals to the IC. The egress transceiver 104 receives signals from the IC, processes the received signals, and outputs the processed signals to the communication link.

[0034] The ingress transceiver 102 includes a line analog signal processor (Line-ASP) 106 and a line digital signal processor (Line-DSP) 108. The egress transceiver 104 includes a host analog signal processor (Host-ASP) 110 and a host digital signal processor (Host-DSP) 112.

[0035] The input multiplexer 114 is configured to select between the output of Line-ASP 106 and the output of Line-DSP 108. Similarly, the output multiplexer 116 is configured to select between the output of Host-ASP 112 and the output of Host-DSP 114. A PHY controller 118 is coupled to the input multiplexer 114 and the output multiplexer 116 to control the selection of the operating mode.

[0036] Analog signal processing components, including Line-ASP 106 and Host-ASP 112, typically include various analog circuits for signal amplification and conditioning, and can be designed to provide low-latency signal processing.

[0037] Digital signal processing components, including the Line-DSP 108 and Host-DSP 112, offer more advanced signal processing capabilities and can include digital signal processing functions such as error correction, equalization, encoding / decoding, and algorithms for signal enhancement and data manipulation, as well as algorithms for sample retiming. Digital processing enhances channel signal quality and retims channel sampling to minimize sampling errors.

[0038] PHY controller 118 manages the operation of PHY device 100 by configuring ingress multiplexer 114 and egress multiplexer 116. This configuration allows PHY device 100 to switch between analog eye diagram enable mode (or analog mode) and DSP retimer mode (or DSP mode), in which the signal primarily passes through analog components, and in DSP retimer mode, the signal undergoes both analog and digital processing. PHY controller 118 can select the configuration of ingress transceiver 102 and / or egress transceiver 104 based on various factors such as delay requirements, signal quality, power requirements, or specific application requirements. In some embodiments, some configurations may be hardwired, selected during reset, selected by firmware, selected by the operator, and / or selected based on signal quality measurements.

[0039] In some embodiments, signal quality (or equivalently, channel conditions) may be measured or estimated by the ingress transceiver 102, the egress transceiver 104, and / or the controller 118.

[0040] Figure 2 This is a block diagram schematically illustrating a dual-mode hybrid PHY device 200 according to embodiments disclosed herein. The dual-mode hybrid PHY 200 includes multiple channels, each channel including a dual-mode ingress transceiver 202 and a dual-mode egress transceiver 204 (in some embodiments, one or all of the ingress and / or egress transceivers may include a single-mode transceiver). Each channel is configured to communicate on a corresponding communication link (e.g., an optical link).

[0041] In this embodiment, the dual-mode ingress transceiver 202 is configured to process incoming channel signals in either analog or DSP mode (as defined above). Similarly, the dual-mode egress transceiver 204 is configured to process incoming host signals in either analog or DSP mode (in some cases, combined operating modes may be used, with some digital circuitry active). This will be referred to... Figure 5 (As described below).

[0042] The hybrid PHY 200 also includes a controller 206 coupled to a dual-mode ingress transceiver 202 and a dual-mode egress transceiver 204 for each channel. In some embodiments, the controller 206 is configured to independently manage the operating modes of the ingress transceiver and the egress transceiver for each channel. This architecture allows the dual-mode hybrid PHY device 200 to adapt its signal processing capabilities on a per-channel basis, potentially optimizing performance for varying channel conditions or application requirements.

[0043] For example, in some embodiments, controller 206 may select the operating mode of a given channel based on specific channel conditions (or equivalently, signal quality). The signal quality or channel conditions may be measured or estimated by the corresponding ingress transceiver 202, the corresponding egress transceiver 204, and / or by controller 206.

[0044] Figure 3 This is a block diagram schematically illustrating a hybrid PHY device 300 according to embodiments disclosed herein. Figure 3 In the example embodiment illustrated, the hybrid PHY device relays information between a host ASIC (also referred to as the host below) and a communication link, in this example, an optical channel. Communication between the host and the hybrid PHY device in both directions takes place in the analog domain, where internal processing within the transceiver can be performed in both the digital and / or analog domains. Communication between the transceiver and the optical channel—through converting analog signals to light to drive a laser in the optical channel and through a photodetector that converts light to analog signals to receive signals from the optical channel—also takes place in the analog domain.

[0045] We will use the following terminology for both paths (hereinafter, "host" refers to HOST-ASIC):

[0046] HRX-LTX (Host-Rx, Line-Tx) — an export transceiver that receives data from the host and transmits data to the optical components;

[0047] LRX-HTX (Line-Rx, Host-Tx) — an ingress transceiver that receives data from the optics and transmits data to the host.

[0048] In both cases, DSP and analog refer to the operating modes of the receive path—Host-Rx and Line-Rx.

[0049] In an embodiment, the HRX-LTX path of the hybrid PHY device 300 includes: an analog front-end amplifier 302 for amplifying the input signal; a continuous-time linear equalizer 304 for compensating for channel distortion and equalizing the frequency response of the received signal; a programmable gain amplifier 306 for adjusting the signal amplitude; an analog-to-digital converter (ADC) 308 for converting the signal into a digital representation; an Rx-DSP 310 for performing advanced signal processing operations and retiming data sampling (for improved channel performance); a protocol decoder 312 for decoding the input data; and a protocol encoder 314 for encoding the output data according to a specific protocol.

[0050] In this embodiment, the HRX-LTX path further includes: a DSP-Tx 316 for applying digital processing to the output signal; a digital-to-analog converter (DAC) 318 for converting the digital signal back to analog format; a programmable gain amplifier (PGA) 320 for adjusting the gain of the analog transmission path; an output mode selector 322 for selecting between the DAC 318 in DSP mode and the PGA 320 in analog mode; an analog transmitter 324; and a laser driver 326.

[0051] The LRX-HTX path of the hybrid PHY device 300 includes: a transimpedance amplifier (TIA) 328 for amplifying the signal from the photodetector; an analog front-end amplifier 330 for amplifying the analog input signal; a linear equalizer 332 for compensating for channel distortion; a PGA 334 for improving dynamic range utilization; an ADC 336 for converting the LRX-HTX stream into a digital stream; a DSP-Rx 338 for performing additional signal processing operations and retiming data sampling (to improve channel performance); a protocol decoder 340 for decoding the input stream received from the optics; and a protocol encoder 342 for encoding the symbols to be transmitted to the host.

[0052] In this embodiment, the LRX-HTX path further includes: a Tx-DSP 344 for performing additional transmission signal processing operations; a DAC 346 for converting the transmission signal into an analog signal; a PGA 348 for adjusting the transmission power level; an analog multiplexer 350 for selecting between the DAC 346 in DSP mode and the PGA 348 in analog mode; and an analog transmitter 352 for sending the analog signal to the Host-ASIC.

[0053] It should be noted that although some circuits in the HRX-LTX and LRX-HTX paths have the same names and perform the same or similar functions, the actual implementation can vary depending on the required functionality. Therefore, for example, the ADC336 and ADC 308 can have different resolutions; the PGA 306 and PGA 348 can have different specifications, and so on.

[0054] The following table shows which cells are active in each mode for the HRX-LTX and LRX-HTX paths:

[0055] Figure 4AThis is a block diagram schematically illustrating an HDSP-LDSP mode hybrid PHY device 400 coupled to an optical link (“line”) according to embodiments disclosed herein. The hybrid PHY device transmits data between the host and the optical link via a TIA driver and optics 402. The term HDSP-LDSP means that both the host input (output) and the line input are DSP mode receivers.

[0056] The PHY device 400 includes: an output transceiver 404 for receiving input signals from a host, processing the input signals, and sending output signals to a TIA driver and optics 402, which will transmit corresponding optical signals on the optical link; and an input transceiver 406 for receiving input signals from the TIA driver and optics 402, processing the input signals, and sending corresponding output signals to the host. Figure 4A In the example embodiment illustrated, both the output transceiver 404 and the input transceiver 406 are configured in DSP mode. This configuration can be useful when advanced signal processing is required in both directions.

[0057] Figure 4B This is a block diagram schematically illustrating an HDSP-LANALOG mode hybrid PHY device 420 coupled to an optical link, according to embodiments disclosed herein. PHY device 420 is similar to PHY device 400 (…). Figure 4A In addition to its output transceiver 404 being configured in DSP mode and its input transceiver 406 being configured in analog mode, this configuration can be useful, for example, when advanced signal processing is required to handle input data from the host, but low-latency reception is preferred in the path from the optical link.

[0058] Figure 4C This is a block diagram schematically illustrating a HANALOG-LDSP mode hybrid PHY device 440 coupled to an optical link, according to embodiments disclosed herein. PHY device 440 is similar to PHY device 400 (…). Figure 4A The exception is that its output transceiver 404 is configured in analog mode and its input transceiver 406 is configured in DSP mode. This mode can be advantageous, for example, when complex signal processing is required for signals received from the optical link, but not for the host signal.

[0059] Figure 4D This is a block diagram schematically illustrating a HANALOG-LANALOG hybrid PHY device 460 coupled to an optical link, according to embodiments disclosed herein. PHY device 460 and PHY device 400 ( Figure 4ASimilarly, except that both the export transceiver 404 and the import transceiver 406 are configured in analog mode. This configuration provides the lowest latency in both directions.

[0060] In some embodiments, the receiver of a hybrid PHY device can be configured in hybrid mode, in which the ASP output is directly routed to the transmission circuitry, but some or all of the DSP circuitry is active. This can be useful, for example, in telemetry applications where the hybrid PHY device provides channel telemetry information in addition to handling communication functions.

[0061] Figure 5 This is a block diagram schematically illustrating a hybrid PHY device 500 configured to provide both rich telemetry information and low latency, according to embodiments disclosed herein. In the host-to-optics path, the hybrid PHY device 500 includes an output transceiver 502 that processes input signals output from the host and transmits output signals to an optical fiber via a driver and laser circuitry 504. In the optics-to-host path, the hybrid PHY device includes an input transceiver 506 that processes input signals output from a photodetector and TIA circuitry 508 and transmits output signals to the host.

[0062] The export transceiver 502 includes an ASP 509 and a DSP 510; similarly, the import transceiver 506 includes an ASP 512 and a DSP 514.

[0063] according to Figure 5 In the illustrated example embodiment, the hybrid PHY device 500 is required to exhibit low signal latency in both the host-to-fiber and fiber-to-host directions; however, the hybrid PHY device 500 is also required to provide channel telemetry information regarding both the fiber interface signal and the host interface signal. For this purpose, in this embodiment, both the outgoing transceiver 502 and the incoming transceiver 506 are configured in hybrid mode, in which both ASP 509, ASP 512 and DSP 510, DSP 514 are active. Low latency is achieved by forwarding the outputs of ASP 509, ASP 512 to the host and the photodetector and TIA circuit 508, respectively. Telemetry is provided by collecting host interface and fiber channel telemetry information (e.g., voltage levels, spectrum, etc.) using portions of the DSP circuits 510, 514 and sending the channel information to the host via the telemetry circuit 516. In some embodiments, the telemetry circuit 516 uses the same wires to transmit channel telemetry information multiplexed with the fiber optic ingress data; in other embodiments, the telemetry circuit 516 transmits channel telemetry information on a sideband channel.

[0064] The ability to flexibly configure different operating modes and feature combinations brings (but is not limited to) the following benefits and advantages: 1. Designers are not forced to make prior compromises when selecting components; at this point, they only have incomplete knowledge about the final application requirements of the final product. 2. The system can adapt to different operating conditions, even if these conditions change during the product's lifespan. 3. System vendors only need to maintain a single inventory unit (SKU, or part number) for various application requirements, thereby simplifying inventory management. 4. In addition to being optimized for steady-state task modes under application and operating conditions, PHY devices can also be temporarily reconfigured for debugging and diagnostic purposes. 5. PHY devices can be configured to provide specific combinations of attributes (e.g., low latency and rich telemetry) that are desirable for end users.

[0065] refer to Figures 6 to 8 Three example embodiments of a hybrid PHY IC (also referred to as a chip) in three optical communication systems are described. The receiver circuitry of the hybrid PHY chip in the example embodiments described below can be configured to be in analog mode or DSP mode (or, as described above, in hybrid mode).

[0066] Figure 6 This is a block diagram schematically illustrating the physical layout of an optical communication system 600 according to embodiments disclosed herein. A host ASIC 602 sends electrical information to and receives electrical information from an optical subsystem 606 (which typically includes a laser, photodetector, TIA, and optical fiber) via a hybrid PHY chip 604.

[0067] To improve performance, the following guidelines should be followed: 1. Use a short on-die route between the input and output circuits of the hybrid PHY chip 604. 2. To achieve efficient layout utilization, the DSP circuit system is built around the serializer / deserializer (SerDes) circuit. 3. To reduce the routing distance of the critical Rx to Tx path, SerDes circuits are clustered close to each other.

[0068] Figure 7This is a block diagram schematically illustrating the physical layout of an optical communication system 700 according to embodiments disclosed herein. A host ASIC 702 transmits and receives electrical information via a hybrid PHY chip 704, which is converted into optical signals and then transmitted to / received from an optical subsystem. The hybrid PHY chip 704 includes a host-side receiver circuit (HRX) 706, which processes the input signals transmitted by the host ASIC 702 and outputs the processed signals to a line-side transmission (LTX) circuit 708. The LTX circuit 708 sends a corresponding drive signal to a laser 712, which then transmits optical signals to the optical subsystem.

[0069] On the receiving side, photodetector 714 converts light into an electrical signal, which is amplified by TIA 716. In the hybrid PHY chip 704, line-side receiver circuit (LRX) 718 processes the signal transmitted by TIA 716 and sends the processed signal to host-side transmission circuit (HTX), which then sends an output to host ASIC 702 based on the received optical signal.

[0070] In addition to the guidelines presented above, please refer to Figure 6 The lead positions on all four sides of the chip package can be optimized to minimize the physical distance between the laser driver 710 and the LTX 708, and between the TIA 716 and the LRX 718.

[0071] In some embodiments, some or all of the laser driver 710 and TIA 716 are integrated into the hybrid PHY chip 704. In other embodiments, silicon photonics technology may be used to integrate some or all of the optical components into the hybrid PHY chip.

[0072] Figure 8 This is a block diagram illustrating the physical layout of an optical communication system 800 according to embodiments disclosed herein. The optical communication system 800 includes a host ASIC 802, a hybrid PHY chip 804, and TIA driver and optical device circuitry 806. The hybrid PHY chip 804 includes a host-side HRX-HTX receiver / transmitter 808 and a line-side LRX-LTX receiver / transmitter 810.

[0073] according to Figure 8In the example embodiment shown, the DSP circuitry for both the ingress (optics to host) path and the egress (host to optics) path is physically located at the center of the hybrid PHY chip 804. However, for low analog-mode latency, routing signals from the host side of the chip to the optics side via metal and polysilicon conductors is not desirable due to the relatively long on-die delay of the polysilicon and / or metallized traces. Instead, in some embodiments, high-quality, low-loss gold bonding wires are used to cover the physical distance to improve signal quality.

[0074] Figure 9 This is a flowchart 900 schematically illustrating a method for configuring a hybrid transceiver according to embodiments disclosed herein. It is assumed that each PHY transceiver (input or output) includes an ASP, a DSP, telemetry circuitry (for transmitting telemetry data collected by the DSP to the host), and a mode selection switch to select either ASP output or DSP output.

[0075] In this embodiment, the flowchart can be executed by the user, who prepares configuration data for the processor that configures the PHY transceiver.

[0076] Configuration data may include, for example, the following switches (each transceiver individually): 1. ASP circuit: Turn on or off 2. DSP circuit: On or off 3. Output selection switch: ASP or DSP 4. Telemetry circuit: On or off.

[0077] Note that in this example embodiment, the hybrid mode is a combination where the output selection switch is set to select the ASP, but both the ASP circuitry and the DSP circuitry are activated.

[0078] The processor typically configures the transceiver based on configuration data according to reset and / or boot operations. In some embodiments, if the signal quality measurement changes during runtime, a full or partial configuration or reconfiguration can be initiated (e.g., if the bit error rate (BER) measurement falls below a preset threshold, the transceiver can be reconfigured from analog mode to DSP mode). The user executes flowchart 900 individually for each transceiver to be configured.

[0079] The method begins with the SET-ASP-On operation 902, where the user enables the ASP circuitry. Next, at the Check-High-Noise operation 904, the user checks whether the channel coupled to the transceiver is a high-noise channel, in which digital signal processing must be performed to accurately decode the received signal. If so, the user proceeds to the Set-Output-Select-DSP operation 906, setting the output selection switch to DSP, and then to the Set-DSP Circuit-On operation 908 to enable the DSP circuitry.

[0080] If the channel noise is low enough in operation 904 that the DSP is not required, the user proceeds to operation 910 (Set-Output-Select-ASP) to set the output selection switch to ASP, and then to operation 912 (Check-Telemetry-Required). If telemetry is not required, the flowchart ends. If telemetry is required in operation 912, the user proceeds to operation 914 (Set-Telemetry Circuit-On) to enable the telemetry circuit, and then to operation 908 (Set-DSP Circuit-On) to enable the DSP circuit. The flowchart ends after operation 908.

[0081] Therefore, according to Figure 9 The example flowchart shown in the figure and described above allows users to configure the configuration data of any or all transceivers of the PHY device by selectively enabling the transceiver's ASP, DSP, and telemetry circuitry, and by configuring the transceiver's output selection to choose ASP or DSP, based on channel noise conditions and telemetry requirements.

[0082] Figure 9 The configuration of flowchart 900 shown and described above is referenced by way of example. Other configurations may be used in alternative embodiments. For example, in one embodiment, low latency requirements may override signal quality checks, and the output selection may be set to ASP even when signal quality is low. In some embodiments, telemetry requires a predefined set of DSP functions, and only portions of the DSP circuitry are enabled when telemetry is required.

[0083] Figures 1 to 8 The configuration of the network device PHY circuitry shown and described above is referenced by way of example. In alternative embodiments, other configurations may be used. For example, in some embodiments, in hybrid PHY device 300 ( Figure 3In this embodiment, the host ASIC receives digital data (e.g., via a high-speed parallel bus), and therefore, the DAC 346 is not needed, the PGA 348 is replaced by the ADC, and the analog multiplexer 350 is a digital multiplexer. In another embodiment, the host ASIC sends digital data to the hybrid PHY device 300, and the HRX-LTX path changes accordingly.

[0084] In some embodiments, telemetry of the host line is not required, and therefore, telemetry circuit 516 ( Figure 5 The PHY 500 is configured to send only line-related telemetry information. In other embodiments, the hybrid PHY 500... Figure 5 In this configuration, low latency in one direction is not important, and therefore, one or both of the outgoing transceiver 502 and the incoming transceiver 506 can be set to DSP mode.

[0085] The various components of the disclosed PHY and network devices can be implemented using dedicated hardware or firmware, such as hard-wired or programmable logic in one or more application-specific integrated circuits (ASICs) or field-programmable gate arrays (FPGAs). Additionally or alternatively, some components of the disclosed PHY and network devices can be implemented in software and / or using a combination of hardware and software components. For clarity, components not essential for understanding the disclosed technology have been omitted from the figures.

[0086] In some embodiments, certain functions of the disclosed PHY device and network device, such as controller 118 and / or controller 206, may be implemented in one or more programmable processors (e.g., one or more central processing units (CPUs) or microcontrollers), which are programmed in software to implement the functions described herein. The software may be downloaded electronically to any processor via a network, or alternatively or additionally provided and / or stored on a non-transitory tangible medium such as magnetic memory, optical memory, or electronic memory.

[0087] Although the embodiments described herein primarily relate to optical transceivers, the methods and systems described herein can also be used with electrical transceivers, such as line card PHY chips printed on a PC board or PHY chips embedded in an active cable.

[0088] It should be noted that the embodiments described above are cited by way of example, and the invention is not limited to what has been specifically shown and described above. Rather, the scope of the invention includes combinations and sub-combinations of the various features described above, as well as variations and modifications thereof that would be conceived by those skilled in the art upon reading the foregoing description and that are not disclosed in the prior art. Documents incorporated herein by reference are considered part of this application; however, if any definition of a term in these incorporated documents conflicts with the definitions express or implied in this specification, only the definitions in this specification shall be considered.

Claims

1. A physical layer PHY device, comprising: An ingress transceiver and an egress transceiver, each of which includes a corresponding analog signal processing (ASP) circuit system and a corresponding digital signal processing (DSP) circuit system; as well as A controller configured to select an operating mode between (i) a digital mode and (ii) an analog mode for one or both of the ingress transceiver and the egress transceiver, wherein in the digital mode both the ASP circuitry and the DSP circuitry are active, and in the analog mode the ASP circuitry is active and the DSP circuitry is bypassed.

2. The PHY device of claim 1, wherein the controller is configured to independently select the operating mode for the ingress transceiver and the egress transceiver.

3. The PHY device according to claim 1 or 2, wherein the ASP circuit system includes an analog repeater circuit system configured to amplify analog signals.

4. The PHY device according to claim 1 or 2, wherein the DSP circuit system includes a digital retiming circuit system configured to digitally adjust the sampling timing of the digital signal.

5. The PHY device according to claim 1 or 2, wherein the DSP circuit system has a first delay, and wherein the ASP circuit system has a second delay less than the first delay.

6. The PHY device according to claim 1 or 2, wherein, When either or both of the ingress transceiver and the egress transceiver are operating in the analog mode, the DSP circuitry is bypassed but active and configured to collect telemetry information while being bypassed.

7. The PHY device according to claim 1 or 2, wherein: The ingress transceiver and the egress transceiver are configured to receive and transmit signals on the communication link, respectively; and The controller is configured to select the operating mode by comparing the channel conditions of the communication link with a defined level.

8. A network device, comprising: Multiple physical layer PHY devices are configured to communicate on corresponding network links. Each PHY device includes an ingress transceiver and an egress transceiver, and each of the ingress transceiver and the egress transceiver includes a corresponding analog signal processing (ASP) circuit system and a corresponding digital signal processing (DSP) circuit system. as well as A controller configured to select an operating mode for one or both of the ingress transceiver and the egress transceiver of each PHY device, the operating mode being selected between (i) a digital mode and (ii) an analog mode, in which both the ASP circuitry and the DSP circuitry are active, and in the analog mode, the ASP circuitry is active and the DSP circuitry is bypassed.

9. The network device of claim 8, wherein the controller is configured to independently select the operating mode for the first PHY device and the second PHY device.

10. The network device according to claim 8, wherein, For a given PHY device among the plurality of PHY devices, the controller is configured to independently select the operating mode for the ingress transceiver and the egress transceiver of the given PHY device.

11. The network device according to any one of claims 8 to 10, wherein the ASP circuit system includes an analog repeater circuit system configured to amplify analog signals.

12. The network device according to any one of claims 8 to 10, wherein the DSP circuit system includes a digital retiming circuit system configured to digitally adjust the sampling timing of a digital signal.

13. The network device according to any one of claims 8 to 10, wherein the DSP circuit system has a first delay, and wherein the ASP circuit system has a second delay less than the first delay.

14. The network device according to any one of claims 8 to 10, wherein, In a given PHY device among the plurality of PHY devices, when either or both of the ingress transceiver and the egress transceiver are operating in the analog mode, the DSP circuitry is bypassed but active and configured to collect telemetry information while being bypassed.

15. The network device according to any one of claims 8 to 10, wherein, For a given PHY device among the plurality of PHY devices: The ingress transceiver and the egress transceiver are configured to receive and transmit signals on the communication link, respectively; and The controller is configured to select the operating mode by comparing the channel conditions of the communication link with a defined level.

16. A method in a physical layer PHY device, the PHY device including an ingress transceiver and an egress transceiver, each of the ingress transceiver and the egress transceiver including a corresponding analog signal processing (ASP) circuit system and a corresponding digital signal processing (DSP) circuit system, the method comprising: For one or both of the ingress transceiver and the egress transceiver, an operating mode is selected between (i) digital mode and (ii) analog mode, in which both the ASP circuit system and the DSP circuit system are active, and in the analog mode, the ASP circuit system is active and the DSP circuit system is bypassed. as well as Communication is performed on the communication link according to the selected operating mode.

17. The method of claim 16, wherein the selection of the operating mode is performed independently for the ingress transceiver and the egress transceiver.

18. The method of claim 16 or 17, wherein the DSP circuit system has a first delay, and wherein the ASP circuit system has a second delay less than the first delay.

19. The method according to claim 16 or 17, further comprising: When one or both of the ingress transceiver and the egress transceiver are operating in the analog mode and the DSP circuitry is bypassed, the bypassed DSP circuitry is used to collect telemetry information.

20. The method of claim 16 or 17, wherein selecting the operating mode comprises: The channel conditions of the communication link are compared with the defined level.

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