Display device

Abstract

A display device includes a plurality of pixels, each of the plurality of pixels including a plurality of light emitting elements arranged in the plurality of pixels, a color conversion layer arranged on the plurality of light emitting elements of the plurality of pixels, an optical layer arranged on the color conversion layer, and an organic layer arranged on the optical layer, and the organic layer is disposed on the optical layer. At least one of the optical layer and the organic layer includes a plurality of recessed patterns disposed between the plurality of pixels.

Description

Technical Field

[0001] The present disclosure relates to a display device. Background Art

[0002] As interest in information display increases, research and development of display devices continues. Utility Model Content

[0003] Technical issues

[0004] An object to be solved by the present disclosure is to improve the reliability of a display device by minimizing warpage.

[0005] The purpose of the present disclosure is not limited to the above contents, and other advantages not described will be clearly understood from the following description by those skilled in the art.

[0006] Technical Solutions

[0007] According to an embodiment of the present disclosure, a display device may include a plurality of pixels, a color conversion layer, an optical layer, and an organic layer, each of the plurality of pixels includes a plurality of light-emitting elements arranged in the plurality of pixels, the color conversion layer is arranged on the plurality of light-emitting elements of the plurality of pixels, the optical layer is arranged on the color conversion layer, and the organic layer is arranged on the optical layer. At least one of the optical layer and the organic layer includes a plurality of recessed patterns arranged between the plurality of pixels.

[0008] The display device may further include a first cover layer disposed between the color conversion layer and the optical layer, and a second cover layer disposed between the optical layer and the organic layer.

[0009] The display device may further include a third capping layer disposed in the plurality of concave patterns.

[0010] The third covering layer may not overlap the plurality of pixels in a plan view.

[0011] The display device may further include a central portion and an outer portion surrounding the central portion. The number of the plurality of recessed patterns arranged per unit area in the central portion may be smaller than the number of the plurality of recessed patterns arranged per unit area in the outer portion.

[0012] The display device may further include a central portion and an outer portion surrounding the central portion. A depth of the plurality of recessed patterns arranged in the central portion may be smaller than a depth of the plurality of recessed patterns arranged in the outer portion.

[0013] The display device may further include a plurality of banks disposed between the plurality of pixels, and the color conversion layer may be disposed between the plurality of banks.

[0014] The display device may further include a color filter layer disposed on the organic layer.

[0015] The refractive index of the optical layer may be about 1.1 to about 1.3.

[0016] The optical layer may include hollow particles.

[0017] According to an embodiment, a display device may include: a plurality of pixels, a dam including an opening overlapping the plurality of pixels in a plan view, a plurality of light emitting elements arranged in the plurality of pixels, a color conversion layer arranged on the plurality of light emitting elements, an optical layer arranged on the color conversion layer, and an organic layer arranged on the optical layer. The color conversion layer, the optical layer, and the organic layer may be arranged in the opening of the dam.

[0018] Each of the plurality of pixels may include a first sub-pixel and a second sub-pixel. A dam may be disposed between the first sub-pixel and the second sub-pixel.

[0019] The dam may separate a portion of the optical layer overlapping the first sub-pixel in a plan view from a portion of the optical layer overlapping the second sub-pixel in a plan view.

[0020] The dam may separate a portion of the organic layer overlapping the first sub-pixel in a plan view from a portion of the organic layer overlapping the second sub-pixel in a plan view.

[0021] The display device may further include a first cover layer disposed between the color conversion layer and the optical layer, and a second cover layer disposed between the optical layer and the organic layer.

[0022] The first cover layer or the second cover layer may be disposed on the first sub-pixel and on the second sub-pixel.

[0023] The display device may further include a central portion and an outer portion surrounding the central portion. A height of the dam disposed in the central portion may be smaller than a height of the dam disposed in the outer portion.

[0024] The display device may further include a first connection electrode electrically connected to first ends of the plurality of light emitting elements and a second connection electrode electrically connected to second ends of the plurality of light emitting elements.

[0025] The display device may further include a color filter layer disposed on the organic layer.

[0026] The display device may further include an overcoat layer disposed on the color filter layer.

[0027] Details of other implementations are included in the detailed description and accompanying drawings.

[0028] Beneficial Effects

[0029] According to an embodiment of the present disclosure, a concave pattern may be formed in the optical layer and / or the organic layer, and thus the contraction stress may be dispersed when the optical layer and / or the organic layer is deformed. Therefore, the reliability of the display panel may be improved by minimizing warpage.

[0030] Effects according to the embodiments are not limited to the above-described contents, and other effects may be included in the specification. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 and Figure 2 are a schematic perspective view and a schematic cross-sectional view showing a light emitting element according to an embodiment;

[0032] Figure 3 is a schematic plan view showing a display device according to an embodiment;

[0033] Figures 4 to 6 is a schematic plan view showing a sub-pixel according to an embodiment;

[0034] Figure 7 is a schematic diagram showing an equivalent circuit of a sub-pixel according to an embodiment;

[0035] Figure 8 and Fig. 9 is a schematic cross-sectional view showing a sub-pixel according to an embodiment;

[0036] Fig.10 and Fig.11 is a schematic cross-sectional view showing first to third sub-pixels according to an embodiment;

[0037] Fig.12 is a schematic cross-sectional view showing first to third sub-pixels according to an embodiment; and

[0038] Figures 13 to 16 is a schematic cross-sectional view showing each process step of a method of manufacturing a display device according to an embodiment. DETAILED DESCRIPTION

[0039] The present disclosure will be described more fully hereinafter with reference to the accompanying drawings in which embodiments are shown. However, the present disclosure may be implemented in different forms and should not be construed as being limited to the embodiments set forth herein. Instead, these embodiments are provided so that the present disclosure will be thorough and complete and will fully convey the scope of the present disclosure to those skilled in the art. The present disclosure is limited only by the scope of the claims.

[0040] The terms used in this specification are used to describe the embodiments and are not intended to limit the present disclosure. In the specification and claims, for the purpose of its meaning and interpretation, the term "and / or" is intended to include any combination of the terms "and" and "or". For example, "A and / or B" may be understood to mean "A, B, or A and B". The terms "and" and "or" may be used in conjunction or disjunction and may be understood to be equivalent to "and / or".

[0041] As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0042] In the specification and claims, for the purposes of its meaning and interpretation, the phrase "at least one of" is intended to include "at least one selected from the group of..." For example, "at least one of A and B" may be understood to mean "A, B, or A and B."

[0043] As used herein, "about," "substantially," or "approximately" are inclusive of the stated value and mean within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art, taking into account the errors associated with the measurements and the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, "about" can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value.

[0044] The terms “comprises” and / or “comprising” do not exclude the existence of or addition to the described components, steps, operations and / or elements.

[0045] The term "coupling" or "connection" may refer to physical and / or electrical coupling or connection. This may refer to direct or indirect coupling or connection and integral or non-integral coupling or connection.

[0046] The case where an element or a layer is referred to as being “on” another element or layer includes the case where another layer or another element is disposed directly on the other element or between the other layers. The same reference numerals denote the same components throughout the specification.

[0047] Although the terms "first", "second", etc. are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from another component. Therefore, within the technical spirit of the present disclosure, the first component described below may be the second component.

[0048] Hereinafter, embodiments of the present disclosure are described in detail with reference to the accompanying drawings.

[0049] Figure 1 and Figure 2 are a schematic perspective view and a schematic cross-sectional view showing a light emitting element according to an embodiment. Figure 1 and Figure 2A pillar-shaped light emitting element LD is shown, but the type and / or shape of the light emitting element LD is not limited thereto.

[0050] Reference Figure 1 and Figure 2 The light emitting element LD may include a first semiconductor layer 11 , an active layer 12 , a second semiconductor layer 13 and / or an electrode layer 14 .

[0051] The light emitting element LD may be formed in a column shape extending in one direction. The light emitting element LD may have a first end EP1 and a second end EP2. One of the first semiconductor layer 11 and the second semiconductor layer 13 may be arranged at the first end EP1 of the light emitting element LD. The other of the first semiconductor layer 11 and the second semiconductor layer 13 may be arranged at the second end EP2 of the light emitting element LD. For example, the first semiconductor layer 11 may be arranged at the first end EP1 of the light emitting element LD, and the second semiconductor layer 13 may be arranged at the second end EP2 of the light emitting element LD.

[0052] According to an embodiment, the light emitting element LD may be a light emitting element manufactured into a column shape by an etching method or the like. In the specification, the column shape may include a rod shape or a bar shape having an aspect ratio greater than 1, such as a cylinder or a polygonal column, and the shape of its cross section is not limited.

[0053] The light emitting element LD may have a size as small as nanometer to micrometer. For example, each light emitting element LD may have a diameter D (or width) and / or a length L ranging from nanometer to micrometer. However, the size of the light emitting element LD is not limited thereto, and the size of the light emitting element LD may vary according to the design conditions of a device (e.g., a display device or the like) using a light emitting device that uses the light emitting element LD as a light source.

[0054] The first semiconductor layer 11 may be a semiconductor layer of the first conductivity type. For example, the first semiconductor layer 11 may include a p-type semiconductor layer. For example, the first semiconductor layer 11 may include at least one semiconductor material among InAlGaN, GaN, AlGaN, InGaN, and AlN, and may include a p-type semiconductor layer doped with a first conductivity type dopant such as Mg. However, the material of the first semiconductor layer 11 is not limited thereto, and other materials may be used in the first semiconductor layer 11.

[0055] The active layer 12 may be disposed between the first semiconductor layer 11 and the second semiconductor layer 13. The active layer 12 may have any one of a single well structure, a multi-well structure, a single quantum well structure, a multi-quantum well (MQW) structure, a quantum dot structure, and a quantum wire structure, but the embodiment is not limited thereto. The active layer 12 may include GaN, InGaN, InAlGaN, AlGaN, or AlN, and other materials may be used in the active layer 12.

[0056] When a voltage equal to or greater than the threshold voltage is applied to both ends of the light emitting element LD, electron-hole pairs are combined in the active layer 12, and thus the light emitting element LD emits light. By controlling the emission of the light emitting element LD using this principle, the light emitting element LD can be used as a light source in a light emitting device including a pixel of a display device.

[0057] The second semiconductor layer 13 may be arranged on the active layer 12, and may include a semiconductor layer of a different type from the type of the first semiconductor layer 11. The second semiconductor layer 13 may include an n-type semiconductor layer. For example, the second semiconductor layer 13 may include any semiconductor material among InAlGaN, GaN, AlGaN, InGaN, and AlN, and may include an n-type semiconductor layer doped with a second conductive type dopant such as phosphorus Si, Ge, and Sn. However, the material used in the second semiconductor layer 13 is not limited thereto, and the second semiconductor layer 13 may include other materials.

[0058] The electrode layer 14 may be disposed on the first end EP1 and / or the second end EP2 of the light emitting element LD. Figure 2 The case where the electrode layer 14 is formed on the first semiconductor layer 11 is shown, but the present disclosure is not limited thereto. For example, a separate contact electrode may also be arranged on the second semiconductor layer 13 .

[0059] The electrode layer 14 may include a transparent metal or a transparent metal oxide. For example, the electrode layer 14 may include at least one of indium tin oxide (ITO), indium zinc oxide (IZO), and zinc tin oxide (ZTO), but the embodiment is not limited thereto. As described above, when the electrode layer 14 is formed of a transparent metal or a transparent metal oxide, light generated in the active layer 12 of the light emitting element LD may pass through the electrode layer 14 and may be emitted to the outside of the light emitting element LD.

[0060] The insulating film INF may be provided on the surface of the light emitting element LD. The insulating film INF may be directly disposed on the surface of the first semiconductor layer 11, the active layer 12, the second semiconductor layer 13, and / or the electrode layer 14. The insulating film INF may expose the first end EP1 and the second end EP2 of the light emitting element LD having different polarities. According to an embodiment, the insulating film INF may expose the side portions of the electrode layer 14 and / or the second semiconductor layer 13 adjacent to the first end EP1 and the second end EP2 of the light emitting element LD.

[0061] The insulating film INF can prevent electrical short circuits that may occur when the active layer 12 contacts conductive materials other than the first and second semiconductor layers 11 and 13. The insulating film INF can minimize surface defects of the light emitting element LD, thereby improving the lifetime and emission efficiency of the light emitting element LD.

[0062] The insulating film INF may include at least one of silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy), aluminum nitride (AlNx), aluminum oxide (AlOx), zirconium oxide (ZrOx), hafnium oxide (HfOx), and titanium oxide (TiOx). For example, the insulating film INF may be configured as a double layer, and each layer of the double layer may include a different material. For example, the insulating film INF may be configured as a double layer including aluminum oxide (AlOx) and silicon oxide (SiOx), but the embodiment is not limited thereto. According to an embodiment, the insulating film INF may be omitted.

[0063] The light emitting device including the above-mentioned light emitting element LD can be used in various devices (including display devices) that require a light source. For example, the light emitting element LD can be arranged in each pixel of the display panel, and the light emitting element LD can be used as the light source of each pixel. However, the application field of the light emitting element LD is not limited to the above-mentioned example. For example, the light emitting element LD can also be used in other types of devices (such as lighting devices) that require a light source.

[0064] Figure 3 is a schematic plan view showing a display device according to an embodiment. Figures 4 to 6 is a schematic plan view showing a sub-pixel according to an embodiment.

[0065] exist Figure 3 In, as can be Figure 1 and Figure 2 An example of an electronic device in which the light emitting element LD described in the embodiment is used as a light source is shown, and a display panel PNL provided in a display device is shown.

[0066] Each pixel unit PXU of the display panel PNL and each sub-pixel PXL of the pixel unit PXU may include at least one light emitting element LD. Figure 3 , the structure of the display panel PNL is briefly shown based on the display area DA. However, according to an embodiment, at least one driving circuit unit (eg, at least one of a scan driver and a data driver), lines and / or pads not shown may also be arranged on the display panel PNL.

[0067] Reference Figure 3, the display panel PNL may include a substrate SUB and a pixel unit PXU arranged on the substrate SUB. The pixel unit PXU may include a first subpixel PXL1, a second subpixel PXL2 and / or a third subpixel PXL3. Hereinafter, when at least one subpixel among the first subpixel PXL1, the second subpixel PXL2 and the third subpixel PXL3 is arbitrarily referred to, or when two or more types of subpixels are collectively referred to, at least one subpixel or two or more types of subpixels are referred to as "subpixel PXL" or "plurality of subpixels PXL".

[0068] The substrate SUB may include a base member of the display panel PNL, and may be a rigid or flexible substrate or film. For example, the substrate SUB may be formed of a rigid substrate formed of glass or tempered glass, or a flexible substrate (or film) formed of a plastic or metal material, and the material and / or physical properties of the substrate SUB are not particularly limited.

[0069] The display panel PNL and the substrate SUB for forming the same may include a display area DA for displaying an image and a non-display area NDA other than the display area DA. The sub-pixels PXL may be arranged in the display area DA. Lines, pads, and / or built-in circuits of the sub-pixels PXL connected to the display area DA may be arranged in the non-display area NDA. The sub-pixels PXL may be arranged according to stripes or PENTILE TM However, the arrangement structure of the sub-pixels PXL is not limited thereto, and the sub-pixels PXL may be arranged in the display area DA in other structures and / or methods.

[0070] According to an embodiment, two or more types of sub-pixels PXL emitting light of different colors may be arranged in the display area DA. For example, a first sub-pixel PXL1 emitting light of a first color, a second sub-pixel PXL2 emitting light of a second color, and a third sub-pixel PXL3 emitting light of a third color may be arranged in the display area DA. At least one of the first sub-pixel PXL1, the second sub-pixel PXL2, and the third sub-pixel PXL3 arranged adjacent to each other may be included in the pixel unit PXU capable of emitting light of multiple colors. For example, each of the first sub-pixel PXL1, the second sub-pixel PXL2, and the third sub-pixel PXL3 may be a sub-pixel emitting light of a selected color. According to an embodiment, the first sub-pixel PXL1 may be a red pixel emitting red light, the second sub-pixel PXL2 may be a green pixel emitting green light, and the third sub-pixel PXL3 may be a blue pixel emitting blue light, but is not limited thereto.

[0071] In an embodiment, the first sub-pixel PXL1, the second sub-pixel PXL2, and the third sub-pixel PXL3 may include a light-emitting element emitting light of the same color, and may include a color conversion layer and / or a color filter of different colors arranged on the corresponding light-emitting element to emit light of the first color, the second color, and the third color, respectively. In other examples, the first sub-pixel PXL1, the second sub-pixel PXL2, and the third sub-pixel PXL3 may include a light-emitting element of the first color, a light-emitting element of the second color, and a light-emitting element of the third color as a light source to emit light of the first color, the second color, and the third color, respectively. However, the color, type, number, and / or the like of the sub-pixel PXL included in each pixel unit PXU are not limited. The color of the light emitted by each sub-pixel PXL may change.

[0072] The sub-pixel PXL may include at least one light source driven by a selected control signal (eg, a scan signal and a data signal) and / or a selected power (eg, a first power and a second power). Figure 1 and Figure 2 At least one light emitting element LD of any of the embodiments, such as an ultra-small columnar light emitting element LD having a size in the range of nanometers to micrometers. However, the present disclosure is not limited thereto, and other types of light emitting elements LD may be used as the light source of the sub-pixel PXL.

[0073] In an embodiment, each sub-pixel PXL may be configured as an active pixel. However, the type, structure and / or driving method of the sub-pixel PXL applicable to the display device are not limited. For example, each sub-pixel PXL may be configured as a pixel of a passive or active light-emitting display device using other types of if structure driving methods.

[0074] The display area DA may include a first area A1 and a second area A2.

[0075] The first area A1 may correspond to a central portion, and the second area A2 may correspond to an outer portion surrounding the central portion. For example, the second area A2 may correspond to an area spaced about 40 mm to about 50 mm from an edge of the display area DA.

[0076] As the organic layers including the display panel PNL are repeatedly stacked and cured, warping may occur, and thus the reliability of the display panel PNL may be reduced. Such warping may increase in the second area A2 corresponding to the outer portion compared to the first area A1 as the central portion. Accordingly, in the display device according to the embodiment, the recessed portion RA may be formed between the sub-pixels PXL so as to disperse the contraction stress generated during the deformation of the organic layers including the display panel PNL as the organic layers are repeatedly stacked and cured. Figures 4 to 6A detailed description of the recessed portion RA is provided. Figures 4 to 6 , a view in a plane formed by a first direction (X-axis direction) and a second direction (Y-axis direction) observed from a third direction (Z-axis direction) is shown, wherein the third direction (Z-axis direction) may be perpendicular to the plane formed by the first direction (X-axis direction) and the second direction (Y-axis direction).

[0077] The recessed portion RA may be disposed between the first sub-pixel PXL1, the second sub-pixel PXL2, and the third sub-pixel PXL3. The recessed portion RA may include at least one recessed pattern RP. Figure 4 As shown in , the recessed pattern RP may have a stripe or slit shape extending along the second direction (Y-axis direction). Figure 5 As shown in FIG. 1 , a plurality of recessed patterns RP may exist in one recessed portion RA. The recessed pattern RP may have Figure 6 However, the shape of the recessed pattern RP is not limited thereto and may be changed within a range capable of dispersing the shrinkage stress of the organic layer.

[0078] In an embodiment, the number of the recessed patterns RP per unit area of ​​the first area A1 may be different from the number of the recessed patterns RP per unit area of ​​the second area A2. For example, the number of the recessed patterns RP per unit area of ​​the first area A1 may be less than the number of the recessed patterns RP per unit area of ​​the second area A2. As described above, when a large number of recessed patterns RP are formed in the second area A2 corresponding to the outer portion, the warping phenomenon may be minimized because the contraction stress of the second area A2 may be dispersed. According to an embodiment, the number of the recessed patterns RP per unit area of ​​the second area A2 may increase from a point adjacent to the first area A1 to an edge of the display area DA. Accordingly, the contraction stress increased toward the edge of the display area DA may be dispersed.

[0079] The depth of the recessed pattern RP of the first area A1 may be different from the depth of the recessed pattern RP of the second area A2. For example, the depth of the recessed pattern RP of the first area A1 may be less than the depth of the recessed pattern RP of the second area A2. As described above, when the recessed pattern RP is deeply formed in the second area A2 corresponding to the outer portion, the warping phenomenon can be minimized because the contraction stress of the second area A2 can be dispersed. According to an embodiment, the depth of the recessed pattern RP of the second area A2 may increase from a point adjacent to the first area A1 to an edge of the display area DA. Accordingly, the contraction stress increased toward the edge of the display area DA can be more dispersed.

[0080] Figure 7 is a schematic diagram showing an equivalent circuit of a sub-pixel according to an embodiment.

[0081] Reference Figure 7 , the sub-pixel PXL may include a light emitting unit LSU for generating light with brightness corresponding to the data signal, and a pixel circuit PXC for driving the light emitting unit LSU.

[0082] The light emitting unit LSU may include at least one light emitting element LD electrically connected between the first power VDD and the second power VSS. For example, the light emitting unit LSU may include a first electrode ELT1 electrically connected to the first power VDD through the pixel circuit PXC and the first power line PL1, a second electrode ELT2 electrically connected to the second power VSS through the second power line PL2, and a light emitting element LD electrically connected between the first electrode ELT1 and the second electrode ELT2. In an embodiment, the first electrode ELT1 may be an anode electrode, and the second electrode ELT2 may be a cathode electrode.

[0083] Each of the light emitting elements LD may include a first terminal EP1 electrically connected to the first power VDD through the first electrode ELT1 and / or the pixel circuit PXC, and a second terminal EP2 electrically connected to the second power VSS through the second electrode ELT2. For example, the light emitting element LD may be connected between the first electrode ELT1 and the second electrode ELT2 in the forward direction. Each light emitting element LD electrically connected between the first power VDD and the second power VSS in the forward direction may include a corresponding effective light source, and the set of effective light sources may include a light emitting unit LSU of the sub-pixel PXL.

[0084] The first power VDD and the second power VSS may have different potentials so that the light emitting element LD can emit light. For example, the first power VDD may be set to a high potential power, and the second power VSS may be set to a low potential power. During the emission period of at least the sub-pixel PXL, the potential difference between the first power VDD and the second power VSS may be set to be greater than or equal to the threshold voltage of the light emitting element LD.

[0085] One end of the light emitting element LD included in each light emitting unit LSU may be commonly connected to the pixel circuit PXC through an electrode of the light emitting unit LSU (e.g., the first electrode ELT1 of each sub-pixel PXL), and may be electrically connected to the first power VDD through the pixel circuit PXC and the first power line PL1. The other end of the light emitting element LD may be commonly connected to the second power VSS through another electrode of the light emitting unit LSU (e.g., the second electrode ELT2 of each sub-pixel PXL) and the second power line PL2.

[0086] The light emitting element LD may emit light having a brightness corresponding to the driving current supplied by the corresponding pixel circuit PXC. For example, during each frame period, the pixel circuit PXC may supply a driving current corresponding to a grayscale value to be expressed in the corresponding frame to the light emitting unit LSU. The driving current supplied to the light emitting unit LSU may be divided and may flow through a plurality of light emitting elements LD electrically connected in a forward direction. Accordingly, the light emitting unit LSU may emit light having a brightness corresponding to the driving current, and each light emitting element LD emits light having a brightness corresponding to the current flowing therein.

[0087] The pixel circuit PXC may be electrically connected between the first power VDD and the first electrode ELT1. The pixel circuit PXC may be electrically connected to the scan line Si and the data line Dj of the corresponding sub-pixel PXL. For example, when the sub-pixel PXL is arranged on the i-th (i is a natural number) horizontal line (row) and the j-th (j is a natural number) vertical line (column) of the display area DA, the pixel circuit PXC may be connected to the i-th scan line Si and the j-th data line Dj of the display area DA.

[0088] According to an embodiment, the pixel circuit PXC may include transistors (eg, first, second, and third transistors T1 , T2 , and T3 ) and at least one storage capacitor (eg, storage capacitor Cst).

[0089] The first transistor T1 may be electrically connected between the first power VDD and the light emitting unit LSU. For example, a first electrode (e.g., a drain electrode) of the first transistor T1 may be electrically connected to the first power VDD, and a second electrode (e.g., a source electrode) of the first transistor T1 may be electrically connected to the first electrode ELT1. A gate electrode of the first transistor T1 may be electrically connected to a first node N1. The first transistor T1 may control a driving current supplied to the light emitting unit LSU in response to a voltage of the first node N1. For example, the first transistor T1 may be a driving transistor that controls a driving current of the subpixel PXL.

[0090] In an embodiment, the first transistor T1 may further include a lower conductive layer BML (also referred to as a "lower electrode", "back gate electrode" or "lower light blocking layer"). The gate electrode of the first transistor T1 and the lower conductive layer BML may overlap each other, and an insulating layer may be interposed therebetween. The lower conductive layer BML may be electrically connected to an electrode of the first transistor T1, for example, a source electrode or a drain electrode.

[0091] In the case where the first transistor T1 includes a lower conductive layer BML, when the sub-pixel PXL is driven, a reverse bias technique (or a sync technique) may be applied to move the threshold voltage of the first transistor T1 in a negative direction or a positive direction by applying a reverse bias voltage to the lower conductive layer BML of the first transistor T1. For example, by applying a source-sink technique to electrically connect the lower conductive layer BML to the source electrode of the first transistor T1, the threshold voltage of the first transistor T1 may be moved in a negative direction or a positive direction. When the lower conductive layer BML is arranged below the semiconductor pattern including the channel of the first transistor T1, the lower conductive layer BML may be used as a light-blocking pattern and may stabilize the operating characteristics of the first transistor T1. However, the function and / or utilization method of the lower conductive layer BML are not limited thereto.

[0092] The second transistor T2 may be electrically connected between the data line Dj and the first node N1. For example, the first electrode of the second transistor T2 may be electrically connected to the data line Dj, and the second electrode of the second transistor T2 may be electrically connected to the first node N1. The gate electrode of the second transistor T2 may be electrically connected to the scan line Si. When a scan signal SSi of a gate-on voltage (e.g., a high-level voltage) is supplied from the scan line Si, the second transistor T2 may be turned on to electrically connect the data line Dj and the first node N1.

[0093] In each frame period, a data signal DSj of a corresponding frame may be supplied to the data line Dj, and during a period of the scan signal SSi in which a gate-on voltage is supplied, the data signal DSj may be transmitted to the first node N1 through the turned-on second transistor T2. For example, the second transistor T2 may be a switching transistor for transmitting each data signal DSj to the inside of the subpixel PXL.

[0094] The third transistor T3 may be electrically connected between the first transistor T1 and the sensing line SLj. For example, one electrode of the third transistor T3 may be electrically connected to the second electrode (e.g., source electrode) of the first transistor T1 electrically connected to the first electrode ELT1, and the other electrode of the third transistor T3 may be electrically connected to the sensing line SLj. In the case where the sensing line SLj is omitted, the other electrode of the third transistor T3 may be electrically connected to the data line Dj.

[0095] The gate electrode of the third transistor T3 may be electrically connected to the sensing control line SCLi. In the case where the sensing control line SCLi is omitted, the gate electrode of the third transistor T3 may be electrically connected to the scan line Si. The third transistor T3 may be turned on by a sensing control signal SCSi of a gate-on voltage (e.g., a high level voltage) supplied to the sensing control line SCLi during the sensing period to electrically connect the sensing line SLj and the first transistor T1.

[0096] According to an embodiment, the sensing period may be a period in which the characteristic of each of the sub-pixels PXL arranged in the display area DA (for example, the threshold voltage of the first transistor T1 or the like) is extracted. During the sensing period, the first transistor T1 may be turned on by supplying a reference voltage that allows the first transistor T1 to be turned on to the first node N1 through the data line Dj and the second transistor T2 or by electrically connecting each sub-pixel PXL to a current source or the like. The third transistor T3 may be turned on by supplying a sensing control signal SCSi of a gate-on voltage to the third transistor T3 to electrically connect the first transistor T1 to the sensing line SLj. The sensing signal SENj may be obtained through the sensing line SLj, and the characteristic of each sub-pixel PXL including the threshold voltage of the first transistor T1 or the like may be detected using the sensing signal SENj. Information on the characteristic of each sub-pixel PXL may be used to convert image data so that characteristic deviations between the sub-pixels PXL arranged in the display area DA may be compensated.

[0097] One electrode of the storage capacitor Cst may be electrically connected to the second electrode of the first transistor T1, and the other electrode may be electrically connected to the first node N1. The storage capacitor Cst may charge a voltage corresponding to the data signal DSj supplied to the first node N1 during each frame period.

[0098] Figure 7 An embodiment in which all effective light sources and light emitting elements LD included in each light emitting unit LSU are connected in parallel is shown, but the present disclosure is not limited thereto. For example, the light emitting unit LSU of each sub-pixel PXL may include a series structure of at least two stages. The light emitting elements included in each series stage may be connected in series with each other through at least one intermediate electrode.

[0099] exist Figure 7 In the embodiment, all transistors included in the pixel circuit PXC are n-type transistors, but the present disclosure is not limited thereto. For example, at least one of the first transistor T1, the second transistor T2, and the third transistor T3 may be changed to a p-type transistor.

[0100] The structure and driving method of the sub-pixel PXL can be changed. For example, the pixel circuit PXC can be composed of Figure 7 It is composed of other structures and / or driving methods other than the structures and / or driving methods shown in .

[0101] Figure 8 and Fig. 9 is a schematic cross-sectional view showing a sub-pixel according to an embodiment.

[0102] Figure 8 and Fig. 9 1 shows the light emitting element layer EL of the sub-pixel PXL. Figure 8 and Fig. 9The figure shows the Figure 7 The first transistor T1 among the circuit elements in the pixel circuit PXC. When the first transistor T1, the second transistor T2, and the third transistor T3 are not individually specified, the first transistor T1, the second transistor T2, and the third transistor T3 may be collectively referred to as "transistor T" or "plurality of transistors T". The structure of the transistor T, the position of each layer, and / or the like are not limited to Figure 8 and Fig. 9 The embodiments shown in FIG. 1 and may be varied in other embodiments.

[0103] Reference Figure 8 and Fig. 9 , the light emitting element layer EL of the sub-pixel PXL according to the embodiment may include a circuit element including a transistor T arranged on a substrate SUB, and a line electrically connected to the circuit element. The first electrode ELT1 and the second electrode ELT2 (also referred to as "alignment electrodes") of the light emitting unit LSU, the light emitting element LD, and / or the first connection electrode CNE1 and the second connection electrode CNE2 may be arranged on the circuit element. Hereinafter, the first electrode ELT1 and the second electrode ELT2 may be collectively referred to as "electrode ELT". Depending on the context, any of the individual electrodes may be individually referred to as "electrode ELT". Similarly, the first connection electrode CNE1 and the second connection electrode CNE2 may be collectively referred to as "connection electrode CNE". Any of the individual connection electrodes may be individually referred to as "connection electrode CNE".

[0104] The substrate SUB may include a base member, and may be a rigid or flexible substrate or film. For example, the substrate SUB may be a rigid substrate formed of glass or tempered glass, a flexible substrate (or film) formed of a plastic or metal material, or an insulating layer of at least one layer. The material and / or physical properties of the substrate SUB are not particularly limited. In an embodiment, the substrate SUB may be substantially transparent. Here, "substantially transparent" may mean that light can be transmitted at a selected transmittance or higher. In other embodiments, the substrate SUB may be translucent or opaque. According to other embodiments, the substrate SUB may include a reflective material.

[0105] The first conductive layer C1 may be disposed on the substrate SUB. The first conductive layer C1 may include a lower conductive layer BML of the transistor T and a first electrically conductive layer PL2a. The lower conductive layer BML and the first electrically conductive layer PL2a may be disposed on the same layer. For example, the lower conductive layer BML and the first electrically conductive layer PL2a may be formed simultaneously in the same process, but are not limited thereto. The first electrically conductive layer PL2a may include a reference Figure 7 The second power line PL2 described in the above description.

[0106] The first conductive layer C1 may be configured as a single layer or a multilayer formed of at least one of molybdenum (Mo), copper (Cu), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and indium tin oxide (ITO), or alloys thereof.

[0107] The buffer layer BFL may be disposed on the first conductive layer C1. The buffer layer BFL may prevent impurities from diffusing into the circuit element. The buffer layer BFL may be configured as a single layer, but may be configured as a multilayer of at least two or more layers. When the buffer layer BFL is formed of a multilayer, each layer may be formed of the same material or may be formed of different materials.

[0108] The semiconductor patterns SCP may be arranged on the buffer layer BFL. For example, each semiconductor pattern SCP may include a first region electrically contacting the first transistor electrode TE1, a second region electrically contacting the second transistor electrode TE2, and a channel region between the first region and the second region. According to an embodiment, one of the first region and the second region may be a source region, and the other may be a drain region.

[0109] According to an embodiment, the semiconductor pattern SCP may be formed of polysilicon, amorphous silicon, an oxide semiconductor, or the like. The channel region of the semiconductor pattern SCP may be an intrinsic semiconductor as a semiconductor pattern not doped with impurities. Each of the first and second regions of the semiconductor pattern SCP may be a semiconductor doped with impurities.

[0110] The gate insulating layer GI may be disposed on the buffer layer BFL and the semiconductor pattern SCP. For example, the gate insulating layer GI may be disposed between the semiconductor pattern SCP and the gate electrode GE. The gate insulating layer GI may be disposed between the buffer layer BFL and the second power conductive layer PL2b. The gate insulating layer GI may be configured as a single layer or a multilayer, and may include an inorganic material including silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy), aluminum nitride (AlNx), aluminum oxide (AlOx), zirconium oxide (ZrOx), hafnium oxide (HfOx), or titanium oxide (TiOx).

[0111] The second conductive layer C2 may be arranged on the gate insulating layer GI. The second conductive layer C2 may include a gate electrode GE of the transistor T and a second power conductive layer PL2b. The gate electrode GE and the second power conductive layer PL2b may be arranged on the same layer. For example, the gate electrode GE and the second power conductive layer PL2b may be formed simultaneously in the same process, but is not limited thereto. The gate electrode GE may overlap the semiconductor pattern SCP in a third direction (Z-axis direction) on the gate insulating layer GI. The second power conductive layer PL2b may overlap the first power conductive layer PL2a in a third direction (Z-axis direction) on the gate insulating layer GI. The second power conductive layer PL2b may include, together with the first power conductive layer PL2a Figure 7The second power line PL2 described in etc.

[0112] The second conductive layer C2 may be configured as a single layer or multiple layers formed of at least one of titanium (Ti), copper (Cu), indium tin oxide (ITO), molybdenum (Mo), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd), or an alloy thereof. For example, the second conductive layer C2 may be formed as a multilayer in which titanium (Ti), copper (Cu), and / or indium tin oxide (ITO) are sequentially or repeatedly stacked.

[0113] The interlayer insulating layer ILD may be disposed on the second conductive layer C2. For example, the interlayer insulating layer ILD may be disposed between the gate electrode GE and the first and second transistor electrodes TE1 and TE2. The interlayer insulating layer ILD may be disposed between the second and third power conductive layers PL2b and PL2c.

[0114] The interlayer insulating layer ILD may be configured as a single layer or a multilayer, and may include an inorganic material including silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy), aluminum nitride (AlNx), aluminum oxide (AlOx), zirconium oxide (ZrOx), hafnium oxide (HfOx), or titanium oxide (TiOx).

[0115] The third conductive layer C3 may be arranged on the interlayer insulating layer ILD. The third conductive layer C3 may include the first transistor electrode TE1 and the second transistor electrode TE2 of the transistor T and the third power conductive layer PL2c. The first transistor electrode TE1 and the second transistor electrode TE2 and the third power conductive layer PL2c may be arranged on the same layer. For example, the first transistor electrode TE1 and the second transistor electrode TE2 and the third power conductive layer PL2c may be formed simultaneously in the same process, but are not limited thereto.

[0116] The first transistor electrode TE1 and the second transistor electrode TE2 may be arranged on the interlayer insulating layer ILD. The first transistor electrode TE1 and the second transistor electrode TE2 may be arranged to overlap with the semiconductor pattern SCP in a third direction (Z-axis direction). The first transistor electrode TE1 and the second transistor electrode TE2 may be electrically connected to the semiconductor pattern SCP. For example, the first transistor electrode TE1 may be electrically connected to the first region of the semiconductor pattern SCP through a contact hole passing through the interlayer insulating layer ILD. The second transistor electrode TE2 may be electrically connected to the second region of the semiconductor pattern SCP through a contact hole passing through the interlayer insulating layer ILD. The second transistor electrode TE2 may be electrically connected to the lower conductive layer BML through a contact hole passing through the interlayer insulating layer ILD and the buffer layer BFL. According to an embodiment, one of the first transistor electrode TE1 and the second transistor electrode TE2 may be a source electrode, and the other may be a drain electrode.

[0117] The third power conductive layer PL2c may overlap with the first power conductive layer PL2a and / or the second power conductive layer PL2b in the third direction (Z-axis direction). The third power conductive layer PL2c may be electrically connected to the first power conductive layer PL2a and / or the second power conductive layer PL2b. For example, the third power conductive layer PL2c may be electrically connected to the first power conductive layer PL2a through a contact hole passing through the interlayer insulating layer ILD and the buffer layer BFL. The third power conductive layer PL2c may be electrically connected to the second power conductive layer PL2b through a contact hole passing through the interlayer insulating layer ILD. The third power conductive layer PL2c may overlap with the first power conductive layer PL2a and / or the second power conductive layer PL2b in the third direction (Z-axis direction). Figure 7 The first electrically conductive layer PL2a and / or the second electrically conductive layer PL2b described in, for example, together include the second power line PL2.

[0118] The third conductive layer C3 may be configured as a single layer or multiple layers formed of at least one of aluminum (Al), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and indium tin oxide (ITO) or alloys thereof.

[0119] The protective layer PSV may be disposed on the third conductive layer C3. The protective layer PSV may be configured as a single layer or multiple layers, and may include an inorganic material including silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy), aluminum nitride (AlNx), aluminum oxide (AlOx), zirconium oxide (ZrOx), hafnium oxide (HfOx), or titanium oxide (TiOx).

[0120] The via layer VIA may be arranged on the protective layer PSV. The via layer VIA may be formed of an organic material to planarize the lower step difference. For example, the via layer VIA may include an organic material such as an acrylate resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, a polyester resin, a polyphenylene sulfide resin, or a benzocyclobutene (BCB). However, the present disclosure is not limited thereto, and the via layer VIA may include an inorganic material including silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy), aluminum nitride (AlNx), aluminum oxide (AlOx), zirconium oxide (ZrOx), hafnium oxide (HfOx), or titanium oxide (TiOx).

[0121] The first dam pattern BNP1 may be arranged on the via layer VIA. According to an embodiment, the first dam pattern BNP1 may have various shapes. In an embodiment, the first dam pattern BNP1 may have a shape protruding in a third direction (Z-axis direction) on the substrate SUB. The first dam pattern BNP1 may have an inclined surface inclined at a selected angle relative to the substrate SUB. However, the present disclosure is not limited thereto, and the first dam pattern BNP1 may have a sidewall having a bent surface, a step shape, or the like. For example, the first dam pattern BNP1 may have a cross section having a semicircular shape, a semi-elliptical shape, or the like.

[0122] The electrodes and the insulating layer arranged on the first dam pattern BNP1 may have a shape corresponding to the first dam pattern BNP1. For example, the first electrode ELT1 and the second electrode ELT2 arranged on the first dam pattern BNP1 may include an inclined surface or a bent surface having a shape corresponding to the shape of the first dam pattern BNP1. Accordingly, the first dam pattern BNP1 may function as a reflective member that improves the emission efficiency of the display panel PNL by guiding light emitted from the light emitting element LD in a front direction (e.g., a third direction (Z-axis direction) of the sub-pixel PXL) together with the first electrode ELT1 and the second electrode ELT2 provided on the first dam pattern BNP1.

[0123] The first dam pattern BNP1 may include at least one organic material and / or inorganic material. For example, the first dam pattern BNP1 may include an organic material such as an acrylate resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, a polyester resin, a polyphenylene sulfide resin, or a benzocyclobutene (BCB). However, the present disclosure is not limited thereto, and the first dam pattern BNP1 may include an inorganic material including silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy), aluminum nitride (AlNx), aluminum oxide (AlOx), zirconium oxide (ZrOx), hafnium oxide (HfOx), or titanium oxide (TiOx).

[0124] The fourth conductive layer C4 may be disposed on the via layer VIA and the first dam pattern BNP1. The fourth conductive layer C4 may include a first electrode ELT1 and a second electrode ELT2. The first electrode ELT1 and the second electrode ELT2 may be disposed to be spaced apart from each other in the subpixel PXL. The first electrode ELT1 and the second electrode ELT2 may be disposed in the same layer. For example, the first electrode ELT1 and the second electrode ELT2 may be simultaneously formed in the same process, but are not limited thereto.

[0125] The first electrode ELT1 may be electrically connected to the first transistor electrode TE1 of the transistor T through a contact hole passing through the via layer VIA and the protection layer PSV. The second electrode ELT2 may be electrically connected to the third power conductive layer PL2c through a contact hole passing through the via layer VIA and the protection layer PSV.

[0126] The first electrode ELT1 and the second electrode ELT2 may receive an alignment signal in the alignment step of the light emitting element LD. Accordingly, an electric field may be formed between the first electrode ELT1 and the second electrode ELT2, and thus the light emitting element LD supplied to each of the plurality of sub-pixels PXL may be aligned between the first electrode ELT1 and the second electrode ELT2.

[0127] The fourth conductive layer C4 may include at least one conductive material. For example, the fourth conductive layer C4 may include at least one metal including silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), molybdenum (Mo) and copper (Cu) or an alloy including the metal, such as indium tin oxide (ITO), indium zinc oxide (IZO), indium tin zinc oxide (ITZO), zinc oxide (ZnO), aluminum zinc oxide (AZO), gallium zinc oxide (GZO), zinc tin oxide (ZTO) or gallium tin oxide (GTO) Conductive oxide, and at least one conductive material among conductive polymers such as PEDOT, but the embodiment is not limited thereto.

[0128] The first insulating layer INS1 may be disposed on the fourth conductive layer C4. The first insulating layer INS1 may be configured as a single layer or a multilayer, and may include an inorganic material including silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy), aluminum nitride (AlNx), aluminum oxide (AlOx), zirconium oxide (ZrOx), hafnium oxide (HfOx), or titanium oxide (TiOx).

[0129] The second dam pattern BNP2 may be disposed on the first insulating layer INS1. The second dam pattern BNP2 may form a dam structure that separates emission regions to be supplied to the light emitting element LD in the step of supplying the light emitting element LD to each of the plurality of sub-pixels PXL. For example, a desired type and / or amount of light emitting element ink may be supplied to regions separated by the second dam pattern BNP2.

[0130] The second dam pattern BNP2 may include an organic material such as acrylate resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, polyester resin, polyphenylene sulfide resin, or benzocyclobutene (BCB). However, the present disclosure is not limited thereto, and the second dam pattern BNP2 may include an inorganic material such as silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy), aluminum nitride (AlNx), aluminum oxide (AlOx), zirconium oxide (ZrOx), hafnium oxide (HfOx), or titanium oxide (TiOx).

[0131] According to an embodiment, the second dam pattern BNP2 may include at least one light blocking and / or reflective material. Accordingly, light leakage between adjacent sub-pixels PXL may be prevented. For example, the second dam pattern BNP2 may include at least one black matrix material, a color filter material, and / or the like. For example, the second dam pattern BNP2 may be formed as a black opaque pattern capable of blocking transmission of light. In an embodiment, a reflective layer or the like, not shown, may be formed on a surface (e.g., a sidewall) of the second dam pattern BNP2 to increase the light efficiency of each sub-pixel PXL.

[0132] The light emitting element LD may be arranged on the first insulating layer INS1. The light emitting element LD may be arranged between the first electrode ELT1 and the second electrode ELT2 on the first insulating layer INS1. The light emitting element LD may be dispersed in the light emitting element ink and may be supplied to each sub-pixel PXL by an inkjet printing method or a similar method. For example, the light emitting element LD may be dispersed in a volatile solvent and provided to each of the plurality of sub-pixels PXL. Subsequently, when an alignment signal is supplied to the first electrode ELT1 and the second electrode ELT2, an electric field may be formed between the first electrode ELT1 and the second electrode ELT2, and thus the light emitting element LD may be aligned between the first electrode ELT1 and the second electrode ELT2. After the light emitting element LD is aligned, the solvent may be evaporated or removed by other methods to stably arrange the light emitting element LD between the first electrode ELT1 and the second electrode ELT2.

[0133] The second insulating layer INS2 may be disposed on the first insulating layer INS1 and the light emitting element LD. For example, the second insulating layer INS2 may be partially provided on the first insulating layer INS1 and the light emitting element LD, and may expose the first end EP1 and the second end EP2 of the light emitting element LD. When the second insulating layer INS2 is formed on the light emitting element LD after the alignment of the light emitting element LD is completed, the light emitting element LD may be prevented from being separated from the aligned position. By forming the second insulating layer INS2 on the light emitting element LD, the first connection electrode CNE1 and the second connection electrode CNE2 to be described later may be stably separated.

[0134] The second insulating layer INS2 may include an inorganic material including silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy), aluminum nitride (AlNx), aluminum oxide (AlOx), zirconium oxide (ZrOx), hafnium oxide (HfOx), or titanium oxide (TiOx).

[0135] The first connection electrode CNE1 and the second connection electrode CNE2 may be respectively arranged on the first end EP1 and the second end EP2 of the light emitting element LD exposed by the second insulating layer INS2. The first connection electrode CNE1 may be directly arranged on the first end EP1 of the light emitting element LD and may be in electrical contact with the first end EP1 of the light emitting element LD. The second connection electrode CNE2 may be directly arranged on the second end EP2 of the light emitting element LD and may be in electrical contact with the second end EP2 of the light emitting element LD. The first connection electrode CNE1 may be electrically connected to the first electrode ELT1 through a contact hole passing through the second insulating layer INS2 and the first insulating layer INS1. The second connection electrode CNE2 may be electrically connected to the second electrode ELT2 through a contact hole passing through the second insulating layer INS2 and the first insulating layer INS1.

[0136] Reference Figure 8 , the first connection electrode CNE1 and the second connection electrode CNE2 may be arranged in the same layer. For example, the fifth conductive layer C5 may include the first connection electrode CNE1 and the second connection electrode CNE2. The first connection electrode CNE1 and the second connection electrode CNE2 may be simultaneously formed in the same process, but are not limited thereto.

[0137] Reference Fig. 9 , the first connection electrode CNE1 and the second connection electrode CNE2 may be arranged at different layers. For example, the fifth conductive layer C5 may include the first connection electrode CNE1, and the sixth conductive layer C6 may include the second connection electrode CNE2. The third insulating layer INS3 may also be arranged between the fifth conductive layer C5 and the sixth conductive layer C6. The third insulating layer INS3 may cover the first connection electrode CNE1 forming the fifth conductive layer C5 and expose the second end EP2 of the light emitting element LD. The second connection electrode CNE2 forming the sixth conductive layer C6 may be arranged on the second end EP2 of the light emitting element LD exposed by the third insulating layer INS3. When the third insulating layer INS3 is arranged between the first connection electrode CNE1 and the second connection electrode CNE2 forming different conductive layers, the first connection electrode CNE1 and the second connection electrode CNE2 may be stably separated by the third insulating layer INS3. Therefore, the electrical stability between the first end EP1 and the second end EP2 of the light emitting element LD may be improved.

[0138] The fifth conductive layer C5 and / or the sixth conductive layer C6 may be formed of a transparent conductive material. For example, the fifth conductive layer C5 and / or the sixth conductive layer C6 may include at least one transparent conductive material such as indium tin oxide (ITO), indium zinc oxide (IZO), indium tin zinc oxide (ITZO), aluminum zinc oxide (AZO), gallium zinc oxide (GZO), zinc tin oxide (ZTO), and gallium tin oxide (GTO). The fifth conductive layer C5 and the sixth conductive layer C6 may be substantially transparent or translucent and may satisfy a selected light transmittance. Accordingly, light emitted from the first end EP1 and the second end EP2 of the light emitting element LD may pass through the first connection electrode CNE1 and the second connection electrode CNE2 and may be emitted to the outside of the display panel PNL.

[0139] The third insulating layer INS3 may be configured as a single layer or a multilayer, and may include an inorganic material including silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy), aluminum nitride (AlNx), aluminum oxide (AlOx), zirconium oxide (ZrOx), hafnium oxide (HfOx), or titanium oxide (TiOx).

[0140] Fig.10 and Fig.11 is a schematic cross-sectional view showing first to third sub-pixels according to an embodiment. Fig.10 and Fig.11 shows the reference provided Figure 8 and Fig. 9 The dam BNK, the color conversion layer CCL and / or the color filter layer CFL on the light emitting element layer EL of the sub-pixel PXL described in the foregoing.

[0141] Reference Fig.10 and Fig.11 , the dam BNK may be disposed on the light emitting element layer EL of the first subpixel PXL1, the second subpixel PXL2, and the third subpixel PXL3. For example, the dam BNK may be disposed between the first subpixel PXL1, the second subpixel PXL2, and the third subpixel PXL3, and may include an opening overlapping each of the first subpixel PXL1, the second subpixel PXL2, and the third subpixel PXL3. The opening of the dam BNK may overlap the first subpixel PXL1, the second subpixel PXL2, and the third subpixel PXL3 in a plan view. The opening of the dam BNK may provide a space in which the color conversion layer CCL may be provided.

[0142] The dam BNK may include an organic material such as an acrylate resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, a polyester resin, a polyphenylene sulfide resin, or a benzocyclobutene (BCB). However, the present disclosure is not limited thereto, and the dam BNK may include an inorganic material including silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy), aluminum nitride (AlNx), aluminum oxide (AlOx), zirconium oxide (ZrOx), hafnium oxide (HfOx), or titanium oxide (TiOx).

[0143] According to an embodiment, the dam BNK may include at least one light blocking and / or reflective material. Accordingly, light leakage between adjacent sub-pixels PXL may be prevented. For example, the dam BNK may include at least one black matrix material, a color filter material, and / or the like. For example, the dam BNK may be formed of a black opaque pattern capable of blocking light. In an embodiment, a reflective film or the like, not shown, may be formed on a surface (e.g., a sidewall) of the dam BNK to increase the light efficiency of each sub-pixel PXL.

[0144] The color conversion layer CCL may be disposed on the light emitting element layer EL including the light emitting element LD in the opening of the dam BNK.

[0145] The color conversion layer CCL may include a first color conversion layer CCL1 disposed in the first subpixel PXL1 , a second color conversion layer CCL2 disposed in the second subpixel PXL2 , and a scattering layer LSL disposed in the third subpixel PXL3 .

[0146] In an embodiment, the first subpixel PXL1, the second subpixel PXL2, and the third subpixel PXL3 may include a light emitting element LD emitting light of the same color. For example, the first subpixel PXL1, the second subpixel PXL2, and the third subpixel PXL3 may include a light emitting element LD emitting light of a third color (e.g., blue light). A color conversion layer CCL including color conversion particles may be disposed on each of the first subpixel PXL1, the second subpixel PXL2, and the third subpixel PXL3 to display a full-color image.

[0147] The first color conversion layer CCL1 may include first color conversion particles that convert the third color light emitted from the light emitting element LD into the first color light. For example, the first color conversion layer CCL1 may include first quantum dots QD1 dispersed in a selected matrix material such as a base resin.

[0148] In an embodiment, when the light emitting element LD is a blue light emitting element emitting blue light and the first sub-pixel PXL1 is a red pixel, the first color conversion layer CCL1 may include a first quantum dot QD1 that converts blue light emitted from the blue light emitting element into red light. The first quantum dot QD1 may absorb blue light and shift the wavelength according to energy transition to emit red light. In the case where the first sub-pixel PXL1 is a pixel of a different color, the first color conversion layer CCL1 may include a first quantum dot QD1 that converts light emitted from the light emitting element LD into light corresponding to the color of the first sub-pixel PXL1.

[0149] The second color conversion layer CCL2 may include second color conversion particles that convert the third color light emitted from the light emitting element LD into the second color light. For example, the second color conversion layer CCL2 may include second quantum dots QD2 dispersed in a selected matrix material such as a base resin.

[0150] In an embodiment, when the light emitting element LD is a blue light emitting element emitting blue light and the second sub-pixel PXL2 is a green pixel, the second color conversion layer CCL2 may include a second quantum dot QD2 that converts the blue light emitted from the blue light emitting element into green light. The second quantum dot QD2 may absorb the blue light and shift the wavelength according to energy transition to emit green light. In the case where the second sub-pixel PXL2 is a pixel of a different color, the second color conversion layer CCL2 may include a second quantum dot QD2 that converts the light emitted from the light emitting element LD into light corresponding to the color of the second sub-pixel PXL2.

[0151] In an embodiment, the absorption coefficient of the first quantum dot QD1 and the second quantum dot QD2 may be increased by using blue light having a relatively short wavelength in the visible light region for each of the first quantum dot QD1 and the second quantum dot QD2. Accordingly, the final efficiency of the light emitted from the first sub-pixel PXL1 and the second sub-pixel PXL2 may be improved, and the color reproducibility may be improved. In the case where the light emitting units LSU of the first sub-pixel PXL1, the second sub-pixel PXL2, and the third sub-pixel PXL3 use the light emitting elements LD of the same color (e.g., blue light emitting elements), the manufacturing efficiency of the display device may also be increased.

[0152] The scattering layer LSL may be provided to effectively use the light of the third color (or blue) emitted from the light emitting element LD. For example, when the light emitting element LD is a blue light emitting element emitting blue light and the third subpixel PXL3 is a blue pixel, the scattering layer LSL may include at least one type of scatterer SCT to effectively use the light emitted from the light emitting element LD.

[0153] For example, the scattering layer LSL may include a scatterer SCT dispersed in a selected matrix material such as a base resin. For example, the scattering layer LSL may include a scatterer SCT such as silica, but the material of the scatterer SCT is not limited thereto. The scatterer SCT may be arranged not only in the third subpixel PXL3 but may also be selectively included in the first color conversion layer CCL1 or the second color conversion layer CCL2. According to an embodiment, the scatterer SCT may be omitted to provide a scattering layer LSL formed of a transparent polymer.

[0154] The first cover layer CP1 may be disposed on the color conversion layer CCL. The first cover layer CP1 may be provided throughout the first subpixel PXL1, the second subpixel PXL2, and the third subpixel PXL3. The first cover layer CP1 may cover the color conversion layer CCL. The first cover layer CP1 may prevent impurities such as moisture or air from penetrating from the outside and damaging or contaminating the color conversion layer CCL.

[0155] The first covering layer CP1 may be an inorganic layer, and may include silicon nitride (SiNx), aluminum nitride (AlNx), titanium nitride (TiNx), silicon oxide (SiOx), aluminum oxide (AlOx), titanium oxide (TiOx), silicon oxycarbide (SiOxCy), silicon oxynitride (SiOxNy), or the like.

[0156] The optical layer OPL may be disposed on the first cover layer CP1. The optical layer OPL may be provided throughout the first sub-pixel PXL1, the second sub-pixel PXL2, and the third sub-pixel PXL3.

[0157] The optical layer OPL may be used to improve light extraction efficiency by recycling light provided from the color conversion layer CCL through total reflection. The optical layer OPL may have a relatively low refractive index compared to the color conversion layer CCL to recycle light. For example, the refractive index of the color conversion layer CCL may be about 1.6 to about 2.0, and the refractive index of the optical layer OPL may be about 1.1 to about 1.3, but the embodiment is not limited thereto.

[0158] According to an embodiment, the optical layer OPL may include a base resin and hollow particles dispersed in the base resin. The hollow particles may include hollow silica particles. In other examples, the hollow particles may be pores formed by a porogen, but the embodiment is not limited thereto. The optical layer OPL may include at least one of zinc oxide (ZnO) particles, titanium dioxide (TiO2) particles, and nanosilicate particles, but the embodiment is not limited thereto.

[0159] The second cover layer CP2 may be disposed on the optical layer OPL. The second cover layer CP2 may be provided throughout the first subpixel PXL1, the second subpixel PXL2, and the third subpixel PXL3. The second cover layer CP2 may cover the optical layer OPL. The second cover layer CP2 may prevent impurities such as moisture or air from penetrating from the outside and damaging or contaminating the optical layer OPL.

[0160] The second covering layer CP2 may be an inorganic layer, and may include silicon nitride (SiNx), aluminum nitride (AlNx), titanium nitride (TiNx), silicon oxide (SiOx), aluminum oxide (AlOx), titanium oxide (TiOx), silicon oxycarbide (SiOxCy), silicon oxynitride (SiOxNy), or the like.

[0161] The organic layer OL may be disposed on the second cover layer CP2. The organic layer OL may be provided throughout the first sub-pixel PXL1, the second sub-pixel PXL2, and the third sub-pixel PXL3.

[0162] The organic layer OL may include an organic material such as acrylate resin, epoxy resin, phenol resin, polyamide resin, polyimide resin, polyester resin, polyphenylene sulfide resin, or benzocyclobutene (BCB).

[0163] At least one of the optical layer OPL and the organic layer OL may include a recessed pattern RP formed in the recessed portion RA. As described above, when the recessed pattern RP is formed in the optical layer OPL and / or the organic layer OL, since the contraction stress in a process in which the optical layer OPL and / or the organic layer OL are deformed can be dispersed, the reliability of the display panel PNL can be improved by minimizing the warpage as described above.

[0164] In an embodiment, if Fig.10 As shown in , the optical layer OPL and the organic layer OL may include a recessed pattern RP formed in the recessed portion RA. The recessed pattern RP may be formed by partially removing the optical layer OPL and the organic layer OL from the recessed portion RA. For example, the depth of the recessed pattern RP in the third direction (Z-axis direction) may be formed to be 25% to 55% of the thickness of the optical layer OPL and the organic layer OL in the third direction (Z-axis direction), but the embodiment is not limited thereto.

[0165] In other embodiments, Fig.11As shown in FIG, only the organic layer OL may include a recessed pattern RP formed in the recessed portion RA. The recessed pattern RP may be formed by partially removing the organic layer OL from the recessed portion RA. For example, the depth of the recessed pattern RP in the third direction (Z-axis direction) may be formed to be 25% to 55% of the thickness of the organic layer OL in the third direction (Z-axis direction), but the embodiment is not limited thereto. The depth of the recessed pattern RP in the third direction (Z-axis direction) may be changed within a range capable of dispersing the contraction stress of the optical layer OPL or the organic layer OL.

[0166] The third cover layer CP3 may be disposed in the recessed pattern RP. The third cover layer CP3 may be disposed between the first sub-pixel PXL1, the second sub-pixel PXL2, and the third sub-pixel PXL3. For example, in a plan view, the third cover layer CP3 may not overlap with the first sub-pixel PXL1, the second sub-pixel PXL2, and the third sub-pixel PXL3, but the embodiment is not limited thereto.

[0167] The third cover layer CP3 may be an inorganic layer, and may include silicon nitride (SiNx), aluminum nitride (AlNx), titanium nitride (TiNx), silicon oxide (SiOx), aluminum oxide (AlOx), titanium oxide (TiOx), silicon oxycarbide (SiOxCy), silicon oxynitride (SiOxNy), or the like. According to an embodiment, the third cover layer CP3 may be omitted.

[0168] The color filter layer CFL may be disposed on the organic layer OL. The color filter layer CFL may include a color filter (e.g., a first color filter CF1, a second color filter CF2, and a third color filter CF3) that matches the color of each sub-pixel PXL. As the color filter (e.g., a first color filter CF1, a second color filter CF2, and a third color filter CF3) that matches the color of each of the first sub-pixel PXL1, the second sub-pixel PXL2, and the third sub-pixel PXL3 is disposed, a full-color image may be displayed.

[0169] The color filter layer CFL may include a first color filter CF1 arranged in the first subpixel PXL1 to selectively transmit light emitted from the first subpixel PXL1, a second color filter CF2 arranged in the second subpixel PXL2 to selectively transmit light emitted from the second subpixel PXL2, and a third color filter CF3 arranged in the third subpixel PXL3 to selectively transmit light emitted from the third subpixel PXL3.

[0170] In an embodiment, the first color filter CF1, the second color filter CF2, and the third color filter CF3 may be a red color filter, a green color filter, and a blue color filter, respectively, but are not limited thereto. Hereinafter, two or more of the first color filter CF1, the second color filter CF2, and the third color filter CF3 may be collectively referred to as a "color filter CF", and any one of these color filters may be individually referred to as a "color filter CF".

[0171] The first color filter CF1 may overlap the light emitting element layer EL (or light emitting element LD) of the first sub-pixel PXL1 and the first color conversion layer CCL1 in the third direction (Z-axis direction). The first color filter CF1 may include a color filter material that selectively transmits light of the first color (or red). For example, when the first sub-pixel PXL1 is a red pixel, the first color filter CF1 may include a red color filter material.

[0172] The second color filter CF2 may overlap the light emitting element layer EL (or light emitting element LD) of the second sub-pixel PXL2 and the second color conversion layer CCL2 in the third direction (Z-axis direction). The second color filter CF2 may include a color filter material that selectively transmits light of the second color (or green). For example, when the second sub-pixel PXL2 is a green pixel, the second color filter CF2 may include a green color filter material.

[0173] The third color filter CF3 may overlap the light emitting element layer EL (or light emitting element LD) and the scattering layer LSL of the third sub-pixel PXL3 in the third direction (Z-axis direction). The third color filter CF3 may include a color filter material that selectively transmits light of a third color (or blue). For example, when the third sub-pixel PXL3 is a blue pixel, the third color filter CF3 may include a blue color filter material.

[0174] According to an embodiment, the light blocking layer BM may also be arranged among the first color filter CF1, the second color filter CF2, and the third color filter CF3. As described above, the light blocking layer BM is formed among the first color filter CF1, the second color filter CF2, and the third color filter CF3, and thus, a color mixing defect visually recognized from the front or side of the display device can be prevented. The material of the light blocking layer BM is not particularly limited, and may be formed of other light blocking materials. For example, the light blocking layer BM may be implemented by stacking the first color filter CF1, the second color filter CF2, and the third color filter CF3 on each other.

[0175] The overcoat layer OC may be disposed on the color filter layer CFL. The overcoat layer OC may be provided throughout the first subpixel PXL1, the second subpixel PXL2, and the third subpixel PXL3. The overcoat layer OC may cover the lower member including the color filter layer CFL. The overcoat layer OC may prevent moisture or air from penetrating into the lower member. The overcoat layer OC may protect the lower member from foreign matter such as dust.

[0176] The outer coating OC may include an organic material such as an acrylate resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, a polyester resin, a polyphenylene sulfide resin, or a benzocyclobutene (BCB). However, the present disclosure is not limited thereto, and the outer coating OC may include an inorganic material including silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy), aluminum nitride (AlNx), aluminum oxide (AlOx), zirconium oxide (ZrOx), hafnium oxide (HfOx), or titanium oxide (TiOx).

[0177] According to an embodiment, the concave pattern RP formed in the optical layer OPL and / or the organic layer OL can disperse the contraction stress that may occur during deformation of the optical layer OPL and / or the organic layer OL. Therefore, the reliability of the display panel PNL can be improved by minimizing the warping phenomenon.

[0178] In the following embodiments, the same elements as those described above are denoted by the same reference numerals, and repeated descriptions may be omitted or simplified.

[0179] Fig.12 is a schematic cross-sectional view showing first to third sub-pixels according to an embodiment.

[0180] Reference Fig.12 , this implementation is similar to Figures 1 to 11 The embodiment of FIG. 4 is different from that of FIG. 4 in that the color conversion layer CCL, the optical layer OPL and / or the organic layer OL are arranged in the opening of the dam BNK.

[0181] For example, the dam BNK may be disposed between the first subpixel PXL1, the second subpixel PXL2, and the third subpixel PXL3, and may include an opening overlapping each of the first subpixel PXL1, the second subpixel PXL2, and the third subpixel PXL3. The color conversion layer CCL, the optical layer OPL, and / or the organic layer OL may be disposed in the opening of the dam BNK. The dam BNK may separate the color conversion layer CCL, the optical layer OPL, and / or the organic layer OL of each of the first subpixel PXL1, the second subpixel PXL2, and the third subpixel PXL3.

[0182] In a plan view, the dam BNK may separate a portion of the optical layer OPL overlapping the first subpixel PXL1 from a portion of the optical layer OPL overlapping the second subpixel PXL2. Similarly, the dam BNK may separate portions of the organic layer OL overlapping the first subpixel PXL1 and the second subpixel PXL2. The dam BNK may separate portions of the optical layer OPL and the organic layer OL overlapping the second subpixel PXL2 and the third subpixel PXL3 from each other.

[0183] The color conversion layer CCL may be arranged on the light emitting element layer EL including the light emitting element LD in the opening of the dam BNK. The optical layer OPL may be arranged on the color conversion layer CCL in the opening of the dam BNK. The organic layer OL may be arranged on the optical layer OPL in the opening of the dam BNK. As described above, when the optical layer OPL and / or the organic layer OL of each of the plurality of sub-pixels PXL are arranged in the opening of the dam BNK and separated from each other, the contraction stress generated in the process of repeatedly stacking and curing the optical layer OPL and the organic layer OL may be dispersed. Therefore, the reliability of the display panel PNL may be improved by minimizing the warping phenomenon.

[0184] In an embodiment, Figure 3 The height of the dam BNK in the third direction (Z-axis direction) of the first area A1 may be different from Figure 3 The height of the dam BNK in the third direction (Z-axis direction) of the second area A2 may be less than the height of the dam BNK in the third direction (Z-axis direction) of the dam BNK of the first area A1. For example, the height of the dam BNK in the third direction (Z-axis direction) of the dam BNK of the first area A1 may be less than the height of the dam BNK in the third direction (Z-axis direction) of the dam BNK of the second area A2. As described above, when the dam BNK is high in the second area A2 corresponding to the outer portion, the contraction stress of the second area A2 may be dispersed. Therefore, the warping phenomenon may be minimized. However, the present disclosure is not limited thereto, and the height of the dam BNK in the third direction (Z-axis direction) of the dam BNK of the first area A1 may be formed to be substantially the same as the height of the dam BNK in the third direction (Z-axis direction) of the dam BNK of the second area A2.

[0185] The first cover layer CP1 may be disposed between the color conversion layer CCL and the optical layer OPL. The second cover layer CP2 may be disposed between the optical layer OPL and the organic layer OL. The first cover layer CP1 and / or the second cover layer CP2 may be provided throughout the first subpixel PXL1, the second subpixel PXL2, and the third subpixel PXL3.

[0186] Due to the reference Fig.10 and Fig.11 The bank BNK, the color conversion layer CCL, the optical layer OPL, the organic layer OL, the first cover layer CP1, and the second cover layer CP2 are described in detail, and thus their descriptions will not be repeated.

[0187] Subsequently, a method of manufacturing a display device according to an embodiment is described.

[0188] Figures 13 to 16 2 is a schematic cross-sectional view illustrating process steps of a method of manufacturing a display device according to an embodiment. Figures 13 to 16 It shows the manufacturing Fig.10 A schematic cross-sectional view of a method of displaying a device and a Fig.10 Substantially the same components are denoted by the same reference numerals and the detailed reference numerals are omitted.

[0189] Reference Fig.13 First, a dam BNK is formed, and a color conversion layer CCL is formed between the dams BNK. The dam BNK may be formed on the light emitting element layer EL of the sub-pixel PXL.

[0190] The dam BNK may be formed between the first subpixel PXL1, the second subpixel PXL2, and the third subpixel PXL3, and may include an opening overlapping each of the first subpixel PXL1, the second subpixel PXL2, and the third subpixel PXL3. The color conversion layer CCL may be formed in the opening of the dam BNK. The first color conversion layer CCL1 may be formed in the opening of the dam BNK of the first subpixel PXL1. The second color conversion layer CCL2 may be formed in the opening of the dam BNK of the second subpixel PXL2. The scattering layer LSL may be formed in the opening of the dam BNK of the third subpixel PXL3.

[0191] Reference Fig.14 , then, a first cover layer CP1, an optical layer OPL, a second cover layer CP2 and / or an organic layer OL are formed. The first cover layer CP1, the optical layer OPL, the second cover layer CP2 and / or the organic layer OL may be sequentially formed on the dam BNK and the color conversion layer CCL. The first cover layer CP1, the optical layer OPL, the second cover layer CP2 and / or the organic layer OL may be formed throughout the first sub-pixel PXL1, the second sub-pixel PXL2 and the third sub-pixel PXL3.

[0192] Reference Fig.15 , and then, a recessed pattern RP is formed in the recessed portion RA. The recessed portion RA may be located at the boundary of the first subpixel PXL1, the second subpixel PXL2, and the third subpixel PXL3. The recessed pattern RP may be formed by partially removing the optical layer OPL and / or the organic layer OL. The process of forming the recessed pattern RP may be performed by a general etching process such as a dry etching method, a wet etching method, a reactive ion etching (RIE) method, and an inductively coupled plasma reactive ion etching (ICP-RIE) method, but the embodiment is not limited thereto.

[0193] Reference Fig.16 , then, a third cover layer CP3 is then formed in the recessed pattern RP. The third cover layer CP3 may be provided only partially inside the recessed pattern RP. For example, the third cover layer CP3 may be formed only in the recessed portion RA between the first sub-pixel PXL1, the second sub-pixel PXL2, and the third sub-pixel PXL3.

[0194] Subsequently, a color filter layer CFL may be formed, and thus the Fig.10The color filter layer CFL may include a first color filter CF1 formed in the first subpixel PXL1, a second color filter CF2 formed in the second subpixel PXL2, and a third color filter CF3 formed in the third subpixel PXL3. The light blocking layer BM may be arranged among the first color filter CF1, the second color filter CF2, and the third color filter CF3.

[0195] According to an embodiment, as the concave pattern RP is formed in the optical layer OPL and / or the organic layer OL, the contraction stress may be dispersed when the optical layer OPL and / or the organic layer OL are deformed. Therefore, the reliability of the display panel PNL may be improved by minimizing the warping phenomenon.

[0196] Embodiments have been disclosed herein, and although terms are employed, they are used and interpreted in a general and descriptive sense only and not for purposes of limitation. In some cases, as will be apparent to one of ordinary skill in the art, features, characteristics, and / or elements described in conjunction with an embodiment may be used alone or in combination with features, characteristics, and / or elements described in conjunction with other embodiments, unless expressly indicated otherwise. Accordingly, one of ordinary skill in the art will understand that various changes in form and detail may be made without departing from the spirit and scope of the present disclosure as set forth in the appended claims.

Claims

1. A display device, characterized in that: include: a plurality of pixels, each of the plurality of pixels comprising a plurality of light emitting elements arranged in the plurality of pixels; a color conversion layer disposed on the plurality of light emitting elements of the plurality of pixels; an optical layer disposed on the color conversion layer; as well as an organic layer, the organic layer being arranged on the optical layer, Wherein, at least one of the optical layer and the organic layer includes a plurality of concave patterns arranged between the plurality of pixels.

2. The display device according to claim 1, characterized in that Also includes: a first covering layer disposed between the color conversion layer and the optical layer; as well as A second covering layer is disposed between the optical layer and the organic layer.

3. The display device according to claim 1, characterized in that Also includes: A third covering layer is disposed in the plurality of recessed patterns.

4. The display device according to claim 3, characterized in that: The third covering layer does not overlap the plurality of pixels in a plan view.

5. The display device according to claim 1, characterized in that Also includes: Central part; as well as an outer portion, said outer portion surrounding said central portion, The number of the plurality of recessed patterns arranged per unit area in the central portion is smaller than the number of the plurality of recessed patterns arranged per unit area in the outer portion.

6. The display device according to claim 1, characterized in that: Also includes: Central part; as well as an outer portion, said outer portion surrounding said central portion, wherein a depth of the plurality of recessed patterns arranged in the central portion is less than a depth of the plurality of recessed patterns arranged in the outer portion.

7. The display device according to claim 1, characterized in that: Also includes: a plurality of dams, the plurality of dams being arranged between the plurality of pixels, Wherein, the color conversion layer is arranged between the plurality of dams.

8. The display device according to claim 1, characterized in that: Also includes: A color filter layer is disposed on the organic layer.

9. The display device according to claim 1, characterized in that: The refractive index of the optical layer is 1.1 to 1.

3.

10. The display device according to claim 9, characterized in that: The optical layer includes hollow particles.

11. A display device, characterized in that: include: Multiple pixels; a dam including an opening overlapping the plurality of pixels in plan view; a plurality of light emitting elements, the plurality of light emitting elements being arranged in the plurality of pixels; a color conversion layer disposed on the plurality of light emitting elements; an optical layer disposed on the color conversion layer; as well as an organic layer, the organic layer being arranged on the optical layer, Wherein, the color conversion layer, the optical layer and the organic layer are arranged in the opening of the dam.

12. The display device according to claim 11, characterized in that: Each of the plurality of pixels includes a first sub-pixel and a second sub-pixel, and The dam is disposed between the first sub-pixel and the second sub-pixel.

13. The display device according to claim 12, characterized in that: The dam separates a portion of the optical layer overlapping the first sub-pixel in a plan view from a portion of the optical layer overlapping the second sub-pixel in a plan view.

14. The display device according to claim 12, characterized in that: The dam separates a portion of the organic layer overlapping the first sub-pixel in a plan view from a portion of the organic layer overlapping the second sub-pixel in a plan view.

15. The display device according to claim 12, characterized in that: Also includes: a first covering layer disposed between the color conversion layer and the optical layer; as well as A second covering layer is disposed between the optical layer and the organic layer.

16. The display device according to claim 15, characterized in that: The first cover layer or the second cover layer is arranged on the first sub-pixel and on the second sub-pixel.

17. The display device according to claim 11, characterized in that: Also includes: Central part; as well as an outer portion, said outer portion surrounding said central portion, Wherein, the height of the dam arranged in the central portion is smaller than the height of the dam arranged in the outer portion.

18. The display device according to claim 11, characterized in that: Also includes: a first connecting electrode, the first connecting electrode being electrically connected to first ends of the plurality of light emitting elements; as well as A second connecting electrode is electrically connected to the second ends of the plurality of light emitting elements.

19. The display device according to claim 11, characterized in that: Also includes: A color filter layer is disposed on the organic layer.

20. The display device according to claim 19, characterized in that Also includes: An overcoat layer is disposed on the color filter layer.

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