Display device

Abstract

The present disclosure relates to a display device including: a light emitting element including a porous layer; a first protective layer disposed on the light emitting element and including an opening exposing a side surface of the porous layer; and a second protective layer covering the opening of the first protective layer. The porous layer includes a color conversion member.

Description

Technical Field

[0001] The present disclosure relates to a display device. Background Art

[0002] Recently, as interest in information display increases, research and development of display devices are continuously being conducted. Utility Model Content

[0003] The present disclosure provides a display device having a simple manufacturing process and improved light extraction efficiency.

[0004] The objects of the present disclosure are not limited to the above objects, and other technical objects that are not described will be clearly understood by those skilled in the art from the following description.

[0005] According to an embodiment of the present disclosure, a display device may include: a light emitting element including a porous layer; a first protective layer disposed on the light emitting element and including an opening exposing a side surface of the porous layer; and a second protective layer covering the opening of the first protective layer. The porous layer may include a color conversion member.

[0006] The light emitting element may further include a first semiconductor layer, a second semiconductor layer, and an active layer disposed between the first semiconductor layer and the second semiconductor layer.

[0007] The porous layer and the second semiconductor layer may include the same material.

[0008] The porous layer may include nanoscale pores.

[0009] The color conversion member may be disposed in the hole.

[0010] The second protective layer may contact the porous layer exposed by the opening of the first protective layer.

[0011] The display device may further include an organic layer disposed between the light emitting elements.

[0012] The display device may further include a third protective layer disposed between the second protective layer and the organic layer.

[0013] The display device may further include an optical pattern layer disposed on the light emitting element.

[0014] The optical pattern layer may be directly disposed on the porous layer.

[0015] According to an embodiment of the present disclosure, a display device may include: a first light-emitting element, a second light-emitting element, and a third light-emitting element, each light-emitting element including a porous layer; a first protective layer disposed on the first to third light-emitting elements and including a first opening exposing a side surface of the first light-emitting element; and a second protective layer disposed on the first protective layer and including a second opening exposing a side surface of the second light-emitting element. The porous layer of the first light-emitting element may include a first color conversion member, and the porous layer of the second light-emitting element may include a second color conversion member.

[0016] The second protective layer may contact the porous layer of the first light emitting element exposed by the first opening of the first protective layer.

[0017] The display device may further include a third protective layer disposed on the second protective layer.

[0018] The third protective layer may contact the porous layer of the second light emitting element exposed by the second opening of the second protective layer.

[0019] The display device may further include an organic layer disposed between the first to third light emitting elements.

[0020] The porous layer of the third light emitting element may include a scatterer.

[0021] Each of the first to third light emitting elements may further include a first semiconductor layer, a second semiconductor layer, and an active layer disposed between the first and second semiconductor layers.

[0022] The display device may further include an optical pattern layer disposed on the first to third light emitting elements.

[0023] The second semiconductor layer may be disposed directly on the first surface of the porous layer.

[0024] The optical pattern layer may be directly disposed on the second surface of the porous layer.

[0025] Details of other implementations are included in the detailed description and accompanying drawings.

[0026] According to an embodiment of the present disclosure, a manufacturing process may be simplified by injecting a color conversion material into the porous layer through an opening of the protective layer exposing a side surface of the porous layer, and light extraction efficiency may be improved by forming an optical pattern layer on the porous layer.

[0027] The effects of the present disclosure are not limited to the above-mentioned contents, and more various effects are included in the specification. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The above and other features of the present disclosure will become more apparent by describing embodiments of the present disclosure in more detail with reference to the accompanying drawings, in which:

[0029] Figure 1 is a plan view showing a display device according to an embodiment;

[0030] Figure 2 is a schematic diagram of an equivalent circuit of a pixel according to an embodiment;

[0031] Figure 3 and Figure 4 is a schematic cross-sectional view showing a pixel according to an embodiment;

[0032] Figures 5 to 14 is a schematic cross-sectional view of each process step of a method for manufacturing a display device according to an embodiment; and

[0033] Figures 15 to 18 is a schematic cross-sectional view of each process step of a method of manufacturing a display device according to an embodiment. DETAILED DESCRIPTION

[0034] With reference to the embodiments described in detail below in conjunction with the accompanying drawings, the advantages and features of the present disclosure and the methods for achieving them will become apparent. However, the present disclosure is not limited to the embodiments disclosed below and can be implemented in various different forms. The embodiments are provided so that the present disclosure will be thorough and complete, and the technical personnel in the field to which the present disclosure belongs can fully understand the scope of the present disclosure. The present disclosure is limited only by the scope of the claims.

[0035] The use of cross-hatching and / or shading is generally provided in the drawings to clarify the boundaries between adjacent elements. Therefore, the presence or absence of cross-hatching or shading does not convey or indicate any preference or requirement for a particular material, material property, size, ratio, commonality between the elements shown, and / or any other characteristics, attributes, properties, etc. of the elements, unless otherwise specified. In addition, in the drawings, the size and relative size of the elements may be exaggerated for the purpose of clarity and / or description. When the embodiments can be implemented differently, a specific process sequence may be performed differently from the described sequence. For example, two processes described in succession may be performed substantially simultaneously, or in an order opposite to the described order.

[0036] The terms used in this specification are used to describe embodiments and are not intended to limit the present disclosure. As used herein, the singular forms "one", "a kind of" and "the" are intended to also include plural forms unless the context clearly indicates otherwise. In addition, when used in this specification, the terms "include", "include", "include" and / or "include" specify the presence of the features, integral bodies, steps, operations, elements, components and / or its groups, but do not exclude the presence or addition of one or more other features, integral bodies, steps, operations, elements, components and / or its groups. It should also be noted that, as used herein, the terms "substantially", "about" and similar terms are used as approximate terms and not as degree terms, and are therefore used to explain the inherent deviations of measured values, calculated values ​​and / or provided values ​​that will be recognized by those of ordinary skill in the art.

[0037] When an element or layer is referred to as being "on," "connected to," or "coupled to" another element or layer, it may be directly on, directly connected to, or directly coupled to the other element or layer, or there may be intervening elements or layers. However, when an element or layer is referred to as being "directly" "on," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers. For this purpose, the term "connected" may refer to a physical connection, an electrical connection, and / or a fluid connection with or without intervening elements. In addition, when an element is referred to as being "in contact with" or "contacting" another element, etc., the element may be "in electrical contact with" or "in physical contact with" the other element; or "indirectly in contact with" or "directly in contact with" the other element.

[0038] For descriptive purposes, spatially relative terms such as "below," "below," "under," "lower," "above," "upper," "above," "higher," "side" (e.g., as in "sidewall"), etc. may be used herein, and thereby describe the relationship of one element to another (or multiple) element(s) as shown in the accompanying drawings. In addition to the orientations depicted in the accompanying drawings, spatially relative terms are intended to also include different orientations of the device in use, operation, and / or manufacture. For example, if the device in the accompanying drawings is flipped, an element described as being "below" or "below" other elements or features will then be oriented as being "above" the other elements or features. Thus, the exemplary term "below" can include both the orientations of above and below. In addition, the device can be oriented in other ways (e.g., rotated 90 degrees or in other orientations), and therefore, the spatially relative descriptors used herein should be interpreted accordingly.

[0039] For the purpose of this disclosure, "at least one of A and B" may be interpreted as only A, only B, or any combination of A and B. In addition, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" may be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. Throughout the specification, the same reference numerals denote the same components.

[0040] Although first, second, etc. are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from another component. Therefore, within the technical spirit of the present disclosure, the first component described below may be the second component.

[0041] Unless otherwise defined or implied herein, all terms (including technical and scientific terms) used have the same meaning as commonly understood by those skilled in the art to which the present disclosure belongs. It will also be understood that terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology, and should not be interpreted in an idealized or overly formal sense, unless clearly defined in this specification.

[0042] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0043] Figure 1 is a plan view showing a display device according to an embodiment.

[0044] Figure 1 A display device using a light emitting element as a light source, particularly a display panel PNL included in the display device, is shown.

[0045] For ease of description, Figure 1 , the structure of the display panel PNL is schematically shown based on the display area DA, and the display panel PNL may be substantially parallel to a plane defined by a first direction (X-axis direction) and a second direction (Y-axis direction). However, according to an embodiment, at least one driving circuit unit (e.g., at least one of a scan driver and a data driver), a line and / or a pad not shown may also be provided on the display panel PNL.

[0046] refer to Figure 1, the display panel PNL may include a substrate SUB and a pixel unit PXU disposed on the substrate SUB. The pixel unit PXU may include a first pixel PXL1, a second pixel PXL2, and / or a third pixel PXL3. Hereinafter, in the case where at least one of the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3 is arbitrarily referenced, or in the case where two or more types of pixels are commonly referenced, at least one pixel or two or more types of pixels may be referred to as a "pixel PXL" or "a plurality of pixels PXL".

[0047] The substrate SUB may configure a base member of the display panel PNL, and may be a rigid or flexible substrate or film. For example, the substrate SUB may be a rigid substrate formed of glass or tempered glass, or a flexible substrate (or film) of plastic or metal, but the material and / or physical properties of the substrate SUB are not particularly limited.

[0048] The display panel PNL and the substrate SUB for forming the display panel PNL may include a display area DA for displaying an image and a non-display area NDA other than the display area DA. The pixels PXL may be disposed in the display area DA. Various lines, pads, and / or built-in circuits connected to the pixels PXL in the display area DA may be disposed in the non-display area NDA. The pixels PXL may be arranged according to stripes or However, the arrangement structure of the pixels PXL is not necessarily limited thereto, and the pixels PXL may be arranged in the display area DA in various structures and / or methods.

[0049] According to an embodiment, two or more types of pixels PXL emitting light of different colors may be arranged in the display area DA. For example, in the display area DA, a first pixel PXL1 emitting light of a first color, a second pixel PXL2 emitting light of a second color, and a third pixel PXL3 emitting light of a third color may be arranged. At least one of the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3 disposed adjacent to each other may configure a pixel unit PXU emitting light of various colors. For example, each of the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3 may be a sub-pixel emitting light of a color (predetermined or selectable color). According to an embodiment, the first pixel PXL1 may be a red pixel emitting red light, the second pixel PXL2 may be a green pixel emitting green light, and the third pixel PXL3 may be a blue pixel emitting blue light, but the present disclosure is not necessarily limited thereto.

[0050] In an embodiment, each of the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3 may include a light emitting element emitting light of the same color, and may include a color filter and / or a color conversion layer of different colors disposed on the corresponding light emitting element to emit light of the first color, the second color, and the third color, respectively. In another embodiment, the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3 may include a light emitting element of the first color, a light emitting element of the second color, and a light emitting element of the third color as light sources, respectively, to emit light of the first color, the second color, and the third color, respectively. However, the color, type, number, etc. of the pixel PXL configuring the pixel unit PXU are not particularly limited.

[0051] The pixel PXL may include at least one light source driven by a control signal (e.g., a scan signal and a data signal) and / or power (e.g., a first power and a second power). In an embodiment, the light source may include an ultra-small columnar light-emitting element having a size as small as nanometer to micrometer. However, the present disclosure is not necessarily limited thereto, and various types of light-emitting elements may be used as the light source of the pixel PXL.

[0052] In an embodiment, each pixel PXL may be configured as an active pixel. However, the type, structure and / or driving method of the pixel PXL that can be applied to the display device is not particularly limited. For example, each pixel PXL may be configured as a pixel of a passive or active light-emitting display device of various structures and / or driving methods.

[0053] Figure 2 is a schematic diagram of an equivalent circuit of a pixel according to an embodiment.

[0054] Figure 2 The electrical connection relationship between components included in the pixel PXL which may be applied to an active display device is schematically shown. However, the types of components included in the pixel PXL are not necessarily limited thereto.

[0055] According to an embodiment, Figure 2 The pixel PXL shown in FIG. 1 may be arranged in Figure 1 The first pixel PXL1, the second pixel PXL2, and the third pixel PXL3 may have structures substantially the same as or similar to each other.

[0056] refer to Figure 2 Each pixel PXL may include a light emitting unit EMU that generates light of brightness corresponding to the data signal. The pixel PXL may also include a pixel circuit PXC for driving the light emitting unit EMU.

[0057] According to an embodiment, the light emitting unit EMU may include at least one light emitting element LD connected between a first power line PL1 to which a voltage of a first power VDD is applied and a second power line PL2 to which a voltage of a second power VSS is applied. For example, the light emitting unit EMU may include a first electrode EL1 connected to the first power VDD via a pixel circuit PXC and the first power line PL1, a second electrode EL2 connected to the second power VSS via a second power line PL2, and a light emitting element LD connected between the first electrode EL1 and the second electrode EL2. In an embodiment, the first electrode EL1 may be an anode electrode, and the second electrode EL2 may be a cathode electrode.

[0058] The light emitting element LD may include one end connected to the first power VDD and the other end connected to the second power VSS. According to an embodiment, the one end of the light emitting element LD may be integrally provided with the first electrode EL1 and connected to the first electrode EL1, and the other end of the light emitting element LD may be integrally provided with the second electrode EL2 and connected to the second electrode EL2. The first power VDD and the second power VSS may have different potentials. During the emission period of the pixel PXL, the potential difference between the first power VDD and the second power VSS may be set to be greater than or equal to the threshold voltage of the light emitting element LD.

[0059] The light emitting element LD may configure an effective light source of the light emitting unit EMU. The light emitting element LD may emit light having a brightness corresponding to a driving current provided by the pixel circuit PXC. For example, during each frame period, the pixel circuit PXC may provide a driving current corresponding to a grayscale value of corresponding frame data to the light emitting unit EMU. The driving current provided to the light emitting unit EMU may flow through the light emitting element LD. Therefore, the light emitting unit EMU may emit light while the light emitting element LD emits light having a brightness corresponding to the driving current.

[0060] The pixel circuit PXC may be connected to the scan line Si and the data line Dj of the pixel PXL. For example, in the case where the pixel PXL is disposed in the i-th (i is a positive integer) row and the j-th (j is a positive integer) column of the display area DA, the pixel circuit PXC of the pixel PXL may be connected to the i-th scan line Si and the j-th data line Dj of the display area DA. According to an embodiment, the pixel circuit PXC may include a first transistor T1 and a second transistor T2 and a storage capacitor Cst. However, the structure of the pixel circuit PXC is not limited to Figure 2 The embodiment shown in .

[0061] The pixel circuit PXC may include first and second transistors T1 and T2 and a storage capacitor Cst.

[0062] A first terminal of the first transistor (or driving transistor) T1 may be connected to a first power VDD, and a second terminal of the first transistor (or driving transistor) T1 may be electrically connected to the light emitting element LD. A gate electrode of the first transistor T1 may be connected to a first node N1. The first transistor T1 may control the amount of driving current provided to the light emitting element LD in response to a voltage of the first node N1.

[0063] A first terminal of the second transistor (or switch transistor) T2 may be connected to the j-th data line Dj, and a second terminal of the second transistor (or switch transistor) T2 may be connected to the first node N1. The first terminal and the second terminal of the second transistor T2 may be different terminals. For example, when the first terminal is a source electrode, the second terminal may be a drain electrode. The gate electrode of the second transistor T2 may be connected to the i-th scan line Si.

[0064] In the case where a scan signal of a voltage at which the second transistor T2 can be turned on is provided from the i-th scan line Si, the second transistor T2 can be turned on to electrically connect the j-th data line Dj and the first node N1. A data signal of a corresponding frame can be provided to the j-th data line Dj, and thus the data signal can be transmitted to the first node N1. The data signal transmitted to the first node N1 can be stored in the storage capacitor Cst.

[0065] The storage capacitor Cst may charge a voltage corresponding to the data signal supplied to the first node N1 and maintain the charged voltage until a data signal of a next frame is supplied.

[0066] Figure 2 The pixel circuit PXC is shown to include a second transistor T2 for transmitting a data signal to the pixel PXL, a storage capacitor Cst for storing the data signal, and a first transistor T1 for providing a driving current corresponding to the data signal to the light emitting element LD, but the present disclosure is not necessarily limited thereto, and the structure of the pixel circuit PXC can be variously modified and implemented. For example, the pixel circuit PXC may also include other circuit elements such as at least one transistor element (such as a transistor element for compensating for the threshold voltage of the first transistor T1, a transistor element for initializing the first node N1, a transistor element for controlling the emission time of the light emitting element LD) and / or a boost capacitor for increasing the voltage of the first node N1. The first transistor T1 and the second transistor T2 of the pixel circuit PXC are not limited to Figure 2 The transistor shown in , and can be variously changed to NMOS or PMOS.

[0067] Figure 3 and Figure 4 is a schematic cross-sectional view showing a pixel according to an embodiment.

[0068] Figure 3 and Figure 4 The cross-sectional structures of the first pixel PXL1 , the second pixel PXL2 , and the third pixel PXL3 adjacent to each other are schematically shown.

[0069] refer to Figure 3 and Figure 4 , a pixel PXL according to an embodiment and a display device including the pixel PXL may include a substrate SUB, a light emitting element LD disposed on the substrate SUB, and an optical pattern layer OPL disposed on the light emitting element LD.

[0070] The substrate SUB may be a driving substrate including circuit elements, etc., including a circuit element configuring each pixel PXL. Figure 2 transistor of the pixel circuit PXC.

[0071] The light emitting element LD may include a first semiconductor layer 11 , an active layer 12 , a second semiconductor layer 13 , and a porous layer 14 .

[0072] The first semiconductor layer 11 , the active layer 12 , the second semiconductor layer 13 , and the porous layer 14 may be sequentially stacked on the substrate SUB in the third direction (Z-axis direction).

[0073] The first semiconductor layer 11 may include at least one p-type semiconductor layer. For example, the first semiconductor layer 11 may include a semiconductor material such as GaN, InGaN, InAlGaN, AlGaN, AlN, AlGaAs, GaAsP, AlGaInP, or GaP, and may include a p-type semiconductor layer doped with a first conductive dopant (or p-type dopant) such as Mg, Zn, Ca, Sr, or Ba. For example, the first semiconductor layer 11 may include a GaN semiconductor material doped with a first conductive dopant (or p-type dopant), but is not necessarily limited thereto, and various other materials may configure the first semiconductor layer 11.

[0074] The first semiconductor layer 11 may be electrically connected to a region of the substrate SUB. For example, the first electrode EL1 may be disposed on the first semiconductor layer 11, and the first semiconductor layer 11 may be electrically connected to the substrate SUB through the first electrode EL1. According to an embodiment, a first connection layer may also be disposed between the first electrode EL1 and the substrate SUB. When the first electrode EL1 and the substrate SUB are bonded through the first connection layer, the first semiconductor layer 11 and the substrate SUB may be coupled. The first connection layer may include a metal or a metal oxide. For example, the first connection layer may include copper (Cu), gold (Au), chromium (Cr), titanium (Ti), aluminum (Al), nickel (Ni), oxides thereof, alloys, indium tin oxide (ITO), etc., but is not necessarily limited thereto.

[0075] The active layer 12 may be disposed between the first semiconductor layer 11 and the second semiconductor layer 13. The active layer 12 may include one of a single well structure, a multi-well structure, a single quantum well structure, a multi-quantum well (MQW) structure, a quantum dot structure, and a quantum wire structure, but is not necessarily limited thereto. The active layer 12 may include GaN, InGaN, InAlGaN, AlGaN, AlN, AlGaAs, GaAsP, AlGaInP, or GaP, and various other materials may configure the active layer 12.

[0076] When a signal (or voltage) is applied to each end of the light emitting element LD, the light emitting element LD can emit light when electron-hole pairs are coupled in the active layer 12 of the light emitting element LD. By controlling the emission of each light emitting element LD using this principle, the light emitting element LD can be used as a light source of various light emitting devices including the pixel PXL of the display device.

[0077] According to an embodiment, an electron blocking layer may be further provided between the active layer 12 and the first semiconductor layer 11. The electron blocking layer may block the flow of electrons provided from the second semiconductor layer 13 to the first semiconductor layer 11, thereby increasing the electron-hole recombination probability in the active layer 12. The energy band gap of the electron blocking layer may be greater than the energy band gap of the active layer 12 and / or the first semiconductor layer 11, but is not necessarily limited thereto.

[0078] According to an embodiment, a superlattice layer (SL) may be further provided between the active layer 12 and the second semiconductor layer 13. The superlattice layer may relieve stress of the active layer 12 and the second semiconductor layer 13 to improve the quality of the light emitting element LD. The superlattice layer may be formed in a structure in which InGaN and GaN are alternately stacked with each other, but is not necessarily limited thereto.

[0079] The second semiconductor layer 13 may be disposed on the active layer 12, and may include a semiconductor layer of a different type from the semiconductor layer type of the first semiconductor layer 11. In an embodiment, the second semiconductor layer 13 may include at least one n-type semiconductor layer. For example, the second semiconductor layer 13 may include a semiconductor material such as GaN, InGaN, InAlGaN, AlGaN, AlN, AlGaAs, GaAsP, AlGaInP or GaP, and may be an n-type semiconductor layer doped with a second conductive dopant (or n-type dopant) such as Si, Ge or Sn. For example, the second semiconductor layer 13 may include a GaN semiconductor material doped with a second conductive dopant (or n-type dopant). However, the material configuring the second semiconductor layer 13 is not limited thereto, and various other materials may configure the second semiconductor layer 13.

[0080] The second semiconductor layer 13 may be electrically connected to another region of the substrate SUB. For example, the second electrode EL2 may be disposed on the second semiconductor layer 13, and the second semiconductor layer 13 may be electrically connected to the substrate SUB through the second electrode EL2. According to an embodiment, a second connection layer may also be disposed between the second electrode EL2 and the substrate SUB. When the second electrode EL2 and the substrate SUB are bonded through the second connection layer, the second semiconductor layer 13 and the substrate SUB may be coupled. The second connection layer may include a metal or a metal oxide. For example, the second connection layer may include copper (Cu), gold (Au), chromium (Cr), titanium (Ti), aluminum (Al), nickel (Ni), oxides thereof, alloys, indium tin oxide (ITO), etc., but is not necessarily limited thereto.

[0081] The porous layer 14 may be disposed on the second semiconductor layer 13. For example, the porous layer 14 may be disposed (e.g., directly disposed) on the second semiconductor layer 13. The porous layer 14 and the second semiconductor layer 13 may include the same material, but are not necessarily limited thereto. For example, the porous layer 14 may include at least one n-type semiconductor layer. For example, the porous layer 14 may include a semiconductor material such as GaN, InGaN, InAlGaN, AlGaN, or AlN, and may be an n-type semiconductor layer doped with a second conductive dopant (or n-type dopant) such as Si, Ge, or Sn. For example, the porous layer 14 may include a GaN semiconductor material doped with a second conductive dopant (or n-type dopant). However, the material configuring the porous layer 14 is not limited thereto, and various other materials may configure the porous layer 14.

[0082] The porous layer 14 may include a plurality of pores NP. The pores NP of the porous layer 14 may be nanoscale (or may have a nanometer size) pores NP formed by electrochemical etching, but are not necessarily limited thereto.

[0083] The porous layer 14 can improve the light emission efficiency by scattering the light emitted from the active layer 12. For example, the porous layer 14 can be used as a scattering layer. As described above, in the case where the porous layer 14 is included in the light emitting element LD, the scattering layer separately provided in the pixel PXL can be omitted, thereby simplifying the manufacturing process and reducing costs.

[0084] The pores NP of the porous layer 14 may include color conversion materials (or color conversion members) CC1 and CC2 and / or scatterers LS. Figure 3 , the porous layer 14 of the light emitting element LD of the first pixel PXL1 may include the first color conversion material CC1, and the porous layer 14 of the light emitting element LD of the second pixel PXL2 may include the second color conversion material CC2.

[0085] The first color conversion material CC1 may be disposed in the pores NP of the porous layer 14 of the light emitting element LD of the first pixel PXL1. In the case where the first pixel PXL1 is a red pixel, the first color conversion material CC1 may include a first quantum dot that converts blue light into red light. The first quantum dot may absorb blue light and emit red light by shifting the wavelength according to energy transition. In the case where the first pixel PXL1 is a pixel of another color, the first color conversion material CC1 may include a first quantum dot corresponding to the color of the first pixel PXL1.

[0086] The second color conversion material CC2 may be disposed in the hole NP of the porous layer 14 of the light emitting element LD of the second pixel PXL2. In the case where the second pixel PXL2 is a green pixel, the second color conversion material CC2 may include a second quantum dot that converts blue light into green light. The second quantum dot may absorb blue light and emit green light by shifting the wavelength according to energy transition. In the case where the second pixel PXL2 is a pixel of another color, the second color conversion material CC2 may include a second quantum dot corresponding to the color of the second pixel PXL2.

[0087] The absorption coefficient of the first and second quantum dots can be increased by causing blue light having a relatively short wavelength in the visible light region to be incident on each of the first and second quantum dots. Therefore, the efficiency of light emitted from the first and second pixels PXL1 and PXL2 can be improved, and excellent color reproducibility can be ensured.

[0088] refer to Figure 4 , the porous layer 14 of the light emitting element LD of the third pixel PXL3 may include a scatterer LS. The scatterer LS may be disposed in the pore NP of the porous layer 14 of the light emitting element LD of the third pixel PXL3.

[0089] The scatterer LS may be provided to effectively utilize the light of the third color (or blue) emitted from the light emitting element LD. For example, the scatterer LS may include titanium oxide (TiO 2 ), barium sulfate (BaSO 4 ), calcium carbonate (CaCO 3 ), silicon oxide (SiO 2 ), silicon nitride (Si 3 N 4 ), aluminum oxide (Al 2 O 3 ), zirconium oxide (ZrO 2 ) and zinc oxide (ZnO) in order to effectively use the light emitted from the light emitting element LD, but is not necessarily limited thereto. According to an embodiment, the scatterer LS may be omitted, or a transparent polymer may be provided instead of the scatterer LS.

[0090] Reference again Figure 3 , a first protective layer PSV1 may be disposed on the light emitting element LD. The first protective layer PSV1 may prevent an electrical short circuit that may occur when the active layer 12 contacts a conductive material other than the first semiconductor layer 11 and the second semiconductor layer 13. The first protective layer PSV1 may minimize surface defects of each light emitting element LD to improve the life span and light emitting efficiency of each light emitting element LD.

[0091] The first protective layer PSV1 may include a first opening OP1 and a second opening OP2 exposing a side surface of the light emitting element LD. For example, the first opening OP1 of the first protective layer PSV1 may expose a side surface of the light emitting element LD of the first pixel PXL1. The first opening OP1 of the first protective layer PSV1 may expose a side surface of the porous layer 14 of the light emitting element LD of the first pixel PXL1. In an embodiment, the first color conversion material CC1 may be injected into the porous layer 14 of the light emitting element LD of the first pixel PXL1 through the first opening OP1 of the first protective layer PSV1. Figure 8 Describe it in detail.

[0092] The second opening OP2 of the first protective layer PSV1 may expose the side surface of the light emitting element LD of the second pixel PXL2. The second opening OP2 of the first protective layer PSV1 may expose the side surface of the porous layer 14 of the light emitting element LD of the second pixel PXL2. In an embodiment, the second color conversion material CC2 may be injected into the porous layer 14 of the light emitting element LD of the second pixel PXL2 through the second opening OP2 of the first protective layer PSV1. Fig.10 Describe it in detail.

[0093] The first protective layer PSV1 may include silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), Silicon Oxycarbide (SiO x C y ), aluminum oxide (AlO x ), aluminum nitride (AlN x ), zirconium oxide (ZrO x ), hafnium oxide (HfO x ), titanium oxide (TiO x ), etc., but are not necessarily limited thereto.

[0094] The second protective layer PSV2 may be disposed on the first protective layer PSV1. The second protective layer PSV2 may cover the first opening OP1 of the first protective layer PSV1. For example, the second protective layer PSV2 may contact the porous layer 14 of the light emitting element LD of the first pixel PXL1 exposed by the first opening OP1 of the first protective layer PSV1.

[0095] The second protective layer PSV2 may include a second opening OP2 exposing a side surface of the light emitting element LD of the second pixel PXL2. For example, the second opening OP2 of the second protective layer PSV2 may expose a side surface of the light emitting element LD of the second pixel PXL2. The second opening OP2 of the second protective layer PSV2 may expose a side surface of the porous layer 14 of the light emitting element LD of the second pixel PXL2. In an embodiment, the second color conversion material CC2 may be injected into the porous layer 14 of the light emitting element LD of the second pixel PXL2 through the second opening OP2 of the second protective layer PSV2. Fig.10 Describe it in detail.

[0096] The second protective layer PSV2 may include silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), Silicon Oxycarbide (SiO x C y ), aluminum oxide (AlO x ), aluminum nitride (AlN x ), zirconium oxide (ZrO x ), hafnium oxide (HfO x ), titanium oxide (TiO x ), etc., but are not necessarily limited thereto.

[0097] The third protective layer PSV3 may be disposed on the second protective layer PSV2. The third protective layer PSV3 may cover the second opening OP2 of the first protective layer PSV1 and the second protective layer PSV2. For example, the third protective layer PSV3 may contact the porous layer 14 of the light emitting element LD of the second pixel PXL2 exposed by the second opening OP2 of the first protective layer PSV1 and the second protective layer PSV2.

[0098] The third protective layer PSV3 may include silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), Silicon Oxycarbide (SiO x C y ), aluminum oxide (AlO x ), aluminum nitride (AlNx ), zirconium oxide (ZrO x ), hafnium oxide (HfO x ), titanium oxide (TiO x ), etc., but are not necessarily limited thereto.

[0099] refer to Figure 4 , the first protective layer PSV1, the second protective layer PSV2, and the third protective layer PSV3 may include a third opening OP3 exposing the side surface of the light emitting element LD of the third pixel PXL3. For example, the third opening OP3 of the first protective layer PSV1, the second protective layer PSV2, and the third protective layer PSV3 may expose the side surface of the light emitting element LD of the third pixel PXL3. The third opening OP3 of the first protective layer PSV1, the second protective layer PSV2, and the third protective layer PSV3 may expose the side surface of the porous layer 14 of the light emitting element LD of the third pixel PXL3. In an embodiment, the scatterer LS may be injected into the porous layer 14 of the light emitting element LD of the third pixel PXL3 through the third opening OP3 of the first protective layer PSV1, the second protective layer PSV2, and the third protective layer PSV3. Refer to the following Fig.16 Describe it in detail.

[0100] The fourth protective layer PSV4 may be disposed on the third protective layer PSV3. The fourth protective layer PSV4 may cover the third opening OP3 of the first protective layer PSV1, the second protective layer PSV2, and the third protective layer PSV3. For example, the fourth protective layer PSV4 may contact the porous layer 14 of the light emitting element LD of the third pixel PXL3 exposed by the third opening OP3 of the first protective layer PSV1, the second protective layer PSV2, and the third protective layer PSV3.

[0101] The fourth protective layer PSV4 may include silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), Silicon Oxycarbide (SiO x C y ), aluminum oxide (AlO x ), aluminum nitride (AlN x ), zirconium oxide (ZrO x ), hafnium oxide (HfO x ), titanium oxide (TiO x ), etc., but are not necessarily limited thereto.

[0102] The first protective layer PSV1, the second protective layer PSV2, the third protective layer PSV3 and / or the fourth protective layer PSV4 may be partially removed to expose the upper surface of the light emitting element LD. For example, the first protective layer PSV1, the second protective layer PSV2, the third protective layer PSV3 and / or the fourth protective layer PSV4 may be partially removed to expose the first semiconductor layer 11 or the second semiconductor layer 13 of the light emitting element LD.

[0103] According to the above-described embodiment, the color conversion materials CC1 and CC2 or the scatterer LS can be injected into the porous layer 14 through the openings OP1, OP2, and OP3 of the protective layers PSV1, PSV2, and PSV3 that expose the side surface of the porous layer 14 of the light emitting element LD. Therefore, since a process of etching a layer (e.g., an undoped GaN layer) formed on the porous layer 14 to inject the color conversion materials CC1 and CC2 or the scatterer LS into the porous layer 14 can be omitted, the manufacturing process can be simplified and a robust chip can be manufactured.

[0104] The organic layer OL may be disposed between the light emitting elements LD. The organic layer OL may be formed between the light emitting elements LD and used to fix the light emitting elements LD. The organic layer OL may include an organic material such as an acrylate resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, a polyester resin, a polyphenylene sulfide resin, or benzocyclobutene (BCB), but is not necessarily limited thereto.

[0105] The optical pattern layer OPL may be disposed on the light emitting element LD. The optical pattern layer OPL may be disposed (e.g., directly disposed) on the porous layer 14. The optical pattern layer OPL may include undoped GaN, InGaN, InAlGaN, AlGaN, AlN, AlGaAs, GaAsP, AlGaInP, GaP, etc., but is not necessarily limited thereto.

[0106] In an embodiment, the optical pattern layer OPL may be formed by applying a patterned sapphire substrate (PSS). For example, the upper surface of the optical pattern layer OPL may be separated from the PSS and may have a shape according to the pattern shape of the PSS. For example, the optical pattern layer OPL may have a hemispherical pattern, but is not necessarily limited thereto. By forming the optical pattern layer OPL having a high refractive index pattern on the porous layer 14 using the PSS, the light extraction efficiency may be improved.

[0107] According to the above-mentioned embodiment, by injecting color conversion materials CC1 and CC2 or scatterer LS into the porous layer 14 through the openings OP1, OP2 and OP3 of the side surface of the porous layer 14 of the protective layers PSV1, PSV2 and PSV3 exposing the light-emitting element LD, the manufacturing process can be simplified, and the light extraction efficiency can be improved by forming an optical pattern layer OPL on the porous layer 14.

[0108] A method of manufacturing the display device according to the above-described embodiment is described below.

[0109] Figures 5 to 14 is a schematic cross-sectional view of each process step of a method of manufacturing a display device according to an embodiment. Figures 5 to 14 It shows the manufacturing Figure 3 A schematic cross-sectional view of a method of displaying a device and a method of Figure 3 Components in which substantially the same components are represented by the same reference numerals, and detailed description is omitted.

[0110] refer to Figure 5 , a base layer BSL may be prepared, and a first semiconductor layer 11, an active layer 12, and a second semiconductor layer 13 of a light emitting element LD may be formed on the base layer BSL. The base layer BSL may be PSS, but is not necessarily limited thereto. The first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13 may be formed by growing a seed crystal via an epitaxial method, but are not necessarily limited thereto.

[0111] refer to Figure 6 , the second semiconductor layer 13 can be etched to form the porous layer 14. For example, nanoscale pores NP of the porous layer 14 can be formed by electrochemically etching the second semiconductor layer 13. In the process of electrochemically etching the second semiconductor layer 13, the size, shape and distribution of the pores NP of the porous layer 14 can be controlled according to the etchant, voltage and / or doping concentration.

[0112] refer to Figure 7 , a first protective layer PSV1 may be formed on the light emitting element LD. The first protective layer PSV1 may be formed over the entire area of ​​the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3. A portion of the first protective layer PSV1 may be etched to expose the side surface of the light emitting element LD. For example, the first protective layer PSV1 may include a first opening OP1 that exposes the side surface of the porous layer 14 of the light emitting element LD of the first pixel PXL1.

[0113] refer to Figure 8, the first color conversion material CC1 may be injected into the porous layer 14 of the light emitting element LD of the first pixel PXL1. The first color conversion material CC1 may be injected into the pore NP of the porous layer 14 of the first pixel PXL1 through the first opening OP1 of the first protective layer PSV1. The first color conversion material CC1 may be injected by an inkjet process or spin coating, but is not necessarily limited thereto.

[0114] refer to Fig. 9 , a second protective layer PSV2 may be formed on the first protective layer PSV1. The second protective layer PSV2 may be formed over the entire area of ​​the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3. The second protective layer PSV2 may cover the first opening OP1 of the first protective layer PSV1. For example, the second protective layer PSV2 may cover the porous layer 14 of the light emitting element LD of the first pixel PXL1 that is exposed by the first opening OP1 of the first protective layer PSV1.

[0115] A portion of the second protective layer PSV2 and a portion of the first protective layer PSV1 may be etched to expose the side surface of the light emitting element LD. For example, the second protective layer PSV2 and the first protective layer PSV1 may include a second opening OP2 exposing the side surface of the porous layer 14 of the light emitting element LD of the second pixel PXL2.

[0116] refer to Fig.10 , the second color conversion material CC2 may be injected into the porous layer 14 of the light emitting element LD of the second pixel PXL2. The second color conversion material CC2 may be injected into the pores NP of the porous layer 14 of the second pixel PXL2 through the second openings OP2 of the second protective layer PSV2 and the first protective layer PSV1. The second color conversion material CC2 may be injected through an inkjet process or spin coating, but is not necessarily limited thereto. As described above, since the color conversion materials CC1 and CC2 may be injected into the porous layer 14 through the openings OP1 and OP2 of the protective layers PSV1 and PSV2 exposing the side surfaces of the porous layer 14 of the light emitting element LD, since the process of etching the layers on the porous layer 14 may be omitted, the manufacturing process may be simplified, and a robust light emitting element LD chip may be manufactured as described above.

[0117] refer to Fig.11, a third protective layer PSV3 may be formed on the second protective layer PSV2. The third protective layer PSV3 may be formed throughout the entire area of ​​the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3. The third protective layer PSV3 may cover the second protective layer PSV2 and the second opening OP2 of the first protective layer PSV1. For example, the third protective layer PSV3 may cover the porous layer 14 of the light emitting element LD of the second pixel PXL2 that is exposed by the second protective layer PSV2 and the second opening OP2 of the first protective layer PSV1.

[0118] refer to Fig.12 , an organic layer OL may be formed between the light emitting elements LD. The organic layer OL may be formed (eg, directly formed) on the third protective layer PSV3.

[0119] refer to Fig.13 , a first electrode EL1 and a second electrode EL2 may be formed on the light emitting element LD. A portion of the first protective layer PSV1, a portion of the second protective layer PSV2, and a portion of the third protective layer PSV3 may be removed to expose the surface of the first semiconductor layer 11 or the second semiconductor layer 13 of the light emitting element LD. The first electrode EL1 may be formed on the first semiconductor layer 11 exposed by the first protective layer PSV1, the second protective layer PSV2, and the third protective layer PSV3. The second electrode EL2 may be formed on the second semiconductor layer 13 exposed by the first protective layer PSV1, the second protective layer PSV2, and the third protective layer PSV3.

[0120] refer to Fig.14 , the light emitting element LD may be connected to the substrate SUB. The substrate SUB may be a driving substrate including circuit elements, etc., the circuit elements, etc. including the components configuring each pixel PXL. Figure 2 The first semiconductor layer 11 of the light emitting element LD may be electrically connected to a region of the substrate SUB through the first electrode EL1. The second semiconductor layer 13 of the light emitting element LD may be electrically connected to another region of the substrate SUB through the second electrode EL2.

[0121] After the light emitting element LD is connected to the substrate SUB, the base layer BSL may be separated. In the process of separating the base layer BSL, an optical pattern layer OPL may be formed on the porous layer 14. For example, in the case where the base layer BSL includes a pattern (a predetermined or selectable pattern) as a PSS, the upper surface of the optical pattern layer OPL separated from the base layer BSL may have a pattern shape according to the pattern shape of the base layer BSL. For example, the optical pattern layer OPL may have a hemispherical pattern, but is not necessarily limited thereto. As described above, by applying PSS to the base layer BSL, by forming the optical pattern layer OPL on the porous layer 14, the light extraction efficiency may be improved.

[0122] Hereinafter, another embodiment is described. In the following embodiment, substantially the same configuration as that described previously is denoted by the same reference numerals, and the detailed description is omitted or simplified.

[0123] Figures 15 to 18 is a schematic cross-sectional view of each process step of a method of manufacturing a display device according to an embodiment. Figures 15 to 18 It shows the manufacturing Figure 4 A schematic cross-sectional view of a method for displaying a device. Figure 4 Components in which substantially the same components are represented by the same reference numerals, and detailed description is omitted.

[0124] refer to Fig.15 , a third protective layer PSV3 may be formed on the second protective layer PSV2. Figures 5 to 10 The process steps of forming the second protection layer PSV2 and injecting the second color conversion material CC2 are described, and thus overlapping contents are omitted.

[0125] The third protective layer PSV3 may be formed over the entire area of ​​the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3. The third protective layer PSV3 may cover the second opening OP2 of the first protective layer PSV1 and the second protective layer PSV2. For example, the third protective layer PSV3 may cover the porous layer 14 of the light emitting element LD of the second pixel PXL2 exposed by the second opening OP2 of the first protective layer PSV1 and the second protective layer PSV2.

[0126] A portion of the third protective layer PSV3, a portion of the second protective layer PSV2, and a portion of the first protective layer PSV1 may be etched to expose the side surface of the light emitting element LD. For example, the third protective layer PSV3, the second protective layer PSV2, and the first protective layer PSV1 may include a third opening OP3 exposing the side surface of the porous layer 14 of the light emitting element LD of the third pixel PXL3.

[0127] refer to Fig.16, the scatterer LS can be injected into the porous layer 14 of the light-emitting element LD of the third pixel PXL3. The scatterer LS can be injected into the hole NP of the porous layer 14 of the third pixel PXL3 through the third opening OP3 of the third protective layer PSV3, the second protective layer PSV2, and the first protective layer PSV1. The scatterer LS can be injected by an inkjet process or spin coating, but is not necessarily limited thereto. As described above, since the color conversion materials CC1 and CC2 or the scatterer LS can be injected into the porous layer 14 through the openings OP1, OP2, and OP3 of the side surfaces of the porous layer 14 of the protective layers PSV1, PSV2, and PSV3 that expose the light-emitting element LD, since the process of etching the layer on the porous layer 14 can be omitted, the manufacturing process can be simplified and a robust light-emitting element LD chip can be manufactured.

[0128] refer to Fig.17 , a fourth protective layer PSV4 may be formed on the third protective layer PSV3. The fourth protective layer PSV4 may be formed throughout the entire area of ​​the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3. The fourth protective layer PSV4 may cover the third protective layer PSV3, the second protective layer PSV2, and the third opening OP3 of the first protective layer PSV1. For example, the fourth protective layer PSV4 may cover the porous layer 14 of the light emitting element LD of the third pixel PXL3 that is exposed by the third protective layer PSV3, the second protective layer PSV2, and the third opening OP3 of the first protective layer PSV1. An organic layer OL may be formed between the light emitting elements LD. The organic layer OL may be formed (e.g., directly formed) on the fourth protective layer PSV4.

[0129] refer to Fig.18 , a first electrode EL1 and a second electrode EL2 may be formed on the light emitting element LD. A portion of the first protective layer PSV1, a portion of the second protective layer PSV2, a portion of the third protective layer PSV3, and a portion of the fourth protective layer PSV4 may be removed to expose the surface of the first semiconductor layer 11 or the second semiconductor layer 13 of the light emitting element LD. The first electrode EL1 may be formed on the first semiconductor layer 11 exposed by the first protective layer PSV1, the second protective layer PSV2, the third protective layer PSV3, and the fourth protective layer PSV4. The second electrode EL2 may be formed on the second semiconductor layer 13 exposed by the first protective layer PSV1, the second protective layer PSV2, the third protective layer PSV3, and the fourth protective layer PSV4.

[0130] The light emitting element LD may be coupled to a substrate SUB. The substrate SUB may be a driving substrate including circuit elements, etc., including a circuit element configuring each pixel PXL. Figure 2The first semiconductor layer 11 of the light emitting element LD may be electrically connected to a region of the substrate SUB through the first electrode EL1. The second semiconductor layer 13 of the light emitting element LD may be electrically connected to another region of the substrate SUB through the second electrode EL2.

[0131] After the light emitting element LD is connected to the substrate SUB, the base layer BSL may be separated. In the process of separating the base layer BSL, an optical pattern layer OPL may be formed on the porous layer 14. For example, in the case where the base layer BSL includes a pattern (a predetermined or selectable pattern) as a PSS, the upper surface of the optical pattern layer OPL separated from the base layer BSL may have a pattern shape according to the pattern shape of the base layer BSL. For example, the optical pattern layer OPL may have a hemispherical pattern, but is not necessarily limited thereto. As described above, by applying PSS to the base layer BSL, by forming the optical pattern layer OPL on the porous layer 14, the light extraction efficiency may be improved.

[0132] The above description is an example of the technical features of the present disclosure, and a person skilled in the art will be able to make various modifications and changes.Therefore, the embodiments of the present disclosure described above can be implemented individually or in combination with each other.

[0133] Therefore, the embodiments disclosed in the present disclosure are not intended to limit the technical spirit of the present disclosure, but to describe the technical spirit of the present disclosure, and the scope of the technical spirit of the present disclosure is not limited by these embodiments. The protection scope of the present disclosure should be interpreted by the attached claims, and it should be understood that all technical spirits within the equivalent scope are included in the scope of the present disclosure.

Claims

1. A display device, characterized in that: include: a light emitting element including a porous layer; a first protective layer disposed on the light emitting element and including an opening exposing a side surface of the porous layer; as well as a second protective layer, covering the opening of the first protective layer, Wherein, the porous layer includes a color conversion member.

2. The display device according to claim 1, characterized in that The light emitting element further includes: a first semiconductor layer, a second semiconductor layer, and an active layer disposed between the first semiconductor layer and the second semiconductor layer.

3. The display device according to claim 2, characterized in that: The porous layer and the second semiconductor layer include the same material.

4. The display device according to claim 1, characterized in that The porous layer includes nanoscale pores.

5. The display device according to claim 4, characterized in that: The color conversion member is disposed in the hole.

6. The display device according to claim 1, characterized in that: The second protective layer contacts the porous layer exposed by the opening of the first protective layer.

7. The display device according to claim 1, characterized in that: Also includes: The organic layer is arranged between the light emitting elements.

8. The display device according to claim 7, characterized in that: Also includes: The third protective layer is disposed between the second protective layer and the organic layer.

9. The display device according to claim 1, characterized in that: Also includes: The optical pattern layer is arranged on the light emitting element.

10. The display device according to claim 9, characterized in that: The optical pattern layer is directly disposed on the porous layer.

Images