Display device

Abstract

A display device includes a substrate, a first planarization layer, a first light emitting element, a second light emitting element, a third light emitting element, and a second planarization layer. The first planarization layer is disposed on the substrate. A first light-emitting element, a second light-emitting element, and a third light-emitting element are arranged on the first planarization layer, and the first light-emitting element includes a first emission region, the second light-emitting element includes a second emission region, the third light-emitting element includes a third emission region, the first emission region, the second emission region, and the third emission region emitting light of different wavelengths. The second planarization layer is disposed between the first planarization layer and the first emitter region. The second emitter region does not overlap the second planarization layer.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application is based on and claims the benefit of priority from Korean Patent Application No. 10-2023-0039051, filed on March 24, 2023, in the Korean Intellectual Property Office, and No. 10-2023-0041495, filed on March 29, 2023, in the Korean Intellectual Property Office, the disclosures of which are incorporated herein in their entirety by reference. Technical Field

[0003] One or more embodiments relate to a display device, and more particularly, to a display device having improved display quality. Background Art

[0004] Organic light emitting display devices have self-emission characteristics and, unlike liquid crystal display devices, do not require a separate light source and thus may have reduced thickness and weight. In addition, organic light emitting display devices have high quality characteristics such as low power consumption, high brightness, and high response speed. Utility Model Content

[0005] One or more embodiments include a display device having improved display quality by reducing a reflective color banding phenomenon caused by asymmetric reflection of external light. However, the embodiments are merely examples, and the scope of the present disclosure is not limited thereto.

[0006] Additional aspects will be set forth in part in the detailed description which follows and, in part, will be obvious from the description, or may be learned by practice of the presented embodiments of the disclosure.

[0007] According to one or more embodiments, a display device may include: a substrate; a first planarization layer, which is arranged on the substrate; a first light-emitting element, a second light-emitting element, and a third light-emitting element, which are arranged on the first planarization layer, and the first light-emitting element includes a first emission region, the second light-emitting element includes a second emission region, the third light-emitting element includes a third emission region, and the first emission region, the second emission region, and the third emission region emit light of different wavelengths; and a second planarization layer, which is arranged between the first planarization layer and the first emission region, wherein the first emission region overlaps with the second planarization layer, and the second emission region does not overlap with the second planarization layer.

[0008] In an embodiment, a second planarization layer is further disposed between the first planarization layer and the third emission region.

[0009] In an embodiment, the display device may further include: a plurality of first conductive lines arranged under the first planarization layer to overlap with the first emission region and spaced apart from each other under the first emission region; and a conductive layer arranged under the first planarization layer to overlap with the second emission region, wherein the second emission region covers the conductive layer.

[0010] In an embodiment, a first pixel electrode of the first light emitting element may be disposed on an upper surface of the second planarization layer, and a second pixel electrode of the second light emitting element may be disposed on an upper surface of the first planarization layer.

[0011] In an embodiment, a lower surface of the first pixel electrode may contact an upper surface of the second planarization layer, and a lower surface of the second pixel electrode may contact an upper surface of the first planarization layer.

[0012] In an embodiment, the first pixel electrode may include a first body portion overlapping the first emission region and a first contact portion extending from the first body portion, the second pixel electrode may include a second body portion overlapping the second emission region and a second contact portion extending from the second body portion, and the area of ​​the second planarization layer under the first emission region may be greater than the area of ​​the first body portion.

[0013] In an implementation, a distance between an upper surface of the substrate and a lower surface of the first body portion may be greater than a distance between an upper surface of the substrate and a lower surface of the second body portion.

[0014] In an implementation, the first contact portion of the first pixel electrode may extend along the inclined surface of the second planarization layer and may be disposed on an upper surface of the first planarization layer.

[0015] In an embodiment, the display device may further include: a pixel defining film covering an edge of each of the first body portion and the second body portion and having a first pixel opening and a second pixel opening respectively exposing a central portion of the first body portion and the second body portion, and the pixel defining film may cover an edge of the second planarization layer.

[0016] In an embodiment, the display device may further include: a plurality of second conductive lines arranged under the first planarization layer to overlap the third emission region and spaced apart from each other under the third emission region.

[0017] In an embodiment, a third pixel electrode of the third light emitting element may be disposed on an upper surface of the second planarization layer.

[0018] In an implementation, the second planarization layer may include an island pattern.

[0019] In an implementation, a height of the first planarization layer may be equal to a height of the second planarization layer.

[0020] In an embodiment, according to one or more embodiments, a display device may include: a substrate; a first planarization layer, the first planarization layer being arranged on the substrate; a first light-emitting element, a second light-emitting element and a third light-emitting element, the first light-emitting element, the second light-emitting element and the third light-emitting element being arranged on the first planarization layer, and the first light-emitting element includes a first emission region, the second light-emitting element includes a second emission region, the third light-emitting element includes a third emission region, and the first emission region, the second emission region and the third emission region emit light of different wavelengths; a second planarization layer, the second planarization layer including a first island pattern arranged between the first planarization layer and the first emission region and a second island pattern arranged between the first planarization layer and the third emission region; a first pixel electrode, the first pixel electrode being arranged on an upper surface of the first island pattern to overlap with the first emission region; a second pixel electrode, the second pixel electrode being arranged on an upper surface of the first planarization layer to overlap with the second emission region; and a third pixel electrode, the third pixel electrode being arranged on an upper surface of the second island pattern to overlap with the third emission region.

[0021] In an embodiment, the display device may further include: a plurality of first conductive lines arranged under the first planarization layer to overlap with the first emission region and spaced apart from each other under the first emission region; a conductive layer arranged under the first planarization layer to overlap with the second emission region; and a plurality of second conductive lines arranged under the first planarization layer to overlap with the third emission region and spaced apart from each other under the third emission region, and the second emission region may cover the conductive layer.

[0022] In an embodiment, a lower surface of the first pixel electrode may contact an upper surface of the first island pattern, a lower surface of the second pixel electrode may contact an upper surface of the first planarization layer, and a lower surface of the third pixel electrode may contact an upper surface of the second island pattern.

[0023] In an embodiment, the first pixel electrode may include a first body portion overlapping the first emission region and a first contact portion extending from the first body portion, the second pixel electrode may include a second body portion overlapping the second emission region and a second contact portion extending from the second body portion, the third pixel electrode may include a third body portion overlapping the third emission region and a third contact portion extending from the third body portion, the area of ​​the first island pattern may be larger than the area of ​​the first body portion, and the area of ​​the second island pattern may be larger than the area of ​​the third body portion.

[0024] In an embodiment, a distance between an upper surface of the substrate and a lower surface of the first body portion may be greater than a distance between an upper surface of the substrate and a lower surface of the second body portion and may be equal to a distance between an upper surface of the substrate and a lower surface of the third body portion.

[0025] In an implementation, an area of ​​the third emission region may be greater than that of the first emission region, an area of ​​the third body portion may be greater than that of the first body portion, and an area of ​​the second island pattern may be greater than that of the first island pattern.

[0026] In an implementation, a distance between an edge of the first body portion and an edge of the first island pattern may be equal to a distance between an edge of the third body portion and an edge of the second island pattern. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The above and other aspects, features and advantages of certain embodiments of the present disclosure will become more apparent from the following description taken in conjunction with the accompanying drawings, in which:

[0028] Figure 1 is a schematic perspective view of a display device according to an embodiment;

[0029] Figure 2 A light emitting element provided in any one pixel of a display device and a pixel circuit connected thereto according to an embodiment are shown;

[0030] Figure 3 is a schematic cross-sectional view of a display device according to an embodiment;

[0031] Figure 4 is a schematic plan view of a portion of a pixel arrangement in a display area; and

[0032] Figure 5 is along Figure 4 The line B-B' intercepts Figure 1 A cross-sectional view of a display device. DETAILED DESCRIPTION

[0033] Reference will now be made in detail to the embodiments illustrated in the accompanying drawings, wherein like reference numerals refer to like elements throughout this specification. In this regard, the embodiments may have different forms and should not be construed as being limited to the description set forth herein. Therefore, the embodiments are described below only by reference to the drawings to explain various aspects of the description.

[0034] As used herein, the word "or" means a logical "or", so that the expression "A, B, or C" means "A and B and C," "A and B but not C," "A and C but not B," "B and C but not A," "A but not B and not C," "B but not A and not C," and "C but not A and not B," unless the context indicates otherwise. Throughout this disclosure, the expression "at least one of a, b, and c" means only a, only b, only c, both a and b, both a and c, both b and c, all of a, b, and c, or variations thereof.

[0035] Various modifications may be applied to this embodiment, and specific embodiments will be illustrated in the drawings and described in the detailed description section. The effects and features of this embodiment and methods for implementing them will be more clearly understood by referring to the detailed description below in conjunction with the drawings. However, this embodiment can be implemented in various forms and is not limited to the embodiments presented below.

[0036] Hereinafter, the embodiments will be described in detail with reference to the accompanying drawings, and in the description with reference to the accompanying drawings, the same or corresponding components are denoted by the same reference numerals, and redundant descriptions thereof are omitted.

[0037] In the following embodiments, it will be understood that although the terms "first", "second", etc. may be used herein to describe various components, these components should not be limited by these terms. These terms are only used to distinguish one component from another component.

[0038] In the following embodiments, unless clearly defined otherwise in the context, a singular expression in this specification includes a plural expression.

[0039] In the following embodiments, it will be further understood that the words "comprising", "including" and / or "having" (and their variations, such as "comprises") used herein specify the presence of the features or components, but do not exclude the presence or addition of one or more other features or components.

[0040] In the following embodiments, it will be understood that when one layer, region or component is connected to another layer, region or component, the layers, regions or components may not only be directly connected, but also be indirectly connected via another layer, region or component therebetween. For example, in this specification, when one layer, region or component is electrically connected to another layer, region or component, the layers, regions or components may not only be directly electrically connected, but also be indirectly electrically connected via another layer, region or component therebetween.

[0041] In the following embodiments, it will be understood that when a layer, region or component is referred to as being "formed on" another layer, region or component, it can be directly or indirectly formed on the other layer, region or component. That is, for example, there may be intervening layers, regions or components.

[0042] For the convenience of explanation, the size of the components in the drawings may be exaggerated. In other words, since the size and thickness of the components in the drawings are arbitrarily illustrated for the convenience of explanation, the following embodiments are not limited thereto.

[0043] When a specific embodiment can be implemented in different ways, the specific process order can be performed differently from the described order. For example, two processes described in succession can be performed substantially simultaneously or in the reverse order of the described order.

[0044] Figure 1 is a schematic perspective view of a display device 1 according to an embodiment.

[0045] In an embodiment, the display device 1 displays moving images or still images and can be used as a display screen for various products such as a television, a notebook computer, a monitor, a billboard, or an Internet of Things (IOT) device, and a portable device such as a mobile phone, a smart phone, a tablet personal computer, a mobile communication terminal, an electronic notebook, an electronic book, a portable multimedia player (PMP), a navigation device, or an ultra mobile personal computer (UMPC).

[0046] In addition, in an embodiment, the display device 1 can be used in wearable devices such as smart watches, watch phones, glasses-type displays, and head-mounted displays (HMDs). In addition, in an embodiment, the display device 1 can be used as a display of a vehicle instrument panel, a central information display (CID) arranged on a central dashboard or instrument panel of a vehicle, an interior mirror display replacing a side mirror of a vehicle, or a display arranged at the rear side of a front seat as an entertainment facility for a rear seat of a vehicle. For the convenience of explanation, Figure 1 The display device 1 is illustrated as being used as a smartphone.

[0047] refer to Figure 1 , the display device 1 according to the embodiment may include a display area DA and a non-display area NDA located outside the display area DA. Figure 1 The display area DA is illustrated to have a substantially rectangular shape, but the present disclosure is not limited thereto. The display area DA may have various shapes such as a circular shape, an elliptical shape, and other polygonal shapes.

[0048] The display area DA is a portion for displaying an image, and a plurality of pixels P may be arranged in the display area DA. Each of the plurality of pixels P may include an organic light emitting diode OLED (see Figure 2 Each of the plurality of pixels P may emit, for example, red light, green light, blue light, or white light.

[0049] The display area DA may provide a specific image via light emitted from the pixel P. As described above, the pixel P in this specification may be defined as an emission area that emits light of any one color among red, green, blue, and white.

[0050] The non-display area NDA is an area in which no pixels P are arranged and may not provide an image. A terminal unit to which a printed circuit board including a power supply line and a driving circuit unit each for driving the pixels P or a driver integrated circuit (IC) is connected may be arranged in the non-display area NDA.

[0051] Hereinafter, as a display device 1 according to an embodiment, an organic light-emitting display device is described as an example. However, the display device 1 of the present disclosure is not limited thereto. For example, the display device 1 of the present disclosure may be an inorganic light-emitting display device (or an inorganic electroluminescent (EL) display device) or a quantum dot light-emitting display device. For example, the emission layer included in the light-emitting element provided in the display device 1 may include an organic material or an inorganic material. In addition, the quantum dot may be located on the path of light emitted from the emission layer.

[0052] Figure 2 A light emitting element provided in any one pixel P of the display device 1 and a pixel circuit PC connected thereto according to the embodiment are shown.

[0053] refer to Figure 2 , an organic light emitting diode OLED as a light emitting element is connected to the pixel circuit PC. The pixel circuit PC may include a first thin film transistor T1, a second thin film transistor T2, and a storage capacitor Cst. The organic light emitting diode OLED may emit, for example, red light, green light, or blue light, or may emit red light, green light, blue light, or white light.

[0054] The second thin film transistor T2 as a switching thin film transistor is connected to the scan line SL and the data line DL, and can transmit the data voltage input from the data line DL to the first thin film transistor T1 according to the switching voltage input from the scan line SL. The storage capacitor Cst is connected to the second thin film transistor T2 and the driving voltage line PL, and can store a voltage corresponding to the difference between the voltage received from the second thin film transistor T2 and the first power voltage ELVDD supplied to the driving voltage line PL.

[0055] The first thin film transistor T1 as a driving thin film transistor is connected to the driving voltage line PL and the storage capacitor Cst, and can control the driving current flowing from the driving voltage line PL to the organic light emitting diode OLED according to the voltage value stored in the storage capacitor Cst. The organic light emitting diode OLED can emit light with a specific brightness by the driving current. The common electrode (e.g., cathode) of the organic light emitting diode OLED can receive the second power voltage ELVSS.

[0056] Figure 2The pixel circuit PC is illustrated to include two thin film transistors and one storage capacitor (a first thin film transistor T1, a second thin film transistor T2, and a storage capacitor Cst), but in another embodiment, the number of thin film transistors or the number of storage capacitors may vary according to the design of the pixel circuit PC.

[0057] Figure 3 is a schematic cross-sectional view of a display device 1 according to an embodiment, and is a schematic cross-sectional view of a display device 1 according to an embodiment. Figure 1 A cross-sectional view of the display device 1 taken along line AA′.

[0058] refer to Figure 3 , the display device 1 according to the embodiment may include a substrate 100 , a display layer 200 , a low-reflection layer 300 , a thin-film encapsulation layer 400 , a touch sensor layer 500 , and an anti-reflection layer 600 .

[0059] The substrate 100 may include glass or a polymer resin. For example, the polymer resin may include polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, or cellulose acetate propionate. The substrate 100 including the polymer resin may be flexible, rollable, or bendable. The substrate 100 may have a multilayer structure including a layer including a polymer resin and an inorganic layer (not shown).

[0060] The display layer 200 may include an organic light emitting diode as a light emitting element, a thin film transistor electrically connected to the organic light emitting diode, and an insulating layer arranged between the organic light emitting diode and the thin film transistor.

[0061] The low reflection layer 300 may be disposed on the display layer 200, and the thin film encapsulation layer 400 may be disposed on the low reflection layer 300. For example, the display layer 200 or the low reflection layer 300 may be sealed with the thin film encapsulation layer 400. The thin film encapsulation layer 400 may include at least one inorganic film layer and at least one organic film layer. In some embodiments, the low reflection layer 300 may be omitted.

[0062] In some embodiments, the display device 1 may include an encapsulation substrate (not shown) formed of a glass material instead of the thin film encapsulation layer 400. The encapsulation substrate may be disposed on the display layer 200, and the display layer 200 may be arranged between the substrate 100 and the encapsulation substrate. There may be a gap between the encapsulation substrate and the display layer 200, and the gap may be filled with a filler.

[0063] The touch sensor layer 500 may be disposed on the thin film encapsulation layer 400. The touch sensor layer 500 may detect an external input (e.g., a touch of a finger or an object such as a stylus pen) so that the display device 1 may obtain coordinate information corresponding to a touch position. The touch sensor layer 500 may include a touch electrode and a trace connected to the touch electrode. The touch sensor layer 500 may detect an external input by using a mutual capacitance method or a self capacitance method.

[0064] In an embodiment, the touch sensor layer 500 may be directly formed on the thin film encapsulation layer 400. Alternatively, the touch sensor layer 500 may be separately formed and then bonded to the thin film encapsulation layer 400 by using an adhesive layer such as an optically clear adhesive (OCA).

[0065] The anti-reflection layer 600 may be disposed on the touch sensor layer 500. The anti-reflection layer 600 may reduce reflectivity of light (external light) incident toward the display apparatus 1.

[0066] Figure 4 is a schematic plan view of a portion of a pixel arrangement in a display area DA. For convenience of explanation, Figure 4 Only some of the components included in the display device 1 are illustrated. Figure 1 and Figure 4 , a pixel arrangement structure of a display device 1 according to an embodiment is briefly described.

[0067] refer to Figure 1 and Figure 4 , the display device 1 may include a plurality of pixels P arranged in a display area DA, and the plurality of pixels P may include a first pixel P1, a second pixel P2, and a third pixel P3 that emit different colors. For example, the first pixel P1 may emit red light, the second pixel P2 may emit green light, and the third pixel P3 may emit blue light. However, the present disclosure is not limited thereto. For example, the first pixel P1 may emit blue light, the second pixel P2 may emit green light, and the third pixel P3 may emit red light, and various modifications may be made.

[0068] In an embodiment, the first pixel P1, the second pixel P2, and the third pixel P3 may have a circular planar shape. In another embodiment, the first pixel P1, the second pixel P2, and the third pixel P3 may have various planar shapes such as a polygon, a polygon with rounded corners, and an ellipse.

[0069] In an embodiment, the sizes of the first pixel P1, the second pixel P2, and the third pixel P3 may be different from each other. For example, the size of the second pixel P2 may be smaller than the sizes of the first pixel P1 and the third pixel P3, and the size of the third pixel P3 may be larger than the size of the first pixel P1. In another embodiment, the sizes of the first pixel P1, the second pixel P2, and the third pixel P3 may be substantially the same, and various modifications may be made.

[0070] In this specification, the sizes of the first pixel P1, the second pixel P2, and the third pixel P3 may be referred to as the size of the emission area EA of the light emitting element of each pixel, and the emission area EA may be defined by the pixel definition film 213 (see Figure 5 ) is defined by the pixel opening 213OP. For example, the emission area EA may include a first emission area EA1 that can emit red light, a second emission area EA2 that can emit green light, and a third emission area EA3 that can emit blue light, but the present disclosure is not limited thereto.

[0071] In an embodiment, the first pixel P1, the second pixel P2, and the third pixel P3 may be arranged to have Figure 4 . However, the present disclosure is not limited thereto. For example, the first pixel P1, the second pixel P2, and the third pixel P3 may be arranged in a shape such as pentile Various pixel arrangement structures including structure, stripe structure, mosaic structure and delta structure.

[0072] Figure 5 is along Figure 4 The line B-B' intercepts Figure 1 1 is a cross-sectional view of a display device 1. In the following, reference is made to Figure 4 and Figure 5 , components of the display device 1 according to the embodiment are described in detail according to a stacking order.

[0073] refer to Figure 4 and Figure 5 , the display device 1 according to the embodiment may include a substrate 100 , a display layer 200 , a low-reflection layer 300 , a thin-film encapsulation layer 400 , a touch sensor layer 500 , and an anti-reflection layer 600 .

[0074] The display layer 200 may include a first organic light emitting diode OLED1, a second organic light emitting diode OLED2, and a third organic light emitting diode OLED3, and thin film transistors TFT1, TFT2, and TFT3, and may include a buffer layer 201 as an insulating layer, a gate insulating layer 203, an interlayer insulating layer 205, a through hole insulating layer 207, a first planarization layer 209, a second planarization layer 211, and a pixel defining film 213. Each of the thin film transistors TFT1, TFT2, and TFT3 may include a semiconductor layer ACT, a gate electrode GE, a source electrode SE, and a drain electrode DE. The first organic light emitting diode OLED1 may include a first pixel electrode PE1, a first intermediate layer ML1, and a common electrode CE, and may be referred to as a first light emitting element. The second organic light emitting diode OLED2 may include a second pixel electrode PE2, a second intermediate layer ML2, and a common electrode CE, and may be referred to as a second light emitting element. The third organic light emitting diode OLED3 may include a third pixel electrode PE3, a third intermediate layer ML3, and a common electrode CE, and may be referred to as a third light emitting element.

[0075] The buffer layer 201 may be disposed on the substrate 100, and thus may reduce or block the penetration of foreign matter, moisture, or external air from the lower portion of the substrate 100, and provide a flat surface on the substrate 100. The buffer layer 201 may include an inorganic material such as an oxide or a nitride, an organic material, or an organic / inorganic composite, and may be formed as a single layer or multilayer structure of an inorganic material and an organic material. A barrier layer (not shown) may also be included between the substrate 100 and the buffer layer 201 to block the penetration of external air. The buffer layer 201 may include silicon oxide (SiO 2 ) or silicon nitride (SiN X ).

[0076] Thin film transistors TFT1, TFT2, and TFT3 may be disposed on the buffer layer 201. Each of the thin film transistors TFT1, TFT2, and TFT3 may include a semiconductor layer ACT, a gate electrode GE, a source electrode SE, and a drain electrode DE. The thin film transistors TFT1, TFT2, and TFT3 may be connected to and drive the first organic light emitting diode OLED1, the second organic light emitting diode OLED2, and the third organic light emitting diode OLED3, respectively.

[0077] The semiconductor layer ACT may be arranged on the buffer layer 201 and may include polycrystalline silicon. Alternatively, the semiconductor layer ACT may include amorphous silicon. Alternatively, the semiconductor layer ACT may include an oxide of at least one material selected from the group consisting of indium (In), gallium (Ga), tin (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), and zinc (Zn). The semiconductor layer ACT may include a channel region and a source region and a drain region doped with impurities.

[0078] The gate electrode GE, the source electrode SE, and the drain electrode DE may be formed of various conductive materials. The gate electrode GE may include at least one of molybdenum, aluminum, copper, and titanium. For example, the gate electrode GE may have a single layer of molybdenum, or may have a three-layer structure including a molybdenum layer, an aluminum layer, and a molybdenum layer. The source electrode SE and the drain electrode DE may each include at least one material selected from the group including copper, titanium, and aluminum. For example, the source electrode SE and the drain electrode DE may each have a three-layer structure including a titanium layer, an aluminum layer, and a titanium layer.

[0079] Meanwhile, in order to ensure insulation between the semiconductor layer ACT and the gate electrode GE, a gate insulating layer 203 including an inorganic material such as silicon oxide, silicon nitride, or silicon oxynitride may be arranged between the semiconductor layer ACT and the gate electrode GE. In addition, an interlayer insulating layer 205 including silicon oxide, silicon nitride, or silicon oxynitride may be arranged above the gate electrode GE, and a source electrode SE and a drain electrode DE may be arranged on the interlayer insulating layer 205. Thus, an insulating film including an inorganic material may be formed by using chemical vapor deposition (CVD) or atomic layer deposition (ALD). The same applies to the following embodiments.

[0080] The through hole insulating layer 207 may be arranged on the thin film transistors TFT1, TFT2 and TFT3. The through hole insulating layer 207 may include an organic insulating material and may provide a flat upper surface. The through hole insulating layer 207 may include a general polymer (such as photosensitive polyimide, polyimide, polycarbonate (PC), benzocyclobutene (BCB), hexamethyldisiloxane (HMDSO), polymethylmethacrylate (PMMA) or polystyrene (PS)), a polymer derivative having a phenol group, an acrylic polymer, an imide-based polymer, an aryl ether-based polymer, an amide-based polymer, a fluorine-based polymer, a p-xylene-based polymer or a vinyl alcohol-based polymer.

[0081] The first conductive line CTP1, the conductive layer CTL, and the second conductive line CTP2 may be disposed on the through hole insulating layer 207. In an embodiment, the first conductive line CTP1 may overlap the first emission region EA1, the conductive layer CTL may overlap the second emission region EA2, and the second conductive line CTP2 may overlap the third emission region EA3.

[0082] The first conductive line CTP1 may be arranged above the through-hole insulating layer 207 and below the first planarization layer 209 to overlap the first emission area EA1. The first conductive lines CTP1 may be separated from each other in the first emission area EA1. For example, the first conductive lines CTP1 may extend in the y direction and may be separated from each other in the x direction. In an embodiment, the first conductive line CTP1 may be a line for transmitting various signals or voltages to the thin film transistor TFT1. For example, the first conductive line CTP1 may include a data line for transmitting a data voltage to the thin film transistor TFT1.

[0083] The conductive layer CTL may be arranged above the through-hole insulating layer 207 and below the first planarization layer 209 to overlap with the second emission area EA2. The conductive layer CTL may completely cover the second emission area EA2. For example, the conductive layer CTL may have an area larger than that of the second emission area EA2. In addition, the conductive layer CTL may have an area larger than that of the second body portion PE2a of the second pixel electrode PE2. Therefore, the conductive layer CTL may block external light from entering the thin film transistor TFT2 or various lines below the conductive layer CTL from the upper portion of the display device 1, thereby preventing defects in the thin film transistor TFT2 and the lines. In an embodiment, the conductive layer CTL may send the first power voltage ELVDD to the thin film transistors TFT1, TFT2, and TFT3.

[0084] The second conductive line CTP2 may be arranged above the through hole insulating layer 207 and below the first planarization layer 209 to overlap with the third emission area EA3. The second conductive lines CTP2 may be separated from each other in the third emission area EA3. For example, the second conductive lines CTP2 may extend in the y direction and may be separated from each other in the x direction. In an embodiment, the second conductive line CTP2 may be a line for transmitting various signals or voltages to the thin film transistor TFT3. For example, the second conductive line CTP2 may include a data line for transmitting a data voltage to the thin film transistor TFT3.

[0085] The first conductive line CTP1, the conductive layer CTL, and the second conductive line CTP2 may be formed of various conductive materials. For example, the first conductive line CTP1, the conductive layer CTL, and the second conductive line CTP2 may each include at least one material selected from the group consisting of copper, titanium, and aluminum. For example, the first conductive line CTP1, the conductive layer CTL, and the second conductive line CTP2 may each have a three-layer structure including a titanium layer, an aluminum layer, and a titanium layer.

[0086] In an embodiment, the first conductive line CTP1, the conductive layer CTL, and the second conductive line CTP2 may be formed substantially simultaneously. For example, after a metal layer is completely formed on the via insulating layer 207, the metal layer is etched to form the first conductive line CTP1, the conductive layer CTL, and the second conductive line CTP2.

[0087] The first planarization layer 209 may be arranged on the first conductive line CTP1, the conductive layer CTL, and the second conductive line CTP2. The first planarization layer 209 may cover the first conductive line CTP1, the conductive layer CTL, and the second conductive line CTP2 on the through hole insulating layer 207. The first planarization layer 209 may include an organic insulating material. The first planarization layer 209 may be completely arranged in the display area DA. The first planarization layer 209 may be completely arranged in the first emission area EA1, the second emission area EA2, and the third emission area EA3.

[0088] The second planarization layer 211 may be disposed on the first planarization layer 209. The second planarization layer 211 may be disposed on the first planarization layer 209 to overlap only some of the first emission area EA1, the second emission area EA2, and the third emission area EA3. For example, the second planarization layer 211 may not be formed in the second emission area EA2 overlapping the conductive layer CTL, and may be formed to correspond only to the first emission area EA1 and the third emission area EA3 overlapping the first conductive line CTP1 and the second conductive line CTP2. In other words, the second planarization layer 211 may overlap the first emission area EA1 and the third emission area EA3, and may not overlap the second emission area EA2.

[0089] In the first planarization layer 209, the first portion overlapping the conductive layer CTL having a large area may provide a substantially flat upper surface, but the second portion overlapping the first conductive line CTP1 and the third portion overlapping the second conductive line CTP2 may each provide a more or less uneven upper surface. In this case, when the second planarization layer 211 is not arranged and the first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode PE3 are directly arranged on the upper surface of the first planarization layer 209, the flatness of each of the first pixel electrode PE1 overlapping the first conductive line CTP1 and the third pixel electrode PE3 overlapping the second conductive line CTP2 may be reduced, and therefore, external light is asymmetrically reflected by the first pixel electrode PE1 and the third pixel electrode PE3, and a reflection color band phenomenon in which asymmetrical color separation occurs around the reflected light may occur. At the same time, when the first planarization layer 209 is formed to be thick or the second planarization layer 211 is completely formed in the display area DA to increase the flatness of each of the first pixel electrode PE1 and the third pixel electrode PE3, the first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode PE3 may be reduced as the volume of the organic insulating layer increases. In order to prevent this, in the display device 1 according to the embodiment, as the second planarization layer 211 is not formed in the second emission area EA2 (a region with high flatness of the upper surface of the first planarization layer 209) overlapping the conductive layer CTL and is formed to correspond only to the first emission area EA1 and the third emission area EA3 (a region with low flatness of the upper surface of the first planarization layer 209) overlapping the first conductive line CTP1 and the second conductive line CTP2, the reflection color band phenomenon is prevented or reduced, and at the same time the increase in the volume of the organic insulating layer is minimized, so that the phenomenon in which the first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode PE3 are reduced can be prevented or reduced.

[0090] In an embodiment, the second planarization layer 211 may include island patterns arranged separately from each other. For example, the second planarization layer 211 may include a first island pattern 211a overlapping the first emission area EA1 and a second island pattern 211b overlapping the third emission area EA3. The first island pattern 211a and the second island pattern 211b are described in detail in the following description.

[0091] In an embodiment, the height h1 of the first planarization layer 209 and the height h2 of the second planarization layer 211 may be substantially the same. For example, the height h1 of the first planarization layer 209 and the height h2 of the second planarization layer 211 may both be about 1 μm to about 2 μm. In another embodiment, the height h1 of the first planarization layer 209 and the height h2 of the second planarization layer 211 may be different from each other.

[0092] In an embodiment, the first planarization layer 209 and the second planarization layer 211 may be formed by using the same material. In addition, the first planarization layer 209 and the second planarization layer 211 may be formed by different processes. For example, the first planarization layer 209 may be formed by coating an organic insulating material on the through hole insulating layer 207 to cover the first conductive line CTP1, the conductive layer CTL, and the second conductive line CTP2. Next, a first contact hole may be formed in the first planarization layer 209. In addition, after an organic layer is formed by coating an organic insulating material on the first planarization layer 209, a portion of the organic layer is removed to form the second planarization layer 211 including the first island pattern 211a and the second island pattern 211b. In addition, when necessary, a portion of the organic layer may be removed, and a second contact hole may be formed in the second planarization layer 211 at the same time. In this case, when the first contact hole and the second contact hole overlap each other, the second contact hole may be formed to be larger than the first contact hole. For example, the first contact hole of the first planarization layer 209 and the second contact hole of the second planarization layer 211 may each have a structure with a stepped cross section.

[0093] In the first emission area EA1, the first organic light emitting diode OLED1 may be disposed on the first island pattern 211a of the second planarization layer 211. In the second emission area EA2, the second organic light emitting diode OLED2 may be disposed on the first planarization layer 209. In the third emission area EA3, the third organic light emitting diode OLED3 may be disposed on the second island pattern 211b of the second planarization layer 211.

[0094] The first organic light emitting diode OLED1 may include a first pixel electrode PE1, a first intermediate layer ML1 and a common electrode CE. The second organic light emitting diode OLED2 may include a second pixel electrode PE2, a second intermediate layer ML2 and a common electrode CE. The third organic light emitting diode OLED3 may include a third pixel electrode PE3, a third intermediate layer ML3 and a common electrode CE.

[0095] The first pixel electrode PE1 may be a reflective electrode. In this case, the first pixel electrode PE1 may include a reflective film including silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr) and compounds thereof, and a transparent or semi-transparent conductive layer formed on the reflective film. The transparent or semi-transparent conductive layer may include a material selected from the group consisting of indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In 2 O 3 ), at least one material selected from the group consisting of indium gallium oxide (IGO) and aluminum zinc oxide (AZO). For example, the first pixel electrode PE1 may have a stack structure of ITO / Ag / ITO.

[0096] At least a portion of the first pixel electrode PE1 may be disposed on an upper surface of the first island pattern 211a of the second planarization layer 211 to overlap the first emission area EA1. In an embodiment, a lower surface of the first pixel electrode PE1 may contact an upper surface of the first island pattern 211a of the second planarization layer 211.

[0097] In an embodiment, the first pixel electrode PE1 may include a first body portion PE1a and a first contact portion PE1b extending from the first body portion PE1a. The first body portion PE1a may overlap the entire first emission area EA1. For example, the area of ​​the first body portion PE1a may be greater than that of the first emission area EA1.

[0098] In an embodiment, the first island pattern 211a of the second planarization layer 211 may overlap the entire first body portion PE1a of the first pixel electrode PE1. For example, the area of ​​the first island pattern 211a may be greater than the area of ​​the first body portion PE1a. In detail, the area of ​​the upper surface of the first island pattern 211a may be greater than the area of ​​the lower surface of the first body portion PE1a. In other words, the entire first body portion PE1a may be arranged on the upper surface of the first island pattern 211a.

[0099] In an embodiment, the first body portion PE1a may have a planar shape corresponding to the first emission area EA1, and the first island pattern 211a may have a planar shape corresponding to the first body portion PE1a. Figure 4 The first emission area EA1, the first body portion PE1a, and the first island pattern 211a are each illustrated to have a circular planar shape, but the present disclosure is not limited thereto. In another embodiment, each of the first emission area EA1, the first body portion PE1a, and the first island pattern 211a may have various planar shapes such as a polygon, a polygon with rounded corners, and an ellipse.

[0100] The first contact portion PE1b may extend from the first body portion PE1a. In an embodiment, the first contact portion PE1b may extend along the inclined surface of the first island pattern 211a, and an end portion of the first contact portion PE1b may be disposed on an upper surface of the first planarization layer 209. The end portion of the first contact portion PE1b may be electrically connected to the source electrode SE or the drain electrode DE of the thin film transistor TFT1 via the through-hole insulating layer 207 and a contact hole formed in the first planarization layer 209. Therefore, the first pixel electrode PE1 may be electrically connected to the thin film transistor TFT1.

[0101] The second pixel electrode PE2 may be a reflective electrode. At least a portion of the second pixel electrode PE2 may be disposed on the upper surface of the first planarization layer 209 to overlap the second emission area EA2. In an embodiment, the lower surface of the second pixel electrode PE2 may contact the upper surface of the first planarization layer 209.

[0102] In an embodiment, the second pixel electrode PE2 may include a second body portion PE2a and a second contact portion PE2b extending from the second body portion PE2a. The second body portion PE2a may overlap the entire second emission area EA2. For example, the area of ​​the second body portion PE2a may be greater than the area of ​​the second emission area EA2. In an embodiment, the second body portion PE2a may have a planar shape corresponding to the second emission area EA2.

[0103] The second contact portion PE2b may extend from the second body portion PE2a. In an embodiment, the second contact portion PE2b may be disposed on an upper surface of the first planarization layer 209. An end portion of the second contact portion PE2b may be electrically connected to the source electrode SE or the drain electrode DE of the thin film transistor TFT2 via the through-hole insulating layer 207 and a contact hole formed in the first planarization layer 209. Therefore, the second pixel electrode PE2 may be electrically connected to the thin film transistor TFT2.

[0104] The third pixel electrode PE3 may be a reflective electrode. At least a portion of the third pixel electrode PE3 may be arranged on the upper surface of the second island pattern 211b of the second planarization layer 211 to overlap the third emission area EA3. In an embodiment, the lower surface of the third pixel electrode PE3 may contact the upper surface of the second island pattern 211b of the second planarization layer 211.

[0105] In an embodiment, the third pixel electrode PE3 may include a third body portion PE3a and a third contact portion PE3b extending from the third body portion PE3a. The third body portion PE3a may overlap the entire third emission area EA3. For example, the area of ​​the third body portion PE3a may be greater than the area of ​​the third emission area EA3.

[0106] In an embodiment, the second island pattern 211b of the second planarization layer 211 may overlap the entire third body portion PE3a of the third pixel electrode PE3. For example, the area of ​​the second island pattern 211b may be greater than the area of ​​the third body portion PE3a. In detail, the area of ​​the upper surface of the second island pattern 211b may be greater than the area of ​​the lower surface of the third body portion PE3a. In other words, the entire third body portion PE3a may be arranged on the upper surface of the second island pattern 211b.

[0107] The third body portion PE3a may have a planar shape corresponding to the third emission area EA3, and the second island pattern 211b may have a planar shape corresponding to the third body portion PE3a.

[0108] The third contact portion PE3b may extend from the third body portion PE3a. In an embodiment, the third contact portion PE3b may extend along the inclined surface of the second island pattern 211b, and an end portion of the third contact portion PE3b may be arranged on the upper surface of the first planarization layer 209. The end portion of the third contact portion PE3b may be electrically connected to the source electrode SE or the drain electrode DE of the thin film transistor TFT3 via the through-hole insulating layer 207 and the contact hole formed in the first planarization layer 209. Therefore, the third pixel electrode PE3 may be electrically connected to the thin film transistor TFT3.

[0109] In an embodiment, as the first pixel electrode PE1 and the third pixel electrode PE3 are disposed on the upper surface of the second planarization layer 211, and the second pixel electrode PE2 is disposed on the upper surface of the first planarization layer 209, some of the first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode PE3 may have different levels. For example, a distance d1 between the upper surface of the substrate 100 and the lower surface of the first body portion PE1a of the first pixel electrode PE1 may be greater than a distance d2 between the upper surface of the substrate 100 and the lower surface of the second body portion PE2a of the second pixel electrode PE2. For example, a distance d3 between the upper surface of the substrate 100 and the lower surface of the third body portion PE3a of the third pixel electrode PE3 may be greater than a distance d2 between the upper surface of the substrate 100 and the lower surface of the second body portion PE2a of the second pixel electrode PE2. For example, a distance d1 between the upper surface of the substrate 100 and the lower surface of the first body portion PE1a of the first pixel electrode PE1 may be substantially the same as a distance d3 between the upper surface of the substrate 100 and the lower surface of the third body portion PE3a of the third pixel electrode PE3.

[0110] In an embodiment, the areas of the first emission area EA1, the second emission area EA2, and the third emission area EA3 may be different from each other. For example, the area of ​​the second emission area EA2 may be smaller than the areas of the first emission area EA1 and the third emission area EA3, and the area of ​​the third emission area EA3 may be larger than the area of ​​the first emission area EA1. In this case, the areas of the first body portion PE1a, the second body portion PE2a, and the third body portion PE3a of the first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode PE3 may be different from each other. For example, the area of ​​the second body portion PE2a may be smaller than the areas of the first body portion PE1a and the third body portion PE3a, and the area of ​​the third body portion PE3a may be larger than the area of ​​the first body portion PE1a. In addition, the areas of the first island pattern 211a and the second island pattern 211b of the second planarization layer 211 may be different from each other. For example, the area of ​​the second island pattern 211b may be larger than the area of ​​the first island pattern 211a.

[0111] In an embodiment, a distance d4 between an edge of the first body portion PE1a and an edge of the first island pattern 211a may be substantially the same as a distance d5 between an edge of the third body portion PE3a and an edge of the second island pattern 211b. For example, the distance d4 between an edge of the first body portion PE1a and an edge of the first island pattern 211a and the distance d5 between an edge of the third body portion PE3a and an edge of the second island pattern 211b may both be about 1.5 μm to about 2.5 μm. In another embodiment, the distance d4 between an edge of the first body portion PE1a and an edge of the first island pattern 211a may be different from the distance d5 between an edge of the third body portion PE3a and an edge of the second island pattern 211b.

[0112] The pixel defining film 213 may be arranged on the first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode PE3. The pixel defining film 213 may have pixel openings 213OP that expose central portions of the first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode PE3, respectively. For example, the pixel defining film 213 may have a first pixel opening 213OP1 that exposes a central portion of a first body portion PE1a of the first pixel electrode PE1, a second pixel opening 213OP2 that exposes a central portion of a second body portion PE2a of the second pixel electrode PE2, and a third pixel opening 213OP3 that exposes a central portion of a third body portion PE3a of the third pixel electrode PE3.

[0113] In an embodiment, the pixel defining film 213 may cover the edge of the second planarization layer 211. For example, the pixel defining film 213 may cover the edge of the first island pattern 211a, and the first pixel opening 213OP1 may expose the central portion of the first island pattern 211a. The pixel defining film 213 may cover the edge of the second island pattern 211b, and the second pixel opening 213OP2 may expose the central portion of the second island pattern 211b.

[0114] The pixel defining film 213 may include an organic insulating material. Alternatively, the pixel defining film 213 may include an inorganic insulating material such as silicon nitride, silicon oxynitride or silicon oxide. Alternatively, the pixel defining film 213 may include an organic insulating material and an inorganic insulating material. In an embodiment, the pixel defining film 213 may include a light-blocking material and may be black. The light-blocking material may include a resin or paste containing carbon black, carbon nanotubes or a black dye, metal particles such as nickel, aluminum, molybdenum and their alloys, metal oxide particles (e.g., chromium oxide) or metal nitride particles (e.g., chromium nitride). When the pixel defining film 213 includes a light-blocking material, the reflection of external light by the metal structure arranged below the pixel defining film 213 may be reduced. However, the present disclosure is not limited thereto. In another embodiment, the pixel defining film 213 may not include a light-blocking material, but may include a light-transmitting organic insulating material.

[0115] The first middle layer ML1 including the first common layer CL1, the first emission layer EL1, and the second common layer CL2 may be disposed on the first pixel electrode PE1 and the pixel defining film 213. The second middle layer ML2 including the first common layer CL1, the second emission layer EL2, and the second common layer CL2 may be disposed on the second pixel electrode PE2 and the pixel defining film 213. The third middle layer ML3 including the first common layer CL1, the third emission layer EL3, and the second common layer CL2 may be disposed on the third pixel electrode PE3 and the pixel defining film 213.

[0116] The first emission layer EL1 may be arranged in the first pixel opening 213OP1 of the pixel defining film 213. The first emission layer EL1 may be a low molecular weight or polymer organic material including a fluorescent or phosphorescent material capable of emitting blue light, green light, or red light. Alternatively, the first emission layer EL1 may be an inorganic material including quantum dots. In particular, quantum dots refer to crystals of semiconductor compounds and may include any material capable of emitting light of various emission wavelengths according to the size of the crystals. Quantum dots may include, for example, III-VI semiconductor compounds, II-VI semiconductor compounds, III-V semiconductor compounds, III-VI semiconductor compounds, I-III-VI semiconductor compounds, IV-VI semiconductor compounds, IV elements or compounds, or any combination thereof. For example, the first emission layer EL1 may emit red light.

[0117] The second emission layer EL2 may be arranged in the second pixel opening 213OP2 of the pixel defining film 213. The second emission layer EL2 may be a low molecular weight or polymer organic material containing a fluorescent or phosphorescent material capable of emitting blue light, green light, or red light. Alternatively, the second emission layer EL2 may be an inorganic material containing quantum dots. For example, the second emission layer EL2 may emit green light.

[0118] The third emission layer EL3 may be arranged in the third pixel opening 213OP3 of the pixel defining film 213. The third emission layer EL3 may be a low molecular weight or polymer organic material containing a fluorescent or phosphorescent material capable of emitting blue light, green light, or red light. Alternatively, the third emission layer EL3 may be an inorganic material containing quantum dots. For example, the third emission layer EL3 may emit blue light.

[0119] The first common layer CL1 and the second common layer CL2 may be arranged under and on the first emission layer EL1, the second emission layer EL2, and the third emission layer EL3, respectively. The first common layer CL1 may include, for example, a hole transport layer (HTL), or may include a hole transport layer and a hole injection layer (HIL). The second common layer CL2 may include, for example, an electron transport layer (ETL), or may include an electron transport layer and an electron injection layer (EIL). In an embodiment, the second common layer CL2 may not be provided.

[0120] The first emission layer EL1, the second emission layer EL2, and the third emission layer EL3 may be arranged in corresponding pixels to respectively correspond to the first pixel opening 213OP1, the second pixel opening 213OP2, and the third pixel opening 213OP3 of the pixel defining film 213, and the first common layer CL1 and the second common layer CL2 may be integrally formed to completely cover the substrate 100. In other words, the first common layer CL1 and the second common layer CL2 may be integrally formed to completely cover the display area DA of the substrate 100.

[0121] The common electrode CE may be a cathode serving as an electron injection electrode. The common electrode CE may include a conductive material having a low work function. For example, the common electrode CE may include a (semi) transparent layer containing silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), ytterbium (Yb) or an alloy thereof. For example, the common electrode CE may be AgMg or AgYb. Alternatively, the common electrode CE may also include a (semi) transparent layer containing the above-mentioned materials such as ITO, IZO, ZnO or In 2 O 3 layer.

[0122] In an embodiment, the display device 1 may further include a cover layer 230 disposed on the first organic light emitting diode OLED1, the second organic light emitting diode OLED2, and the third organic light emitting diode OLED3. According to the principle of constructive interference, the cover layer 230 may be used to increase the light emitting efficiency of the first organic light emitting diode OLED1, the second organic light emitting diode OLED2, and the third organic light emitting diode OLED3. The cover layer 230 may include, for example, a material having a refractive index of 1.6 or greater with respect to light of a wavelength of 589 nm.

[0123] The capping layer 230 may be an organic capping layer comprising an organic material, an inorganic capping layer comprising an inorganic material, or a composite capping layer comprising an organic material and an inorganic material. For example, the capping layer 230 may include a carbocyclic compound, a heterocyclic compound, an amine-containing compound, a porphyrin derivative, a phthalocyanine derivative, a naphthalocyanine derivative, an alkali metal complex, an alkaline earth metal complex, or any combination thereof. The carbocyclic compound, the heterocyclic compound, and the amine-containing compound may be selectively substituted with a substituent comprising O, N, S, Se, Si, F, Cl, Br, I, or any combination thereof.

[0124] The low reflection layer 300 may be disposed on the cap layer 230. Since the cap layer 230 may be disposed on the first organic light emitting diode OLED1, the second organic light emitting diode OLED2, and the third organic light emitting diode OLED3, the low reflection layer 300 may be disposed on the first organic light emitting diode OLED1, the second organic light emitting diode OLED2, and the third organic light emitting diode OLED3. The low reflection layer 300 may include an inorganic material having a low reflectivity, and in an embodiment, may include a metal or a metal oxide. When the low reflection layer 300 includes a metal, for example, the low reflection layer 300 may include ytterbium (Yb), bismuth (Bi), cobalt (Co), molybdenum (Mo), titanium (Ti), zirconium (Zr), aluminum (Al), chromium (Cr), niobium (Nb), platinum (Pt), tungsten (W), indium (In), tin (Sn), iron (Fe), nickel (Ni), tantalum (Ta), manganese (Mn), zinc (Zn), germanium (Ge), silver (Ag), magnesium (Mg), gold (Au), copper (Cu), calcium (Ca), or a combination thereof. In addition, when the low reflection layer 300 includes a metal oxide, for example, the low reflection layer 300 may include SiO 2 、TiO 2 、ZrO 2 、 2 O 5 , HfO 2 、Al 2 O 3 , ZnO, Y 2 O 3 , BeO, MgO, PbO 2 , WO 3、SiNx、LiF、CaF 2 MgF 2 , CdS or a combination thereof.

[0125] In an embodiment, the inorganic material included in the low reflection layer 300 may have an absorption coefficient (k) of at least 0.5 and not more than 4.0 (0.5≤k≤4.0). In addition, the inorganic material included in the low reflection layer 300 may have a refractive index (n) of 1 or more (n≥1.0).

[0126] The low-reflection layer 300 causes destructive interference between light incident into the inside of the display device 1 and light reflected by the metal arranged below the low-reflection layer 300, thereby reducing the external light reflectivity. Therefore, the display quality and visibility of the display device 1 can be improved by reducing the external light reflectivity of the display device 1 through the low-reflection layer 300.

[0127] Figure 5 A structure in which the low-reflection layer 300 is arranged on the entire surface of the substrate 100 like the common electrode CE and the capping layer 230 is illustrated, but the present disclosure is not limited thereto. In another embodiment, the low-reflection layer 300 may be patterned and provided for each pixel P. In this case, the low-reflection layer 300 may be patterned to correspond to the emission area EA of each pixel P, and the area of ​​the low-reflection layer 300 may be equal to or greater than the area of ​​the emission area EA.

[0128] The thin film encapsulation layer 400 may be disposed on the low reflection layer 300. The thin film encapsulation layer 400 may include at least one inorganic film layer and at least one organic film layer. For example, the thin film encapsulation layer 400 may include a first inorganic encapsulation layer 410, an organic encapsulation layer 420, and a second inorganic encapsulation layer 430 stacked sequentially.

[0129] The first inorganic encapsulation layer 410 and the second inorganic encapsulation layer 430 may include silicon oxide (SiO 2 ), silicon nitride (SiN X ), silicon oxynitride (SiON), aluminum oxide (Al 2 O 3 ), titanium oxide (TiO 2 ), Tantalum Oxide (Ta 2 O 5 ), hafnium oxide (HfO 2 ) or zinc oxide (ZnO) inorganic insulating material. The first inorganic encapsulating layer 410 and the second inorganic encapsulating layer 430 may each have a single layer or multi-layer structure including the above inorganic insulating material.

[0130] The organic encapsulation layer 420 can relieve the internal stress of the first inorganic encapsulation layer 410 or the second inorganic encapsulation layer 430. The organic encapsulation layer 420 may include a polymer-based material. The polymer-based material may include polyethylene terephthalate, polyethylene naphthalate, polycarbonate, polyimide, polyethylene sulfonate, polyoxymethylene, polyarylate, hexamethyldisiloxane, acrylic resin (e.g., polymethyl methacrylate or polyacrylic acid), or any combination thereof.

[0131] The organic encapsulation layer 420 may be formed by coating a material having fluidity and including a monomer, and then reacting the monomer to combine and form a polymer by using heat or light such as ultraviolet rays. Alternatively, the organic encapsulation layer 420 may be formed by coating a polymer material.

[0132] Even when cracks occur in the thin film encapsulation layer 400 due to the above-mentioned multi-layer structure, the thin film encapsulation layer 400 may allow the cracks not to be connected between the first inorganic encapsulation layer 410 and the organic encapsulation layer 420 or between the organic encapsulation layer 420 and the second inorganic encapsulation layer 430. Therefore, formation of a path through which external moisture or oxygen penetrates into the display area DA may be prevented or minimized.

[0133] In an embodiment, when the thin film encapsulation layer 400 is disposed on the first organic light emitting diode OLED1, the second organic light emitting diode OLED2, and the third organic light emitting diode OLED3, the substrate 100 may include a polymer resin. However, the present disclosure is not limited thereto.

[0134] The touch sensor layer 500 may be disposed on the thin film encapsulation layer 400. The touch sensor layer 500 may include a first conductive layer MTL1, a first touch insulating layer 510, a second conductive layer MTL2, and a second touch insulating layer 520. The first conductive layer MTL1 may be directly disposed on the thin film encapsulation layer 400. In this case, the first conductive layer MTL1 may be directly disposed on the second inorganic encapsulation layer 430 of the thin film encapsulation layer 400. However, the present disclosure is not limited thereto.

[0135] In addition, the touch sensor layer 500 may include an insulating film (not shown) arranged between the first conductive layer MTL1 and the thin film encapsulation layer 400. The insulating film may be arranged on the second inorganic encapsulation layer 430 of the thin film encapsulation layer 400 to make the surface on which the first conductive layer MTL1 and the like are arranged flat. In this case, the first conductive layer MTL1 may be directly arranged on the insulating film. The insulating film may include a silicon oxide (SiO 2 ), silicon nitride (SiN X ) or an inorganic insulating material such as silicon oxynitride (SiON). Alternatively, the insulating film may include an organic insulating material.

[0136] In an embodiment, the first touch insulating layer 510 may be arranged on the first conductive layer MTL1. The first touch insulating layer 510 may include an inorganic material or an organic material. When the first touch insulating layer 510 includes an inorganic material, the first touch insulating layer 510 may include at least one material selected from the group including silicon nitride, aluminum nitride, zirconium nitride, titanium nitride, hafnium nitride, tantalum nitride, silicon oxide, aluminum oxide, titanium oxide, tin oxide, cerium oxide, and silicon oxynitride. When the first touch insulating layer 510 includes an organic material, the first touch insulating layer 510 may include at least one material selected from the group including acrylic resin, methacrylic resin, polyisoprene, vinyl resin, epoxy resin, urethane-based resin, cellulose-based resin, and perylene-based resin.

[0137] In an embodiment, the second conductive layer MTL2 may be arranged on the first touch insulating layer 510. The second conductive layer MTL2 may be used as a sensor for detecting a user's touch input. The first conductive layer MTL1 may be used as a connector for connecting the patterned second conductive layer MTL2 in one direction. In an embodiment, both the first conductive layer MTL1 and the second conductive layer MTL2 may be used as sensors. In this case, the first conductive layer MTL1 and the second conductive layer MTL2 may be electrically connected to each other through the contact hole CH. Therefore, since both the first conductive layer MTL1 and the second conductive layer MTL2 are used as sensors, the resistance of the touch electrode is reduced, and thus the user's touch input may be quickly detected.

[0138] In an embodiment, the first conductive layer MTL1 and the second conductive layer MTL2 may each have, for example, a mesh structure so that light emitted from the first organic light emitting diode OLED1, the second organic light emitting diode OLED2, and the third organic light emitting diode OLED3 may pass therethrough. In this case, the first conductive layer MTL1 and the second conductive layer MTL2 may be arranged so as not to overlap with the first emission area EA1, the second emission area EA2, and the third emission area EA3 of the first organic light emitting diode OLED1, the second organic light emitting diode OLED2, and the third organic light emitting diode OLED3.

[0139] The first conductive layer MTL1 and the second conductive layer MTL2 may include a metal layer or a transparent conductive layer. The metal layer may include molybdenum (Mo), silver (Ag), titanium (Ti), copper (Cu), aluminum (Al), and alloys thereof. The transparent conductive layer may include a transparent conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), or indium tin zinc oxide (ITZO). In addition, the transparent conductive layer may include a conductive polymer such as PEDOT, metal nanowires, carbon nanotubes, or graphene.

[0140] In an embodiment, the second touch insulating layer 520 may be arranged on the second conductive layer MTL2. The second touch insulating layer 520 may include an inorganic material or an organic material. When the second touch insulating layer 520 includes an inorganic material, the second touch insulating layer 520 may include at least one material selected from the group including silicon nitride, aluminum nitride, zirconium nitride, titanium nitride, hafnium nitride, tantalum nitride, silicon oxide, aluminum oxide, titanium oxide, tin oxide, cerium oxide, and silicon oxynitride. When the second touch insulating layer 520 includes an organic material, the second touch insulating layer 520 may include at least one material selected from the group including acrylic resin, methacrylic resin, polyisoprene, vinyl resin, epoxy resin, urethane-based resin, cellulose-based resin, and perylene-based resin.

[0141] The anti-reflection layer 600 may be disposed on the touch sensor layer 500. The anti-reflection layer 600 may include a light blocking layer 610 and a color filter layer 621. In an embodiment, the anti-reflection layer 600 may further include an overcoat layer 625 disposed on the light blocking layer 610 and the color filter layer 621.

[0142] The light blocking layer 610 may include a material capable of blocking light. For example, the light blocking layer 610 may include an organic material having a high light absorptivity. The light blocking layer 610 may include a black pigment or a black dye. The light blocking layer 610 may include a photosensitive organic material and may include, for example, a colorant such as a pigment or a dye.

[0143] The light blocking layer 610 includes an opening 610OP overlapping the emission area EA. The opening 610OP may include a first opening 610OP1, a second opening 610OP2, and a third opening 610OP3 corresponding to the first organic light emitting diode OLED1, the second organic light emitting diode OLED2, and the third organic light emitting diode OLED3, respectively. The emission area EA may be defined by the pixel opening 213OP of the pixel defining film 213, and in an embodiment, the opening 610OP of the light blocking layer 610 may overlap with the pixel opening 213OP of the pixel defining film 213, and the width of the opening 610OP of the light blocking layer 610 may be greater than the width of the pixel opening 213OP of the pixel defining film 213.

[0144] The body portion of the light blocking layer 610 including the opening 610OP may overlap with the body portion of the pixel defining film 213. For example, the body portion of the light blocking layer 610 may overlap only with the body portion of the pixel defining film 213. The body portion of the light blocking layer 610 is different from the opening 610OP of the light blocking layer 610 and refers to a portion having a specific volume (thickness). Similarly, the body portion of the pixel defining film 213 is different from the pixel opening 213OP of the pixel defining film 213 and refers to a portion having a specific volume.

[0145] The color filter layer 621 may include first, second, and third color filters 621 a , 621 b , and 621 c of different colors corresponding to the first, second, and third organic light emitting diodes OLED1 , OLED2 , and OLED3 , respectively.

[0146] In an embodiment, the first color filter 621a, the second color filter 621b, and the third color filter 621c may be arranged in the first opening 610OP1, the second opening 610OP2, and the third opening 610OP3 of the light blocking layer 610, respectively. In an embodiment, the first color filter 621a, the second color filter 621b, and the third color filter 621c may have colors corresponding to the light emitted from the first organic light emitting diode OLED1, the second organic light emitting diode OLED2, and the third organic light emitting diode OLED3, respectively. In an embodiment, when the first organic light emitting diode OLED1 emits red light, the first color filter 621a may be a red color filter, when the second organic light emitting diode OLED2 emits green light, the second color filter 621b may be a green color filter, and when the third organic light emitting diode OLED3 emits blue light, the third color filter 621c may be a blue color filter. The light blocking layer 610 may be arranged between adjacent color filters, and may be arranged to surround an edge of each of the first pixel P1 , the second pixel P2 , and the third pixel P3 .

[0147] The overcoat layer 625 may be disposed on the light blocking layer 610 and the color filter layer 621. The overcoat layer 625 is a colorless light transmission layer that does not have a color in the visible light band, and may flatten the upper surface of the light blocking layer 610 and the upper surface of the color filter layer 621. The overcoat layer 625 may include a colorless light transmission organic material such as an acrylic resin, and may be covered with a window (not shown). The window may include a transparent (light transmission) material. For example, the window may include a glass substrate or a polymer substrate.

[0148] As described above, according to the embodiment, a display device with improved display quality can be realized by reducing a reflective color banding phenomenon caused by asymmetric reflection of external light. However, the scope of the present disclosure is not limited thereto.

[0149] It should be understood that the embodiments described herein should be considered in a descriptive sense only and not for limiting purposes. The description of features or aspects within each embodiment should generally be considered as other similar features or aspects that can be used in other embodiments. Although one or more embodiments have been described with reference to the figures, it will be understood by those of ordinary skill in the art that various changes in form and detail may be made therein without departing from the scope and spirit as defined in the appended claims.

Claims

1. A display device, characterized in that: include: substrate; a first planarization layer, the first planarization layer being arranged on the substrate; A first light-emitting element, a second light-emitting element, and a third light-emitting element, wherein the first light-emitting element, the second light-emitting element, and the third light-emitting element are arranged on the first planarization layer, and the first light-emitting element includes a first emission region, the second light-emitting element includes a second emission region, and the third light-emitting element includes a third emission region, and the first emission region, the second emission region, and the third emission region emit light of different wavelengths; as well as a second planarization layer, the second planarization layer being arranged between the first planarization layer and the first emission region, The first emission region overlaps with the second planarization layer, and the second emission region does not overlap with the second planarization layer.

2. The display device according to claim 1, characterized in that The second planarization layer is also arranged between the first planarization layer and the third emission region.

3. The display device according to claim 1, characterized in that Also includes: a plurality of first conductive lines arranged under the first planarization layer to overlap the first emission region and spaced apart from each other under the first emission region; as well as a conductive layer, the conductive layer being arranged below the first planarization layer to overlap with the second emission region, Wherein, the second emission region covers the conductive layer.

4. The display device according to claim 1, characterized in that The first pixel electrode of the first light emitting element is arranged on the upper surface of the second planarization layer, and The second pixel electrode of the second light emitting element is arranged on the upper surface of the first planarization layer.

5. The display device according to claim 4, characterized in that The first pixel electrode includes a first body portion overlapping the first emission region and a first contact portion extending from the first body portion. The second pixel electrode includes a second body portion overlapping the second emission region and a second contact portion extending from the second body portion, and An area of ​​the second planarization layer below the first emission region is larger than an area of ​​the first body portion.

6. The display device according to claim 5, characterized in that A distance between an upper surface of the substrate and a lower surface of the first body portion is greater than a distance between the upper surface of the substrate and a lower surface of the second body portion.

7. A display device, characterized in that: include: substrate; a first planarization layer, the first planarization layer being arranged on the substrate; A first light-emitting element, a second light-emitting element, and a third light-emitting element, wherein the first light-emitting element, the second light-emitting element, and the third light-emitting element are arranged on the first planarization layer, and the first light-emitting element includes a first emission region, the second light-emitting element includes a second emission region, and the third light-emitting element includes a third emission region, and the first emission region, the second emission region, and the third emission region emit light of different wavelengths; a second planarization layer, the second planarization layer comprising a first island pattern arranged between the first planarization layer and the first emission region and a second island pattern arranged between the first planarization layer and the third emission region; a first pixel electrode disposed on an upper surface of the first island pattern to overlap the first emission region; a second pixel electrode, the second pixel electrode being arranged on an upper surface of the first planarization layer to overlap with the second emission region; as well as A third pixel electrode is disposed on an upper surface of the second island pattern to overlap the third emission region.

8. The display device according to claim 7, characterized in that Also includes: a plurality of first conductive lines arranged under the first planarization layer to overlap the first emission region and spaced apart from each other under the first emission region; a conductive layer, the conductive layer being arranged below the first planarization layer to overlap with the second emission region; as well as a plurality of second conductive lines arranged under the first planarization layer to overlap the third emission region and spaced apart from each other under the third emission region, Wherein, the second emission region covers the conductive layer.

9. The display device according to claim 7, characterized in that: The lower surface of the first pixel electrode contacts the upper surface of the first island pattern. The lower surface of the second pixel electrode contacts the upper surface of the first planarization layer, and A lower surface of the third pixel electrode contacts the upper surface of the second island pattern.

10. The display device according to claim 7, characterized in that The first pixel electrode includes a first body portion overlapping the first emission region and a first contact portion extending from the first body portion. The second pixel electrode includes a second body portion overlapping the second emission region and a second contact portion extending from the second body portion. The third pixel electrode includes a third body portion overlapping the third emission region and a third contact portion extending from the third body portion, The area of ​​the first island pattern is larger than the area of ​​the first body portion, and An area of ​​the second island pattern is greater than an area of ​​the third body portion.

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