Display device

Abstract

A display device according to an embodiment includes a transistor disposed on a substrate, a first conductive layer electrically connected to the transistor, a first metal layer electrically connected to the first conductive layer, a first electrode electrically connected to the first metal layer, and an emission layer electrically connected to the first electrode. The first metal layer includes a first layer including Zn-ITO, a second layer including Ag, and a third layer including Zn-ITO.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0005655 filed on January 13, 2023 in the Korean Intellectual Property Office (KIPO), the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to a display device. Background Art

[0004] The light emitting element is an element in which holes supplied from an anode and electrons supplied from a cathode combine in an emission layer to form excitons and emit light while the excitons are stabilized.

[0005] Light emitting elements have several advantages such as a wide viewing angle, a fast response speed, a thin thickness, and low power consumption, so that light emitting diodes are widely used in various electric and electronic devices such as televisions, monitors, mobile phones, and the like.

[0006] The above information disclosed in this Background section is only for enhancement of understanding of the background of the present disclosure and therefore it may contain information that does not form the prior art that is already known in this country to a person of ordinary skill in the art. Utility Model Content

[0007] The present disclosure is directed to providing a display device including a first metal layer having high reflectivity and excellent interface contact characteristics.

[0008] According to an embodiment of the present disclosure, a display device may include a transistor disposed on a substrate, a first conductive layer electrically connected to the transistor, a first metal layer electrically connected to the first conductive layer, a first electrode electrically connected to the first metal layer, and an emission layer electrically connected to the first electrode. The first metal layer may include a first layer including Zn-ITO, a second layer including Ag, and a third layer including Zn-ITO.

[0009] The display device may include a display region and a pad region, and the first conductive layer, the first metal layer, and the first electrode may contact each other in the pad region.

[0010] The first conductive layer may include a first layer including titanium and a second layer including copper, and the second layer of the first conductive layer may contact the first layer of the first metal layer.

[0011] The first conductive layer may include a first layer including titanium, a second layer including copper, and a third layer including indium tin oxide, and the third layer of the first conductive layer may contact the first layer of the first metal layer.

[0012] The first electrode may include indium tin oxide, and the third layer of the first metal layer may contact the first electrode.

[0013] The second layer of the first metal layer may be thicker than the first layer of the first metal layer and the third layer of the first metal layer in a thickness direction of the substrate.

[0014] In the thickness direction of the substrate, the thickness of the first layer of the first metal layer may be about to about within the range.

[0015] In the thickness direction of the substrate, the thickness of the second layer of the first metal layer may be about to about within the range.

[0016] In the thickness direction, the thickness of the third layer of the first metal layer may be about to about within the range.

[0017] The content of Zn included in the Zn-ITO of the first and third layers may be equal to or greater than about 10 at %.

[0018] The content of Zn included in the Zn-ITO of the first and third layers may be in the range of about 18 at % to about 20 at %.

[0019] The Zn—ITO included in the first layer and the third layer may be amorphous.

[0020] In the case where the heat treatment at about 250° C. is performed, the Zn—ITO included in the first metal layer may be amorphous.

[0021] The first metal layer may not be etched by TMAH and KOH.

[0022] A reflectivity of the first metal layer at a wavelength within a range of about 400 nm to about 800 nm may be equal to or greater than about 80%.

[0023] The emissive layer may include nanorods.

[0024] The transistor may include a semiconductor layer and a gate electrode. The display device may further include a second conductive layer disposed between the semiconductor layer and the first conductive layer and electrically connecting the semiconductor layer and the first conductive layer.

[0025] The display device may further include a cell barrier disposed between the first conductive layer and the first metal layer. The cell barrier may include an opening overlapping the emission layer in a plan view.

[0026] Light emitted by the emission layer may be reflected by the first metal layer.

[0027] The semiconductor layer may include an oxide semiconductor.

[0028] According to the embodiment, a display device including a first metal layer having high reflectivity and excellent interface contact characteristics is provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 is a schematic cross-sectional view of a display region of a display device according to an embodiment.

[0030] Figure 2 is a schematic cross-sectional view of a pad region of a display device according to an embodiment.

[0031] Figure 3 is a schematic cross-sectional view of the first metal layer.

[0032] Figure 4 is a schematic cross-sectional view showing corrosion and oxidation reactions occurring at a contact interface when the first metal layer includes aluminum.

[0033] Figure 5 is a graph showing reflectivity of a first metal layer made of Zn-ITO / Ag / Zn-ITO with respect to wavelength according to an embodiment.

[0034] Figure 6 : is a graph showing XRD of Zn-ITO in which the content of Zn is about 18 at % and Zn-ITO in which the content of Zn is about 20 at % before / after heat treatment at 250° C. DETAILED DESCRIPTION

[0035] In the following detailed description, embodiments of the present disclosure are shown and described by way of example only. As those skilled in the art will appreciate, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present disclosure.

[0036] The drawings and description are to be regarded as illustrative in nature and not restrictive, and like reference numerals refer to like elements throughout the specification.

[0037] For better understanding and ease of description, the size and thickness of each configuration shown in the drawings are arbitrarily shown, but the present disclosure is not limited thereto. In the drawings, the thickness of layers, films, panels, regions, etc. are exaggerated for clarity. For ease of explanation, the thickness of some layers and regions is exaggerated.

[0038] When an element, such as a layer, is referred to as being "on," "connected to," or "coupled to" another element or layer, it may be directly on, directly connected to, or directly coupled to, another element or layer, or there may be intervening elements or layers. However, when an element or layer is referred to as being "directly on," "directly connected to," or "directly coupled to," another element or layer, there are no intervening elements or layers. For this reason, the term "connected" may refer to a physical connection, an electrical connection, and / or a fluid connection with or without an intervening element. In addition, when an element is referred to as being "in contact with" or "contacting" another element, etc., the element may be "electrically in contact with" or "physically in contact with" another element; or "indirectly in contact with" or "directly in contact with" another element.

[0039] For descriptive purposes, spatially relative terms such as "below," "beneath," "under," "down," "above," "on," "above," "above," "side" (e.g., as in "sidewall"), etc. may be used herein and thereby describe the relationship of one element to another element(s) as shown in the accompanying drawings. In addition to the orientations depicted in the accompanying drawings, spatially relative terms are intended to encompass different orientations of the device in use, operation, and / or manufacture. For example, if the device in the accompanying drawings is flipped, elements described as being "below" or "below" other elements or features will then be oriented "above" the other elements or features. Thus, the exemplary term "below" may encompass both above and below orientations. Additionally, the device may be oriented in other ways (e.g., rotated 90 degrees or in other orientations), and therefore, the spatially relative descriptors used herein are interpreted accordingly.

[0040] The terms used herein are used for the purpose of describing specific embodiments and are not intended to be limiting. As used herein, the singular forms "a", "a kind of" and "the" are intended to also include plural forms, unless the context clearly indicates otherwise. In addition, when used in this specification, the terms "comprises", "comprising", "includes" and / or "including" specify the existence of stated features, integral bodies, steps, operations, elements, components and / or groups thereof, but do not exclude the existence or addition of one or more other features, integral bodies, steps, operations, elements, components and / or groups thereof. It should also be noted that, as used herein, the terms "substantially", "about" and other similar terms are used as approximate terms and are not used as terms of degree, and therefore, are used to illustrate the inherent deviations in the values ​​measured, calculated and / or provided that will be recognized by those of ordinary skill in the art.

[0041] Although the terms "first", "second", etc. may be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another element. Therefore, without departing from the teachings of the present disclosure, the first element discussed below may be referred to as the second element.

[0042] The phrase "in a plan view" means that the target portion is viewed from the top, and the phrase "in a cross-sectional view" means that a cross section vertically cutting the target portion is viewed from the side.

[0043] For the purpose of this disclosure, "at least one of A and B" may be interpreted as only A, only B, or any combination of A and B. In addition, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" may be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0044] Unless otherwise defined or implied herein, all terms (including technical and scientific terms) used have the same meaning as commonly understood by those skilled in the art to which the present disclosure belongs. It will also be understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and should not be interpreted in an idealized or overly formal sense unless clearly defined in the specification.

[0045] A display device according to an embodiment will now be described with reference to the accompanying drawings. Figure 1 is a schematic cross-sectional view of a display region of a display device according to an embodiment. Figure 2 is a schematic cross-sectional view of a pad region of a display device according to an embodiment.

[0046] refer to Figure 1 and Figure 2 , a substrate SUB is provided. The substrate SUB may include at least one of polystyrene, polyvinyl alcohol, poly(methyl methacrylate), polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, cellulose triacetate, and cellulose acetate propionate. The substrate SUB may be a rigid substrate or a flexible substrate that can be bent, folded, or curled. The substrate SUB may be a single layer or a multilayer. The substrate SUB may have a structure in which at least one inorganic layer and at least one base layer including a polymer resin stacked in sequence are alternately stacked with each other.

[0047] The light blocking layer BML may be disposed on the substrate SUB. The light blocking layer BML may include at least one of aluminum (Al), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), chromium (Cr), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), copper (Cu), and metal oxides, and may be a single layer or a multilayer including the same. For example, the light blocking layer BML may have a double layer of Ti / Cu, but the present disclosure is not limited thereto.

[0048] The buffer layer BUF may be disposed on the light blocking layer BML. The buffer layer BUF may include silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ) and at least one of amorphous silicon (Si).

[0049] The semiconductor layer ACT may be disposed on the buffer layer BUF. The semiconductor layer ACT may include an oxide semiconductor. The oxide semiconductor may include at least one of indium (In), tin (Sn), zinc (Zn), hafnium (Hf), and aluminum (Al). For example, the semiconductor layer ACT may include indium gallium zinc oxide (IGZO). In an embodiment, the semiconductor layer ACT may include polycrystalline silicon.

[0050] The gate insulating layer GI may be disposed on the semiconductor layer ACT. The gate insulating layer GI may include silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ) and at least one of amorphous silicon (Si).

[0051] The gate electrode GE may be disposed on the gate insulating layer GI. The gate electrode GE may include at least one of aluminum (Al), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), chromium (Cr), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), copper (Cu), and metal oxides, and may be a single layer or a multilayer including the same. For example, the gate electrode GE may be a double layer of Ti / Cu, but the present disclosure is not limited thereto. The gate electrode GE may overlap the semiconductor layer ACT in a direction perpendicular to the substrate SUB.

[0052] The first insulating layer IL1 may be disposed on the gate electrode GE. The first insulating layer IL1 may include silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ) and at least one of amorphous silicon (Si).

[0053] The second conductive layer SD2 may be disposed on the first insulating layer IL1. The second conductive layer SD2 may include at least one of aluminum (Al), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), chromium (Cr), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), copper (Cu), and metal oxides, and may be a single layer or multiple layers including the same. For example, the second conductive layer SD2 may be a double layer of Ti / Cu, but the present disclosure is not limited thereto. In another embodiment, the second conductive layer SD2 may be a triple layer of Ti / Cu / ITO. The second conductive layer SD2 may contact the semiconductor layer ACT through an opening formed in the first insulating layer IL1 and the gate insulating layer GI.

[0054] The second insulating layer IL2 may be disposed on the second conductive layer SD2. The second insulating layer IL2 may include silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ) and at least one of amorphous silicon (Si).

[0055] The first conductive layer SD1 may be disposed on the second insulating layer IL2. The first conductive layer SD1 may include at least one of aluminum (Al), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), chromium (Cr), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), copper (Cu), and metal oxides, and may be a single layer or multiple layers including the same. For example, the first conductive layer SD1 may be a double layer of Ti / Cu. For example, the first conductive layer SD1 may include a first layer including titanium and a second layer including copper. However, the present disclosure is not limited thereto. In another embodiment, the first conductive layer SD1 may be a triple layer of Ti / Cu / ITO.

[0056] The first conductive layer SD1 may contact the second conductive layer SD2 through an opening formed in the second insulating layer IL2. For example, the first conductive layer SD1 may be connected to the semiconductor layer ACT through the second conductive layer SD2. In an embodiment, the first conductive layer SD1 and the second insulating layer IL2 may be omitted.

[0057] The third insulating layer IL3 may be disposed on the first conductive layer SD1. The third insulating layer IL3 may include silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ) and at least one of amorphous silicon (Si).

[0058] The cell barrier 350 may be disposed on the third insulating layer IL3. The cell barrier 350 may include an organic insulating material such as a general polymer such as poly(methyl methacrylate) (PMMA) or polystyrene (PS), a polymer derivative having a phenol-based group, an acryl-based polymer, an imide-based polymer, polyimide, or a siloxane-based polymer. For example, the cell barrier 350 may include polyimide.

[0059] The cell barrier 350 may include an opening 355. As described below, the emission layer NED may overlap with the opening 355 of the cell barrier 350 in a plan view. The emission layer NED may include nanorods arranged in one direction. A detailed description of the emission layer NED and the connection relationship will be described below.

[0060] The first metal layer MTL1 may be disposed on the cell barrier 350. The first metal layer MTL1 may contact the first conductive layer SD1 through an opening penetrating the cell barrier 350 and the third insulating layer IL3. Figure 1 As shown in FIG. 1 , the first metal layer MTL1 may be connected to the semiconductor layer ACT and the emission layer NED, and may transmit a voltage from a transistor including the semiconductor layer ACT to the emission layer NED.

[0061] The first metal layer MTL1 may reflect light emitted by the emission layer NED. The first metal layer MTL1 may be three layers. Figure 3 is a schematic cross-sectional view of the first metal layer MTL1. Figure 3 , the first metal layer MTL1 may include a first layer M1 including Zn-ITO, a second layer M2 including Ag, and a third layer M3 including Zn-ITO. The Zn in the Zn-ITO of the first layer M1 and the third layer M3 may be equal to or greater than about 10at%. The Zn-ITO of the first layer M1 and the third layer M3 may be amorphous and may remain amorphous after a heat treatment of about 250°C, so the first layer M1 and the third layer M3 may be wet etched in a subsequent process. In the case where the first metal layer MTL1 is a triple layer of Zn-ITO / Ag / Zn-ITO, the pad area may have excellent contact characteristics and high reflective characteristics. The effect of the first metal layer MTL1 according to the embodiment will be described below.

[0062] The second layer M2 of the first metal layer MTL1 may be thicker than the first layer M1 of the first metal layer MTL1 and the third layer M3 of the first metal layer MTL1 in the thickness direction of the substrate SUB. This is because the second layer M2 containing Ag may have an influence on the reflection characteristics, and in the case where the second layer M2 is thick, the second layer M2 may have excellent reflection characteristics. The first layer M1 and the third layer M3 may increase the interface characteristics with the adjacent layers, and the first layer M1 and the third layer M3 may not be thick.

[0063] For example, the thickness of the first layer M1 and the third layer M3 may be about to about In the range of . The thickness of the first layer M1 and the third layer M3 is equal to or less than about In the case of a thickness equal to or greater than about In this case, the reflectivity of the first metal layer MTL1 may be deteriorated.

[0064] The thickness of the second layer M2 can be about to about In the range of . The thickness of the second layer M2 is less than about In the case of the first metal layer MTL1 may not have sufficient reflective properties, and when the thickness of the second layer M2 is greater than about In this case, the first metal layer MTL1 may become very thick, which may be undesirable.

[0065] refer to Figure 1 The fourth insulating layer IL4 may be disposed on the first metal layer MTL1. The fourth insulating layer IL4 may include silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ) and at least one of amorphous silicon (Si).

[0066] The first electrode 191 may be disposed on the fourth insulating layer IL4. The first electrode 191 may contact the first metal layer MTL1 through the opening of the fourth insulating layer IL4. The second electrode 192 and the first electrode 191 may be disposed on the same layer. The first electrode 191 and the second electrode 192 may include a transparent conductive oxide, for example, indium tin oxide (ITO).

[0067] refer to Figure 1 , the emission layer NED may be disposed on the fourth insulating layer IL4. The emission layer NED may overlap the opening 355 of the cell barrier 350 in a plan view. The emission layer NED may include nanorods. The nanorods may be arranged in one direction, may include an inorganic material, and may emit light when receiving a voltage.

[0068] refer to Figure 1, the first electrode 191 may be connected to one side of the emission layer NED, and the second electrode 192 may be connected to the other side of the emission layer NED. The second electrode 192 may be electrically connected to another semiconductor layer ACT. The fifth insulating layer IL5 may be disposed on the upper portion of the emission layer NED to insulate the first electrode 191 and the second electrode 192 from each other. The embankment BANK may be disposed on the fourth insulating layer IL4.

[0069] Figure 1 schematically shows a cross-sectional view of a display area of ​​a display device, and Figure 2 is a schematic cross-sectional view of a pad region of a display device. Figure 2 , a buffer layer BUF and a gate insulating layer GI may be sequentially disposed on a substrate SUB. Description and reference of corresponding components Figure 1 The components described are the same, so they will be omitted. For example, Figure 2 The pad area and Figure 1 The display area may be formed by the same process, and the materials and thicknesses of corresponding layers in the display area and the pad area may be the same.

[0070] refer to Figure 2 The gate electrode GE, the first insulating layer IL1, the second conductive layer SD2, the second insulating layer IL2 and the first conductive layer SD1 may be sequentially disposed on the gate insulating layer GI. Figure 1 The constituent elements described are the same, so they will be omitted.

[0071] The first conductive layer SD1 may include at least one of aluminum (Al), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), chromium (Cr), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), copper (Cu), and metal oxides, and may be a single layer or multiple layers thereof. For example, the first conductive layer SD1 may be a double layer of Ti / Cu. In another embodiment, the first conductive layer SD1 may be a triple layer of Ti / Cu / ITO.

[0072] refer to Figure 2 , the third insulating layer IL3 may be disposed on the first conductive layer SD1. The third insulating layer IL3 may include an opening overlapping the first conductive layer SD1 in a plan view.

[0073] The first metal layer MTL1 may be disposed on the third insulating layer IL3. The first metal layer MTL1 may contact the first conductive layer SD1 in the opening of the third insulating layer IL3. The first metal layer MTL1 may be three layers. As described above, the first metal layer MTL1 may include a first layer M1 including Zn-ITO, a second layer M2 including Ag, and a third layer M3 including Zn-ITO.

[0074] The first electrode 191 may be disposed on the first metal layer MTL1. The first electrode 191 may include indium tin oxide (ITO). Figure 2 As shown in FIG, the first conductive layer SD1, the first metal layer MTL1, and the first electrode 191 may contact each other in the pad region. Therefore, contact characteristics at respective interfaces may be important.

[0075] like Figure 2 As shown in FIG. 1 , the sixth insulating layer IL6 may be disposed on the first electrode 191. The sixth insulating layer IL6 may include silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ) and at least one of amorphous silicon (Si).

[0076] Figure 3 is a schematic cross-sectional view of the first metal layer MTL1. Figure 3 The first metal layer MTL1 may include a first layer M1 including Zn-ITO, a second layer M2 including Ag, and a third layer M3 including Zn-ITO. The thickness of the first layer M1 and the third layer M3 may be about 1000 nm. to about and the thickness of the second layer M2 may be in the range of about to about within the range.

[0077] The second layer M2 may include Ag, and Ag may have the greatest reflective property among metals, and thus the first metal layer MTL1 may have excellent reflective properties.

[0078] The first layer M1 and the third layer M3 may include Zn-ITO. The third layer M3 may contact the first electrode 191 including ITO. Since the third layer M3 includes Zn-ITO, the third layer M3 may contact the first electrode 191 including ITO. Therefore, the first metal layer MTL1 may contact the first electrode 191.

[0079] The first layer M1 may contact the first conductive layer SD1. The first conductive layer SD1 may be a double layer of Ti / Cu, or may be a triple layer of Ti / Cu / ITO. The first layer M1 may include Zn-ITO, and thus the first layer M1 may contact the first conductive layer SD1 made of Ti / Cu or Ti / Cu / ITO.

[0080] In the case where the first metal layer MTL1 includes aluminum, aluminum may have defects of increasing corrosion and oxidation reactions due to the difference in reduction potential between ITO and the standard. ITO and aluminum may not form a good ohmic contact, and in the case where aluminum is exposed on the upper portion, it may be melted by a solution such as KOH or TMAH used in a subsequent process.

[0081] Figure 4 2 is a schematic cross-sectional view showing corrosion and oxidation reactions in the case where the first metal layer MTL1 includes aluminum. Figure 4 The region marked with an arrow is shown in the interface.

[0082] However, in the display device according to the embodiment, the first metal layer MTL1 may include a first layer M1 including Zn-ITO, a second layer M2 including Ag, and a third layer M3 including Zn-ITO. Therefore, as described above, the display device may have high reflective characteristics and may have excellent contact characteristics at the interfaces of the first metal layer MTL1 and the first electrode 191 and the first metal layer MTL1 and the first conductive layer SD1.

[0083] Figure 5 is a graph showing the reflectivity of the first metal layer MTL1 made of Zn-ITO / Ag / Zn-ITO with respect to wavelength according to an embodiment. Figure 5 It was found that the first metal layer MTL1 of Zn-ITO / Ag / Zn-ITO had excellent reflectivity in the entire wavelength region of visible light. For example, it was found that the reflectivity was 80% in the wavelength region of about 400 nm to about 800 nm.

[0084] In an embodiment, Zn in the Zn-ITO of the first layer M1 and the third layer M3 may be equal to or greater than about 10 at%. For example, Zn may be in the range of about 18 at% to about 20 at% of the Zn-ITO of the first layer M1 and the third layer M3. After performing a heat treatment at about 250° C., the Zn-ITO having the Zn content may remain amorphous, and wet etching may be performed in a subsequent process.

[0085] Figure 6 is a graph showing XRD of Zn-ITO in which the content of Zn is about 18 at % and Zn-ITO in which the content of Zn is about 20 at % before / after heat treatment at about 250° C. Figure 6, it is found that after performing a heat treatment of about 250° C., Zn-ITO can remain amorphous. Therefore, Zn-ITO can be wet-etched, and subsequent processes can be performed. For example, when ITO without Zn is crystallized, it is difficult to perform wet etching in subsequent processes. However, since the Zn-ITO according to the embodiment is amorphous, wet etching can be easily performed.

[0086] Table 1 shows evaluation results of reflectivity, a state of contacting ITO, and etching characteristics of subsequent processes while changing the composition of the first metal layer MTL1.

[0087] [Table 1]

[0088]

[0089]

[0090] Referring to Table 1, in the case where the first metal layer includes aluminum, it cannot perform ohmic contact with ITO, so the contact at the interface is unstable. In addition, in the case where the first metal layer includes ITO / Ag / ITO, the reflectivity increases compared to the case where the first metal layer includes aluminum, but etching is impossible in the subsequent process due to polycrystalline ITO. In the case of the first metal layer having a structure of Zn-ITO / Ag / Zn-ITO according to the embodiment, the reflectivity increases compared to the case where the first metal layer includes aluminum, the first metal layer can contact ITO, and the first metal layer is as Figure 5 The first metal layer MTL1 can be etched in a subsequent process. For example, in the display device according to the embodiment, the first metal layer MTL1 can have three layers of Zn-ITO / Ag / Zn-ITO. Therefore, the first metal layer MTL1 can stably contact the first electrode 191 and the first conductive layer SD1 on the pad area, and the first metal layer MTL1 can include Ag, so it has a high reflectivity, and also has amorphous characteristics after the Zn-ITO undergoes heat treatment, so the first metal layer MTL1 can be easily etched in a subsequent process. The display device including the first metal layer MTL1 can increase the reflectivity to a high level, and the manufacturing process can be simplified because in the case where the first metal layer MTL1 includes aluminum, there is no need to avoid the additional mask process required for the ITO of the first electrode to contact the aluminum. In addition, the first metal layer MTL1 can have a damage-free and stable structure for TMAH or KOH as a developing solution for Zn-ITO / Ag / Zn-ITO, so the subsequent process can be easily performed.

[0091] The above description is an example of the technical features of the present disclosure, and a person skilled in the art to which the present disclosure belongs will be able to make various modifications and changes.Therefore, the embodiments of the present disclosure described above can be implemented individually or in combination with each other.

[0092] Therefore, the embodiments disclosed in the present disclosure are not intended to limit the technical spirit of the present disclosure, but to describe the technical spirit of the present disclosure, and the scope of the technical spirit of the present disclosure is not limited by these embodiments. The protection scope of the present disclosure should be interpreted by the attached claims, and it should be understood that all technical spirits within the equivalent scope are included in the scope of the present disclosure.

Claims

1. A display device, characterized in that: include: A transistor is disposed on a substrate; a first conductive layer electrically connected to the transistor; a first metal layer electrically connected to the first conductive layer; a first electrode electrically connected to the first metal layer; as well as an emission layer, electrically connected to the first electrode, The first metal layer includes a first layer comprising Zn-ITO, a second layer comprising Ag, and a third layer comprising Zn-ITO.

2. The display device according to claim 1, characterized in that The display device comprises a display area and a pad area, and The first conductive layer, the first metal layer, and the first electrode contact each other in the pad region.

3. The display device according to claim 2, characterized in that: The first conductive layer includes a first layer including titanium and a second layer including copper, and The second layer of the first conductive layer contacts the first layer of the first metal layer.

4. The display device according to claim 1, characterized in that The first conductive layer includes a first layer including titanium, a second layer including copper, and a third layer including indium tin oxide, and The third layer of the first conductive layer contacts the first layer of the first metal layer.

5. The display device according to claim 2, characterized in that: The first electrode includes indium tin oxide, and The third layer of the first metal layer contacts the first electrode.

6. The display device according to claim 1, characterized in that: The second layer of the first metal layer is thicker than the first layer of the first metal layer and the third layer of the first metal layer in a thickness direction of the substrate.

7. The display device according to claim 1, characterized in that: In the thickness direction of the substrate, the thickness of the first layer of the first metal layer is to within the range.

8. The display device according to claim 7, characterized in that: In the thickness direction of the substrate, the thickness of the second layer of the first metal layer is to within the range.

9. The display device according to claim 8, characterized in that: In the thickness direction, the thickness of the third layer of the first metal layer is to within the range.

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