Display device

Abstract

A display device includes: a substrate; and a first pixel unit disposed on the substrate, in which the first pixel unit includes a first pixel emitting light of a first color. The first pixel includes: a pixel electrode; a bank layer disposed on the pixel electrode, in which a pixel opening is defined in the bank layer to expose at least a portion of the pixel electrode; a plurality of insulating members disposed on the pixel electrode in the pixel opening, in which the plurality of insulating members are arranged to be spaced apart from each other; an intermediate layer disposed on the bank layer to cover the plurality of insulating members; and a common electrode disposed on the intermediate layer.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2023-0039196 filed on March 24, 2023 and Korean Patent Application No. 10-2023-0097800 filed on July 26, 2023 and all rights derived therefrom, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0002] One or more embodiments relate to a device, and more particularly, to a display device. Background Art

[0003] Generally, a display device operates using a thin film transistor and a light emitting element such as an organic light emitting diode formed on a substrate, and the light emitting element emits light.

[0004] In detail, each pixel of the display device may include a light-emitting element such as an organic light-emitting diode, in which an intermediate layer including an emission layer is arranged between a pixel electrode and a counter electrode. The display device generally controls whether each pixel emits light and the degree of light emission via a thin film transistor electrically connected to the pixel electrode. Some layers included in the intermediate layer of the light-emitting element are commonly provided in a plurality of light-emitting elements. Utility Model Content

[0005] One or more embodiments include a display device with improved coherence.However, the embodiments are merely examples, and the scope of the present disclosure is not limited thereto.

[0006] According to one or more embodiments, a display device includes: a substrate; and a first pixel unit disposed on the substrate, wherein the first pixel unit includes a first pixel emitting light of a first color. In such an embodiment, the first pixel includes: a pixel electrode; a bank layer disposed on the pixel electrode, wherein a pixel opening is defined in the bank layer to expose at least a portion of the pixel electrode; a plurality of insulating members disposed on the pixel electrode in the pixel opening, wherein the plurality of insulating members are arranged to be spaced apart from each other; an intermediate layer disposed on the bank layer to cover the plurality of insulating members; and a common electrode disposed on the intermediate layer.

[0007] In an embodiment, each of the plurality of insulating members may be provided to have a longitudinal direction in the first direction.

[0008] In an embodiment, the plurality of insulating members may be spaced apart from each other in a second direction crossing the first direction.

[0009] In an embodiment, the plurality of insulating members may have a stripe pattern in a plan view.

[0010] In embodiments, a plurality of insulating members may be spaced apart from the bank layer.

[0011] In an embodiment, the first pixel unit may further include a second pixel emitting light of a second color and a third pixel emitting light of a third color, the first color may be red, the second color may be green, and the third color may be blue.

[0012] In an embodiment, the second pixel may be spaced apart from the first pixel in a first direction, and the third pixel may be spaced apart from the first pixel in a second direction crossing the first direction.

[0013] In an embodiment, a distance between the plurality of insulating members of the first pixel in the second direction may be smaller than a distance between the first pixel and the second pixel in the first direction.

[0014] In an embodiment, a distance between the plurality of insulating members of the first pixel in the second direction may be smaller than a distance between the first pixel and the third pixel in the second direction.

[0015] In an embodiment, the length of the first pixel in the first direction may be smaller than the length of the second pixel in the first direction, and the length of the second pixel in the first direction may be smaller than the length of the third pixel in the first direction.

[0016] According to one or more embodiments, a display device includes: a substrate; and a first pixel unit disposed on the substrate, wherein the first pixel unit includes a first pixel emitting light of a first color. In such an embodiment, the first pixel includes: a pixel electrode; a bank layer disposed on the pixel electrode, wherein a pixel opening is defined in the bank layer to expose at least a portion of the pixel electrode; a plurality of insulating members disposed on the pixel electrode in the pixel opening; an intermediate layer disposed on the bank layer to cover the plurality of insulating members; and a common electrode disposed on the intermediate layer, and a plurality of first openings are respectively defined between adjacent insulating members among the plurality of insulating members.

[0017] In an embodiment, each of the plurality of first openings may be provided to have a longitudinal direction in the first direction.

[0018] In an embodiment, the plurality of first openings may be spaced apart from one another in a second direction crossing the first direction.

[0019] In an embodiment, the plurality of insulating members may have a stripe pattern in a plan view.

[0020] In embodiments, a plurality of insulating members may be spaced apart from the bank layer.

[0021] In an embodiment, the first pixel unit may further include a second pixel emitting light of a second color and a third pixel emitting light of a third color, the first color may be red, the second color may be green, and the third color may be blue.

[0022] In an embodiment, the second pixel may be spaced apart from the first pixel in a first direction, and the third pixel may be spaced apart from the first pixel in a second direction crossing the first direction.

[0023] In an embodiment, a distance in the second direction between adjacent insulating members among the plurality of insulating members of the first pixel may be smaller than a distance in the first direction between the first pixel and the second pixel.

[0024] In an embodiment, a distance between adjacent insulating members among the plurality of insulating members of the first pixel in the second direction may be smaller than a distance between the first pixel and the third pixel in the second direction.

[0025] In an embodiment, the length of the first pixel in the first direction may be smaller than the length of the second pixel in the first direction, and the length of the second pixel in the first direction may be smaller than the length of the third pixel in the first direction.

[0026] Features of the embodiments other than those described above will become apparent from the following drawings, claims and detailed description of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The above and other features of certain embodiments of the present disclosure will become more apparent from the following description taken in conjunction with the accompanying drawings, in which:

[0028] Figure 1 is a schematic plan view of a display device according to an embodiment;

[0029] Figure 2 is a schematic plan view of a first pixel unit;

[0030] Figure 3 is a schematic cross-sectional view of a portion of a display device according to an embodiment;

[0031] Figure 4 is a schematic cross-sectional view of a portion of a display device according to an embodiment; and

[0032] Figure 5 is an equivalent circuit diagram of a pixel circuit electrically connected to a light emitting diode included in one pixel. DETAILED DESCRIPTION

[0033] The present invention will now be described more fully below with reference to the accompanying drawings in which various embodiments are shown. However, the present invention may be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. On the contrary, these embodiments are provided to make the present disclosure comprehensive and complete and to fully convey the scope of the present invention to those skilled in the art.

[0034] The terms used herein are only used to describe the purpose of a particular embodiment, and are not intended to be limited. As used herein, "one", "the (described)" and "at least one" do not represent the limitation of quantity, and are intended to include both the singular and the plural, unless the context clearly indicates otherwise. Therefore, the reference to the element in the claim is followed by the reference to the "described" element and includes an element and multiple elements. For example, "element" has the same meaning as "at least one element", unless the context clearly indicates otherwise. "At least one" should not be interpreted as being limited to "one". "Or" means "and / or". As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. Throughout the disclosure, the expression "at least one of a, b and c" or "selected from at least one of a, b and c" indicates only a, only b, only c, a and b, a and c, b and c, a, b and c all or its variant.

[0035] Various modifications may be applied to the embodiments presented, and specific embodiments will be illustrated in the drawings and described in the detailed description section. Figure 1 The effects and features of the embodiments presented and the methods for achieving these effects and features will become more clear with the detailed description of the embodiments presented below. However, these embodiments can be implemented in various forms and are not limited to the embodiments presented below.

[0036] Hereinafter, the embodiments will be described in detail with reference to the accompanying drawings, and in the description with reference to the accompanying drawings, the same or corresponding elements are denoted by the same reference numerals, and any repeated detailed description thereof may be omitted or simplified.

[0037] In the following embodiments, it should be understood that although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element.

[0038] It will be further understood that when used in this specification, the term "includes" and / or its variations or "comprises" and / or its variations indicate the presence of stated features, regions, wholes, steps, operations, elements and / or parts, but does not exclude the presence or addition of one or more other features, regions, wholes, steps, operations, elements, parts and / or groups thereof.

[0039] In the following embodiments, it should be understood that when a layer, region or element is referred to as being "formed on" another layer, region or element, it may be directly or indirectly formed on the other layer, region or element. That is, for example, there may be intervening layers, regions or elements.

[0040] For the convenience of explanation, the size of the elements in the drawings may be exaggerated. In other words, since the size and thickness of the elements in the drawings are arbitrarily illustrated for the convenience of explanation, the following embodiments are not limited thereto.

[0041] In addition, relative terms such as "lower" or "bottom" and "upper" or "top" may be used herein to describe the relationship between one element and another element as illustrated in the figure. It should be understood that relative terms are intended to cover different orientations of the device in addition to the orientation depicted in the figure. For example, if the device in one of the figures is turned over, the element described as being on the "lower" side of the other elements will then be oriented to be on the "upper" side of the other elements. Therefore, the term "lower" can cover both "lower" and "upper" orientations, depending on the specific orientation of the figure. Similarly, if the device in one of the figures is turned over, the element described as being "below" or "below" the other elements will then be oriented to be "above" the other elements. Therefore, the term "below" or "below" can cover both upper and lower orientations.

[0042] In the following embodiments, the x-axis direction, the y-axis direction, and the z-axis direction are not limited to the directions corresponding to the three axes of the rectangular coordinate system, and can be interpreted in a broader sense. For example, the x-axis direction, the y-axis direction, and the z-axis direction can be perpendicular to each other, or can represent different directions that are not perpendicular to each other.

[0043] When a specific embodiment can be implemented differently, the specific processing order can be performed differently from the described order. For example, two consecutively described processes can be performed substantially simultaneously or in the reverse order of the described order.

[0044] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. It should be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology and the present disclosure, and will not be interpreted in an idealized or overly formal sense unless explicitly defined as such in this article.

[0045] Embodiments are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments. Thus, variations in the illustrated shapes due to, for example, manufacturing techniques and / or tolerances can be expected. Therefore, the embodiments described herein should not be construed as being limited to the specific shapes of the zones illustrated herein, but should include deviations in shapes due to, for example, manufacturing. For example, a zone illustrated or described as flat may typically have rough and / or nonlinear features. In addition, illustrated sharp corners may be rounded. Therefore, the zones illustrated in the figures are schematic in nature, and their shapes are not intended to illustrate the precise shapes of the zones, and are not intended to limit the scope of the present disclosure.

[0046] Figure 1 is a schematic plan view of a display device according to an embodiment. In detail, Figure 1 It is a schematic diagram of a pixel unit and a circuit driving unit of a display device.

[0047] The display device according to the embodiment is a device for displaying a moving image or a still image, and may be a display device for extended reality (XR). For example, the display device according to the embodiment may be a display device for virtual reality (VR), augmented reality (AR), or mixed reality (MR).

[0048] The display device according to the embodiment is a device for displaying a moving image or a still image, and can be used as a display screen of various products such as a television, a laptop, a monitor, a billboard, or an Internet of Things (IoT) device, and a display screen of a portable electronic device such as a mobile phone, a smart phone, a tablet personal computer (tablet PC), a mobile communication terminal, an electronic notebook, an electronic book, a portable multimedia player (PMP), a navigation device, or an ultra-mobile PC (UMPC). In addition, the display device according to the embodiment can be used in wearable devices such as smart watches, watch phones, glasses-type displays, and head-mounted displays (HMD). In addition, the display device according to the embodiment can be used as a display of a vehicle dashboard, a central information display (CID) arranged on the center instrument panel or dashboard of the vehicle, an interior mirror display instead of a vehicle side mirror, or a display arranged on the back of the front seat as an entertainment facility for the rear seat of the vehicle.

[0049] In an embodiment, Figure 1As shown in , the display device 1 may include a first display area DA1 and a second display area DA2. In other words, the substrate 100 included in the display device 1 may include the first display area DA1 and the second display area DA2, or the first display area DA1 and the second display area DA2 may be defined on the substrate 100. The second display area DA2 may be arranged to surround at least a portion of the first display area DA1 in a plan view (i.e., when viewed in the thickness direction or z-axis direction of the substrate 100). The first display area DA1 may be completely surrounded by the second display area DA2. The first display area DA1 may be provided to have a quadrilateral shape. In detail, the length of the first display area DA1 extending in the first direction (e.g., the y-axis direction) may be less than the length of the first display area DA1 extending in the second direction (e.g., the x-axis direction). However, the present disclosure is not limited thereto. Alternatively, the first display area DA1 may be provided to have a circular shape, a square shape, or an elliptical shape, and the length of the first display area DA1 extending in the first direction (e.g., the y-axis direction) may be greater than the length of the first display area DA1 extending in the second direction (e.g., the x-axis direction).

[0050] In an embodiment, the first pixel cell PXs1 may be arranged in the first display area DA1, and the second pixel cell PXs2 may be arranged in the second display area DA2. The first pixel circuit unit PCs1 for driving the first pixel cell PXs1 arranged in the first display area DA1 may be arranged in the first display area DA1. In detail, the first pixel circuit unit PCs1 may be arranged to overlap with the first pixel cell PXs1. The second pixel circuit unit PCs2 for driving the second pixel cell PXs2 arranged in the second display area DA2 may be arranged in the second display area DA2. In detail, the second pixel circuit unit PCs2 for driving the second pixel cell PXs2 may be arranged not to overlap with the second pixel cell PXs2. However, the present disclosure is not limited thereto.

[0051] Not only the second pixel unit PXs2 and the second pixel circuit unit PCs2 may be arranged in the second display area DA2, but also the circuit driving units 11 and 12 for driving the first pixel circuit unit PCs1 and the second pixel circuit unit PCs2 may be arranged in the second display area DA2. The circuit driving units 11 and 12 may include a scan driving unit 12 and a data driving unit 11. The data driving unit 11 may extend in a second direction (e.g., an x-axis direction) and be arranged in the second display area DA2. The scan driving unit 12 may extend in a first direction (e.g., a y-axis direction) and be arranged in the second display area DA2.

[0052] The data driving unit 11 may supply a data signal to the first pixel circuit unit PCs1 via the first data line DL1, and may supply a data signal to the second pixel circuit unit PCs2 via the second data line DL2. The scanning driving unit 12 may supply a scanning signal to the first pixel circuit unit PCs1 via the first scanning line SL1, and may supply a scanning signal to the second pixel circuit unit PCs2 via the second scanning line SL2.

[0053] In an embodiment, the first pixel unit PXs1 and the first pixel circuit unit PCs1 arranged in the first display area DA1 may be arranged to overlap each other in a plan view (or in a thickness direction of the substrate 100). Since the data driving unit 11 and the scan driving unit 12 are arranged in the second display area DA2, in an embodiment in which the second pixel unit PXs2 is arranged to overlap with the data driving unit 11 and the scan driving unit 12, the second pixel circuit unit PCs2 may be arranged not to overlap with the second pixel unit PXs2. The second pixel unit PXs2 is also arranged in the second display area DA2 in which the data driving unit 11 and the scan driving unit 12 are arranged, and therefore, the area of ​​the area of ​​the display device 1 in which the picture is displayed is widened, and the resolution can be increased.

[0054] Figure 2 is a schematic plan view of a first pixel unit.

[0055] refer to Figure 2 In an embodiment, the first pixel unit PXs1 may include a first pixel PX1, a second pixel PX2, and a third pixel PX3. The first pixel PX1 may emit light of a first color, the second pixel PX2 may emit light of a second color, and the third pixel PX3 may emit light of a third color. The first color, the second color, and the third color are different from each other. In an embodiment, for example, the light of the first color may be red light, the light of the second color may be green light, and the light of the third color may be blue light.

[0056] The first pixel PX1 may be a first emission area EA1 in which light of a first color is emitted, and the second pixel PX2 may be a second emission area EA2 in which light of a second color is emitted. In addition, the third pixel PX3 may be a third emission area EA3 in which light of a third color is emitted. The sum of the areas of the emission areas of the first pixel unit PXs1 may be the sum of the areas of the first emission area EA1 of the first pixel PX1, the second emission area EA2 of the second pixel PX2, and the third emission area EA3 of the third pixel PX3.

[0057] The second pixel PX2 may be spaced apart from the first pixel PX1 in a first direction (e.g., y-axis direction), the third pixel PX3 may be spaced apart from the first pixel PX1 in a second direction (e.g., x-axis direction), and the third pixel PX3 may be spaced apart from the second pixel PX2 in the second direction (e.g., x-axis direction). The first direction (e.g., y-axis direction) and the second direction (e.g., x-axis direction) may intersect each other.

[0058] In a plan view, each of the first pixel PX1, the second pixel PX2, and the third pixel PX3 may have a quadrilateral shape. The length d1-2 of the first pixel PX1 in the first direction (e.g., the y-axis direction) may be smaller than the length d2-2 of the second pixel PX2 in the first direction (e.g., the y-axis direction). The length d2-2 of the second pixel PX2 in the first direction (e.g., the y-axis direction) may be smaller than the length d3-2 of the third pixel PX3 in the first direction (e.g., the y-axis direction).

[0059] The length d1-1 of the first pixel PX1 in the second direction (e.g., the x-axis direction) may be equal to the length d2-1 of the second pixel PX2 in the second direction (e.g., the x-axis direction). In an embodiment, for example, the length d1-1 of the first pixel PX1 in the second direction (e.g., the x-axis direction), the length d2-1 of the second pixel PX2 in the second direction (e.g., the x-axis direction), and the length d3-1 of the third pixel PX3 in the second direction (e.g., the x-axis direction) may be equal to each other.

[0060] In an embodiment, the sum of the length d1-2 of the first pixel PX1 in the first direction (e.g., y-axis direction), the length d2-2 of the second pixel PX2 in the first direction (e.g., y-axis direction), and the distance d4 between the first pixel PX1 and the second pixel PX2 in the first direction (e.g., y-axis direction) may be equal to the length d3-2 of the third pixel PX3 in the first direction (e.g., y-axis direction). In addition, the distance d5 between the first pixel PX1 and the third pixel PX3 in the second direction (e.g., x-axis direction) may be equal to the distance d6 between the second pixel PX2 and the third pixel PX3 in the second direction (e.g., x-axis direction).

[0061] In the structure described above, in a plan view, the areas of the first emission area EA1, the second emission area EA2, and the third emission area EA3 may increase in the order described. However, this is only an example, and the shapes and sizes of the first pixel PX1, the second pixel PX2, and the third pixel PX3 may vary depending on the types of the first color, the second color, and the third color.

[0062] Figure 3is a schematic cross-sectional view of a portion of a display device according to an embodiment. Figure 3 Can correspond to along Figure 2 A cross section of the display device 1 taken along line III-III'.

[0063] refer to Figure 3 , an embodiment of the display device 1 may include a stacked structure of a substrate 100 , a pixel circuit layer PCL, a display element layer DEL, and an encapsulation layer 300 .

[0064] The substrate 100 may have a multilayer structure including a base layer including a polymer resin and an inorganic layer. In an embodiment, for example, the substrate 100 may include a base layer including a polymer resin and a barrier layer that is an inorganic insulating layer. In an embodiment, for example, the substrate 100 may include a first base layer 101, a first barrier layer 102, a second base layer 103, and a second barrier layer 104 stacked in sequence. Each of the first base layer 101 and the second base layer 103 may include polyimide (PI), polyethersulfone (PES), polyarylate, polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polycarbonate, triacetyl cellulose (TAC) or / and cellulose acetate propionate (CAP). The first barrier layer 102 and the second barrier layer 104 may include an inorganic insulating material such as silicon oxide, silicon oxynitride, and / or silicon nitride. The substrate 100 may have flexibility.

[0065] The pixel circuit layer PCL is disposed on the substrate 100 . Figure 3 An embodiment is illustrated in which the pixel circuit layer PCL includes a thin film transistor TFT and further includes a buffer layer 111, a first gate insulating layer 112, a second gate insulating layer 113, an interlayer insulating layer 114, a first planarizing insulating layer 115, and a second planarizing insulating layer 116 disposed under or / and on constituent elements of the thin film transistor TFT.

[0066] The buffer layer 111 may reduce or block penetration of foreign matter, moisture, or external air from under the substrate 100, and may provide a flat surface on the substrate 100. The buffer layer 111 may include an inorganic insulating material such as silicon oxide, silicon oxynitride, or silicon nitride, and may have a single-layer or multi-layer structure, each layer of which includes at least one selected from the materials described above.

[0067] The thin film transistor TFT on the buffer layer 111 may include a semiconductor layer Act, and the semiconductor layer Act may include polycrystalline silicon (poly-Si). Alternatively, the semiconductor layer Act may include amorphous silicon (a-Si), an oxide semiconductor, or an organic semiconductor. The semiconductor layer Act may include a channel region C and a drain region D and a source region S respectively arranged on opposite sides of the channel region C. The gate electrode GE may overlap the channel region C.

[0068] The gate electrode GE may include a low resistance metal material. The gate electrode GE may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu) or titanium (Ti), and may have a single layer or multilayer structure, each layer of which includes at least one selected from the materials described above.

[0069] The first gate insulating layer 112 between the semiconductor layer Act and the gate electrode GE may include silicon oxide (SiO 2 ), silicon nitride (SiN x ), silicon oxynitride (SiON), aluminum oxide (Al 2 O 3 ), titanium oxide (TiO 2 ), Tantalum Oxide (Ta 2 O 5 ), hafnium oxide (HfO 2 ) or zinc oxide (ZnO x ) inorganic insulating material. ZnO x It may include zinc oxide (ZnO) and / or zinc peroxide (ZnO 2 ).

[0070] A second gate insulating layer 113 may be provided to cover the gate electrode GE. Similar to the first gate insulating layer 112, the second gate insulating layer 113 may include silicon oxide (SiO 2 ), silicon nitride (SiN x ), silicon oxynitride (SiON), aluminum oxide (Al 2 O 3 ), titanium oxide (TiO 2 ), Tantalum Oxide (Ta 2 O 5 ), hafnium oxide (HfO 2 ) or zinc oxide (ZnO x ) inorganic insulating material. ZnO x It may include ZnO and / or ZnO 2 .

[0071] The upper electrode Cst2 of the storage capacitor Cst may be disposed on the second gate insulating layer 113. The upper electrode Cst2 may overlap the gate electrode GE thereunder. In an embodiment, the gate electrode GE and the upper electrode Cst2 overlapping each other with the second gate insulating layer 113 therebetween may form a storage capacitor Cst. In such an embodiment, the gate electrode GE may serve as the lower electrode Cst1 of the storage capacitor Cst.

[0072] Thus, the storage capacitor Cst and the thin film transistor TFT may overlap each other. In some embodiments, the storage capacitor Cst may be formed not to overlap the thin film transistor TFT.

[0073] The upper electrode Cst2 may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W) and / or copper (Cu), and may have a single-layer or multi-layer structure, each layer of which includes at least one of the materials selected from the above.

[0074] The interlayer insulating layer 114 may cover the upper electrode Cst2. The interlayer insulating layer 114 may include silicon oxide (SiO 2 ), Silicon Nitride (SiN x ), silicon oxynitride (SiON), aluminum oxide (Al 2 O 3 ), titanium oxide (TiO 2 ), Tantalum Oxide (Ta 2 O 5 ), hafnium oxide (HfO 2 ) or zinc oxide (ZnO x ). ZnO x It may include zinc oxide (ZnO) and / or zinc peroxide (ZnO 2 The interlayer insulating layer 114 may have a single-layer or multi-layer structure, each of which includes at least one selected from the inorganic insulating materials described above.

[0075] The drain electrode DE and the source electrode SE may each be disposed on the interlayer insulating layer 114. The drain electrode DE and the source electrode SE may be connected to the drain region D and the source region S, respectively, through contact holes defined or formed in the insulating layer thereunder. Each of the drain electrode DE and the source electrode SE may include a material exhibiting high conductivity. The drain electrode DE and the source electrode SE may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), or titanium (Ti), and may have a single-layer or multi-layer structure, each of which includes at least one selected from the materials described above. In an embodiment, the drain electrode DE and the source electrode SE may each have a multilayer structure of Ti / Al / Ti.

[0076] The first planarization insulating layer 115 may cover the drain electrode DE and the source electrode SE. The first planarization insulating layer 115 may include an organic insulating material such as a general polymer such as polymethyl methacrylate (PMMA) or polystyrene (PS), a polymer derivative having a phenol group, an acrylic polymer, an imide-based polymer, an aryl ether-based polymer, an amide-based polymer, a fluorine-based polymer, a paraxylene-based polymer, a vinyl alcohol-based polymer, or a blend thereof.

[0077] The second planarization insulating layer 116 may be disposed on the first planarization insulating layer 115. The second planarization insulating layer 116 may include the same material as that of the first planarization insulating layer 115, and may include an organic insulating material such as a general polymer such as polymethyl methacrylate (PMMA) or polystyrene (PS), a polymer derivative having a phenol group, an acrylic polymer, an imide-based polymer, an aryl ether-based polymer, an amide-based polymer, a fluorine-based polymer, a paraxylene-based polymer, a vinyl alcohol-based polymer, or a blend thereof.

[0078] The display element layer DEL may be disposed on the pixel circuit layer PCL having the structure described above. The display element layer DEL may include an organic light emitting diode OLED as a display element (i.e., a light emitting element), and the organic light emitting diode OLED may include a stacked structure of a pixel electrode 210, an intermediate layer 220, and a common electrode 230. For example, the organic light emitting diode OLED may emit red light, green light, or blue light, or emit red light, green light, blue light, or white light. The organic light emitting diode OLED may emit light via an emission region, and define an emission region corresponding to the first pixel PX1.

[0079] The pixel electrode 210 of the organic light emitting diode OLED may be electrically connected to the thin film transistor TFT via a contact hole defined or formed in the second planarization insulating layer 116 and the first planarization insulating layer 115 and a contact metal CM disposed on the first planarization insulating layer 115 .

[0080] In an embodiment, the pixel electrode 210 may include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In 2 O 3), indium gallium oxide (IGO) or aluminum zinc oxide (AZO). In an alternative embodiment, the pixel electrode 210 may include a reflective film containing silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr) or a compound thereof. In another alternative embodiment, the pixel electrode 210 may further include a reflective film including ITO, IZO, ZnO or In above / below the reflective film described above. 2 O 3 membrane.

[0081] The bank layer 117 is disposed on the pixel electrode 210, and the bank layer 117 is provided with a pixel opening 117OP defined therein to expose the central portion of the pixel electrode 210. The bank layer 117 may include an organic insulating material and / or an inorganic insulating material. The pixel opening 117OP may define an emission area of ​​light emitted from the organic light emitting diode OLED. In an embodiment, for example, the size / width of the pixel opening 117OP may correspond to the size / width of the emission area. Therefore, the size and / or width of the first pixel PX1 may depend on the size and / or width of the pixel opening 117OP of the bank layer 117 (or may be determined based on the size and / or width of the pixel opening 117OP of the bank layer 117).

[0082] The intermediate layer 220 may include an emission layer 222 formed corresponding to the pixel electrode 210. The emission layer 222 may include a polymer or a low molecular weight organic material that emits light of a specific color. Alternatively, the emission layer 222 may include an inorganic light emitting material or a quantum dot.

[0083] In an embodiment, the intermediate layer 220 may include a first functional layer 221 and a second functional layer 223 disposed below and above the emission layer 222, respectively. The first functional layer 221 may include, for example, a hole transport layer (HTL) or an HTL and a hole injection layer (HIL). The second functional layer 223 disposed above the emission layer 222 may include an electron transport layer (ETL) and / or an electron injection layer (EIL). Like the common electrode 230 described below, the first functional layer 221 and / or the second functional layer 223 may be a common layer formed to completely cover the substrate 100.

[0084] The common electrode 230 is disposed on the pixel electrode 210 and may overlap with the pixel electrode 210. The common electrode 230 may include a conductive material having a low work function. In an embodiment, for example, the common electrode 230 may include a (semi) transparent layer containing silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca) or an alloy thereof. Alternatively, the common electrode 230 may further include a (semi) transparent layer including ITO, IZO, ZnO or Indium on the (semi) transparent layer including the materials described above. 2 O 3 The common electrode 230 may be commonly provided throughout the substrate 100 (ie, integrally formed to completely cover the substrate 100 ).

[0085] The encapsulation layer 300 is disposed on the display element layer DEL and may cover the display element layer DEL. The encapsulation layer 300 includes at least one inorganic encapsulation layer and at least one organic encapsulation layer. Figure 3 As shown in FIG. 1 , the encapsulation layer 300 includes a first inorganic encapsulation layer 310 , an organic encapsulation layer 320 , and a second inorganic encapsulation layer 330 which are sequentially stacked.

[0086] Each of the first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 may include at least one inorganic material selected from aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and silicon oxynitride. The organic encapsulation layer 320 may include a polymer material. The polymer material may include an acrylic resin, an epoxy resin, a polyimide, or polyethylene. In an embodiment, the organic encapsulation layer 320 may include an acrylate. The organic encapsulation layer 320 may be formed by curing a monomer or coating a polymer. The organic encapsulation layer 320 may have transparency.

[0087] In an embodiment, although not shown, a touch sensor layer may be provided on the encapsulation layer 300, and an optical functional layer may be provided on the touch sensor layer. The touch sensor layer may obtain coordinate information according to an external input (e.g., a touch event). The optical functional layer may reduce the reflectivity of light (external light) incident on the display device, and / or may improve the color purity of light emitted from the display device. In an embodiment, the optical functional layer may include a retarder and / or a polarizer. The retarder may be of a film type or a liquid crystal coating type, and may include a λ / 2 retarder and / or a λ / 4 retarder. The polarizer may also be of a film type or a liquid crystal coating type. The film type may include a stretched synthetic resin film, and the liquid crystal coating type may include liquid crystals arranged in a specific arrangement. Each of the retarder and the polarizer may further include a protective film.

[0088] In such an embodiment, an adhesive member (not shown) may be disposed between the touch sensor layer and the optical functional layer. The adhesive member may be any general member generally known in the related art without limitation. The adhesive member may be a pressure sensitive adhesive (PSA) layer.

[0089] Figure 4 is a schematic cross-sectional view of a portion of a display device according to an embodiment. In detail, Figure 4 yes Figure 3 An enlarged view of part A of FIG.

[0090] refer to Figures 2 to 4 In an embodiment, the first pixel PX1 may include a pixel electrode 210 , a bank layer 117 , a plurality of insulating members PIS, an intermediate layer 220 , and a common electrode 230 .

[0091] Figures 2 to 4 The same reference numerals in the drawings refer to the same components, and thus, any repeated detailed description thereof will be omitted.

[0092] In an embodiment, the bank layer 117 is disposed on the pixel electrode 210, and a pixel opening 117OP exposing at least a portion of the pixel electrode 210 may be disposed in the bank layer 117. The bank layer 117 may contact the pixel electrode 210 and the pixel circuit layer PCL. The pixel opening 117OP may be disposed in the center of the pixel electrode 210. Figure 4 As shown in FIG. 1 , in the cross section, an inner peripheral surface of the bank layer 117 defining the pixel opening 117OP may be inclined with respect to an upper surface of the pixel electrode 210 .

[0093] A plurality of insulating members PIS may be disposed on the pixel electrode 210 to be accommodated in the pixel opening 117OP. A plurality of insulating members PIS may be disposed in the pixel opening 117OP in a plan view. A plurality of insulating members PIS may be arranged to be spaced apart from each other. In an embodiment, as shown in FIG. Figure 2 As shown in , in a plan view, each of the plurality of insulating members PIS may be provided to have a longitudinal direction in a first direction (e.g., y-axis direction) (or extend in a first direction (e.g., y-axis direction)). The length of each of the plurality of insulating members PIS in the first direction (e.g., y-axis direction) may be equal to the length of the first emission region EA1 in the first direction (e.g., y-axis direction). The plurality of insulating members PIS may be spaced apart from each other in a second direction (e.g., x-axis direction). The plurality of insulating members PIS may be spaced apart from the bank layer 117.

[0094] The plurality of first openings OP1 may be respectively defined between adjacent insulation members PIS among the plurality of insulation members PIS. Figure 2As shown in , in a plan view, each of the plurality of first openings OP1 may be provided to have a longitudinal direction in a first direction (e.g., y-axis direction). The length of each of the plurality of first openings OP1 in the first direction (e.g., y-axis direction) may be equal to the length of the first emission area EA1 in the first direction (e.g., y-axis direction). The plurality of first openings OP1 may be spaced apart from each other in a second direction (e.g., x-axis direction). Two of the plurality of first openings OP1 may be in contact with the embankment layer 117. In the structure described above, the plurality of insulating members PIS may have a stripe pattern.

[0095] Figure 2 and Figure 4 An embodiment in which the distances between the plurality of insulating members PIS are equal to each other is illustrated, but this is merely an example, and the arrangement of the plurality of insulating members PIS is not limited thereto. Figure 4 An embodiment in which the cross section of each of the plurality of insulation members PIS is a quadrangle is illustrated, but this is merely an example, and the shape of the cross section of each of the plurality of insulation members PIS is not limited thereto.

[0096] The plurality of insulating members PIS may include silicon oxide (SiO x ), Silicon Nitride (SiN x ), silicon oxynitride (SiON), aluminum oxide (Al 2 O 3 ), titanium oxide (TiO 2 ), Tantalum Oxide (Ta 2 O 5 ), hafnium oxide (HfO 2 ) or zinc oxide (ZnO x ) of inorganic insulating materials.

[0097] The intermediate layer 220 may be disposed on the bank layer 117 to cover the plurality of insulating members PIS. The intermediate layer 220 may be in contact with the plurality of insulating members PIS, the pixel electrode 210, and the bank layer 117. The plurality of insulating members PIS may be sealed by the intermediate layer 220 and the pixel electrode 210. The common electrode 230 may be disposed on the intermediate layer 220, and the encapsulation layer 300 may be disposed on the common electrode 230.

[0098] In an embodiment, Figure 4 As shown in , in the cross section, the area of ​​the intermediate layer 220 overlapping with the plurality of first openings OP1 in the z-axis direction (or in a plan view) is referred to as the first area ARE1, and the area of ​​the intermediate layer 220 overlapping with the plurality of insulating members PIS in the z-axis direction is referred to as the second area ARE2. In such an embodiment, the first area ARE1 may not overlap with the plurality of insulating members PIS, and the second area ARE2 may not overlap with the plurality of first openings OP1.

[0099] In the first area ARE1, the intermediate layer 220 may be electrically connected to the pixel electrode 210. Therefore, in the first area ARE1, the intermediate layer 220 may emit light according to interactions with the pixel electrode 210 and the common electrode 230.

[0100] However, in the second area ARE2, the intermediate layer 220 may not be electrically connected to the pixel electrode 210. Because a plurality of insulating members PIS are disposed between the intermediate layer 220 and the pixel electrode 210 in the second area ARE2, current may not flow between the intermediate layer 220 and the pixel electrode 210. Therefore, the intermediate layer 220 may not emit light in the second area ARE2.

[0101] In an embodiment of the display device 1 for extended reality (XR), it is desirable that the intermediate layer 220 emits light having high coherence. In such an embodiment, it is desirable that the coherence length of the light emitted from the intermediate layer 220 increases.

[0102] The coherence length can be expressed as In this regard, λ0 may refer to the central wavelength of the light source, Δλ may refer to the width of the spectrum of the light source, and n may refer to the refractive index of the medium. In an embodiment of the present disclosure, since the emission region of the intermediate layer 220 is divided into a plurality of first regions ARE1, the full width at half maximum (FWHM) is reduced, and therefore, Δλ may be reduced. Therefore, in such an embodiment, as the coherence length increases, the coherence may be improved.

[0103] exist Figure 3 and Figure 4 In FIG. 1 , only the first pixel PX1 is illustrated as an example, but Figure 2 As shown in , like the first pixel PX1, each of the second pixel PX2 and the third pixel PX3 may also include a plurality of insulating members. In other words, in the second pixel PX2, the light of the second color may be divided into a plurality of regions and emitted, and in the third pixel PX3, the light of the third color may be divided into a plurality of regions and emitted. Therefore, the coherence of the light emitted from the second pixel PX2 may be improved. In addition, the coherence of the light emitted from the third pixel PX3 may be improved.

[0104] refer to Figure 2 and Figure 4In an embodiment, a distance d1-3 between the plurality of insulating members PIS arranged in the first pixel PX1, a distance d2-3 between the plurality of insulating members arranged in the second pixel PX2, and a distance d3-3 between the plurality of insulating members arranged in the third pixel PX3 may be equal to each other. In such an embodiment, a width d1-4 of each of the plurality of insulating members PIS arranged in the first pixel PX1, a width d2-4 of each of the plurality of insulating members arranged in the second pixel PX2, and a width d3-4 of each of the plurality of insulating members arranged in the third pixel PX3 may be equal to each other.

[0105] Each of the distance d4 between the first pixel PX1 and the second pixel PX2, the distance d5 between the first pixel PX1 and the third pixel PX3, and the distance d6 between the second pixel PX2 and the third pixel PX3 may be greater than each of the distance d1-3 between the plurality of insulating members PIS arranged in the first pixel PX1, the distance d2-3 between the plurality of insulating members arranged in the second pixel PX2, and the distance d3-3 between the plurality of insulating members arranged in the third pixel PX3. Therefore, mixing of the first color, the second color, and the third color with each other may be significantly reduced or effectively prevented.

[0106] Figure 5 is an equivalent circuit diagram of a pixel circuit electrically connected to a light emitting diode included in one pixel.

[0107] refer to Figure 5 , an embodiment of the pixel circuit PC may include a first transistor T1, a second transistor T2, and a storage capacitor Cst. The second transistor T2 is a switching transistor, may be connected to the scan line SL and the data line DL, and may be turned on by a switching signal input from the scan line SL to transmit a data signal input from the data line DL to the first transistor T1. The storage capacitor Cst may have one end electrically connected to the second transistor T2 and the other end electrically connected to the driving voltage line PL, and may store a voltage corresponding to a difference between a voltage received from the second transistor T2 and a driving power supply voltage ELVDD supplied to the driving voltage line PL.

[0108] The first transistor T1 is a driving transistor and can be connected to the driving voltage line PL and the storage capacitor Cst, and can be configured to control the magnitude of the driving current flowing from the driving voltage line PL to the light emitting diode ED based on the voltage value stored in the storage capacitor Cst. The light emitting diode ED can emit light with a specific brightness by the driving current. The counter electrode of the light emitting diode ED can receive the electrode power supply voltage ELVSS.

[0109] Figure 5An embodiment in which the pixel circuit PC includes two transistors and one storage capacitor is illustrated, but the present disclosure is not limited thereto. For example, the number of transistors or the number of storage capacitors may be changed according to the design of the pixel circuit PC.

[0110] According to the embodiment, a display device with improved coherence can be realized.

[0111] The present invention should not be interpreted as being limited to the embodiments described herein. Instead, these embodiments are provided to make the present disclosure comprehensive and complete, and to fully convey the concept of the present invention to those skilled in the art.

[0112] While the invention has been particularly shown and described with reference to embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit or scope of the invention as defined by the claims.

Claims

1. A display device, comprising: substrate; as well as A first pixel unit is disposed on the substrate, wherein the first pixel unit includes a first pixel that emits light of a first color, Wherein, the first pixel comprises: Pixel electrode; a bank layer disposed on the pixel electrode, wherein a pixel opening is defined in the bank layer to expose at least a portion of the pixel electrode; a plurality of insulating members disposed on the pixel electrode in the pixel opening, wherein the plurality of insulating members are arranged to be spaced apart from each other; an intermediate layer disposed on the bank layer to cover the plurality of insulating members; and The common electrode is arranged on the middle layer.

2. The display device according to claim 1, wherein: Each of the plurality of insulating members is provided to have a longitudinal direction in a first direction.

3. The display device according to claim 2, wherein: The plurality of insulating members are spaced apart from each other in a second direction crossing the first direction.

4. The display device according to claim 3, wherein: The plurality of insulating members have a stripe pattern in a plan view.

5. The display device according to claim 1, wherein: The plurality of insulating members are spaced apart from the bank layer.

6. The display device according to claim 1, wherein: The first pixel unit further comprises: a second pixel that emits light of a second color; and a third pixel, emitting light of a third color, and The first color is red, the second color is green, and the third color is blue.

7. The display device according to claim 6, wherein: The second pixel is spaced apart from the first pixel in a first direction, and The third pixel is spaced apart from the first pixel in a second direction crossing the first direction.

8. The display device according to claim 7, wherein: A distance between the plurality of insulating members of the first pixel in the second direction is smaller than a distance between the first pixel and the second pixel in the first direction.

9. The display device according to claim 7, wherein: A distance between the plurality of insulating members of the first pixel in the second direction is smaller than a distance between the first pixel and the third pixel in the second direction.

10. The display device according to claim 7, wherein: The length of the first pixel in the first direction is smaller than the length of the second pixel in the first direction, and The length of the second pixel in the first direction is smaller than the length of the third pixel in the first direction.

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