Display device

Abstract

The utility model relates to a display device. The display device includes: a substrate; a gate insulating layer; an auxiliary electrode extending in a first direction in a plan view parallel to the main plane of the substrate, and including a first portion and a second portion, the first portion having a first thickness in a second direction crossing the first direction, and the second portion having a second thickness in the second direction; an inorganic insulating layer defining a first opening exposing a portion of the second portion; an organic insulating layer defining a second opening exposing a portion of the second portion; an intermediate layer disposed on the organic insulating layer and defining a third opening exposing a portion of the second portion; and an opposing electrode disposed on the intermediate layer and in contact with an upper surface and a side surface of the auxiliary electrode. The second thickness of the second portion is less than the first thickness of the first portion.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Korean Patent Application No. 10-2023-0039225 filed on March 24, 2023 and Korean Patent Application No. 10-2023-0065234 filed on May 19, 2023, and all rights arising therefrom, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] Embodiments relate to a display device and a method of manufacturing the display device. Background Art

[0004] The display device visually displays data. The display device may provide an image through a light emitting diode. As the use of the display device diversifies, various designs for improving the quality of the display device are being attempted. Utility Model Content

[0005] Embodiments include a display device having improved reliability and quality and a method of manufacturing the display device. However, this purpose is only an example, and the scope of the embodiments is not limited thereto.

[0006] Additional features will be set forth in part in the description which follows and, in part, will be apparent from the description, or may be learned by practice of the presented embodiments of the disclosure.

[0007] In an embodiment of the present disclosure, a display device includes: a substrate; a gate insulating layer disposed on the substrate; an auxiliary electrode disposed on the gate insulating layer, extending in a first direction in a plane parallel to a main plane of the substrate, and including a first part and a second part, the first part having a first thickness in a second direction in the plane intersecting the first direction, and the second part having a second thickness in the second direction; an inorganic insulating layer disposed on the gate insulating layer and defining a first opening exposing at least a portion of the second portion of the auxiliary electrode; an organic insulating layer disposed on the inorganic insulating layer and defining a second opening exposing at least a portion of the second portion of the auxiliary electrode; an intermediate layer disposed on the organic insulating layer and defining a third opening exposing at least a portion of the second portion of the auxiliary electrode; and a relative electrode disposed on the intermediate layer and in contact with an upper surface and a side surface of the auxiliary electrode, wherein the second thickness of the second portion is less than the first thickness of the first portion.

[0008] In an embodiment, an area of ​​the third opening of the intermediate layer may be greater than an area of ​​a region in which the auxiliary electrode is disposed.

[0009] In an implementation, a size of the first opening of the inorganic insulating layer may be greater than a size of the second opening of the organic insulating layer.

[0010] In an implementation, a size of the second opening of the organic insulating layer may be greater than a size of the third opening of the intermediate layer.

[0011] In an embodiment, the display device may further include a first thin film transistor including a semiconductor layer disposed on the substrate, a gate electrode disposed on the semiconductor layer, and a source electrode and a drain electrode disposed on the gate electrode.

[0012] In an embodiment, the display device may further include an organic light emitting diode including a pixel electrode disposed on the organic insulating layer, an intermediate layer disposed on the pixel electrode, and an opposite electrode disposed on the intermediate layer.

[0013] In an embodiment, the display device may further include a pixel defining layer disposed on the pixel electrode and defining an opening exposing at least a portion of the pixel electrode in the pixel defining layer.

[0014] In an implementation, the pixel defining layer may define a fourth opening through which at least a portion of the second portion of the auxiliary electrode is exposed.

[0015] In an implementation, a size of the fourth opening of the pixel defining layer may be greater than each of a size of the second opening of the organic insulating layer and a size of the third opening of the intermediate layer.

[0016] In an embodiment, the intermediate layer may include a third portion adjacent to the third opening and a fourth portion spaced apart from the third opening except for the third portion, and the thickness of the third portion in a direction perpendicular to the main plane of the substrate may be greater than the thickness of the fourth portion in a direction perpendicular to the main plane of the substrate.

[0017] In an embodiment of the present disclosure, a method for manufacturing a display device includes: forming a gate insulating layer on a substrate; forming an auxiliary electrode on the gate insulating layer, the auxiliary electrode extending in a first direction in a plane parallel to a main plane of the substrate and including a first portion having a first thickness in a second direction intersecting the first direction, and a second portion having a second thickness in the second direction; forming an inorganic insulating layer on the gate insulating layer, the inorganic insulating layer defining a first opening exposing at least a portion of the second portion of the auxiliary electrode; forming an organic insulating layer on the inorganic insulating layer, the organic insulating layer defining a second opening exposing at least a portion of the second portion of the auxiliary electrode; forming an intermediate layer on the organic insulating layer, the intermediate layer defining a third opening exposing at least a portion of the second portion of the auxiliary electrode; and forming a relative electrode on the intermediate layer, the relative electrode contacting an upper surface and a side surface of the auxiliary electrode, wherein the second thickness of the second portion is less than the first thickness of the first portion.

[0018] In an embodiment, forming an intermediate layer on the organic insulating layer may include: continuously forming the intermediate layer on the organic insulating layer and the auxiliary electrode; generating heat by applying a pulse voltage to at least a portion of the second portion of the auxiliary electrode; and defining a third opening exposing the second portion of the auxiliary electrode by removing at least a portion of the intermediate layer disposed on the upper surface and side surfaces of the auxiliary electrode using heat.

[0019] In an embodiment, the pulse width of the pulse voltage may be greater than or equal to about 1 microsecond (μs) and less than or equal to about 10 μs.

[0020] In an embodiment, an area of ​​the third opening of the intermediate layer may be greater than an area of ​​a region in which the auxiliary electrode is disposed.

[0021] In an embodiment, a size of the first opening of the inorganic insulating layer may be greater than a size of the second opening of the organic insulating layer, and a size of the second opening of the organic insulating layer may be greater than a size of the third opening of the intermediate layer.

[0022] In an embodiment, the method may further include: before forming the inorganic insulating layer, forming a first thin film transistor, the first thin film transistor including a semiconductor layer disposed on the substrate, a gate electrode disposed on the semiconductor layer, and a source electrode and a drain electrode disposed on the gate electrode.

[0023] In an embodiment, the method may further include: before forming the intermediate layer, forming a pixel electrode on the organic insulating layer, and forming a pixel defining layer on the pixel electrode, defining an opening in the pixel defining layer that exposes at least a portion of the pixel electrode.

[0024] In an implementation, the pixel defining layer may define a fourth opening through which at least a portion of the second portion of the auxiliary electrode is exposed.

[0025] In an embodiment, the intermediate layer may include a third portion adjacent to the third opening, and a fourth portion spaced apart from the third opening except for the third portion, and a thickness of the third portion in a direction perpendicular to a main plane of the substrate is greater than a thickness of the fourth portion in a direction perpendicular to the main plane of the substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The above and other features and advantages of illustrative embodiments of the present disclosure will become more apparent from the following description taken in conjunction with the accompanying drawings, in which:

[0027] Figure 1 and Figure 2 are perspective views each schematically showing an embodiment of a display device;

[0028] Figure 3 and Figure 4 is an equivalent circuit diagram schematically showing an embodiment of a light emitting diode corresponding to a sub-pixel of a display device and a sub-pixel circuit electrically connected to the light emitting diode;

[0029] Figure 5 is a plan view schematically showing an embodiment of a display panel;

[0030] Figure 6 is a plan view schematically showing an embodiment of a display panel.

[0031] Figure 7 It is schematically shown Figure 6 An enlarged plan view of area A in FIG.

[0032] Figure 8 is a cross-sectional view schematically showing an embodiment of a display panel; and

[0033] Figures 9 to 16 is a cross-sectional view schematically illustrating a method of manufacturing a display panel. DETAILED DESCRIPTION

[0034] Reference will now be made in detail to embodiments, exemplary embodiments of which are shown in the accompanying drawings, wherein the same reference numerals represent the same elements throughout. In this regard, the illustrated embodiments may have different forms and should not be construed as being limited to the descriptions set forth herein. Therefore, embodiments are described below only by reference to the accompanying drawings to explain the features of the specification. As used herein, the term "and / or" includes any and all combinations of one or more of the relevant listed items. Throughout this disclosure, the expression "at least one of a, b, and c" means only a, only b, only c, both a and b, both a and c, both b and c, all of a, b, and c, or variations thereof.

[0035] Since the present disclosure allows various changes and multiple embodiments, exemplary embodiments will be shown in the drawings and described in detail in the written description. Hereinafter, the effects and features of the present disclosure and methods for implementing them will be more fully described with reference to the drawings, in which embodiments of the present disclosure are shown. However, the present disclosure can be implemented in many different forms and should not be construed as being limited to the embodiments set forth herein.

[0036] Hereinafter, embodiments will be described with reference to the accompanying drawings, wherein like reference numerals denote like elements throughout and repeated descriptions thereof will be omitted.

[0037] In the following embodiments, terms such as "first" and "second" are used herein only to describe various elements, but these elements are not limited by these terms. These terms are only for the purpose of distinguishing one element from another element.

[0038] In the following embodiments, an expression used in the singular includes an expression in the plural unless it has an apparently different meaning in the context.

[0039] In the following embodiments, terms such as “include” or “comprising” may be interpreted as indicating specific characteristics or elements or a combination thereof, but may not be interpreted as excluding the possibility of existence or addition of one or more other characteristics, elements or a combination thereof.

[0040] It will be understood that when a layer, region or element is referred to as being “formed on” another layer, region or element, it can be directly or indirectly formed on the other layer, region or element. That is, for example, intervening layers, regions or elements may be present.

[0041] For the convenience of explanation, the size of the elements in the drawings may be enlarged or reduced. For example, since the size and thickness of the elements in the drawings are arbitrarily shown for the convenience of explanation, the present disclosure is not limited thereto.

[0042] When the embodiments may be implemented differently, the predetermined process order may be performed differently from the described order. In the embodiments, two consecutively described processes may be performed substantially simultaneously, or in an order opposite to the described order.

[0043] In the present disclosure, "A and / or B" means A or B, or A and B. In addition, "at least one of A and B" means A, B, or A and B.

[0044] It will be understood that when a layer, region, or element is also referred to as being “connected” to another layer, region, or element, it may be “directly connected” to another layer, region, or element, or / and may be “indirectly connected” to another layer, region, or element with other layers, regions, or elements therebetween. In an embodiment, it will be understood that when a layer, region, or element is also referred to as being “electrically connected” to another layer, region, or element, it may be “directly electrically connected” to another layer, region, or element, or / and may be “indirectly electrically connected” to another layer, region, or element with other layers, regions, or elements therebetween.

[0045] The x-axis, y-axis, and z-axis are not limited to the three axes of a quadrilateral coordinate system (eg, a rectangular coordinate system) and may be interpreted in a broader sense. In an embodiment, the x-axis, y-axis, and z-axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other.

[0046] As used herein, "about" or "approximately" includes the stated value and means within an acceptable range of deviation of the particular value determined by one of ordinary skill in the art, in view of the measurements in question and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, a term such as "about" may mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value.

[0047] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. It will also be understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology and the present disclosure, and will not be interpreted in an idealized or overly formal sense unless explicitly so defined herein.

[0048] Figure 1 and Figure 2 It is a perspective view schematically showing an embodiment of the display device 1 .

[0049] refer to Figure 1 and Figure 2 , the display device 1 may include a display area DA and a non-display area NDA disposed outside the display area DA. An image may be displayed in the display area DA by means of sub-pixels PX arranged in the display area DA. The non-display area NDA is a non-display area disposed outside the display area DA and in which an image is not displayed, and may surround the entire display area DA. A driver or the like for providing an electrical signal or power to the display area DA may be disposed in the non-display area NDA. A pad may be disposed in the non-display area NDA, which is an area that may be connected to an electronic component or a printed circuit board.

[0050] Figure 1 An embodiment is shown in which the display area DA has a polygonal shape (eg, a quadrilateral) whose length in the x direction is smaller than its length in the y direction. However, in another embodiment, Figure 2 Another embodiment is shown in which the display area DA has a polygonal shape (eg, a quadrilateral) whose length in the y direction is smaller than its length in the x direction. Figure 1 and Figure 2 The display area DA has an approximately quadrilateral shape, but the present disclosure is not limited thereto. In another embodiment, the display area DA may be an N-gon (N is a natural number greater than or equal to 3), or may have various shapes such as a circle or an ellipse. Figure 1 and Figure 2 In the embodiment, the corner portion of the display area DA has a shape including a vertex where two straight lines intersect. However, in another embodiment, the display area DA may have a polygonal shape whose corner portions are rounded.

[0051] Although the display device 1 is described below as an electronic device for a smart phone, for ease of description, the display device 1 of the embodiment is not limited thereto. The display device 1 can be applied not only to portable electronic devices such as mobile phones, smart phones, tablet personal computers, mobile communication terminals, electronic notebooks, electronic books, portable multimedia players ("PMP"), navigation, or ultra-mobile personal computers ("UMPC"), but also to various products such as televisions, laptop computers, monitors, billboards, or Internet of Things ("IoT") devices. In addition, the display device 1 in the embodiment can be applied to wearable devices such as smart watches, watch phones, glasses-type displays, or head-mounted displays (HMD). In addition, the display device 1 in the embodiment can be applied to an instrument panel of a vehicle, a central information display ("CID") arranged on a central instrument panel or dashboard of a vehicle, an interior mirror display that replaces a side mirror of a vehicle, and a display screen arranged on the rear surface of a front seat as an entertainment device for a rear seat of a vehicle.

[0052] Figure 3 and Figure 4 is an equivalent circuit diagram schematically showing an embodiment of a light emitting diode ED corresponding to a sub-pixel of a display device and a sub-pixel circuit PC electrically connected to the light emitting diode ED.

[0053] refer to Figure 3The light emitting diode ED may be electrically connected to the sub-pixel circuit PC, and the sub-pixel circuit PC may include a first transistor T1, a second transistor T2, and a storage capacitor Cst. A sub-pixel electrode (e.g., an anode) of the light emitting diode ED may be electrically connected to the first transistor T1, and an opposite electrode (e.g., a cathode) of the light emitting diode ED may be electrically connected to an auxiliary line VSL, and may receive a voltage corresponding to a common voltage ELVSS via the auxiliary line VSL.

[0054] The second transistor T2 may transfer the data signal Dm received through the data line DL to the first transistor T1 in response to the scan signal Sgw received through the scan line GW.

[0055] The storage capacitor Cst may be connected to the second transistor T2 and the driving voltage line PL, and may store a voltage corresponding to a voltage difference between a voltage received from the second transistor T2 and a driving voltage ELVDD supplied to the driving voltage line PL.

[0056] The first transistor T1 may be connected to the driving voltage line PL and the storage capacitor Cst, and may control the driving current I in response to a voltage value stored in the storage capacitor Cst. d , driving current I d The light emitting diode ED can be driven by the driving current I d Emitting light having a brightness.

[0057] exist Figure 3 In FIG. 1 , the sub-pixel circuit PC includes two transistors and one storage capacitor. However, the present disclosure is not limited thereto.

[0058] refer to Figure 4 , the sub-pixel circuit PC may include seven transistors and two capacitors.

[0059] The sub-pixel circuit PC may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7, a storage capacitor Cst, and a boost capacitor Cbt. In another embodiment, the sub-pixel circuit PC may not include the boost capacitor Cbt. The sub-pixel electrode (e.g., anode) of the light emitting diode ED may be electrically connected to the first transistor T1 via the sixth transistor T6, and the opposite electrode (e.g., cathode) of the light emitting diode ED may be electrically connected to the auxiliary line VSL, and may receive a voltage corresponding to the common voltage ELVSS via the auxiliary line VSL.

[0060] Some of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are n-channel metal oxide semiconductor field effect transistors ("n-channel MOSFET"; "NMOS"), and the other transistors may be p-channel MOSFETs ("PMOS"). In an embodiment, as Figure 4 As shown, the third transistor T3 and the fourth transistor T4 may be NMOS, and the other transistors may be PMOS. In an embodiment, the third transistor T3 and the fourth transistor T4 may be NMOS including an oxide-based semiconductor material, and the other transistors may be PMOS including a silicon-based semiconductor material. In another embodiment, for example, the third transistor T3, the fourth transistor T4, and the seventh transistor T7 may be NMOS, and the other transistors may be PMOS.

[0061] The first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7, the storage capacitor Cst and the boost capacitor Cbt may be connected to the signal line. The signal line may include a scan line GW, an emission control line EM, a compensation gate line GC, a first initialization gate line GI1, a second initialization gate line GI2 and a data line DL. The sub-pixel circuit PC may be electrically connected to a voltage line, such as a driving voltage line PL, a first initialization voltage line VL1 and a second initialization voltage line VL2.

[0062] The first transistor T1 may be a driving transistor. The first gate electrode of the first transistor T1 may be connected to the storage capacitor Cst, the first electrode of the first transistor T1 may be electrically connected to the driving voltage line PL via the fifth transistor T5, and the second electrode of the first transistor T1 may be electrically connected to the first electrode (e.g., anode) of the light emitting diode ED via the sixth transistor T6. One of the first electrode and the second electrode of the first transistor T1 may be a source electrode, and the other electrode may be a drain electrode. The first transistor T1 may provide a driving current I to the light emitting diode ED in response to a switching operation of the second transistor T2. d .

[0063] The second transistor T2 may be a switching transistor. The second gate electrode of the second transistor T2 may be connected to the scan line GW, the first electrode of the second transistor T2 may be connected to the data line DL, and the second electrode of the second transistor T2 may be electrically connected to the drive voltage line PL and to the first electrode of the first transistor T1 via the fifth transistor T5. One of the first electrode and the second electrode of the second transistor T2 may be a source electrode, and the other electrode may be a drain electrode. The second transistor T2 may be turned on in response to a scan signal Sgw received via the scan line GW, and perform a switching operation for transmitting a data signal Dm received via the data line DL to the first electrode of the first transistor T1.

[0064] The third transistor T3 may be a compensation transistor for compensating for the threshold voltage of the first transistor T1. The third gate electrode of the third transistor T3 may be connected to the compensation gate line GC. The first electrode of the third transistor T3 may be connected to the lower electrode CE1 of the storage capacitor Cst and the first gate electrode of the first transistor T1 via the node connection line 166. The first electrode of the third transistor T3 may be connected to the fourth transistor T4. The second electrode of the third transistor T3 may be electrically connected to the first electrode (e.g., anode) of the light emitting diode ED and to the second electrode of the first transistor T1 via the sixth transistor T6. One of the first electrode and the second electrode of the third transistor T3 may be a source electrode, and the other electrode may be a drain electrode.

[0065] The third transistor T3 may be turned on in response to the compensation signal Sgc received via the compensation gate line GC, and electrically connected to the first gate electrode and the second electrode (eg, the drain electrode) of the first transistor T1 to diode-connect the first transistor T1 .

[0066] The fourth transistor T4 may be an initialization transistor for initializing the first gate electrode of the first transistor T1. The fourth gate electrode of the fourth transistor T4 may be connected to the first initialization gate line GI1. The first electrode of the fourth transistor T4 may be connected to the first initialization voltage line VL1. The second electrode of the fourth transistor T4 may be connected to the lower electrode CE1 of the storage capacitor Cst, the first electrode of the third transistor T3, and the first gate electrode of the first transistor T1. One of the first electrode and the second electrode of the fourth transistor T4 may be a source electrode, and the other electrode may be a drain electrode. The fourth transistor T4 may be turned on in response to the first initialization signal Sgi1 received via the first initialization gate line GI1, and may perform an initialization operation for transferring the first initialization voltage Vint to the first gate electrode of the first transistor T1 and initializing the voltage of the first gate electrode of the first transistor T1.

[0067] The fifth transistor T5 may be an operation control transistor. A fifth gate electrode of the fifth transistor T5 may be connected to the emission control line EM, a first electrode of the fifth transistor T5 may be connected to the driving voltage line PL, and a second electrode of the fifth transistor T5 may be electrically connected to the first electrode of the first transistor T1 and the second electrode of the second transistor T2. One of the first electrode and the second electrode of the fifth transistor T5 may be a source electrode, and the other electrode may be a drain electrode.

[0068] The sixth transistor T6 may be an emission control transistor. A sixth gate electrode of the sixth transistor T6 may be electrically connected to the emission control line EM, a first electrode of the sixth transistor T6 may be connected to the second electrode of the first transistor T1 and the second electrode of the third transistor T3, and a second electrode of the sixth transistor T6 may be electrically connected to the second electrode of the seventh transistor T7 and the first electrode (e.g., anode) of the light emitting diode ED. One of the first electrode and the second electrode of the sixth transistor T6 may be a source electrode, and the other electrode may be a drain electrode.

[0069] The fifth transistor T5 and the sixth transistor T6 may be turned on simultaneously in response to the emission control signal Sem received via the emission control line EM, so that the driving voltage ELVDD is transferred to the light emitting diode ED and the driving current I d flows through the light emitting diode ED.

[0070] The seventh transistor T7 may be a second initialization transistor for initializing a first electrode (e.g., an anode) of the light emitting diode ED. The seventh gate electrode of the seventh transistor T7 may be connected to the second initialization gate line GI2. The first electrode of the seventh transistor T7 may be connected to the second initialization voltage line VL2. The second electrode of the seventh transistor T7 may be connected to the second electrode of the sixth transistor T6 and the first electrode (e.g., an anode) of the light emitting diode ED. The seventh transistor T7 may be turned on in response to a second initialization signal Sgi2 received via the second initialization gate line GI2, and transfer the second initialization voltage Vaint to the first electrode (e.g., an anode) of the light emitting diode ED to initialize the first electrode of the light emitting diode ED.

[0071] In some embodiments, the second initialization voltage line VL2 may be a next scan line. In an embodiment, for example, the second initialization gate line GI2 (the second initialization gate line GI2 is disposed in the i-th (i is a natural number greater than 0) row) connected to the seventh transistor T7 of the sub-pixel circuit PC may correspond to the scan line of the sub-pixel circuit PC disposed in the i+1-th row. In another embodiment, the second initialization voltage line VL2 may be an emission control line EM. In an embodiment, for example, the emission control line EM may be electrically connected to the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7.

[0072] The storage capacitor Cst may include a lower electrode CE1 and an upper electrode CE2. The lower electrode CE1 of the storage capacitor Cst may be connected to the first gate electrode of the first transistor T1, and the upper electrode CE2 of the storage capacitor Cst may be connected to the driving voltage line PL. The storage capacitor Cst may store charges corresponding to a voltage difference between a voltage of the first gate electrode of the first transistor T1 and the driving voltage ELVDD.

[0073] The boosting capacitor Cbt may include a third electrode CE3 and a fourth electrode CE4. The third electrode CE3 may be connected to the second gate electrode of the second transistor T2 and the scan line GW, and the fourth electrode CE4 may be connected to the first electrode of the third transistor T3 and the node connection line 166. When the scan signal Sgw received via the scan line GW is turned off, the boosting capacitor Cbt may increase the voltage of the first node N1, and when the voltage of the first node N1 increases, a black grayscale may be strongly presented.

[0074] The first node N1 may be a region where the first gate electrode of the first transistor T1 , the first electrode of the third transistor T3 , the second electrode of the fourth transistor T4 , and the fourth electrode CE4 of the boosting capacitor Cbt contact each other.

[0075] In an embodiment, Figure 4 It is shown that the third transistor T3 and the fourth transistor T4 are NMOS, and the first transistor T1, the second transistor T2, and the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are PMOS. The first transistor T1, which directly affects the brightness of the display device on which the image is displayed, includes a semiconductor layer including highly reliable polysilicon, so that a high-resolution display device can be realized.

[0076] exist Figure 4 In the embodiment, some transistors are NMOS and other transistors are PMOS. However, the present disclosure is not limited thereto. In another embodiment, the sub-pixel circuit PC may include three transistors that are all NMOS, and various modifications may be made.

[0077] Figure 5 is a plan view schematically showing an embodiment of the display panel 10 .

[0078] refer to Figure 5 The display panel 10 may include first and second scan driving units 20 and 30, a terminal unit 40, a data driving unit 50, and power supply lines disposed on a substrate 100. The power supply lines may include a driving voltage supply line 60 and a common voltage supply line 70.

[0079] The substrate 100 may include a bending area BA in which a portion of the peripheral area PA is bent. When the extended peripheral area PA is folded relative to the bending area BA, the peripheral area PA may partially overlap with the display area DA. With this structure, the extended peripheral area PA may not be visible to the user, and even when the peripheral area PA is visible, the visible area may be minimized.

[0080] A plurality of sub-pixels PX may be arranged in the display area DA. Each of the sub-pixels PX may be implemented by a display element DPE such as an organic light emitting diode. In an embodiment, for example, each of the sub-pixels PX may emit red light, green light, blue light, or white light.

[0081] Each of the sub-pixel circuits PC for driving the sub-pixels PX in the display area DA may be connected to a circuit for controlling the display element DPE (eg, Figure 3 and Figure 4 A signal line or voltage line for turning on / off and brightness of a light emitting diode (LED). In an embodiment, for example, Figure 5 The scan lines SL extending in a first direction (eg, x direction) and the data lines DL extending in a second direction (eg, y direction) are illustrated as signal lines, and the driving voltage lines PL are illustrated as voltage lines.

[0082] Each of the sub-pixel circuits PC for driving the sub-pixels PX may be electrically connected to an external circuit disposed in the peripheral area PA. In the peripheral area PA, the first and second scan driving units 20 and 30, the terminal unit 40, the data driving unit 50, the driving voltage supply line 60, and the common voltage supply line 70 may be disposed.

[0083] The first scan driving unit 20 and the second scan driving unit 30 may generate a scan signal and transmit it to each of the sub-pixel circuits PC via the scan line SL. In an embodiment, one of the first scan driving unit 20 and the second scan driving unit 30 may apply an emission control signal to each of the sub-pixel circuits PC via an emission control line. In an embodiment, a structure in which the first scan driving unit 20 and the second scan driving unit 30 are arranged at opposite sides of the display area DA is shown. However, in another embodiment, the scan driving unit may be provided only at one side of the display area DA. The second scan driving unit 30 may be provided to be symmetrical with the first scan driving unit 20 with respect to the display area DA.

[0084] The data driving unit 50 may generate a data signal and transmit it to each of the sub-pixel circuits PC via the data line DL and the wiring FW. The data driving unit 50 may be disposed at one side of the display area DA, and may be disposed in the peripheral area PA extending from the lower side of the display area DA in the downward direction (eg, y direction). Figure 5 In the embodiment, the data driving unit 50 is disposed on the substrate 100. However, in another embodiment, the data driving unit 50 may be disposed on a flexible printed circuit board connected to the terminal unit 40.

[0085] The terminal unit 40 may be disposed at one end of the substrate 100 and may include a plurality of terminals 41, 42, 43, and 44. The terminal unit 40 may be exposed without being covered by an insulating layer and may be electrically connected to a controller such as a printed circuit board or an integrated circuit ("IC") chip. The control signal of the controller may be provided to the first scan driving unit 20, the second scan driving unit 30, the data driving unit 50, the driving voltage supply line 60, and the common voltage supply line 70 via the terminal unit 40, respectively.

[0086] The driving voltage supply line 60 may be disposed in the peripheral area PA. The driving voltage supply line 60 may provide a driving voltage ELVDD to each of the sub-pixels PX. In an embodiment, the driving voltage supply line 60 may include a first driving voltage supply line 61, a second driving voltage supply line 62, and a third driving voltage supply line 63. The third driving voltage supply line 63 may extend in a first direction (e.g., an x ​​direction), and the first driving voltage supply line 61 and the second driving voltage supply line 62 may each extend in a second direction (e.g., a y direction). In an embodiment, for example, the third driving voltage supply line 63 may be disposed along a first edge E1 of the display area DA. In an embodiment, the first driving voltage supply line 61, the second driving voltage supply line 62, and the third driving voltage supply line 63 may be integrally disposed as a single body. In an embodiment, for example, the driving voltage supply line 60 may have a "π" ("PI") shape as a whole. However, the present disclosure is not limited thereto.

[0087] The driving voltage supply line 60 may be disposed in the peripheral area PA and connected to a plurality of driving voltage lines PL, each of which extends to the display area DA in the second direction (e.g., the y direction). In an embodiment, for example, the third driving voltage supply line 63 may be connected to the driving voltage line PL crossing the display area DA in the second direction (e.g., the y direction).

[0088] The common voltage supply line 70 may be disposed in the peripheral area PA, and may provide a common voltage ELVSS to each of the sub-pixels PX. The common voltage supply line 70 may include a first common voltage supply line 71 and a second common voltage supply line 73, which are arranged adjacent to the first edge E1. Each of the first common voltage supply line 71 and the second common voltage supply line 73 may extend in a second direction (e.g., y direction). In addition, the first common voltage supply line 71 and the second common voltage supply line 73 may be arranged to be spaced apart from each other in a first direction (e.g., x direction) intersecting the second direction (e.g., y direction). The first common voltage supply line 71 and the second common voltage supply line 73 may be arranged at opposite sides of the first edge E1 of the display area DA, respectively. However, the present disclosure is not limited thereto. The common voltage supply line 70 may further include a third common voltage supply line between the first common voltage supply line 71 and the second common voltage supply line 73. When the common voltage supply line 70 includes a third common voltage supply line between the first and second common voltage supply lines 71 and 73 , current density can be reduced and heat generation can be suppressed compared to a case where only the first and second common voltage supply lines 71 and 73 are provided.

[0089] The first and second common voltage supply lines 71 and 73 may be connected to the main body 75 extending along the second, third and fourth edges E2, E3 and E4 of the display area DA. In an embodiment, the first and second common voltage supply lines 71, 73 and the main body 75 may be integrally provided as a single body.

[0090] The dam DM may be disposed in the peripheral area PA. The dam DM may be disposed to surround the outer boundary of the display area DA. The dam DM may be disposed outside the common voltage supply line 70 or may be disposed to partially overlap the common voltage supply line 70.

[0091] The encapsulation layer 300 may be disposed in the display area DA to cover the area in which the sub-pixel PX is disposed, and a portion of the encapsulation layer 300 may extend to the peripheral area PA. The encapsulation layer 300 has a multilayer structure including at least one organic encapsulation layer and at least one inorganic encapsulation layer, and the dam portion DM may prevent a material included in the encapsulation layer 300 for forming the organic encapsulation layer from diffusing toward an edge of the substrate 100 and limit a formation position of the organic encapsulation layer.

[0092] Figure 6 1 is a plan view schematically showing the display panel 10. In the embodiment, for example, the common voltage supply line 70 and the auxiliary electrode 400 are shown.

[0093] refer to Figure 6As described above, the common voltage supply line 70 may include a first common voltage supply line 71, a second common voltage supply line 73, and a main body unit 75. The first common voltage supply line 71 and the second common voltage supply line 73 may be arranged to extend in a second direction (e.g., a y direction or a −y direction), and the first common voltage supply line 71 and the second common voltage supply line 73 may be arranged to be spaced apart from each other in a first direction (e.g., an x ​​direction or a −x direction). The first common voltage supply line 71 and the second common voltage supply line 73 may be electrically connected through the main body unit 75. The common voltage supply line 70 may be disposed in the peripheral area PA (reference Figure 5 ) and can be directed to the sub-pixel PX (reference Figure 5 ) each provides a common voltage ELVSS.

[0094] As the size of the display panel 10 increases, in order to improve the voltage drop phenomenon in which the brightness of the central portion of the display panel 10 is reduced, the auxiliary electrode 400 electrically connected to the common voltage supply line 70 may be disposed in the active area of ​​the display panel 10, thereby reducing the common voltage supply line 70 and the sub-pixel circuit PC (refer to FIG. Figure 3 ) between the two.

[0095] The auxiliary electrodes 400 may be arranged to extend in a first direction (e.g., an x ​​direction or a −x direction). The auxiliary electrodes 400 may be arranged to be spaced apart from each other in a second direction (e.g., a y direction or a −y direction). The auxiliary electrodes 400 may be electrically connected to the main body unit 75 of the common voltage supply line 70. The common voltage ELVSS may be provided to the sub-pixel circuit PC (reference Figure 3 ), so that the common voltage supply line 70 and the sub-pixel circuit PC (reference Figure 3 ), and the voltage drop phenomenon can be improved, and thus the brightness of the central portion of the display panel 10 can be improved. However, the present disclosure is not limited thereto. In another embodiment, the auxiliary electrode 400 may extend in the second direction (e.g., the y direction or the -y direction), and the auxiliary electrodes 400 may be arranged to be spaced apart from each other in the first direction (e.g., the x direction or the -x direction). The auxiliary electrodes 400 each extending in the second direction (e.g., the y direction or the -y direction) may be electrically connected to the main body unit 75 extending in the first direction (e.g., the x direction or the -x direction).

[0096] Figure 7 It is schematically shown Figure 6 Specifically, Figure 7 A plan view of an auxiliary electrode 400 and sub-pixels arranged adjacent to the auxiliary electrode 400 is schematically illustrated.

[0097] refer to Figure 7 , the sub-pixel unit may be arranged to overlap with the auxiliary electrode 400 or be adjacent to the auxiliary electrode 400. The sub-pixel unit may include a first sub-pixel PX1, a second sub-pixel PX2, and a third sub-pixel PX3. The first sub-pixel PX1, the second sub-pixel PX2, and the third sub-pixel PX3 may emit light of different colors from each other. In an embodiment, for example, the first sub-pixel PX1 may emit red light, and the second sub-pixel PX2 may emit green light. In addition, the third sub-pixel PX3 may emit blue light. The first sub-pixel PX1 and the second sub-pixel PX2 may be arranged to be spaced apart from the auxiliary electrode 400. Specifically, the first sub-pixel PX1 and the second sub-pixel PX2 may be arranged to be spaced apart from the auxiliary electrode 400 in the -y direction. The third sub-pixel PX3 may be arranged to overlap with the auxiliary electrode 400.

[0098] The auxiliary electrode 400 may be disposed to extend in a first direction (eg, x direction or -x direction). The auxiliary electrode 400 may include a first portion 400a and a second portion 400b. Although not shown, in the display panel 10 (refer to Figure 6 ), the second portions 400b of the auxiliary electrode 400 may be arranged to be spaced apart from each other in a first direction (e.g., the x direction or the -x direction), and the first portion 400a of the auxiliary electrode 400 is between them. However, the present disclosure is not limited thereto. The auxiliary electrode 400 may be arranged to extend in a second direction (e.g., the y direction or the -y direction), and in this case, the second portions 400b of the auxiliary electrode 400 may be arranged to be spaced apart from each other in a second direction (e.g., the y direction or the -y direction), and the first portion 400a of the auxiliary electrode 400 is located between them.

[0099] The first portion 400a of the auxiliary electrode 400 may have a first thickness t1 in the second direction (e.g., the y direction or the -y direction). The second portion 400b of the auxiliary electrode 400 may have a second thickness t2 in the second direction (e.g., the y direction or the -y direction). The second thickness t2 of the second portion 400b of the auxiliary electrode 400 may be less than the first thickness t1 of the first portion 400a of the auxiliary electrode 400. In other words, the first thickness t1 of the first portion 400a of the auxiliary electrode 400 may be greater than the second thickness t2 of the second portion 400b of the auxiliary electrode 400.

[0100] When the second thickness t2 of the second portion 400b of the auxiliary electrode 400 is set to be less than the first thickness t1 of the first portion 400a of the auxiliary electrode 400, the wiring resistance of the second portion 400b of the auxiliary electrode 400 may be greater than the wiring resistance of the first portion 400a of the auxiliary electrode 400. When a pulse voltage is applied to the second portion 400b (which has a thickness smaller than that of the first portion 400a and has a relatively large wiring resistance), heat may be selectively generated in the second portion 400b of the auxiliary electrode 400 due to Joule heating. Since heat is selectively generated only in the second portion 400b of the auxiliary electrode 400, the ambient temperature is not increased, so that the pixel may not be damaged.

[0101] When a pulse voltage is applied to the second portion 400b of the auxiliary electrode 400 and heat is generated due to Joule heating, the intermediate layer 212 (see Figure 8 ) disposed on the second portion 400b of the auxiliary electrode 400 may be removed. In addition, due to the heat generated in the second portion 400b of the auxiliary electrode 400, at least a portion of the intermediate layer 212 disposed on the first portion 400a of the auxiliary electrode 400 adjacent to the second portion 400b may also be removed. When at least a portion of the intermediate layer 212 disposed on the second portion 400b and the first portion 400a (the first portion 400a is adjacent to the second portion 400b) of the auxiliary electrode 400 is removed, at least a portion of the second portion 400b and the first portion 400a of the auxiliary electrode 400 may be exposed. In this case, the area obtained by removing the intermediate layer 212 adjacent to the second portion 400b of the auxiliary electrode 400 may be larger than the area in which the second portion 400b of the auxiliary electrode 400 is exposed (or disposed). In other words, the second portion 400b of the auxiliary electrode 400 may be disposed inside the area obtained by removing the intermediate layer 212.

[0102] When heat is generated by applying a pulse voltage to the second portion 400b of the auxiliary electrode 400, at least a portion of the intermediate layer 212 disposed on the second portion 400b of the auxiliary electrode 400 and the first portion 400a (the first portion 400a is adjacent to the second portion 400b) may be arranged by being pushed aside from the second portion 400b of the auxiliary electrode 400. In other words, the thickness of the intermediate layer 212 at the point where the region obtained by removing the intermediate layer 212 starts may be greater than the thickness of the adjacent intermediate layer 212. Figure 8 Describe it in more detail.

[0103] When the auxiliary electrode having an undercut shape is set to be spaced apart from the display panel, and due to the difference in incident angles between the intermediate layer deposited on the auxiliary electrode having the undercut shape and the relative electrode, the relative electrode contacts the auxiliary electrode. Since the difference in incident angles is small, the degree of contact between the relative electrode and the auxiliary electrode can be small, and the voltage drop phenomenon of the display panel may not be effectively improved.

[0104] In an embodiment, when a pulse voltage is applied to the second portion 400b of the auxiliary electrode 400 and heat is generated due to Joule heating, at least a portion of the intermediate layer 212 disposed on the second portion 400b of the auxiliary electrode 400 is removed so that the second portion 400b of the auxiliary electrode 400 is exposed, and thus, the counter electrode 213 (reference Figure 8 ) may be disposed to contact the second portion 400b of the auxiliary electrode 400. Since the auxiliary electrode 400 is electrically connected to the display panel 10 (refer to Figure 6 ) of the common voltage supply lines 71, 73 and 75 (reference Figure 6 ), so the common voltage ELVSS and the sub-pixel circuit PC can be reduced (reference Figure 3 ) and can improve the display panel 10 (reference Figure 6 ) in the effective area, thereby improving the brightness.

[0105] Figure 8 is a cross-sectional view schematically showing the display panel 10. Specifically, Figure 8 Schematically shows the Figure 7 The line I-I' in Figure 7 A cross-sectional view of a display panel in FIG.

[0106] refer to Figure 8 The display panel 10 may include a substrate 100, inorganic insulating layers 111, 112 and 113, an organic insulating layer 114, a first thin film transistor TFT1, an auxiliary electrode 400 (refer to Figure 7 ), a pixel defining layer 115 and an organic light emitting diode OLED. In other words, in the display area of ​​the display panel 10, a substrate 100, inorganic insulating layers 111, 112 and 113, an organic insulating layer 114, a first thin film transistor TFT1, an auxiliary electrode 400 (refer to Figure 7 ), a pixel defining layer 115 and an organic light emitting diode OLED.

[0107] Although not shown, the substrate 100 may include a first base layer, a first barrier layer, a second base layer, and a second barrier layer. In an implementation, the first base layer, the first barrier layer, the second base layer, and the second barrier layer may be sequentially stacked in a thickness direction of the substrate 100.

[0108] At least one of the first base layer and the second base layer may include a polymer resin such as polyethersulfone, polyarylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyimide, polycarbonate, cellulose triacetate, or cellulose acetate propionate.

[0109] The first barrier layer and the second barrier layer are barrier layers for preventing external foreign matter from penetrating, and may include a material such as silicon nitride (SiN x ), silicon oxide (SiO 2 ) and / or one or more layers of inorganic materials of silicon oxynitride (SiON).

[0110] Although not shown, a buffer layer may be provided on the substrate 100. The buffer layer may include, for example, SiN x , SiON or SiO 2 of inorganic insulating material, and may be one layer or more layers including the inorganic insulating material described above.

[0111] The inorganic insulating layers 111 , 112 , and 113 may be disposed on the buffer layer. The inorganic insulating layers 111 , 112 , and 113 may include a first gate insulating layer 111 , a second gate insulating layer 112 , and a first inorganic insulating layer 113 .

[0112] The first thin film transistor TFT1 may be disposed in the display area DA. The first thin film transistor TFT1 may include a semiconductor layer Act, a gate electrode GE, a source electrode SE, and a drain electrode DE.

[0113] The semiconductor layer Act may be disposed on the substrate 100. The semiconductor layer Act may include polycrystalline silicon. In an alternative embodiment, the semiconductor layer Act may include amorphous silicon, an oxide semiconductor, an organic semiconductor, etc. The semiconductor layer Act may include a channel region, a drain region, and a source region, and the drain region and the source region are respectively arranged at opposite sides of the channel region.

[0114] The gate electrode GE may be disposed on the semiconductor layer Act. The gate electrode GE may overlap the channel region. The gate electrode GE may include a low-resistance metal material. The gate electrode GE may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), and titanium (Ti), and the gate electrode GE may include one or more layers including the materials described above.

[0115] The first gate insulating layer 111 may be disposed between the semiconductor layer Act and the gate electrode GE. The first gate insulating layer 111 may include an inorganic insulating material such as SiO 2 、SiN x , SiON, Alumina (Al 2 O 3), titanium oxide (TiO 2 ), Tantalum Oxide (Ta 2 O 5 ), hafnium oxide (HfO 2 ) or zinc oxide (ZnO x (which includes ZnO and / or ZnO 2 )).

[0116] The second gate insulating layer 112 may be disposed on the gate electrode GE. The second gate insulating layer 112 may be disposed to cover the gate electrode GE. The second gate insulating layer 112 may include an inorganic insulating material such as SiO 2 、SiN x 、SiON、Al 2 O 3 、TiO 2 、 2 O 5 , HfO 2 or ZnO x (which includes ZnO and / or ZnO 2 ).

[0117] Although not shown, the storage capacitor Cst (reference Figure 4 ) may be disposed on the second gate insulating layer 112. The upper electrode may overlap the gate electrode GE disposed thereunder. In this case, the gate electrode GE and the upper electrode overlapping each other with the second gate insulating layer 112 therebetween may constitute a storage capacitor Cst (reference Figure 4 ). In other words, the gate electrode GE can be used as a storage capacitor Cst (refer to Figure 4 )'s lower electrode.

[0118] As described above, the storage capacitor Cst (reference Figure 4 ) and the first thin film transistor TFT1 may be formed to overlap each other. However, the present disclosure is not limited thereto. In an embodiment, for example, the storage capacitor Cst (refer to Figure 4 ) may be formed so as not to overlap with the first thin film transistor TFT1. In other words, the storage capacitor Cst (reference Figure 4 ) may be an element separated from the gate electrode GE of the first thin film transistor TFT1, and may be disposed to be spaced apart from the gate electrode GE of the first thin film transistor TFT1.

[0119] The upper electrode may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), Mo, Ti, tungsten (W) and / or Cu, and may be one or more layers of the materials described above.

[0120] The drain electrode DE and the source electrode SE may be disposed on the second gate insulating layer 112. The drain electrode DE and the source electrode SE may be connected to the semiconductor layer Act via contact holes disposed in the first gate insulating layer 111 and the second gate insulating layer 112, respectively. Each of the drain electrode DE and the source electrode SE may include a material having good conductivity. Each of the drain electrode DE and the source electrode SE may include a conductive material including Mo, Al, Cu, and Ti, and each of the drain electrode DE and the source electrode SE may include one or more layers including the materials described above. In an embodiment, for example, each of the drain electrode DE and the source electrode SE may have a multilayer structure of a Ti layer, an Al layer, and another Ti layer.

[0121] Auxiliary electrode 400 (reference Figure 7 ) may be disposed on the second gate insulating layer 112. Figure 8 For example, the second portion 400b of the auxiliary electrode 400 may be disposed on the second gate insulating layer 112. The auxiliary electrode 400 (refer to Figure 7 ) may include a material through which current flows. In an embodiment, the auxiliary electrode 400 (reference Figure 7 ) may include a metal film (Mo or Al) or an oxide film (indium tin oxide ("ITO") or indium zinc oxide ("IZO"). However, the present disclosure is not limited thereto. In another embodiment, the auxiliary electrode 400 (refer to Figure 7 ) may be formed in the same process of forming the source electrode SE and the drain electrode DE, and may include the same material as that of the source electrode SE and the drain electrode DE.

[0122] A first opening OP1 may be defined in the first inorganic insulating layer 113, and an auxiliary electrode 400 (refer to Figure 7 ) is exposed through the first opening OP1. In other words, the auxiliary electrode 400 (refer to Figure 7 ) may be disposed in the first opening OP1 of the first inorganic insulating layer 113 .

[0123] The first inorganic insulating layer 113 may be disposed on the second gate insulating layer 112. The first inorganic insulating layer 113 may include SiO 2 、SiN x 、SiON、Al 2 O 3 、TiO 2 、 2 O 5 , HfO 2 、ZnO x (which includes ZnO and / or ZnO 2The first inorganic insulating layer 113 may be one or more layers including the inorganic insulating material described above.

[0124] The organic insulating layer 114 may be disposed on the first inorganic insulating layer 113. Figure 8 In the embodiment, one organic insulating layer 114 is provided. However, the present disclosure is not limited thereto. Two, three or four organic insulating layers 114 may be provided.

[0125] A second opening OP2 may be defined in the organic insulating layer 114, and the auxiliary electrode 400 (refer to Figure 7 ) is exposed through the second opening OP2. In other words, the auxiliary electrode 400 (refer to Figure 7 ) may be disposed in the second opening OP2 of the organic insulation layer 114.

[0126] The organic insulating layer 114 may include an organic insulating material, such as a general polymer (e.g., poly(methyl methacrylate) (“PMMA”) or polystyrene (“PS”)), a polymer derivative having a phenol-based group, an acrylic-based polymer, an imide-based polymer, an aryl ether-based polymer, an amide-based polymer, a fluorine-based polymer, a paraxylene-based polymer, a vinyl alcohol-based polymer, or any combination thereof.

[0127] The light emitting diode may be disposed on the organic insulating layer 114. In an embodiment, for example, an organic light emitting diode OLED may be disposed on the organic insulating layer 114. In an alternative embodiment, although not shown, an inorganic light emitting diode or the like may be disposed on the organic insulating layer 114.

[0128] The organic light emitting diode OLED may emit one of red light, green light, and blue light, or one of red light, green light, blue light, and white light. The organic light emitting diode OLED may include a pixel electrode 211 , an intermediate layer 212 , and an opposing electrode 213 .

[0129] The pixel electrode 211 may be disposed on the organic insulating layer 114. The pixel electrode 211 may be electrically connected to the source electrode SE or the drain electrode DE via a contact hole defined in the organic insulating layer 114 and the first inorganic insulating layer 113. The pixel electrode 211 may include a conductive oxide such as ITO, IZO, ZnO, In 2 O 3, indium gallium oxide ("IGO") or aluminum zinc oxide ("AZO"). In an embodiment, the pixel electrode 211 may include a reflective film including Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr or any combination thereof. In an embodiment, the pixel electrode 211 may also include a reflective film including ITO, IZO, ZnO or In on / below the reflective film described above. 2 O 3 In an implementation, for example, the pixel electrode 211 may have a multi-layer structure of an ITO layer, an Ag layer, and another ITO layer.

[0130] The pixel defining layer 115 may be disposed on the pixel electrode 211, and an opening exposing at least a portion of the pixel electrode 211 may be formed in the pixel defining layer 115. An emission region of light emitted from the organic light emitting diode OLED may be defined by the opening defined in the pixel defining layer 115. In an embodiment, for example, the width of the opening may correspond to the width of the emission region.

[0131] The pixel defining layer 115 may include an organic insulating material. In an optional embodiment, the pixel defining layer 115 may include an inorganic insulating material such as silicon nitride, silicon oxynitride, or silicon oxide. In an optional embodiment, the pixel defining layer 115 may include an organic insulating material and an inorganic insulating material. In an embodiment, the pixel defining layer 115 may include a light blocking material. The light blocking material may include carbon black, carbon nanotubes, a resin or paste including a black dye, metal particles (such as nickel, aluminum, molybdenum, or any alloy thereof), metal oxide particles (e.g., chromium oxide), or metal nitride particles (e.g., chromium nitride). When the pixel defining layer 115 includes a light blocking material, external reflections caused by a metal structure disposed below the pixel defining layer 115 may be reduced.

[0132] The intermediate layer 212 may be disposed on the pixel electrode 211. The intermediate layer 212 may include an emission layer, a first functional layer, and a second functional layer. The emission layer may be disposed in the opening of the pixel defining layer 115. The emission layer may include a polymer or a low molecular weight organic material that emits light of one color.

[0133] The first functional layer may be disposed between the pixel electrode 211 and the emission layer, and the second functional layer may be disposed between the emission layer and the opposite electrode 213. However, at least one of the first functional layer and the second functional layer may be omitted. The following mainly describes the case where the first functional layer and the second functional layer are arranged.

[0134] The first functional layer may include a hole transport layer ("HTL") and / or a hole injection layer ("HIL"). The second functional layer may include an electron transport layer ("ETL") and / or an electron injection layer ("EIL"). The first functional layer and / or the second functional layer may be a common layer formed to cover all layers except the auxiliary electrode 400 (reference electrode) to be described below. Figure 7 ) of the entire substrate 100 except for the portion adjacent to the second portion 400b.

[0135] The opposing electrode 213 may be disposed on the intermediate layer 212. The opposing electrode 213 may include a conductive material having a relatively low work function. In an embodiment, for example, the opposing electrode 213 may include a (semi) transparent layer including Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca or any alloy thereof. In an optional embodiment, the opposing electrode 213 may also include a (semi) transparent layer including ITO, IZO, ZnO or In on the (semi) transparent layer including the materials described above. 2 O 3 layer.

[0136] Set to be connected to the auxiliary electrode 400 (reference Figure 7 ) of the second portion 400b adjacent to the intermediate layer 212 may be disconnected. In an embodiment, for example, a third opening OP3 may be defined in the intermediate layer 212, and the auxiliary electrode 400 (refer to Figure 7 ) is exposed through the third opening OP3. In other words, the auxiliary electrode 400 (refer to Figure 7 ) may be disposed in the third opening OP3 of the intermediate layer 212.

[0137] In an embodiment, the size of the first opening OP1 of the first inorganic insulating layer 113 may be larger than the size of the second opening OP2 of the organic insulating layer 114. The size of the first opening OP1 of the first inorganic insulating layer 113 may be larger than the size of the third opening OP3 of the intermediate layer 212. The size of the second opening OP2 of the organic insulating layer 114 may be larger than the size of the third opening OP3 of the intermediate layer 212.

[0138] The opposing electrode 213 may be continuously disposed on the substrate 100 to contact the auxiliary electrode 400 (refer to Figure 7 ) of the upper surface and the side surface of the second portion 400b. When the auxiliary electrode 400 (reference Figure 7 ) is exposed by the third opening OP3 of the intermediate layer 212, the counter electrode 213 and the auxiliary electrode 400 (reference Figure 7 ) can be arranged to contact each other. Figure 7) is electrically connected to the common voltage supply lines 71, 73 and 75 (reference Figure 6 ), so the auxiliary electrode 400 (reference Figure 7 ) and the opposite electrode 213 may contact each other so that the common voltage ELVSS and the sub-pixel circuit PC (reference Figure 3 ) can be reduced, and thus, the display panel 10 (reference Figure 6 ) and the voltage drop phenomenon in the effective area of ​​the display panel 10 (reference Figure 6 ) brightness.

[0139] The size of the region of the third opening OP3 of the intermediate layer 212 may be larger than the region in which the auxiliary electrode 400 (refer to Figure 7 ) of the region 400A. When the pulse voltage is applied to the second portion 400b, heat may be generated due to Joule heating, and due to the heat, at least a portion of the intermediate layer 212 disposed on the second portion 400b may be removed. Figure 7 ) can remove the heat generated in the intermediate layer 212 disposed on the auxiliary electrode 400 (reference Figure 7 ) on at least a portion of the second portion 400b, and provided on the auxiliary electrode 400 (reference Figure 7 ) on the intermediate layer 212 of the first portion 400a. In other words, by the auxiliary electrode 400 (reference Figure 7 ) is defined by the heat generated in the middle layer 212, and not only can the auxiliary electrode 400 (reference Figure 7 ) of the second portion 400b, and the auxiliary electrode 400 (reference Figure 7 ) at least a portion of the first portion 400a. The auxiliary electrode 400 (reference Figure 7 ) is exposed together with at least a portion of the first portion 400a, so that the counter electrode 213 and the auxiliary electrode 400 (reference Figure 7 ) can be increased, and the display panel 10 (reference Figure 6 )’s voltage drop phenomenon and brightness defects in the effective area.

[0140] Since the auxiliary electrode 400 (reference Figure 7), at least a portion of the intermediate layer 212 disposed on the second portion 400b may be disposed to be pushed to the side of the position where the third opening OP3 of the intermediate layer 212 starts. The intermediate layer 212 may include a third portion 212a disposed at a point where the third opening OP3 starts, and a fourth portion 212b disposed to be spaced apart from the third opening OP3 except the third portion 212a. The third portion 212a may include at least a portion of the intermediate layer 212, which is disposed on the second portion 400b, and then due to the auxiliary electrode 400 (reference Figure 7 ) is pushed to the side of the third opening OP3. The third portion 212a may have a third thickness t3 in a direction perpendicular to the main plane of the substrate 100. The fourth portion 212b may have a fourth thickness t4 in a direction perpendicular to the main plane of the substrate 100. The third thickness t3 of the third portion 212a may be greater than the fourth thickness t4 of the fourth portion 212b. However, the present disclosure is not limited thereto.

[0141] A fourth opening OP4 may be defined in the pixel defining layer 115, and an auxiliary electrode 400 (refer to Figure 7 ) is exposed through the fourth opening OP4. Since the fourth opening OP4 is defined in the pixel defining layer 115, the auxiliary electrode 400 (refer to Figure 7 ) may be exposed to contact the opposite electrode 213. The size of the fourth opening OP4 of the pixel defining layer 115 may be larger than each of the size of the third opening OP3 of the intermediate layer 212 and the size of the second opening OP2 of the organic insulating layer 114.

[0142] Figures 9 to 16 is a cross-sectional view schematically illustrating a method of manufacturing a display panel.

[0143] refer to Fig. 9 A first thin film transistor TFT1 including a semiconductor layer Act, a gate electrode GE, a source electrode SE, and a drain electrode DE may be formed on the substrate 100 . A first gate insulating layer 111 and a second gate insulating layer 112 may be formed on the substrate 100 .

[0144] An auxiliary electrode 400 may be formed on the second gate insulating layer 112 (refer to Figure 7 In an embodiment, for example, an auxiliary electrode 400 may be formed on the second gate insulating layer 112 (refer to Figure 7 ) of the second portion 400b. The auxiliary electrode 400 (reference Figure 7 ) may include a material through which current flows. In an embodiment, for example, the auxiliary electrode 400 (reference Figure 7) may include a metal film (Mo or Al) or an oxide film (ITO or IZO). However, the present disclosure is not limited thereto. In another embodiment, the auxiliary electrode 400 (refer to Figure 7 ) may be formed in the same process of forming the source electrode SE and the drain electrode DE, and may include the same material as that of the source electrode SE and the drain electrode DE.

[0145] refer to Fig.10 , a first inorganic insulating layer 113 may be formed on the second gate insulating layer 112. The first inorganic insulating layer 113 may include SiO 2 、SiN x 、SiON、Al 2 O 3 、TiO 2 、 2 O 5 , HfO 2 、ZnO x (which includes ZnO and / or ZnO 2 ) etc. The first inorganic insulating layer 113 may be one or more layers including the inorganic insulating material described above.

[0146] A first opening OP1 through which at least a portion of the second portion 400b of the auxiliary electrode 400 is exposed may be defined in the first inorganic insulating layer 113. In other words, the second portion 400b of the auxiliary electrode 400 may be disposed in the first opening OP1 of the first inorganic insulating layer 113. The first opening OP1 of the first inorganic insulating layer 113 may be formed to surround the second portion 400b of the auxiliary electrode 400.

[0147] refer to Fig.11 , an organic insulating layer 114 may be formed on the first inorganic insulating layer 113. The organic insulating layer 114 may include an organic insulating material such as a general polymer such as PMMA and PS, a polymer derivative having a phenol-based group, an acrylic-based polymer, an imide-based polymer, an aryl ether-based polymer, an amide-based polymer, a fluorine-based polymer, a p-xylene-based polymer, a vinyl alcohol-based polymer, or any combination thereof.

[0148] A second opening OP2 through which at least a portion of the second portion 400b of the auxiliary electrode 400 is exposed may be defined in the organic insulating layer 114. In other words, the second portion 400b of the auxiliary electrode 400 may be disposed in the second opening OP2 of the organic insulating layer 114. The second opening OP2 of the organic insulating layer 114 may be formed to surround the second portion 400b of the auxiliary electrode 400. The size of the second opening OP2 of the organic insulating layer 114 may be smaller than the size of the first opening OP1 of the first inorganic insulating layer 113.

[0149] refer to Fig.12 and Fig.13 , a pixel electrode 211 may be formed on the organic insulating layer 114, and a pixel defining layer 115 exposing at least a portion of the pixel electrode 211 may be formed on the pixel electrode 211. On the pixel electrode 211, an intermediate layer 212 may be continuously formed on the substrate 100. An opening region of the pixel defining layer 115 through which at least a portion of the pixel electrode 211 is exposed may correspond to an emission region of the organic light emitting diode OLED.

[0150] In an embodiment, a fourth opening OP4 may be defined in the pixel defining layer 115. Through the fourth opening OP4 of the pixel defining layer 115, at least a portion of the second portion 400b of the auxiliary electrode 400 may be exposed. In other words, the second portion 400b of the auxiliary electrode 400 may be disposed in the fourth opening OP4 of the pixel defining layer 115. The pixel defining layer 115 may be formed to surround the second portion 400b of the auxiliary electrode 400.

[0151] refer to Fig.14 and Fig.15 In order to expose the second portion 400b of the auxiliary electrode 400, a pulse voltage 500 may be applied to the second portion 400b of the auxiliary electrode 400. Figure 7 As shown, because the second portion 400b of the auxiliary electrode 400 is relatively smaller than the first portion 400a of the auxiliary electrode 400 in thickness in the second direction (e.g., the y direction or the -y direction), when the pulse voltage 500 is applied, heat may be selectively generated due to Joule heating, and the sub-pixel may not be damaged. The heat generated in the auxiliary electrode 400 by Joule heating may remove at least a portion of the intermediate layer 212 disposed on the second portion 400b of the auxiliary electrode 400. In other words, the third opening OP3 exposing at least a portion of the second portion 400b of the auxiliary electrode 400 may be formed in the intermediate layer 212 by the heat generated in the auxiliary electrode 400 by Joule heating. Due to the heat generated in the second portion 400b of the auxiliary electrode 400, the temperature of the second portion 400b of the auxiliary electrode 400 and the intermediate layer 212 disposed thereon may be greater than or equal to about 300 degrees Celsius (°C) and less than or equal to about 400°C.

[0152] The size of the third opening OP3 of the intermediate layer 212 may be larger than the size of the region 400A in which the second portion 400b of the auxiliary electrode 400 is disposed, and the third opening OP3 exposes at least a portion of the second portion 400b of the auxiliary electrode 400. Due to the heat generated by applying the pulse voltage 500 to the second portion 400b of the auxiliary electrode 400, at least a portion of the first portion 400a of the auxiliary electrode 400 and the second portion 400b of the auxiliary electrode 400 may be exposed. In other words, due to the heat generated by applying the pulse voltage 500 to the second portion 400b, not only the intermediate layer 212 disposed on the second portion 400b of the auxiliary electrode 400 may be removed, but also the intermediate layer 212 disposed on the first portion 400a adjacent thereto may be removed. Since at least a portion of the second portion 400b and the first portion 400a of the auxiliary electrode 400 are exposed to contact the opposing electrode 213, the area of ​​the auxiliary electrode 400 may be increased, thereby effectively improving the voltage drop phenomenon of the display panel.

[0153] In an embodiment, the pulse width of the pulse voltage 500 may be greater than or equal to about 1 microsecond (μs) and less than or equal to about 10 μs. When the pulse width of the pulse voltage 500 is less than or equal to about 1 μs, heat sufficient to remove at least a portion of the intermediate layer 212 disposed on the second portion 400b of the auxiliary electrode 400 may not be generated. When the pulse width of the pulse voltage 500 is less than or equal to about 1 μs, at least a portion of the intermediate layer 212 disposed on the second portion 400b of the auxiliary electrode 400 may not be removed. When the pulse width of the pulse voltage 500 is greater than about 10 μs, the heat generated in the second portion 400b of the auxiliary electrode 400 may diffuse to the area surrounding it, thereby damaging the sub-pixel and adversely affecting the brightness and reliability of the display panel.

[0154] refer to Fig.16 , an opposing electrode 213 may be formed on the side surface and the upper surface of the second portion 400b of the auxiliary electrode 400, which are exposed by the third opening OP3 of the intermediate layer 212. In other words, the opposing electrode 213 may be continuously formed on the substrate 100. By forming the opposing electrode 213 on the pixel electrode 211 and the intermediate layer 212, an organic light emitting diode OLED may be formed on the first thin film transistor TFT1.

[0155] Since the auxiliary electrode 400 is electrically connected to the display panel 10 (refer to Figure 6 ) of the common voltage supply lines 71, 73 and 75 (reference Figure 6 ), so the second portion 400b of the auxiliary electrode 400 and the opposite electrode 213 may be formed to contact each other, thereby reducing the common voltage ELVSS and the sub-pixel circuit PC (reference Figure 3) between the common voltage ELVSS and the sub-pixel circuit PC (reference Figure 3 ) is reduced, a voltage drop phenomenon in an effective area of ​​the display panel 10 can be improved, and the brightness of the display panel 10 can be improved.

[0156] Because the auxiliary electrode having the undercut shape is disposed to be spaced apart from the display panel, and due to the difference in incident angles between the intermediate layer deposited on the auxiliary electrode having the undercut shape and the opposite electrode, when the opposite electrode and the auxiliary electrode contact each other, the difference in incident angles between the intermediate layer and the opposite electrode is small. Therefore, the contact degree between the opposite electrode and the auxiliary electrode may be small, thereby failing to effectively improve the voltage drop phenomenon of the display panel.

[0157] In an embodiment, when heat is generated by applying the pulse voltage 500 to the second portion 400b of the auxiliary electrode 400, at least a portion of the intermediate layer 212 disposed on the second portion 400b of the auxiliary electrode 400 may be removed to expose the second portion 400b of the auxiliary electrode 400, so that the opposing electrode 213 may be disposed to contact the second portion 400b. Since the auxiliary electrode 400 is electrically connected to the common voltage supply line 70 of the display panel, the distance between the common voltage ELVSS and the sub-pixel circuit PC may be reduced, so that the voltage drop phenomenon in the active area of ​​the display panel 10 and the brightness of the display panel may be improved.

[0158] According to the embodiment configured as described above, a display device having improved reliability and quality and a method thereof can be realized. However, the scope of the present disclosure is not limited by these effects.

[0159] It should be understood that the embodiments described herein should be considered in a descriptive sense only and not for limiting purposes. The description of features or advantages within each embodiment should generally be considered to be applicable to other similar features or advantages in other embodiments. Although the embodiments have been described with reference to the accompanying drawings, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope defined by the appended claims.

Claims

1. A display device, characterized in that include: substrate; A gate insulating layer, disposed on the substrate; an auxiliary electrode, disposed on the gate insulating layer, extending in a first direction in a plane parallel to the main plane of the substrate, and comprising a first portion and a second portion, the first portion having a first thickness in a second direction in the plane intersecting the first direction, and the second portion having a second thickness in the second direction; an inorganic insulating layer disposed on the gate insulating layer and defining a first opening exposing at least a portion of the second portion of the auxiliary electrode; an organic insulating layer disposed on the inorganic insulating layer and defining a second opening exposing the at least a portion of the second portion of the auxiliary electrode; an intermediate layer disposed on the organic insulating layer and defining a third opening exposing the at least a portion of the second portion of the auxiliary electrode; as well as a counter electrode disposed on the intermediate layer and in contact with the upper surface and the side surface of the auxiliary electrode, The second thickness of the second portion is smaller than the first thickness of the first portion.

2. The display device according to claim 1, characterized in that An area of ​​the third opening of the intermediate layer is larger than an area of ​​a region in which the auxiliary electrode is disposed.

3. The display device according to claim 1, characterized in that A size of the first opening of the inorganic insulating layer is greater than a size of the second opening of the organic insulating layer.

4. The display device according to claim 3, characterized in that: The size of the second opening of the organic insulating layer is greater than the size of the third opening of the intermediate layer.

5. The display device according to claim 1, characterized in that The invention also includes a first thin film transistor, which includes a semiconductor layer disposed on the substrate, a gate electrode disposed on the semiconductor layer, and a source electrode and a drain electrode disposed on the gate electrode.

6. The display device according to claim 1, characterized in that: An organic light emitting diode is also included. The organic light emitting diode includes a pixel electrode disposed on the organic insulating layer, the intermediate layer disposed on the pixel electrode, and the opposite electrode disposed on the intermediate layer.

7. The display device according to claim 6, characterized in that: A pixel defining layer is also included. The pixel defining layer is disposed on the pixel electrode and defines an opening in the pixel defining layer that exposes at least a portion of the pixel electrode.

8. The display device according to claim 7, characterized in that: The pixel defining layer defines a fourth opening through which the at least a portion of the second portion of the auxiliary electrode is exposed.

9. The display device according to claim 8, characterized in that: A size of the fourth opening of the pixel defining layer is larger than each of a size of the second opening of the organic insulating layer and a size of the third opening of the intermediate layer.

10. The display device according to claim 1, characterized in that The intermediate layer includes a third portion adjacent to the third opening and a fourth portion other than the third portion and spaced apart from the third opening, and A thickness of the third portion in a direction perpendicular to the main plane of the substrate is greater than a thickness of the fourth portion in the direction perpendicular to the main plane of the substrate.

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