Display device

Abstract

A display device is provided. The display device includes a transistor layer disposed on a substrate and including at least one transistor, an insulating layer disposed on the transistor layer, a first pixel electrode disposed on the insulating layer, a first pixel defining layer covering a side surface of the first pixel electrode and a side surface of the insulating layer and defining a first emission region, a first emission layer disposed in the first emission region on the first pixel electrode, a first common electrode disposed on the first emission layer, and a dam disposed on the insulating layer and surrounding the first pixel electrode. The first pixel electrode and the dam are arranged on a same layer and include a same material.

Description

Technical Field

[0001] The present disclosure relates to a display device and a method of making (or manufacturing) a display device. Background Art

[0002] With the progress of the information society, more and more demands are put forward for display devices for displaying images in various ways. For example, display devices are adopted in various electronic devices such as smart phones, digital cameras, laptop computers, navigation devices, smart TVs and the like. The display device may be a flat panel display device such as a liquid crystal display device, a field emission display device, an organic light emitting display device and the like. Among the flat panel display devices, in the light emitting display device, since each of the pixels of the display panel includes a light emitting element that emits light by itself, it is possible to display an image without a light emitting device that provides light to the display panel. Utility Model Content

[0003] The present disclosure provides a display device and a method of manufacturing the display device that can improve emission efficiency of a light emitting element and easily achieve an ultra-fine process of high resolution.

[0004] However, aspects of the present disclosure are not limited to the aspects set forth herein. The above and other aspects of the present disclosure will become more apparent to those skilled in the art to which the present disclosure pertains by referring to the detailed description of the present disclosure given below.

[0005] According to an embodiment, the display device may include a transistor layer arranged on a substrate and including at least one transistor, an insulating layer arranged on the transistor layer, a first pixel electrode arranged on the insulating layer, a first pixel defining layer covering a side surface of the first pixel electrode and a side surface of the insulating layer and defining a first emission region, a first light emitting layer arranged in the first emission region on the first pixel electrode, a first common electrode arranged on the first light emitting layer, and a dam arranged on the insulating layer and surrounding the first pixel electrode. The first pixel electrode and the dam may be arranged (e.g., directly arranged) on the same layer and include the same material.

[0006] The dam may include a first dam disposed on the insulating layer, a second dam disposed on the first dam, and a third dam disposed on the second dam.

[0007] The side surface of the first dam and the side surface of the second dam may be recessed inwardly from the side surface of the third dam.

[0008] The third dam may include a tip protruding from a side surface of the second dam.

[0009] The first common electrode may cover the first pixel defining layer and the insulating layer and may extend to a side surface of the first dam.

[0010] The first pixel electrode may include a first layer disposed on the insulating layer and a second layer disposed on the first layer.

[0011] The first pixel electrode's first layer and first dam may be disposed (eg, directly disposed) on the same layer and include the same material. The first pixel electrode's second layer and second dam may be disposed (eg, directly disposed) on the same layer and include the same material.

[0012] The display device may also include a second pixel electrode arranged on the insulating layer, a second pixel defining layer covering the side surface of the insulating layer and the side surface of the second pixel electrode and defining a second emission area, a second light-emitting layer arranged in the second emission area on the second pixel electrode, and a second common electrode arranged on the second light-emitting layer.

[0013] The second pixel electrode may include a first layer and a second layer, the first layer and the first dam are arranged (eg, directly arranged) on the same layer and include the same material, and the second layer and the second dam are arranged (eg, directly arranged) on the same layer and include the same material.

[0014] The first common electrode and the second common electrode may be electrically connected through the first dam.

[0015] The display device may further include an electrode pattern disposed on the third dam, the electrode pattern and the first common electrode including the same material.

[0016] The display device may further include a first encapsulation layer disposed on the first common electrode and the electrode pattern and covering side surfaces of the first dam and the second dam.

[0017] According to an embodiment, the display device may include a transistor layer arranged on a substrate and including at least one transistor, a first pixel electrode arranged on the transistor layer, a first pixel defining layer covering a side surface of the first pixel electrode and defining a first emission region, a first light emitting layer arranged in the first emission region on the first pixel electrode, a first common electrode arranged on the first light emitting layer, and a dam arranged on the transistor layer and surrounding the first pixel electrode. The first pixel electrode and the dam may be arranged (e.g., directly arranged) on the same layer and include the same material.

[0018] The dam may include a first dam disposed on the transistor layer, a second dam disposed on the first dam, and a third dam disposed on the second dam.

[0019] The first pixel electrode may include a first layer and a second layer, the first layer and the first dam are arranged (eg, directly arranged) on the same layer and include the same material, and the second layer and the second dam are arranged (eg, directly arranged) on the same layer and include the same material.

[0020] According to an embodiment, a method for manufacturing a display device may include: forming an insulating layer on a substrate; forming a first layer and a first dam of a first pixel electrode on the insulating layer; forming a second layer of the first pixel electrode on the first layer of the first pixel electrode and forming a second dam on the first dam; forming a temporary pixel electrode on the second layer of the first pixel electrode and forming a third dam on the second dam; forming a halftone photoresist on the temporary pixel electrode and forming a photoresist thicker than the halftone photoresist on the third dam; and removing the halftone photoresist and the temporary pixel electrode by an etching process and etching a side surface of the first dam and a side surface of the second dam to form a tip of the third dam.

[0021] The method may further include removing the photoresist by a stripping process.

[0022] The method may further include forming a first pixel defining layer covering side surfaces of the insulating layer, side surfaces of the first pixel electrode, and edges of a top surface of the second layer of the first pixel electrode to define the first emission region.

[0023] The method may further include forming a first light emitting layer in the first emission region on the second layer of the first pixel electrode.

[0024] The method may further include forming a first common electrode on the first light emitting layer and forming an electrode pattern on the third dam. Forming the first common electrode and forming the electrode pattern may include depositing a metal material to disconnect and separate the first common electrode and the electrode pattern through a tip of the third dam.

[0025] In the display device and the method of manufacturing the display device according to the embodiment, since light emitted from the light emitting element passes through the light emitting element having a height similar to that of the dam without being blocked by the dam, it is possible to improve light emitting efficiency and easily implement an ultra-fine process with high resolution.

[0026] However, the effects of the present disclosure are not limited to the aforementioned effects, and various other effects are included in the specification. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The above and other aspects and features of the present disclosure will become more apparent by describing in detail embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0028] Figure 1 is a schematic perspective view showing a display device according to an embodiment;

[0029] Figure 2 is a schematic cross-sectional view showing a display device according to an embodiment;

[0030] Figure 3 is a schematic plan view showing a display portion of a display device according to an embodiment;

[0031] Figure 4 is a schematic cross-sectional view showing a portion of a display device according to an embodiment;

[0032] Figure 5 yes Figure 4 A schematic enlarged view of area A1;

[0033] Figures 6 to 12 It is shown Figure 4 A schematic cross-sectional view of a manufacturing process of a display device;

[0034] Fig.13 is a schematic cross-sectional view showing a portion of a display device according to another embodiment; and

[0035] Fig.14 yes Fig.13 Schematic enlarged view of area A2. DETAILED DESCRIPTION

[0036] In the following description, for the purpose of explanation, many specific details are set forth in order to provide a thorough understanding of various embodiments or implementations of the present disclosure. As used herein, "embodiment" and "implementation" are interchangeable words, which are non-limiting examples of devices or methods using one or more of the present disclosure disclosed herein. However, it is apparent that various embodiments can be practiced without these specific details or in the case of one or more equivalent arrangements. In other examples, structures and devices are shown in block diagram form to avoid unnecessary confusion of various embodiments. In addition, various embodiments may be different, but do not have to be exclusive or limit the present disclosure. For example, without departing from the present disclosure, the specific shape, configuration and characteristics of the embodiment can be used or implemented in other embodiments.

[0037] Unless otherwise specified, the embodiments shown will be understood to provide features of varying details that can be implemented in practice in some ways of the present disclosure. Therefore, unless otherwise specified, the features, components, modules, layers, films, panels, regions and / or aspects, etc. (hereinafter referred to as "elements" individually or collectively) of the various embodiments can be combined, separated, interchanged and / or rearranged in other ways without departing from the present disclosure.

[0038] The use of cross-hatching and / or shading in the drawings is generally provided to clarify the boundaries between adjacent elements. Thus, unless otherwise stated, neither the presence or absence of cross-hatching or shading conveys or indicates any preference or requirement for specific materials, material properties, sizes, proportions, commonalities between the illustrated elements, and / or any other characteristics, attributes, properties, etc. of the elements.

[0039] In addition, in the accompanying drawings, the size and relative size of the elements may be exaggerated for clarity and / or descriptive purposes. When the embodiments can be implemented differently, the specific process sequence can be performed differently from the described sequence. For example, two consecutively described processes can be performed substantially simultaneously or in an order opposite to the described sequence. Moreover, similar reference numerals represent similar elements.

[0040] When an element or layer is referred to as being "on" or "connected to" another element or layer, the element or layer may be directly on, directly connected to, or coupled to the other element or layer, or there may be intervening elements or layers. However, when an element or layer is referred to as being "directly on" or "directly connected to" another element or layer, there are no intervening elements or layers. For this purpose, the term "connected" may refer to a physical, electrical, and / or fluid connection with or without intervening elements.

[0041] When a component is described herein as being “connected” to another component or being “connected to” another component, the components may be connected to each other as separate elements, or the components may be integral with each other.

[0042] Throughout the specification, when an element is referred to as being “connected” to another element, the element may be “directly connected” to the other element, or “electrically connected” to the other element with one or more intervening elements interposed therebetween. Also, when an element is referred to as being “in contact with” or the like with another element, the element may be “electrically in contact with” or “physically in contact with” the other element, or “indirectly in contact with” or “directly in contact with” the other element.

[0043] In addition, the X-axis, Y-axis, and Z-axis are not limited to the three axes of the rectangular coordinate system, and therefore the X-axis, Y-axis, and Z-axis can be interpreted in a broader sense. For example, the X-axis, Y-axis, and Z-axis can be perpendicular to each other, or can represent different directions that are not perpendicular to each other.

[0044] For the purposes of this disclosure, "at least one of X, Y, and Z" and "at least one selected from the cluster consisting of X, Y, and Z" may be interpreted as any combination of only X, only Y, only Z, or two or more of X, Y, and Z, such as, for example, XYZ, XYY, YZ, ZZ, or the like. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. For example, "A and / or B" may be understood to mean "A, B, or A and B". The terms "and" and "or" may be used in a conjunction or disjunction sense and may be understood to be equivalent to "and / or".

[0045] Although the terms "first", "second" and similar words can be used in this article to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another element. Therefore, without departing from the teachings of the present disclosure, the first element discussed below can be referred to as the second element.

[0046] Spatially relative terms, such as "beneath," "below," "under," "lower," "above," "upper," "over," "higher," "side" (e.g., as in "sidewall"), and the like, may be used herein for descriptive purposes and thereby describe the relationship of one element to another element as shown in the accompanying drawings. Spatially relative terms are intended to encompass different orientations of the device in use, operation, and / or manufacture in addition to the orientations depicted in the accompanying drawings. For example, if the device in the accompanying drawings is turned over, an element described as being "below" or "beneath" other elements or features would subsequently be oriented "above" the other elements or features. Thus, the term "below" is capable of encompassing both above and below orientations. Furthermore, the device may be oriented in other ways (e.g., rotated 90 degrees or at other orientations), and thus, the spatially relative descriptors used herein should be interpreted accordingly.

[0047] The technical terms used herein are for the purpose of describing specific embodiments and are not intended to be limiting. Unless the context clearly indicates otherwise, the singular forms "a", "an" and "the" as used herein are also intended to include plural forms. In addition, when the terms "comprise", "comprising", "include", "including", "has" and / or "having" are used in this specification, the existence of the stated features, integers, steps, operations, elements, parts and / or their clusters is explained, but the existence or addition of one or more other features, integers, steps, operations, elements, parts and / or their clusters is not excluded. It should also be noted that, as used herein, the terms "substantially", "about" and other similar terms are used as approximate terms and are not used as terms of degree, and thus, are utilized to take into account the inherent deviations of measured values, calculated values ​​and / or provided values ​​that will be recognized by those of ordinary skill in the art.

[0048] Various embodiments are described herein with reference to cross-sectional illustrations and / or exploded illustrations that are schematic illustrations of embodiments and / or intermediate structures. Thus, variations in the shapes of the illustrations due to, for example, manufacturing techniques and / or tolerances are to be expected. Thus, the embodiments disclosed herein should not necessarily be construed as limited to the shapes of the particular illustrated regions, but rather are to include deviations in shape due to, for example, manufacturing. In this manner, the regions illustrated in the drawings may be schematic in nature, and the shapes of these regions may not reflect the actual shapes of the regions of the device, and thus, are not necessarily intended to be limiting.

[0049] The display surface may be parallel to the surface defined by the X-axis direction and the Y-axis direction. The normal direction of the display surface (i.e., the thickness direction of the display device 10) may indicate the Z-axis direction. In this specification, the expression "when viewed from the top or in a plan view" may indicate the situation when viewed in the Z-axis direction. In the following, the front surface (or top surface) and the rear surface (or bottom surface) of each of the multiple layers or multiple units may be distinguished by the Z-axis direction. However, the directions indicated by the X-axis direction to the Z-axis direction may be relative concepts and may be converted relative to each other, for example, converted to the opposite direction.

[0050] As is customary in the art, in terms of functional blocks, units, parts and / or modules, some embodiments are shown and described in the accompanying drawings. It will be appreciated by those skilled in the art that these blocks, units, parts and / or modules are physically implemented by electronic (or optical) circuits (such as logic circuits, discrete components, microprocessors, hard-wired circuits, memory elements, wiring connectors and the like that can be formed using semiconductor-based manufacturing techniques or other manufacturing techniques). In the case of blocks, units, parts and / or modules implemented by microprocessors or other similar hardware, they can be programmed and controlled using software (e.g., microcode) to perform the various functions discussed herein, and can be selectively driven by firmware and / or software. It is also contemplated that each block, unit, part and / or module can be implemented by dedicated hardware, or implemented as a combination of dedicated hardware that performs some functions and a processor that performs other functions (e.g., one or more programmed microprocessors and associated circuits). Moreover, without departing from the scope of the present disclosure, each block, unit, part and / or module of some embodiments can be physically separated into two or more interactive and discrete blocks, units, parts and / or modules. Furthermore, the blocks, units, sections and / or modules of some embodiments may be physically combined into more complex blocks, units, sections and / or modules without departing from the scope of the present disclosure.

[0051] Unless otherwise defined or implied herein, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art to which the present disclosure belongs. It will also be understood that, unless clearly defined as such herein, terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology and the present disclosure, and should not be interpreted in an ideal or overly formal sense.

[0052] Hereinafter, detailed embodiments of the present disclosure are described with reference to the accompanying drawings.

[0053] Figure 1 is a schematic perspective view showing a display device 10 according to an embodiment.

[0054] Reference Figure 1 , the display device 10 may be applied to portable electronic devices such as mobile phones, smart phones, tablet personal computers, mobile communication terminals, electronic notebooks, electronic books, portable multimedia players (PMPs), navigation systems, ultra mobile PCs (UMPCs), or the like. For example, the display device 10 may be applied as a display portion of a television, a laptop computer, a monitor, a billboard, an Internet of Things (IoT) device, or the like. In another embodiment, the display device 10 may be applied to a wearable device such as a smart watch, a watch phone, a glasses-type display, a head-mounted display (HMD), or the like.

[0055] The display device 10 may have a quadrilateral shape in a plan view. For example, the display device 10 may have a quadrilateral shape including a short side in the X-axis direction and a long side in the Y-axis direction in a plan view. The Y-axis direction may intersect with the X-axis direction. The corner where the short side in the X-axis direction intersects with the long side in the Y-axis direction may be rounded to have a curvature (e.g., a predetermined or selectable curvature) or may be a right angle. However, the shape of the display device 10 is not limited thereto, and the shape of the display device 10 in a plan view may be formed to be similar to another polygonal shape, a circular shape, an elliptical shape, or the like.

[0056] The display device 10 may include a display panel 100 , a display driver 200 , a circuit board 300 , and a touch driver 400 .

[0057] The display panel 100 may include a main area MA and a sub area SBA.

[0058] The main area MA may include pixels containing a display image (see, e.g. Figure 3 The display area DA may include a plurality of pixels SP and a non-display area NDA disposed adjacent to the display area DA. For example, the non-display area NDA may surround at least a portion of the display area DA. The display area DA may be illuminated from a plurality of emission areas (see, for example, Figure 4 The display panel 100 may emit light from the first emission area EA1 to the third emission area EA3) or multiple opening areas. For example, the display panel 100 may include a pixel circuit (not shown) including a switching element, a pixel defining layer (not shown) defining an emission area or an opening area, a self-luminous element (not shown), the like, or a combination thereof.

[0059] For example, the self-luminous element may include at least one of an organic light-emitting diode including an organic light-emitting layer, a quantum dot light-emitting diode including a quantum dot light-emitting layer, an inorganic light-emitting diode including an inorganic semiconductor, and a micro light-emitting diode (micro LED), but the present disclosure is not limited thereto.

[0060] The non-display area NDA may be an area arranged adjacent to (or surrounding) the display area DA. The non-display area NDA may be an edge area of ​​the main area MA of the display panel 100. The non-display area NDA may include a gate line (see, for example, Figure 3 The gate line GL) of the gate driver (see for example Figure 3 The gate driver 210 of the display driver 200 and the fan-out lines connecting the display driver 200 to the display area DA (see, for example, Figure 3 The fan-out line FOL).

[0061] The sub-area SBA may extend from one side of the main area MA in the Y-axis direction. The sub-area SBA may include a flexible material that can be bent, folded or curled. For example, when the sub-area SBA is bent, the sub-area SBA may overlap with the main area MA in the thickness direction (Z-axis direction). The Z-axis direction may intersect with the X-axis direction and the Y-axis direction. The sub-area SBA may include a display driver 200 and a pad portion (not shown) connected to the circuit board 300. In another embodiment, the sub-area SBA may be omitted, and the display driver 200 and the pad portion may be arranged in the non-display area NDA.

[0062] The display driver 200 may output signals and voltages for driving the display panel 100. The display driver 200 may supply voltages to the data lines (see, for example, Figure 3 The display driver 200 may supply a power voltage to the power line (not shown) and supply a gate control signal to the gate driver. The display driver 200 may be formed as an integrated circuit (IC) and mounted on the display panel 100 by a chip on glass (COG) method, a chip on plastic (COP) method, an ultrasonic bonding method, or the like. For example, the display driver 200 may be arranged in the sub-area SBA and overlap the main area MA in the thickness direction (Z-axis direction) by bending the sub-area SBA. In another embodiment, the display driver 200 may be mounted on the circuit board 300.

[0063] The circuit board 300 may be attached to the pad portion of the display panel 100 by using an anisotropic conductive film (ACF) or the like. A lead (not shown) of the circuit board 300 may be electrically connected to the pad portion of the display panel 100. The circuit board 300 may be a flexible printed circuit board, a printed circuit board, a flexible film such as a chip on film, or the like.

[0064] The touch driver 400 may be mounted on the circuit board 300. The touch driver 400 may be electrically connected to a touch sensing portion of the display panel 100 (see, for example, Figure 2 The touch driver 400 may supply a touch driving signal to a plurality of touch electrodes of the touch sensing unit (see, for example, Figure 4 The touch driver 400 may be configured to detect a change in capacitance between the touch electrodes TE and sense a change in capacitance between the touch electrodes. For example, the touch drive signal may be a pulse signal having a frequency (e.g., a predetermined or selectable frequency). The touch driver 400 may calculate whether an input is made and the input coordinates based on the change in capacitance between the touch electrodes. The touch driver 400 may be formed by an integrated circuit (IC).

[0065] Figure 2 is a schematic cross-sectional view showing a display device 10 according to an embodiment.

[0066] Reference Figure 2 The display panel 100 may include a display part DU, a touch sensing part TSU, and a color filter layer CFL. The display part DU may include a substrate SUB, a transistor layer TFTL, a light emitting element layer EML, and an encapsulation layer TFEL.

[0067] The substrate SUB may be a base substrate or a base member. The substrate SUB may be a flexible substrate that can be bent, folded, or curled. For example, the substrate SUB may include a polymer resin including polyimide (PI) or the like, but the present disclosure is not limited thereto. In another embodiment, the substrate SUB may include a glass material, a metal material, the like, or a combination thereof.

[0068] The transistor layer TFTL may be arranged on the substrate SUB. The transistor layer TFTL may include pixels (see, for example Figure 3 A plurality of transistors constituting a pixel circuit of a pixel SP) (see, for example, Figure 4 The transistor layer TFTL may further include a gate line (see, for example, Figure 3 The gate line GL), the data line (see for example Figure 3 data lines DL), power lines (see e.g. Figure 3 power line VL), gate control line (see e.g. Figure 3 The gate control line GCL of the display driver 200 is connected to the fan-out line of the data line (see, for example, Figure 3The fan-out line FOL) and the lead connecting the display driver 200 to the pad portion (see, for example Figure 3 ). Each of the transistors may include a semiconductor region (see, for example, Figure 4 semiconductor region ACT), source electrode (see e.g. Figure 4 source electrode SE), drain electrode (see for example Figure 4 The drain electrode DE) and the gate electrode (see for example Figure 4 For example, in a gate driver (see, for example Figure 3 In the case where the gate driver 210 is formed on one side of the non-display area NDA of the display panel 100, the gate driver may include a transistor.

[0069] The transistor layer TFTL may be arranged in the display area DA, the non-display area NDA, and the sub-area SBA. The transistor, gate line, data line, and power line of each of the pixels of the transistor layer TFTL may be arranged in the display area DA. The gate control line and fan-out line of the transistor layer TFTL may be arranged in the non-display area NDA. The lead line of the transistor layer TFTL may be arranged in the sub-area SBA.

[0070] The light emitting element layer EML may be disposed on the transistor layer TFTL. The light emitting element layer EML may include a pixel electrode (see, for example, Figure 4 The first pixel electrode AE1 to the third pixel electrode AE3), the light emitting layer (see for example Figure 4 The first light-emitting layer EL1 to the third light-emitting layer EL3) and the common electrode (see, for example Figure 4 A plurality of light emitting elements (first common electrodes CE1 to third common electrodes CE3) are sequentially stacked to emit light and a pixel defining layer (see, for example, Figure 4 The first pixel defining layer PDL1 to the third pixel defining layer PDL3). The plurality of light emitting elements of the light emitting element layer EML (see, for example, Figure 4 First to third light emitting elements ED1 to ED3) may be arranged in the display area DA.

[0071] For example, the light-emitting layer may be an organic light-emitting layer including an organic material. The light-emitting layer may include a hole transport layer (not shown), an organic light-emitting layer (not shown), and an electron transport layer (not shown). In the case where the pixel electrode receives a voltage (e.g., a predetermined or selectable voltage) from the transistor of the transistor layer TFTL and the common electrode receives a cathode voltage, holes may be transferred to the organic light-emitting layer through the hole transport layer and electrons may be transferred to the electron transport layer (specifically, electrons may be transferred to the organic light-emitting layer through the electron transport layer), and are combined with each other in the organic light-emitting layer to emit light. For example, the pixel electrode may be an anode electrode, and the common electrode may be a cathode electrode, but the present disclosure is not limited thereto.

[0072] In another embodiment, the light emitting element may include a quantum dot light emitting diode including a quantum dot light emitting layer, an inorganic light emitting diode including an inorganic semiconductor, a micro light emitting diode, the like, or a combination thereof.

[0073] The encapsulation layer TFEL may cover the top and side surfaces of the light emitting element layer EML (or be arranged on the top and side surfaces of the light emitting element layer EML) and protect the light emitting element layer EML. The encapsulation layer TFEL may include at least one inorganic layer and at least one organic layer for encapsulating the light emitting element layer EML.

[0074] The touch sensing unit TSU may be disposed on the encapsulation layer TFEL. The touch sensing unit TSU may include a plurality of touch electrodes for sensing a user's touch in a capacitive manner (see, for example, Figure 4 The touch sensing unit TSU may sense the touch of the user by using a mutual capacitance method, a self capacitance method, a similar method, or a combination thereof.

[0075] In another embodiment, the touch sensing unit TSU may be disposed on a separate substrate (not shown) disposed on the display unit DU. For example, the separate substrate supporting the touch sensing unit TSU may be a base member encapsulating the display unit DU.

[0076] The touch electrodes of the touch sensing unit TSU may be arranged in a touch sensor area (not shown) overlapping the display area DA in the thickness direction. The touch wires of the touch sensing unit TSU may be arranged in a touch peripheral area (not shown) overlapping the non-display area NDA in the thickness direction.

[0077] The color filter layer CFL may be disposed on the touch sensing part TSU. The color filter layer CFL may include layers respectively connected to the emission areas (see, for example, Figure 4 A plurality of color filters corresponding to the first emission area EA1 to the third emission area EA3 (see, for example, Figure 4 The color filter layer CFL may selectively transmit light of a wavelength (e.g., a specific wavelength) and block or absorb light of other wavelengths. The color filter layer CFL may absorb part of the light from outside the display device 10 and reduce reflected light due to the external light. Accordingly, the color filter layer CFL may prevent color distortion caused by reflection of the external light.

[0078] Since the color filter layer CFL is disposed (eg, directly disposed) on the touch sensing part TSU, the display device 10 may not require a separate substrate for the color filter layer CFL. Therefore, the thickness of the display device 10 may be relatively reduced.

[0079] The sub-area SBA of the display panel 100 may extend from one side of the main area MA. The sub-area SBA may include a flexible material that can be bent, folded, or curled. For example, when the sub-area SBA is bent, the sub-area SBA may overlap with the main area MA in the thickness direction (Z-axis direction) of the display device 10. The sub-area SBA may include a display driver 200 and a pad portion electrically connected to the circuit board 300.

[0080] Figure 3 1 is a schematic plan view showing a display section DU of the display device 10 according to the embodiment.

[0081] Reference Figure 3 , the display part DU may include a display area DA and a non-display area NDA.

[0082] The display area DA, which is an area for displaying an image, may be a central area of ​​the display panel 100. The display area DA may include a plurality of pixels SP, a plurality of gate lines GL, a plurality of data lines DL, and a plurality of power lines VL. Each of the pixels SP may be a minimum unit of outputting light.

[0083] The gate lines GL may supply gate signals received from the gate driver 210 to the pixels SP. The gate lines GL may extend in the X-axis direction and be spaced apart from each other in the Y-axis direction intersecting the X-axis direction.

[0084] The data lines DL may supply data voltages received from the display driver 200 to the pixels SP. The data lines DL may extend in the Y-axis direction and be spaced apart from each other in the X-axis direction.

[0085] The power lines VL may supply a power voltage received from the display driver 200 to the pixels SP. The power voltage may be at least one of a driving voltage, an initialization voltage, a reference voltage, and a low potential voltage. The power lines VL may extend in the Y-axis direction and be spaced apart from each other in the X-axis direction.

[0086] The non-display area NDA may surround the display area DA (or be arranged adjacent to the display area DA). The non-display area NDA may include a gate driver 210, a fan-out line FOL, and a gate control line GCL. The gate driver 210 may generate a plurality of gate signals based on the gate control signal, and sequentially supply the gate signals to the gate lines GL according to a set order.

[0087] The fan-out line FOL may extend from the display driver 200 to the display area DA. The fan-out line FOL may supply a data voltage received from the display driver 200 to the data line DL.

[0088] The gate control line GCL may extend from the display driver 200 to the gate driver 210. The gate control line GCL may supply a gate control signal received from the display driver 200 to the gate driver 210.

[0089] The sub-area SBA may include the display driver 200 , a display pad area DPA, and first and second touch pad areas TPA1 and TPA2 .

[0090] The display driver 200 may output signals and voltages for driving the display panel 100 to the fan-out lines FOL. The display driver 200 may supply data voltages to the data lines DL through the fan-out lines FOL. The data voltages may be supplied to the pixels SP and determine the brightness of the pixels SP. The display driver 200 may supply gate control signals to the gate driver 210 through the gate control lines GCL.

[0091] The display pad area DPA, the first touch pad area TPA1, and the second touch pad area TPA2 may be arranged at the edge of the sub-area SBA. The display pad area DPA, the first touch pad area TPA1, and the second touch pad area TPA2 may be electrically connected to the circuit board 300 by using a low-resistance, high-reliability material such as anisotropic conductive film, self-assembled anisotropic conductive paste (SAP), the like, or a combination thereof.

[0092] The display pad area DPA may include a plurality of display pad portions DP. The display pad portions DP may be arranged in the display pad area DPA. The display pad portions DP may be electrically connected to a graphics system through a circuit board 300. The display pad portions DP may be connected to the circuit board 300, receive digital video data, and supply the digital video data to the display driver 200.

[0093] The first touch pad area TPA1 may be arranged in an area on one side of the display pad area DPA and include a plurality of first touch pad parts TP1. The first touch pad part TP1 may be arranged in the first touch pad area TPA1. The first touch pad part TP1 may be electrically connected to a touch driver 400 arranged on the circuit board 300. The first touch pad part TP1 may supply a touch drive signal to the drive electrode through a plurality of drive lines.

[0094] The second touch pad area TPA2 may be arranged in another area on the other side of the display pad area DPA, and include a plurality of second touch pad parts TP2. The second touch pad part TP2 may be arranged in the second touch pad area TPA2. The second touch pad part TP2 may be electrically connected to a touch driver 400 arranged on the circuit board 300. The touch driver 400 may receive a touch sensing signal through a plurality of sensing lines connected to the second touch pad part TP2, and sense a change in mutual capacitance between a driving electrode (not shown) and a sensing electrode (not shown).

[0095] Figure 4 is a schematic cross-sectional view showing part of a display device 10 according to an embodiment, and Figure 5 yes Figure 4 Schematic enlarged view of area A1 of FIG.

[0096] Reference Figure 2 , Figure 4 and Figure 5 The display panel 100 may include a display part DU, a touch sensing part TSU, and a color filter layer CFL. The display part DU may include a substrate SUB, a transistor layer TFTL, a light emitting element layer EML, and an encapsulation layer TFEL.

[0097] The substrate SUB may be a base substrate or a base member. The substrate SUB may be a flexible substrate that can be bent, folded, or curled. For example, the substrate SUB may include a polymer resin including polyimide (PI) or the like, but the present disclosure is not limited thereto. In another embodiment, the substrate SUB may include a glass material, a metal material, the like, or a combination thereof.

[0098] The transistor layer TFTL may include a first buffer layer BF1, a light blocking layer BML, a second buffer layer BF2, a transistor TFT, a gate insulating layer GI, a first interlayer insulating layer ILD1, a capacitor electrode CPE, a second interlayer insulating layer ILD2, a first connection electrode CNE1, a first passivation layer PAS1, a second connection electrode CNE2, and a second passivation layer PAS2.

[0099] The first buffer layer BF1 may be disposed on the substrate SUB. The first buffer layer BF1 may include an inorganic layer that prevents penetration of air or moisture. For example, the first buffer layer BF1 may include a plurality of inorganic layers alternately stacked on each other.

[0100] The light blocking layer BML may be disposed on the first buffer layer BF1. For example, the light blocking layer BML may be formed as a single layer or multiple layers including at least one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and alloys thereof. In another embodiment, the light blocking layer BML may be an organic layer including a black pigment or the like.

[0101] The second buffer layer BF2 may be disposed on the first buffer layer BF1 and the light blocking layer BML. The second buffer layer BF2 may include an inorganic layer that prevents penetration of air or moisture. For example, the second buffer layer BF2 may include a plurality of inorganic layers alternately stacked on each other.

[0102] The transistor TFT may be arranged on the second buffer layer BF2 and constitute a pixel circuit of each of the plurality of pixels SP (that is, the pixel circuit of each of the plurality of pixels SP may include the transistor TFT). For example, the transistor TFT may be a switching transistor or a driving transistor of the pixel circuit. The transistor TFT may include a semiconductor region ACT, a source electrode SE, a drain electrode DE, and a gate electrode GE.

[0103] The semiconductor region ACT, the source electrode SE, and the drain electrode DE may be arranged on the second buffer layer BF2. The semiconductor region ACT, the source electrode SE, and the drain electrode DE may overlap the light blocking layer BML in the thickness direction (Z-axis direction). The semiconductor region ACT may overlap the gate electrode GE in the thickness direction. The source electrode SE and the drain electrode DE may be provided by making the material of the semiconductor region ACT conductive.

[0104] The gate electrode GE may be disposed on the gate insulating layer GI. The gate electrode GE may overlap the semiconductor region ACT with the gate insulating layer GI interposed therebetween in the thickness direction.

[0105] The gate insulating layer GI may be disposed on the semiconductor region ACT, the source electrode SE, and the drain electrode DE. For example, the gate insulating layer GI may cover the semiconductor region ACT, the source electrode SE, the drain electrode DE, and the second buffer layer BF2 and insulate the semiconductor region ACT from the gate electrode GE.

[0106] The first interlayer insulating layer ILD1 may be disposed on the gate electrode GE and the gate insulating layer GI. The first interlayer insulating layer ILD1 may insulate the gate electrode GE from the capacitor electrode CPE.

[0107] The capacitor electrode CPE may be disposed on the first interlayer insulating layer ILD1. The capacitor electrode CPE may overlap the gate electrode GE in a thickness direction. The capacitor electrode CPE and the gate electrode GE may form a capacitance.

[0108] The second interlayer insulating layer ILD2 may be disposed on the capacitor electrode CPE and the first interlayer insulating layer ILD1. The second interlayer insulating layer ILD2 may insulate the capacitor electrode CPE from the first connection electrode CNE1.

[0109] The first connection electrode CNE1 may be disposed on the second interlayer insulating layer ILD2. The first connection electrode CNE1 may electrically connect the drain electrode DE of the transistor TFT to the second connection electrode CNE2. The first connection electrode CNE1 may be inserted into a contact hole provided in the second interlayer insulating layer ILD2, the first interlayer insulating layer ILD1, and the gate insulating layer GI, and contact the drain electrode DE of the transistor TFT.

[0110] The first passivation layer PAS1 may cover the first connection electrode CNE1 and the second interlayer insulating layer ILD2. The first passivation layer PAS1 may protect the transistor TFT. The first passivation layer PAS1 may insulate the first connection electrode CNE1 from the second connection electrode CNE2.

[0111] The second connection electrode CNE2 may be disposed on the first passivation layer PAS1. The second connection electrode CNE2 may electrically connect the first connection electrode CNE1 to the first pixel electrode AE1 of the first light emitting element ED1. The second connection electrode CNE2 may be inserted into a contact hole provided in the first passivation layer PAS1 and contact the first connection electrode CNE1.

[0112] The second passivation layer PAS2 may be disposed on the second connection electrode CNE2 and the first passivation layer PAS1. The second passivation layer PAS2 may insulate the second connection electrode CNE2 from the first pixel electrode AE1.

[0113] The light emitting element layer EML may be disposed on the transistor layer TFTL and may include a first insulating layer IL1, first, second and third light emitting elements ED1, ED2 and ED3, first, second and third pixel defining layers PDL1, PDL2 and PDL3, a dam BNK and an electrode pattern CEP.

[0114] The display device 10 may include a plurality of pixels SP arranged in a plurality of rows and columns in a display area DA. Each of the pixels SP may include a corresponding one of a first emission area EA1, a second emission area EA2, and a third emission area EA3 defined by a first pixel defining layer PDL1, a second pixel defining layer PDL2, and a third pixel defining layer PDL3, respectively, and emit light having a peak wavelength (e.g., a predetermined or selectable peak wavelength) through a corresponding one of the first emission area EA1, the second emission area EA2, and the third emission area EA3. Each of the first emission area EA1, the second emission area EA2, and the third emission area EA3 may be an area where light generated from a light emitting element of the display device 10 is emitted to the outside of the display device 10.

[0115] The first emission area EA1, the second emission area EA2, and the third emission area EA3 may emit light having a peak wavelength (e.g., a predetermined or selectable peak wavelength) to the outside of the display device 10. The first emission area EA1 may emit light of a first color, the second emission area EA2 may emit light of a second color, and the third emission area EA3 may emit light of a third color. For example, the first color light may be red light having a peak wavelength in the range of about 610 nm to about 650 nm, the second color light may be green light having a peak wavelength in the range of about 510 nm to about 550 nm, and the third color light may be blue light having a peak wavelength in the range of about 440 nm to about 480 nm, but the present disclosure is not limited thereto.

[0116] For example, in a plan view, the size of the third emission area EA3 may be larger than the size of the first emission area EA1, and the size of the first emission area EA1 may be larger than the size of the second emission area EA2. However, the present disclosure is not limited thereto. In another embodiment, the size of the first emission area EA1, the size of the second emission area EA2, and the size of the third emission area EA3 may all be substantially equal.

[0117] The first insulating layer IL1 may be arranged on the transistor layer TFTL. The first insulating layer IL1 may support the first pixel electrode AE1, the second pixel electrode AE2, and the third pixel electrode AE3, and the dam BNK. The height of the first insulating layer IL1 may determine the height of the first light emitting element ED1, the second light emitting element ED2, and the third light emitting element ED3, and the dam BNK. A portion of the first insulating layer IL1 supporting the first pixel electrode AE1, a portion of the first insulating layer IL1 supporting the second pixel electrode AE2, a portion of the first insulating layer IL1 supporting the third pixel electrode AE3, and a portion of the first insulating layer IL1 supporting the dam BNK may be spaced apart from each other in the X-axis direction and / or the Y-axis direction. The first insulating layer IL1 may include an inorganic insulating material. The first insulating layer IL1 may include at least one of silicon nitride, silicon oxynitride, silicon oxide, titanium oxide, aluminum oxide, and amorphous silicon, but the present disclosure is not limited thereto.

[0118] The first light emitting element ED1 may be disposed in the first emission area EA1 on the first insulating layer IL1. The first light emitting element ED1 may include a first pixel electrode AE1, a first light emitting layer EL1, and a first common electrode CE1.

[0119] The first pixel electrode AE1 may be disposed on the first insulating layer IL1. The first pixel electrode AE1 may be inserted into a contact hole provided in the first insulating layer IL1 and the second passivation layer PAS2 and contact the second connection electrode CNE2. The first pixel electrode AE1 may be electrically connected to the drain electrode DE of the transistor TFT through the first connection electrode CNE1 and the second connection electrode CNE2.

[0120] The first pixel electrode AE1 may include a first layer AE1a and a second layer AE1b. The first layer AE1a of the first pixel electrode AE1 may be disposed on the first insulating layer IL1, and the second layer AE1b of the first pixel electrode AE1 may be disposed on the first layer AE1a. The first layer AE1a of the first pixel electrode AE1 and the first dam BNK1 may be formed in the same process and include the same metal material. The second layer AE1b of the first pixel electrode AE1 and the second dam BNK2 may be formed in the same process and include the same metal material. In the thickness direction, the thickness of the first layer AE1a of the first pixel electrode AE1 may be greater than the thickness of the second layer AE1b.

[0121] The first layer AE1a and the second layer AE1b of the first pixel electrode AE1 may include different metal materials. The first layer AE1a of the first pixel electrode AE1 may include a material having high conductivity and high reflectivity. The second layer AE1b of the first pixel electrode AE1 may be an anode electrode for injecting holes. For example, the first layer AE1a of the first pixel electrode AE1 may include aluminum (Al) or the like, and the second layer AE1b of the first pixel electrode AE1 may include titanium nitride (TiN) or the like, but the present disclosure is not limited thereto.

[0122] The first pixel defining layer PDL1 may define the first emission area EA1. The first pixel defining layer PDL1 may cover the side surface of the first insulating layer IL1 arranged in the first emission area EA1, the side surface of the first pixel electrode AE1, and the edge of the top surface of the second layer AE1b of the first pixel electrode AE1 (or be arranged on the side surface of the first insulating layer IL1 arranged in the first emission area EA1, the side surface of the first pixel electrode AE1, and the edge of the top surface of the second layer AE1b of the first pixel electrode AE1). The first pixel defining layer PDL1 may expose a portion of the top surface of the second layer AE1b of the first pixel electrode AE1. The first pixel defining layer PDL1 may insulate the first pixel electrode AE1 from the first common electrode CE1. The first pixel defining layer PDL1 may include an inorganic insulating material. The first pixel defining layer PDL1 may include at least one of silicon nitride, silicon oxynitride, silicon oxide, titanium oxide, aluminum oxide, and amorphous silicon, but the present disclosure is not limited thereto.

[0123] The first light emitting layer EL1 may be an organic light emitting layer including an organic material. The first light emitting layer EL1 may be disposed (eg, directly disposed) on the second layer AE1b of the first pixel electrode AE1 in the first emission area EA1. The first light emitting layer EL1 may fill a space surrounded by the first pixel defining layer PDL1.

[0124] The first common electrode CE1 may be disposed on the first light emitting layer EL1. The first common electrode CE1 may cover the first pixel defining layer PDL1 and the first insulating layer IL1 (or be disposed on the first pixel defining layer PDL1 and the first insulating layer IL1) and extend to the side surface of the first dam BNK1. The first common electrode CE1 may be electrically connected to the second common electrode CE2 and the third common electrode CE3 through the first dam BNK1 by contacting the side surface of the first dam BNK1. For example, the first common electrode CE1 may receive a common voltage or a low potential voltage. The first common electrode CE1 may include a transparent conductive material and transmit light generated in the first light emitting layer EL1.

[0125] The first pixel electrode AE1 may receive a voltage corresponding to the data voltage from the transistor TFT, and the first common electrode CE1 may receive a common voltage or a cathode voltage. When a potential difference is formed between the first pixel electrode AE1 and the first common electrode CE1, holes may move to the first light emitting layer EL1 through the hole transport layer, and electrons may move to the first light emitting layer EL1 through the electron transport layer, and the first light emitting layer EL1 may emit light.

[0126] The second light emitting element ED2 may be disposed in the second emission area EA2 on the first insulating layer IL1. The second light emitting element ED2 may include a second pixel electrode AE2, a second light emitting layer EL2, and a second common electrode CE2.

[0127] The second pixel electrode AE2 may be disposed on the first insulating layer IL1. The second pixel electrode AE2 may be inserted into a contact hole provided in the first insulating layer IL1 and the second passivation layer PAS2 and contact the second connection electrode CNE2. The second pixel electrode AE2 may be electrically connected to the drain electrode DE of the transistor TFT through the first connection electrode CNE1 and the second connection electrode CNE2.

[0128] The second pixel electrode AE2 may include a first layer AE2a and a second layer AE2b. The first layer AE2a of the second pixel electrode AE2 may be arranged on the first insulating layer IL1, and the second layer AE2b of the second pixel electrode AE2 may be arranged on the first layer AE2a. The first layer AE2a of the second pixel electrode AE2 and the first dam BNK1 may be formed in the same process and include the same metal material. The second layer AE2b of the second pixel electrode AE2 and the second dam BNK2 may be formed in the same process and include the same metal material. In the thickness direction, the thickness of the first layer AE2a of the second pixel electrode AE2 may be greater than the thickness of the second layer AE2b.

[0129] The first layer AE2a and the second layer AE2b of the second pixel electrode AE2 may include metal materials different from each other. The first layer AE2a of the second pixel electrode AE2 may include a material having high conductivity and high reflectivity. The second layer AE2b of the second pixel electrode AE2 may be an anode electrode for injecting holes. For example, the first layer AE2a of the second pixel electrode AE2 may include aluminum (Al) or the like, and the second layer AE2b of the second pixel electrode AE2 may include titanium nitride (TiN) or the like, but the present disclosure is not limited thereto.

[0130] The second pixel defining layer PDL2 may define the second emission area EA2. The second pixel defining layer PDL2 may cover the side surface of the first insulating layer IL1 arranged in the second emission area EA2, the side surface of the second pixel electrode AE2, and the edge of the top surface of the second layer AE2b of the second pixel electrode AE2 (or be arranged on the side surface of the first insulating layer IL1 arranged in the second emission area EA2, the side surface of the second pixel electrode AE2, and the edge of the top surface of the second layer AE2b of the second pixel electrode AE2). The second pixel defining layer PDL2 may expose a portion of the top surface of the second layer AE2b of the second pixel electrode AE2. The second pixel defining layer PDL2 may insulate the second pixel electrode AE2 from the second common electrode CE2. The second pixel defining layer PDL2 may include an inorganic insulating material. The second pixel defining layer PDL2 may include at least one of silicon nitride, silicon oxynitride, silicon oxide, titanium oxide, aluminum oxide, and amorphous silicon, but the present disclosure is not limited thereto.

[0131] The second light emitting layer EL2 may be an organic light emitting layer including an organic material. The second light emitting layer EL2 may be arranged (eg, directly arranged) on the second layer AE2b of the second pixel electrode AE2 in the second emission area EA2. The second light emitting layer EL2 may fill a space surrounded by the second pixel defining layer PDL2.

[0132] The second common electrode CE2 may be disposed on the second light emitting layer EL2. The second common electrode CE2 may cover the second pixel defining layer PDL2 and the first insulating layer IL1 (or be disposed on the second pixel defining layer PDL2 and the first insulating layer IL1) and extend to the side surface of the first dam BNK1. The second common electrode CE2 may be electrically connected to the first common electrode CE1 and the third common electrode CE3 through the first dam BNK1 by contacting the side surface of the first dam BNK1. For example, the second common electrode CE2 may receive a common voltage or a low potential voltage. The second common electrode CE2 may include a transparent conductive material and transmit light generated in the second light emitting layer EL2.

[0133] The second pixel electrode AE2 may receive a voltage corresponding to the data voltage from the transistor TFT, and the second common electrode CE2 may receive a common voltage or a cathode voltage. When a potential difference is formed between the second pixel electrode AE2 and the second common electrode CE2, holes may move to the second light emitting layer EL2 through the hole transport layer, and electrons may move to the second light emitting layer EL2 through the electron transport layer, and the second light emitting layer EL2 may emit light.

[0134] The third light emitting element ED3 may be disposed in the third emission area EA3 on the first insulating layer IL1. The third light emitting element ED3 may include a third pixel electrode AE3, a third light emitting layer EL3, and a third common electrode CE3.

[0135] The third pixel electrode AE3 may be disposed on the first insulating layer IL1. The third pixel electrode AE3 may be inserted into a contact hole provided in the first insulating layer IL1 and the second passivation layer PAS2 and contact the second connection electrode CNE2. The third pixel electrode AE3 may be electrically connected to the drain electrode DE of the transistor TFT through the first connection electrode CNE1 and the second connection electrode CNE2.

[0136] The third pixel electrode AE3 may include a first layer AE3a and a second layer AE3b. The first layer AE3a of the third pixel electrode AE3 may be arranged on the first insulating layer IL1, and the second layer AE3b of the third pixel electrode AE3 may be arranged on the first layer AE3a. The first layer AE3a and the first dam BNK1 of the third pixel electrode AE3 may be formed in the same process and include the same metal material. The second layer AE3b and the second dam BNK2 of the third pixel electrode AE3 may be formed in the same process and include the same metal material. In the thickness direction, the thickness of the first layer AE3a of the third pixel electrode AE3 may be greater than the thickness of the second layer AE3b.

[0137] The first layer AE3a and the second layer AE3b of the third pixel electrode AE3 may include metal materials different from each other. The first layer AE3a of the third pixel electrode AE3 may include a material having high conductivity and high reflectivity. The second layer AE3b of the third pixel electrode AE3 may be an anode electrode for injecting holes. For example, the first layer AE3a of the third pixel electrode AE3 may include aluminum (Al) or the like, and the second layer AE3b of the third pixel electrode AE3 may include titanium nitride (TiN) or the like, but the present disclosure is not limited thereto.

[0138] The third pixel defining layer PDL3 may define the third emission area EA3. The third pixel defining layer PDL3 may cover the side surface of the first insulating layer IL1 arranged in the third emission area EA3, the side surface of the third pixel electrode AE3, and the edge of the top surface of the second layer AE3b of the third pixel electrode AE3 (or be arranged on the side surface of the first insulating layer IL1 arranged in the third emission area EA3, the side surface of the third pixel electrode AE3, and the edge of the top surface of the second layer AE3b of the third pixel electrode AE3). The third pixel defining layer PDL3 may expose a portion of the top surface of the second layer AE3b of the third pixel electrode AE3. The third pixel defining layer PDL3 may insulate the third pixel electrode AE3 from the third common electrode CE3. The third pixel defining layer PDL3 may include an inorganic insulating material. The third pixel defining layer PDL3 may include at least one of silicon nitride, silicon oxynitride, silicon oxide, titanium oxide, aluminum oxide, and amorphous silicon, but the present disclosure is not limited thereto.

[0139] The third light-emitting layer EL3 may be an organic light-emitting layer including an organic material. The third light-emitting layer EL3 may be arranged (e.g., directly arranged) on the second layer AE3b of the third pixel electrode AE3 in the third emission area EA3. The third light-emitting layer EL3 may fill the space surrounded by the third pixel defining layer PDL3. The first light-emitting layer EL1, the second light-emitting layer EL2, and the third light-emitting layer EL3 may be uniformly deposited in the first emission area EA1, the second emission area EA2, and the third emission area EA3 respectively provided by the first pixel defining layer PDL1, the second pixel defining layer PDL2, and the third pixel defining layer PDL3. The first light-emitting layer EL1, the second light-emitting layer EL2, and the third light-emitting layer EL3 may be uniformly deposited in the first emission area EA1, the second emission area EA2, and the third emission area EA3 respectively in the areas surrounded by the first pixel defining layer PDL1, the second pixel defining layer PDL2, and the third pixel defining layer PDL3.

[0140] The third common electrode CE3 may be arranged on the third light emitting layer EL3. The third common electrode CE3 may cover the third pixel defining layer PDL3 and the first insulating layer IL1 (or be arranged on the third pixel defining layer PDL3 and the first insulating layer IL1) and extend to the side surface of the first dam BNK1. The third common electrode CE3 may be electrically connected to the first common electrode CE1 and the second common electrode CE2 through the first dam BNK1 by contacting the side surface of the first dam BNK1. For example, the third common electrode CE3 may receive a common voltage or a low potential voltage. The third common electrode CE3 may include a transparent conductive material and transmit light generated in the third light emitting layer EL3.

[0141] The third pixel electrode AE3 may receive a voltage corresponding to the data voltage from the transistor TFT, and the third common electrode CE3 may receive a common voltage or a cathode voltage. When a potential difference is formed between the third pixel electrode AE3 and the third common electrode CE3, holes may move to the third light emitting layer EL3 through the hole transport layer, and electrons may move to the third light emitting layer EL3 through the electron transport layer, and the third light emitting layer EL3 may emit light.

[0142] The dam BNK may be disposed on the first insulating layer IL1 and surround the first, second, and third light emitting elements ED1, ED2, and ED3 in a plan view. The dam BNK may include an opening surrounding the first, second, and third light emitting elements ED1, ED2, and ED3, and overlap the light blocking member BM of the color filter layer CFL in a thickness direction. The dam BNK may include a first dam BNK1, a second dam BNK2, and a third dam BNK3.

[0143] The first dam BNK1 may be arranged on the first insulating layer IL1, the second dam BNK2 may be arranged on the first dam BNK1, and the third dam BNK3 may be arranged on the second dam BNK2. The side surface of the first dam BNK1 and the side surface of the second dam BNK2 may be recessed inward from the side surface of the third dam BNK3. The side surface of the third dam BNK3 may protrude from the side surface of the second dam BNK2 toward the first light emitting element ED1, and the third dam BNK3 may include a protruding tip. Accordingly, the lower portion of the tip of the third dam BNK3 may have an undercut structure. In the thickness direction, the thickness of the first dam BNK1 may be greater than the thickness of the second dam BNK2 or the third dam BNK3.

[0144] For example, in the dry etching process, the first dam BNK1 and the second dam BNK2 may be etched more than the third dam BNK3. Accordingly, the lateral shapes of the first dam BNK1, the second dam BNK2, and the third dam BNK3 may be determined by the difference in etching rates between the first dam BNK1, the second dam BNK2, and the third dam BNK3. The first dam BNK1, the first layer AE1a of the first pixel electrode AE1, the first layer AE2a of the second pixel electrode AE2, and the first layer AE3a of the third pixel electrode AE3 may be arranged (e.g., directly arranged) on the same layer and include the same material. The second dam BNK2, the second layer AE1b of the first pixel electrode AE1, the second layer AE2b of the second pixel electrode AE2, and the second layer AE3b of the third pixel electrode AE3 may be arranged (e.g., directly arranged) on the same layer and include the same material.

[0145] At least one of the first dam BNK1, the second dam BNK2, and the third dam BNK3 may include different metal materials. The first dam BNK1 may include a material having high conductivity and high reflectivity. The first dam BNK1 may electrically connect the first common electrode CE1, the second common electrode CE2, and the third common electrode CE3 that are spaced apart from each other in the X-axis direction and / or the Y-axis direction. For example, the first dam BNK1 may include aluminum (Al) or the like, the second dam BNK2 may include titanium nitride (TiN) or the like, and the third dam BNK3 may include titanium (Ti) or the like, but the present disclosure is not limited thereto.

[0146] The dam BNK may be surrounded by a mask process, respectively, around the first light emitting element ED1, the second light emitting element ED2, and the third light emitting element ED3 and the first pixel defining layer PDL1, the second pixel defining layer PDL2, and the third pixel defining layer PDL3 in the first emission area EA1, the second emission area EA2, and the third emission area EA3, and the first common electrode CE1, the second common electrode CE2, and the third common electrode CE3 may be formed on the first light emitting element ED1, the second light emitting element ED2, and the third light emitting element ED3 in the first emission area EA1, the second emission area EA2, and the third emission area EA3, respectively. During the execution of the mask process, a structure for mounting the mask may be required, and an excessively wide area of ​​the non-display area NDA may be required to control the dispersion of the mask process. Accordingly, in the case of minimizing the mask process, the structure for mounting the mask may be omitted, and the area of ​​the non-display area NDA for dispersion control may be minimized.

[0147] The electrode pattern CEP and the first common electrode CE1, the second common electrode CE2, and the third common electrode CE3 may be formed in the same process and include the same metal material. The metal material may be deposited on a surface (e.g., the entire surface) of the display device 10, and the first common electrode CE1, the second common electrode CE2, and the third common electrode CE3 and the electrode pattern CEP may be disconnected and separated from each other by a tip formed on the inner wall of the dam BNK. The electrode pattern CEP may be arranged on the third dam BNK3 in an area other than the first emission area EA1, the second emission area EA2, and the third emission area EA3. The electrode pattern CEP may cover the top surface and the side surface of the third dam BNK3 (or be arranged on the top surface and the side surface of the third dam BNK3).

[0148] The first light emitting element ED1, the second light emitting element ED2, and the third light emitting element ED3 may be formed by a mask process and a deposition process. Since at least one of the first dam BNK1, the second dam BNK2, and the third dam BNK3 includes a different metal material, the inner wall of the dam BNK may have a tip structure, and the display device 10 may include different layers formed separately in the first emission area EA1, the second emission area EA2, and the third emission area EA3 by a deposition process. For example, the first common electrode CE1 and the electrode pattern CEP may be deposited using the same organic material in a deposition process (or by a deposition process), and are disconnected and separated from each other by a tip formed on the inner wall of the dam BNK. The first common electrode CE1 may be arranged in the first emission area EA1, and the electrode pattern CEP may be arranged on the dam BNK in an area arranged between the first emission area EA1, the second emission area EA2, and the third emission area EA3.

[0149] In the display device 10, by forming the first dam BNK1 and the second dam BNK2 and the first pixel electrode AE1, the second pixel electrode AE2, and the third pixel electrode AE3 in the same process, the number of masks used in the mask process can be reduced. The display device 10 may include a first pixel defining layer PDL1, a second pixel defining layer PDL2, and a third pixel defining layer PDL3 that define the first emission area EA1, the second emission area EA2, and the third emission area EA3, respectively, and the first light emitting layer EL1, the second light emitting layer EL2, and the third light emitting layer EL3 may be uniformly deposited. Accordingly, the display device 10 may reduce manufacturing costs by omitting unnecessary processes by separating the first light emitting element ED1, the second light emitting element ED2, and the third light emitting element ED3 from each other through a deposition process, and the area of ​​the non-display area NDA may be minimized.

[0150] exist Figure 5, the first layer AE1a and the second layer AE1b of the first pixel electrode AE1 and the first dam BNK1 and the second dam BNK2 may be arranged (e.g., directly arranged) on the same layer. The height of the first light emitting layer EL1 and the first common electrode CE1 may be similar to the height of the third dam BNK3 and the electrode pattern CEP relative to the substrate SUB. For example, in a case where the height of the first light emitting element ED1 is significantly lower than the height of the dam BNK, the light emitted from the first light emitting element ED1 may be blocked by the dam BNK and the light emitting efficiency of the first light emitting element ED1 may be deteriorated, making it difficult to implement a high-resolution ultra-fine process. In a case where the height of the first light emitting element ED1 is similar to the height of the dam BNK, the light emitted from the first light emitting element ED1 may not be blocked by the dam BNK. Accordingly, the display device 10 may include the first light emitting element ED1, the second light emitting element ED2, and the third light emitting element ED3 having a height similar to the height of the dam BNK, thereby improving the light emitting efficiency and easily implementing a high-resolution ultra-fine process.

[0151] The encapsulation layer TFEL may be disposed on the first, second, and third common electrodes CE1, CE2, and CE3 and the electrode pattern CEP. The encapsulation layer TFEL may include a first encapsulation layer TFE1, a second encapsulation layer TFE2, and a third encapsulation layer TFE3.

[0152] The first encapsulation layer TFE1 may be arranged on the first common electrode CE1, the second common electrode CE2, and the third common electrode CE3 and the electrode pattern CEP. The first encapsulation layer TFE1 may cover the side surfaces of the first dam BNK1 and the second dam BNK2 that are recessed inward from the side surface of the third dam BNK3 (or be arranged on the side surfaces of the first dam BNK1 and the second dam BNK2 that are recessed inward from the side surface of the third dam BNK3). The first encapsulation layer TFE1 may include an inorganic material and prevent oxygen or moisture from penetrating into the first light emitting element ED1, the second light emitting element ED2, and the third light emitting element ED3. The first encapsulation layer TFE1 may be an inorganic encapsulation layer. For example, the first encapsulation layer TFE1 may include at least one of silicon nitride, silicon oxynitride, silicon oxide, titanium oxide, aluminum oxide, and amorphous silicon, but the present disclosure is not limited thereto.

[0153] The second encapsulation layer TFE2 may be arranged on the first encapsulation layer TFE1 and flatten the upper end of the light emitting element layer EML. The second encapsulation layer TFE2 may include an organic material and protect the light emitting element layer EML from foreign matter such as dust or the like. For example, the second encapsulation layer TFE2 may include an organic film including an acrylic resin, an epoxy resin, a phenol resin, a polyamide resin, a polyimide resin, the like, or a combination thereof. The second encapsulation layer TFE2 may be formed by curing a monomer, applying a polymer, or the like.

[0154] The third encapsulation layer TFE3 may be disposed on the second encapsulation layer TFE2. The third encapsulation layer TFE3 may include an inorganic material and prevent oxygen or moisture from penetrating into the light emitting element layer EML. For example, the third encapsulation layer TFE3 may include at least one of silicon nitride, silicon oxynitride, silicon oxide, titanium oxide, aluminum oxide, and amorphous silicon, but the present disclosure is not limited thereto.

[0155] The touch sensing part TSU may be disposed on the encapsulation layer TFEL. The touch sensing part TSU may include a third buffer layer BF3, a bridge electrode BRG, a second insulating layer IL2, a touch electrode TE, and a third insulating layer IL3.

[0156] The third buffer layer BF3 may be arranged on the encapsulation layer TFEL. The third buffer layer BF3 may have an insulating function, an optical function, and the like. The third buffer layer BF3 may include at least one inorganic layer. In another embodiment, the third buffer layer BF3 may be omitted.

[0157] The bridge electrode BRG may be disposed on the third buffer layer BF3. The bridge electrode BRG and the touch electrode TE may be disposed at different layers. The bridge electrode BRG may electrically connect adjacent touch electrodes TE to each other.

[0158] The second insulating layer IL2 may be disposed on the bridge electrode BRG and the third buffer layer BF3. The second insulating layer IL2 may have an insulating function, an optical function, and the like. For example, the second insulating layer IL2 may include at least one of silicon nitride, silicon oxynitride, silicon oxide, titanium oxide, aluminum oxide, and amorphous silicon, but the present disclosure is not limited thereto.

[0159] The touch electrode TE may be arranged on the second insulating layer IL2. The touch electrode TE may include a driving electrode and a sensing electrode, and senses a change in mutual capacitance between the driving electrode and the sensing electrode. The touch electrode TE may not be arranged in the first emission area EA1, the second emission area EA2, and the third emission area EA3. The touch electrode TE may be formed as a single layer including molybdenum (Mo), titanium (Ti), copper (Cu), aluminum (Al), indium tin oxide (ITO), the like, or a combination thereof, or may be formed as a stacked structure of aluminum and titanium (Ti / Al / Ti), a stacked structure of aluminum and ITO (ITO / Al / ITO), an APC alloy, a stacked structure of an APC alloy and ITO (ITO / APC / ITO), the like, or a combination thereof.

[0160] The third insulating layer IL3 may be arranged on the touch electrode TE and the second insulating layer IL2. The third insulating layer IL3 may have an insulating function, an optical function, and the like. For example, the third insulating layer IL3 may include at least one of silicon nitride, silicon oxynitride, silicon oxide, titanium oxide, aluminum oxide, and amorphous silicon, but the present disclosure is not limited thereto.

[0161] The color filter layer CFL may be disposed on the touch sensing part TSU. The color filter layer CFL may include a light blocking member BM, a plurality of color filters CF, and a planarization layer OC.

[0162] The light blocking member BM may be arranged on the third insulating layer IL3 and surround the first color filter CF1, the second color filter CF2, and the third color filter CF3 in the first optical region OPT1, the second optical region OPT2, and the third optical region OPT3, respectively. The light blocking member BM may overlap the touch electrode TE in the thickness direction. The light blocking member BM may include a light absorbing material and prevent light reflection. For example, the light blocking member BM may include an inorganic black pigment, an organic black pigment, an organic blue pigment, the like, or a combination thereof. The inorganic black pigment may be a metal oxide such as carbon black, titanium black, or the like, the organic black pigment may include at least one of lactam black, perylene black, and aniline black, and the organic blue pigment may be CI pigment blue or the like, but the present disclosure is not limited thereto. The light blocking member BM may prevent color mixing caused by penetration of visible light between the first emission region EA1, the second emission region EA2, and the third emission region EA3, and improve the color gamut of the display device 10.

[0163] The color filter CF may include first, second, and third color filters CF1, CF2, and CF3. Each of the first, second, and third color filters CF1, CF2, and CF3 may be disposed on the third insulating layer IL3 and correspond to a corresponding one of the first, second, and third emission regions EA1, EA2, and EA3.

[0164] The first color filter CF1 may be arranged in the first emission area EA1 on the third insulating layer IL3. In a plan view, the first color filter CF1 may be surrounded by the light blocking member BM. The edge of the first color filter CF1 may cover a portion of the upper surface of the light blocking member BM (or be arranged on a portion of the upper surface of the light blocking member BM), but the present disclosure is not limited thereto. The first color filter CF1 may selectively transmit light of a first color (e.g., red light) and block or absorb light of a second color (e.g., green light) and light of a third color (e.g., blue light). For example, the first color filter CF1 may be a red color filter and include a red colorant or the like.

[0165] The second color filter CF2 may be arranged in the second emission area EA2 on the third insulating layer IL3. In a plan view, the second color filter CF2 may be surrounded by the light blocking member BM. The edge of the second color filter CF2 may cover a portion of the upper surface of the light blocking member BM (or be arranged on a portion of the upper surface of the light blocking member BM), but the present disclosure is not limited thereto. The second color filter CF2 may selectively transmit light of a second color (e.g., green light) and block or absorb light of a first color (e.g., red light) and light of a third color (e.g., blue light). For example, the second color filter CF2 may be a green color filter and include a green colorant or the like.

[0166] The third color filter CF3 may be arranged in the third emission area EA3 on the third insulating layer IL3. In a plan view, the third color filter CF3 may be surrounded by the light blocking member BM. The edge of the third color filter CF3 may cover a portion of the upper surface of the light blocking member BM (or be arranged on a portion of the upper surface of the light blocking member BM), but the present disclosure is not limited thereto. The third color filter CF3 may selectively transmit light of a third color (e.g., blue light) and block or absorb light of a first color (e.g., red light) and light of a second color (e.g., green light). For example, the third color filter CF3 may be a blue filter and include a blue colorant or the like.

[0167] The first color filter CF1, the second color filter CF2, and the third color filter CF3 can absorb part of the light introduced from the outside of the display device 10 to reduce the reflected light due to the external light. Accordingly, the first color filter CF1, the second color filter CF2, and the third color filter CF3 can prevent color distortion due to the reflection of the external light.

[0168] A planarization layer OC may be disposed on the light blocking member BM and the first, second, and third color filters CF1, CF2, and CF3. The planarization layer OC may planarize an upper end portion of the color filter layer CFL. For example, the planarization layer OC may include an organic insulating material.

[0169] Figures 6 to 12 It is shown Figure 4 Schematic cross-sectional view of a manufacturing process of the display device 10.

[0170] exist Figure 6 In the embodiment, the first insulating layer IL1 may be disposed on the transistor layer TFTL. The first insulating layer IL1 may expose a portion of the transistor layer TFTL. The first insulating layer IL1 may include an inorganic insulating material. The first insulating layer IL1 may include at least one of silicon nitride, silicon oxynitride, silicon oxide, titanium oxide, aluminum oxide, and amorphous silicon, but the present disclosure is not limited thereto.

[0171] The first layer AE1a and the first dam BNK1 of the first pixel electrode AE1 may be formed in the same process and include the same metal material. The second layer AE1b and the second dam BNK2 of the first pixel electrode AE1 may be formed in the same process and include the same metal material. The temporary pixel electrode TPE and the third dam BNK3 may be formed in the same process and include the same metal material. In the thickness direction, the thickness of the first layer AE1a of the first pixel electrode AE1 may be greater than the thickness of the second layer AE1b. The first layer AE1a of the first pixel electrode AE1 may include a material having high conductivity and high reflectivity. The second layer AE1b of the first pixel electrode AE1 may be an anode electrode for injecting holes. For example, the first layer AE1a and the first dam BNK1 of the first pixel electrode AE1 may include aluminum (Al) or the like, the second layer AE1b and the second dam BNK2 of the first pixel electrode AE1 may include titanium nitride (TiN) or the like, and the temporary pixel electrode TPE and the third dam BNK3 may include titanium (Ti) or the like, but the present disclosure is not limited thereto.

[0172] The first pixel electrode AE1, the second pixel electrode AE2, and the third pixel electrode AE3 may be spaced apart from each other in the X-axis direction and / or the Y-axis direction on a portion of the first insulating layer IL1. The first dam BNK1, the second dam BNK2, and the third dam BNK3 may be arranged on another portion of the first insulating layer IL1 and surround the first pixel electrode AE1, the second pixel electrode AE2, and the third pixel electrode AE3 in a plan view. The first insulating layer IL1 may support the first pixel electrode AE1, the second pixel electrode AE2, and the third pixel electrode AE3, and the dam BNK. The height of the first insulating layer IL1 may determine the height of the first light-emitting element ED1, the second light-emitting element ED2, and the third light-emitting element ED3, and the dam BNK. The first insulating layer IL1 supporting the first pixel electrode AE1, the first insulating layer IL1 supporting the second pixel electrode AE2, the first insulating layer IL1 supporting the third pixel electrode AE3, and the first insulating layer IL1 supporting the dam BNK may be spaced apart from each other in the X-axis direction and / or the Y-axis direction.

[0173] The photoresist PR may be disposed on the third dam BNK3 , and the half-tone photoresist HPR may be disposed on the temporary pixel electrode TPE. In the thickness direction, the thickness of the photoresist PR may be greater than the thickness of the half-tone photoresist HPR.

[0174] exist Figure 7In the embodiment of the present invention, the first dam BNK1 and the second dam BNK2 and the temporary pixel electrode TPE may be etched by performing at least one of a dry etching process, a wet etching process, and the like. For example, the first dam BNK1 and the second dam BNK2 and the temporary pixel electrode TPE may be etched by an etching process such as an isotropic dry etching process or the like, but the present disclosure is not limited thereto. The upper surface of the third dam BNK3 may be protected by the photoresist PR, but the side surfaces of the first dam BNK1 and the second dam BNK2 may not be protected by the photoresist PR. Accordingly, after the etching process is completed, the third dam BNK3 may remain, and the side surfaces of the first dam BNK1 and the second dam BNK2 may be recessed inwardly from the side surface of the third dam BNK3. The side surface of the third dam BNK3 may include a tip protruding from the side surface of the second dam BNK2. Accordingly, the lower portion of the tip of the third dam BNK3 may have an undercut structure.

[0175] The halftone photoresist HPR may be removed in an etching process such as an isotropic dry etching process or a similar process. The upper surface of the temporary pixel electrode TPE may not be protected by the halftone photoresist HPR. Accordingly, after the etching process is completed, the temporary pixel electrode TPE may be removed, and the second layer AE1b, the second layer AE2b, and the second layer AE3b of the first pixel electrode AE1, the second pixel electrode AE2, and the third pixel electrode AE3 may be exposed.

[0176] exist Figure 8 In the embodiment, after the etching of the first dam BNK1 and the second dam BNK2 is completed, the photoresist PR may be removed through a stripping process.

[0177] exist Fig. 9 , the first pixel defining layer PDL1 may define the first emission area EA1. The first pixel defining layer PDL1 may cover the side surface of the first insulating layer IL1 arranged in the first emission area EA1, the side surface of the first pixel electrode AE1, and the edge of the top surface of the second layer AE1b of the first pixel electrode AE1 (or be arranged on the side surface of the first insulating layer IL1 arranged in the first emission area EA1, the side surface of the first pixel electrode AE1, and the edge of the top surface of the second layer AE1b of the first pixel electrode AE1). The first pixel defining layer PDL1 may expose a portion of the top surface of the second layer AE1b of the first pixel electrode AE1. The first pixel defining layer PDL1 may insulate the first pixel electrode AE1 from the first common electrode CE1.

[0178] The second pixel defining layer PDL2 may define the second emission area EA2. The second pixel defining layer PDL2 may cover the side surface of the first insulating layer IL1 arranged in the second emission area EA2, the side surface of the second pixel electrode AE2, and the edge of the top surface of the second layer AE2b of the second pixel electrode AE2 (or be arranged on the side surface of the first insulating layer IL1 arranged in the second emission area EA2, the side surface of the second pixel electrode AE2, and the edge of the top surface of the second layer AE2b of the second pixel electrode AE2). The second pixel defining layer PDL2 may expose a portion of the top surface of the second layer AE2b of the second pixel electrode AE2.

[0179] The third pixel defining layer PDL3 may define the third emission area EA3. The third pixel defining layer PDL3 may cover the side surface of the first insulating layer IL1 arranged in the third emission area EA3, the side surface of the third pixel electrode AE3, and the edge of the top surface of the second layer AE3b of the third pixel electrode AE3 (or be arranged on the side surface of the first insulating layer IL1 arranged in the third emission area EA3, the side surface of the third pixel electrode AE3, and the edge of the top surface of the second layer AE3b of the third pixel electrode AE3). The third pixel defining layer PDL3 may expose a portion of the top surface of the second layer AE3b of the third pixel electrode AE3.

[0180] The first pixel defining layer PDL1, the second pixel defining layer PDL2, and the third pixel defining layer PDL3 may include an inorganic insulating material. The first pixel defining layer PDL1, the second pixel defining layer PDL2, and the third pixel defining layer PDL3 may include at least one of silicon nitride, silicon oxynitride, silicon oxide, titanium oxide, aluminum oxide, and amorphous silicon, but the present disclosure is not limited thereto.

[0181] exist Fig.10 In the embodiment, the first light emitting layer EL1 may be disposed (eg, directly disposed) on the second layer AE1b of the first pixel electrode AE1 in the first emission area EA1. The first light emitting layer EL1 may fill a space surrounded by the first pixel defining layer PDL1.

[0182] The second light emitting layer EL2 may be disposed (eg, directly disposed) on the second layer AE2b of the second pixel electrode AE2 in the second emission area EA2. The second light emitting layer EL2 may fill a space surrounded by the second pixel defining layer PDL2.

[0183] The third light emitting layer EL3 may be disposed (eg, directly disposed) on the second layer AE3b of the third pixel electrode AE3 in the third emission area EA3. The third light emitting layer EL3 may fill a space surrounded by the third pixel defining layer PDL3.

[0184] The first light-emitting layer EL1, the second light-emitting layer EL2, and the third light-emitting layer EL3 may be organic light-emitting layers including organic materials. The first light-emitting layer EL1, the second light-emitting layer EL2, and the third light-emitting layer EL3 may be uniformly deposited in the first emission area EA1, the second emission area EA2, and the third emission area EA3 provided by the first pixel defining layer PDL1, the second pixel defining layer PDL2, and the third pixel defining layer PDL3. The first light-emitting layer EL1, the second light-emitting layer EL2, and the third light-emitting layer EL3 may be uniformly deposited in the first emission area EA1, the second emission area EA2, and the third emission area EA3, respectively, on the areas surrounded by the first pixel defining layer PDL1, the second pixel defining layer PDL2, and the third pixel defining layer PDL3, respectively.

[0185] exist Fig.11 The first common electrode CE1 may cover (or be disposed on) the first pixel defining layer PDL1 and the first insulating layer IL1 and extend to a side surface of the first dam BNK1.

[0186] The second common electrode CE2 may be disposed on the second light emitting layer EL2 . The second common electrode CE2 may cover (or be disposed on) the second pixel defining layer PDL2 and the first insulating layer IL1 and extend to a side surface of the first dam BNK1 .

[0187] The third common electrode CE3 may be disposed on the third light emitting layer EL3. The third common electrode CE3 may cover (or be disposed on) the third pixel defining layer PDL3 and the first insulating layer IL1 and extend to a side surface of the first dam BNK1.

[0188] The first common electrode CE1, the second common electrode CE2, and the third common electrode CE3 may contact the side surface of the first dam BNK1 and be electrically connected to each other. For example, the first common electrode CE1, the second common electrode CE2, and the third common electrode CE3 may receive a common voltage or a low potential voltage. The first common electrode CE1, the second common electrode CE2, and the third common electrode CE3 may include a transparent conductive material and transmit light generated in the first light emitting layer EL1, the second light emitting layer EL2, and the third light emitting layer EL3.

[0189] The electrode pattern CEP and the first common electrode CE1, the second common electrode CE2, and the third common electrode CE3 may be formed in the same process and include the same metal material. The metal material may be deposited on a surface (e.g., the entire surface) of the display device 10, and the first common electrode CE1, the second common electrode CE2, and the third common electrode CE3 and the electrode pattern CEP may be disconnected and separated from each other by a tip formed on the inner wall of the dam BNK. The electrode pattern CEP may be arranged on the third dam BNK3 in an area other than the first emission area EA1, the second emission area EA2, and the third emission area EA3. The electrode pattern CEP may cover the top surface and the side surface of the third dam BNK3 (or be arranged on the top surface and the side surface of the third dam BNK3).

[0190] The first light emitting element ED1, the second light emitting element ED2, and the third light emitting element ED3 may be formed by a mask process and a deposition process. Since at least one of the first dam BNK1, the second dam BNK2, and the third dam BNK3 includes a different metal material, the inner wall of the dam BNK may have a tip structure, and the display device 10 may include different layers formed separately in the first emission area EA1, the second emission area EA2, and the third emission area EA3 by a deposition process. For example, the first common electrode CE1 and the electrode pattern CEP may be deposited using the same organic material in a deposition process (or by a deposition process), and are disconnected and separated from each other by a tip formed on the inner wall of the dam BNK. The first common electrode CE1 may be arranged in the first emission area EA1, and the electrode pattern CEP may be arranged on the dam BNK in an area arranged between the first emission area EA1, the second emission area EA2, and the third emission area EA3.

[0191] In the display device 10, the number of masks used in a mask process can be reduced by forming the first dam BNK1 and the second dam BNK2 and the first pixel electrode AE1, the second pixel electrode AE2, and the third pixel electrode AE3 in the same process. Accordingly, the display device 10 can reduce manufacturing costs by omitting unnecessary processes by separating the first light emitting element ED1, the second light emitting element ED2, and the third light emitting element ED3 from each other through a deposition process, and the area of ​​the non-display area NDA can be minimized.

[0192] exist Fig.12In the embodiment of the present invention, the first encapsulation layer TFE1 may be arranged on the first common electrode CE1, the second common electrode CE2, and the third common electrode CE3 and the electrode pattern CEP. The first encapsulation layer TFE1 may cover the side surfaces of the first dam BNK1 and the second dam BNK2 that are recessed inward from the side surface of the third dam BNK3 (or be arranged on the side surfaces of the first dam BNK1 and the second dam BNK2 that are recessed inward from the side surface of the third dam BNK3). The first encapsulation layer TFE1 may include an inorganic material and prevent oxygen or moisture from penetrating into the first light emitting element ED1, the second light emitting element ED2, and the third light emitting element ED3. The first encapsulation layer TFE1 may be an inorganic encapsulation layer. For example, the first encapsulation layer TFE1 may include at least one of silicon nitride, silicon oxynitride, silicon oxide, titanium oxide, aluminum oxide, and amorphous silicon, but the present disclosure is not limited thereto.

[0193] Fig.13 is a schematic cross-sectional view showing a portion of a display device 10 according to another embodiment, and Fig.14 yes Fig.13 Schematic enlarged view of area A2. Fig.13 and Fig.14 The display device 10 and Figure 4 and Figure 5 The display device 10 may be different from each other in configurations of the first pixel electrode AE1, the second pixel electrode AE2, and the third pixel electrode AE3 by omitting the configuration of the first insulating layer IL1. A description of the same configuration as that described above will be briefly given or omitted.

[0194] Reference Figure 2 , Fig.13 and Fig.14 The display panel 100 may include a display part DU, a touch sensing part TSU, and a color filter layer CFL. The display part DU may include a substrate SUB, a transistor layer TFTL, a light emitting element layer EML, and an encapsulation layer TFEL.

[0195] The light emitting element layer EML may be disposed on the transistor layer TFTL and may include first, second, and third light emitting elements ED1, ED2, and ED3, first, second, and third pixel defining layers PDL1, PDL2, and PDL3, a dam BNK, and an electrode pattern CEP.

[0196] The first light emitting element ED1 may be disposed in the first emission area EA1 on the second passivation layer PAS2. The first light emitting element ED1 may include a first pixel electrode AE1, a first light emitting layer EL1, and a first common electrode CE1.

[0197] The first pixel electrode AE1 may be disposed on the second passivation layer PAS2. The first pixel electrode AE1 may be inserted into a contact hole provided in the second passivation layer PAS2 and contact the second connection electrode CNE2. The first pixel electrode AE1 may be electrically connected to the drain electrode DE of the transistor TFT through the first and second connection electrodes CNE1 and CNE2.

[0198] The first pixel electrode AE1 may include a first layer AE1a and a second layer AE1b. The first layer AE1a of the first pixel electrode AE1 may be disposed on the second passivation layer PAS2, and the second layer AE1b of the first pixel electrode AE1 may be disposed on the first layer AE1a. The first layer AE1a of the first pixel electrode AE1 and the first dam BNK1 may be formed in the same process and include the same metal material. The second layer AE1b of the first pixel electrode AE1 and the second dam BNK2 may be formed in the same process and include the same metal material. In the thickness direction, the thickness of the first layer AE1a of the first pixel electrode AE1 may be greater than the thickness of the second layer AE1b.

[0199] The first layer AE1a and the second layer AE1b of the first pixel electrode AE1 may include metal materials different from each other. The first layer AE1a of the first pixel electrode AE1 may include a material having high conductivity and high reflectivity. The second layer AE1b of the first pixel electrode AE1 may be an anode electrode for injecting holes. For example, the first layer AE1a of the first pixel electrode AE1 may include aluminum (Al) or the like, and the second layer AE1b of the first pixel electrode AE1 may include titanium nitride (TiN) or the like, but the present disclosure is not limited thereto.

[0200] The first pixel defining layer PDL1 may define the first emission area EA1. The first pixel defining layer PDL1 may cover the side surface of the first pixel electrode AE1 and the edge of the top surface of the second layer AE1b of the first pixel electrode AE1 (or be arranged on the side surface of the first pixel electrode AE1 and the edge of the top surface of the second layer AE1b of the first pixel electrode AE1). The first pixel defining layer PDL1 may expose a portion of the top surface of the second layer AE1b of the first pixel electrode AE1. The first pixel defining layer PDL1 may insulate the first pixel electrode AE1 from the first common electrode CE1. The first pixel defining layer PDL1 may include an inorganic insulating material. The first pixel defining layer PDL1 may include at least one of silicon nitride, silicon oxynitride, silicon oxide, titanium oxide, aluminum oxide, and amorphous silicon, but the present disclosure is not limited thereto.

[0201] The first light emitting layer EL1 may be an organic light emitting layer including an organic material. The first light emitting layer EL1 may be disposed (eg, directly disposed) on the second layer AE1b of the first pixel electrode AE1 in the first emission area EA1. The first light emitting layer EL1 may fill a space surrounded by the first pixel defining layer PDL1.

[0202] The first common electrode CE1 may be arranged on the first light emitting layer EL1. The first common electrode CE1 may cover the first pixel defining layer PDL1 and the second passivation layer PAS2 (or be arranged on the first pixel defining layer PDL1 and the second passivation layer PAS2) and extend to the side surface of the first dam BNK1. The first common electrode CE1 may be electrically connected to the second common electrode CE2 and the third common electrode CE3 through the first dam BNK1 by contacting the side surface of the first dam BNK1. For example, the first common electrode CE1 may receive a common voltage or a low potential voltage. The first common electrode CE1 may include a transparent conductive material and transmit light generated in the first light emitting layer EL1.

[0203] The first pixel electrode AE1 may receive a voltage corresponding to the data voltage from the transistor TFT, and the first common electrode CE1 may receive a common voltage or a cathode voltage. When a potential difference is formed between the first pixel electrode AE1 and the first common electrode CE1, holes may move to the first light emitting layer EL1 through the hole transport layer, and electrons may move to the first light emitting layer EL1 through the electron transport layer, and the first light emitting layer EL1 may emit light.

[0204] Since the second light emitting element ED2 , the third light emitting element ED3 , and the first light emitting element ED1 may be formed in the same manner, description of the second light emitting element ED2 and the third light emitting element ED3 will be omitted.

[0205] The dam BNK may be disposed on the second passivation layer PAS2 and surround the first light emitting element ED1, the second light emitting element ED2, and the third light emitting element ED3 in a plan view. The dam BNK may include an opening surrounding the first light emitting element ED1, the second light emitting element ED2, and the third light emitting element ED3, and overlap the light blocking member BM of the color filter layer CFL in a thickness direction. The dam BNK may include a first dam BNK1, a second dam BNK2, and a third dam BNK3.

[0206] The first dam BNK1 may be arranged on the second passivation layer PAS2, the second dam BNK2 may be arranged on the first dam BNK1, and the third dam BNK3 may be arranged on the second dam BNK2. The side surface of the first dam BNK1 and the side surface of the second dam BNK2 may be recessed inward from the side surface of the third dam BNK3. The side surface of the third dam BNK3 may protrude from the side surface of the second dam BNK2 toward the first light emitting element ED1, and the third dam BNK3 may include a protruding tip. Accordingly, the lower portion of the tip of the third dam BNK3 may have an undercut structure. In the thickness direction, the thickness of the first dam BNK1 may be greater than the thickness of the second dam BNK2 or the third dam BNK3.

[0207] For example, in the dry etching process, the first dam BNK1 and the second dam BNK2 may be etched more than the third dam BNK3. Accordingly, the lateral shapes of the first dam BNK1, the second dam BNK2, and the third dam BNK3 may be determined by the difference in etching rates between the first dam BNK1, the second dam BNK2, and the third dam BNK3. The first dam BNK1, the first layer AE1a of the first pixel electrode AE1, the first layer AE2a of the second pixel electrode AE2, and the first layer AE3a of the third pixel electrode AE3 may be formed in the same process and include the same material. The second dam BNK2, the second layer AE1b of the first pixel electrode AE1, the second layer AE2b of the second pixel electrode AE2, and the second layer AE3b of the third pixel electrode AE3 may be formed in the same process and include the same material.

[0208] At least one of the first dam BNK1, the second dam BNK2, and the third dam BNK3 may include metal materials different from each other. The first dam BNK1 may include a material having high conductivity and high reflectivity. The first dam BNK1 may electrically connect the first common electrode CE1, the second common electrode CE2, and the third common electrode CE3 spaced apart from each other in the X-axis direction and / or the Y-axis direction. For example, the first dam BNK1 may include aluminum (Al) or the like, the second dam BNK2 may include titanium nitride (TiN) or the like, and the third dam BNK3 may include titanium (Ti) or the like, but the present disclosure is not limited thereto.

[0209] The dam BNK may surround the first light emitting element ED1, the second light emitting element ED2, and the third light emitting element ED3 and the first pixel defining layer PDL1, the second pixel defining layer PDL2, and the third pixel defining layer PDL3 in the first emission area EA1, the second emission area EA2, and the third emission area EA3, respectively, through a mask process, and the first common electrode CE1, the second common electrode CE2, and the third common electrode CE3 may be formed on the first light emitting element ED1, the second light emitting element ED2, and the third light emitting element ED3 in the first emission area EA1, the second emission area EA2, and the third emission area EA3, respectively. In the case of performing a mask process, a structure for mounting a mask may be required, and an excessively wide area of ​​the non-display area NDA may be required to control the dispersion of the mask process. Accordingly, in the case of minimizing the mask process, the structure for mounting a mask may be omitted, and the area of ​​the non-display area NDA for dispersion control may be minimized.

[0210] In the display device 10, by forming the first dam BNK1 and the second dam BNK2 and the first pixel electrode AE1, the second pixel electrode AE2, and the third pixel electrode AE3 in the same process, the number of masks used in the mask process can be reduced. The display device 10 may include a first pixel defining layer PDL1, a second pixel defining layer PDL2, and a third pixel defining layer PDL3 that define the first emission area EA1, the second emission area EA2, and the third emission area EA3, so that the first light emitting layer EL1, the second light emitting layer EL2, and the third light emitting layer EL3 can be uniformly deposited. Accordingly, the display device 10 can reduce the manufacturing cost by omitting unnecessary processes by separating the first light emitting element ED1, the second light emitting element ED2, and the third light emitting element ED3 from each other through a deposition process, and the area of ​​the non-display area NDA can be minimized.

[0211] exist Fig.14, the first layer AE1a and the second layer AE1b of the first pixel electrode AE1 and the first dam BNK1 and the second dam BNK2 may be arranged (e.g., directly arranged) on the same layer. The height of the first light emitting layer EL1 and the first common electrode CE1 may be similar to the height of the third dam BNK3 and the electrode pattern CEP relative to the substrate SUB. For example, in a case where the height of the first light emitting element ED1 is significantly smaller than the height of the dam BNK, the light emitted from the first light emitting element ED1 may be blocked by the dam BNK, and the light emitting efficiency of the first light emitting element ED1 may be deteriorated, making it difficult to implement a high-resolution ultra-fine process. In a case where the height of the first light emitting element ED1 is similar to the height of the dam BNK, the light emitted from the first light emitting element ED1 may not be blocked by the dam BNK. Accordingly, the display device 10 may include the first light emitting element ED1, the second light emitting element ED2, and the third light emitting element ED3 having a height similar to the height of the dam BNK, thereby improving the light emitting efficiency and easily implementing a high-resolution ultra-fine process.

[0212] The above description is an example of the technical features of the present disclosure, and those skilled in the art to which the present disclosure belongs will be able to make various modifications and changes.Therefore, the embodiments of the present disclosure described above may be implemented individually or in combination with each other.

[0213] Therefore, the embodiments disclosed in the present disclosure are not intended to limit the technical spirit of the present disclosure, but to describe the technical spirit of the present disclosure, and the scope of the technical spirit of the present disclosure is not limited by these embodiments. The protection scope of the present disclosure should be interpreted by the attached claims, and it should be understood that all technical spirits within the equivalent scope are included in the scope of the present disclosure.

Claims

1. A display device, characterized in that: include: a transistor layer disposed on the substrate and comprising at least one transistor; an insulating layer, the insulating layer being arranged on the transistor layer; a first pixel electrode, wherein the first pixel electrode is arranged on the insulating layer; a first pixel defining layer, the first pixel defining layer covering a side surface of the first pixel electrode and a side surface of the insulating layer and defining a first emission region; a first light emitting layer, the first light emitting layer being arranged in the first emission region on the first pixel electrode; a first common electrode, wherein the first common electrode is arranged on the first light emitting layer; as well as a dam, the dam being arranged on the insulating layer and surrounding the first pixel electrode, The first pixel electrode and the dam are arranged on the same layer and include the same material.

2. The display device according to claim 1, wherein: The dam comprises: a first dam, the first dam being arranged on the insulating layer; a second dam disposed on the first dam; and A third dam is arranged on the second dam.

3. The display device according to claim 2, wherein: A side surface of the first dam and a side surface of the second dam are recessed inward from a side surface of the third dam.

4. The display device according to claim 2, wherein: The third dam includes a tip protruding from a side surface of the second dam.

5. The display device according to claim 2, wherein: The first common electrode covers the first pixel defining layer and the insulating layer and extends to a side surface of the first dam.

6. The display device according to claim 2, wherein: The first pixel electrode comprises: a first layer disposed on the insulating layer; and A second layer is disposed on the first layer.

7. The display device according to claim 6, wherein: The first layer of the first pixel electrode and the first dam are arranged on the same layer and include the same material, and The second layer of the first pixel electrode and the second dam are disposed on the same layer and include the same material.

8. A display device, characterized in that: include: a transistor layer disposed on the substrate and comprising at least one transistor; a first pixel electrode, the first pixel electrode being arranged on the transistor layer; a first pixel defining layer, the first pixel defining layer covering a side surface of the first pixel electrode and defining a first emission area; a first light emitting layer, the first light emitting layer being arranged in the first emission region on the first pixel electrode; a first common electrode, wherein the first common electrode is arranged on the first light emitting layer; as well as a dam, the dam being arranged on the transistor layer and surrounding the first pixel electrode, The first pixel electrode and the dam are arranged on the same layer and include the same material.

9. The display device according to claim 8, wherein: The dam comprises: a first dam, the first dam being arranged on the transistor layer; a second dam disposed on the first dam; and A third dam is arranged on the second dam.

10. The display device according to claim 9, characterized in that The first pixel electrode comprises: a first layer, the first layer and the first dam being arranged on the same layer and including the same material; and The second layer and the second dam are arranged on the same layer and include the same material.

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