Display device

Abstract

A display device includes a display panel including a light emitting element and a pixel circuit unit connected to the light emitting element. The pixel circuit unit includes: a first transistor connected between a driving voltage line and the light emitting element, and operating according to a potential of a first node; a second transistor connected between the data line and a second node; a first capacitor electrode connected to the first node; a second capacitor electrode connected to the second node and facing the first capacitor electrode to form a first capacitor with the first capacitor electrode; a third capacitor electrode connected to the second node; a fourth capacitor electrode facing the third capacitor electrode to form a second capacitor with the third capacitor electrode, and the fourth capacitor electrode is connected to the driving voltage line; a bridge electrode connecting the second capacitor electrode and the third capacitor electrode; and a shield electrode disposed over the bridge electrode, and the shield electrode overlaps the bridge electrode in a plan view.

Description

Technical Field

[0001] Embodiments of the present disclosure described herein relate to a display device, and more particularly, to a display device with improved picture quality. Background Art

[0002] Among display devices, an emissive display device displays an image using a light emitting diode that generates light through recombination of electrons and holes. The emissive display device has a high response speed and is driven with low power consumption.

[0003] An emissive display device includes pixels connected to a data line and a scan line. Typically, each of the pixels includes a light emitting diode and a pixel circuit unit for controlling the amount of current flowing to the light emitting diode. In response to a data signal, the pixel circuit unit controls the amount of current flowing from a first drive voltage line to a second drive voltage line via the light emitting diode. At this time, light having a predetermined brightness is generated according to the amount of current flowing through the light emitting diode. Utility Model Content

[0004] Embodiments of the present disclosure provide a display device for improving picture quality when operating in a variable frequency mode.

[0005] According to an embodiment, a display device includes: a display panel including a light-emitting element and a pixel circuit unit connected to the light-emitting element. The pixel circuit unit includes: a first transistor connected between a driving voltage line and the light-emitting element, and the first transistor is configured to operate according to the potential of a first node; a second transistor connected between a data line and a second node; a first capacitor electrode electrically connected to the first node; a second capacitor electrode electrically connected to the second node, and the second capacitor electrode is configured to face the first capacitor electrode to form a first capacitor with the first capacitor electrode; a third capacitor electrode electrically connected to the second node; a fourth capacitor electrode electrically connected to the driving voltage line, and the fourth capacitor electrode faces the third capacitor electrode to form a second capacitor with the third capacitor electrode; a bridging electrode configured to electrically connect the second capacitor electrode and the third capacitor electrode; and a shielding electrode disposed above the bridging electrode, and the shielding electrode is configured to overlap with the bridging electrode in a plan view.

[0006] According to an embodiment, a display device includes: a display panel including a light emitting element and a pixel circuit unit connected to the light emitting element. The pixel circuit unit includes: a first transistor connected between a driving voltage line and the light emitting element, and the first transistor is configured to operate according to the potential of a first node; a second transistor connected between a data line and a second node; a first capacitor electrode connected to the first node; a second capacitor electrode and a third capacitor electrode connected to the second node, and the second capacitor electrode and the third capacitor electrode are configured to face the first capacitor electrode to form a first capacitor with the first capacitor electrode, wherein the second capacitor electrode and the third capacitor electrode are provided integrally with each other; a fourth capacitor electrode is configured to face the third capacitor electrode to form a second capacitor with the third capacitor electrode, and the fourth capacitor electrode is connected to the driving voltage line; a bridging electrode configured to electrically connect the second capacitor electrode and the second transistor; and a shielding electrode provided on the bridging electrode, and the shielding electrode is configured to partially overlap with the second capacitor electrode and the second transistor in a plan view. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The above and other aspects and features of the present disclosure will become more apparent by describing in detail embodiments of the present disclosure with reference to the attached drawings.

[0008] Figure 1 is a block diagram of a display device according to an embodiment of the present disclosure.

[0009] Figure 2A is a circuit diagram of a pixel according to an embodiment of the present disclosure.

[0010] Figure 2B is a timing diagram for explaining the operation of a pixel according to an embodiment of the present disclosure.

[0011] Figure 3A is a timing diagram for explaining a display device operating at a first driving frequency in a variable frequency mode according to an embodiment of the present disclosure.

[0012] Figure 3B is a timing diagram for explaining a display device operating at a second driving frequency in a variable frequency mode according to an embodiment of the present disclosure.

[0013] Figure 4 is a cross-sectional view of a display panel according to an embodiment of the present disclosure.

[0014] FIG. 5A to FIG. 5F is a plan view showing the layout of layers stacked in a display panel.

[0015] Figure 5Gis a plan view of a display panel according to an embodiment of the present disclosure.

[0016] Figure 6 is a circuit diagram of a pixel according to another embodiment of the present disclosure.

[0017] Figure 7 is a cross-sectional view of a display panel according to another embodiment of the present disclosure.

[0018] FIG. 8A to FIG. 8G is a plan view showing the layout of layers stacked in a display panel.

[0019] Fig. 9 is a plan view of a display panel according to an embodiment of the present disclosure.

[0020] Fig.10 is a cross-sectional view of a display panel according to yet another embodiment of the present disclosure. DETAILED DESCRIPTION

[0021] In this specification, when a component (or region, layer, part, etc.) is referred to as being "on", "connected to" or "coupled to" another component, this means that the component may be directly on, connected to or coupled to another component, or a third component may exist between the component and the other component.

[0022] The same reference numerals represent the same components. In addition, in the accompanying drawings, for effective description, the thickness, ratio and size of the components are exaggerated. The terms used herein are only used for the purpose of describing specific embodiments and are not intended to be limited. As used herein, "one", "one (kind / person)", "said (the)" and "at least one" do not represent the limitation of quantity, and are intended to include the singular and plural, unless the context clearly states otherwise. For example, "element" has the same meaning as "at least one element", unless the context clearly states otherwise. "At least one" should not be interpreted as limiting "one" or "one (kind / person)". "Or" means "and / or". As used herein, the term "and / or" includes all combinations of one or more combinations defined by the relevant components.

[0023] Terms such as "first" and "second" etc. may be used to describe various components, but the components should not be limited by these terms. These terms may be used only to distinguish one component from other components. For example, without departing from the scope of the present disclosure, a first component may be referred to as a second component, and similarly, a second component may also be referred to as a first component. Unless otherwise specified, a term in the singular may include a plural form.

[0024] In addition, terms such as "below", "below", "above", and "over" are used to describe the relationship of components shown in the drawings. These terms are relative concepts and are described based on the directions shown in the drawings.

[0025] It should be understood that terms such as “include,” “comprises,” and “has,” when used herein, specify the presence of stated features, numbers, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof.

[0026] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the present disclosure belongs. Unless explicitly defined as having such characteristics in the present application, such terms as defined in general dictionaries should be interpreted as having a meaning consistent with the meaning in the context in the relevant field, and should not be interpreted in an idealized or overly formalized meaning.

[0027] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0028] Figure 1 is a block diagram of a display device according to an embodiment of the present disclosure.

[0029] Reference Figure 1 , the display device DD can be activated according to the electrical signal and can display an image. The display device DD can be applied to electronic devices such as smart watches, computers (such as tablet computers or notebook computers), or smart TVs.

[0030] The display device DD includes a display panel DP and a panel driver PDD driving the display panel DP. In an embodiment of the present disclosure, the panel driver PDD may include a driving controller 100, a data driver 200, a scan driver 300, a light emitting driver 350, and a voltage generator 400.

[0031] The driving controller 100 receives the image signal RGB and the control signal CTRL. The driving controller 100 generates the image data DATA by converting the data format of the image signal RGB according to the specification of the interface of the data driver 200. The driving controller 100 outputs the scanning control signal SCS, the data control signal DCS and the emission driving control signal ECS.

[0032] The data driver 200 receives a data control signal DCS and image data DATA from the driving controller 100. The data driver 200 converts the image data DATA into data signals and outputs the data signals to a plurality of data lines DL1, DL2, ... and DLm to be described below. The data signals are analog data voltages corresponding to grayscale values ​​of the image data DATA.

[0033] The voltage generator 400 generates voltages for operation of the display panel DP. In an embodiment of the present disclosure, the voltage generator 400 generates a first driving voltage ELVDD, a second driving voltage ELVSS, a first initialization voltage VINT, and a second initialization voltage AINT. The first initialization voltage VINT and the second initialization voltage AINT may have different voltage levels. In an embodiment of the present disclosure, the voltage generator 400 may additionally generate a reference voltage Vref (reference voltage Vref) supplied to the display panel DP. Figure 2A ). The reference voltage Vref may have a voltage level lower than that of the first driving voltage ELVDD.

[0034] The scan driver 300 receives a scan control signal SCS from the drive controller 100. The scan control signal SCS may include a start signal for starting the operation of the scan driver 300 and a plurality of clock signals. The scan driver 300 generates a plurality of scan signals and sequentially outputs the plurality of scan signals to scan lines to be described below. The light emitting driver 350 may output a light emitting control signal to light emitting control lines EML11 to EML1n and EML21 to EML2n to be described below in response to a light emitting drive control signal ECS from the drive controller 100. In an embodiment, the scan driver 300 and the light emitting driver 350 may be integrated into one circuit.

[0035] The scan driver 300 outputs initialization scan signals to the initialization scan lines GIL1 to GILn of the display panel DP, and outputs compensation scan signals to the compensation scan lines GCL1 to GCLn of the display panel DP. The scan driver 300 outputs write scan signals to the write scan lines GWL1 to GWLn of the display panel DP, and outputs black scan signals to the black scan lines GBL1 to GBLn of the display panel DP.

[0036] The display panel DP includes initialization scan lines GIL1 to GILn, compensation scan lines GCL1 to GCLn, write scan lines GWL1 to GWLn, black scan lines GBL1 to GBLn, first light emission control lines EML11 to EML1n, second light emission control lines EML21 to EML2n, data lines DL1 to DLm, and pixels PX, where m and n are each a natural number greater than 0. The display panel DP has a display area DA and a non-display area NDA defined therein. The initialization scan lines GIL1 to GILn, the compensation scan lines GCL1 to GCLn, the write scan lines GWL1 to GWLn, the black scan lines GBL1 to GBLn, the first light emission control lines EML11 to EML1n, the second light emission control lines EML21 to EML2n, the data lines DL1 to DLm, and the pixels PX may be disposed in the display area DA. Initialization scan lines GIL1 to GILn, compensation scan lines GCL1 to GCLn, write scan lines GWL1 to GWLn, black scan lines GBL1 to GBLn, first light emission control lines EML11 to EML1n, and second light emission control lines EML21 to EML2n extend in the first direction DR1 and are arranged in the second direction DR2 so as to be spaced apart from each other. Data lines DL1 to DLm extend in the second direction DR2 and are arranged in the first direction DR1 so as to be spaced apart from each other.

[0037] The scanning driver 300 and the light emitting driver 350 may be disposed in the non-display area NDA of the display panel DP. In an embodiment of the present disclosure, the scanning driver 300 is disposed adjacent to one side of the display area DA, and the light emitting driver 350 is disposed adjacent to the opposite side of the display area DA opposite to the one side. Figure 1 In the embodiment shown in FIG. 3 , the scan driver 300 and the light emitting driver 350 are disposed on opposite sides of the display area DA, but the present disclosure is not limited thereto. In another embodiment, for example, the scan driver 300 and the light emitting driver 350 may be disposed on one side adjacent to the display panel DP and on the opposite side.

[0038] The plurality of pixels PX are electrically connected to initialization scan lines GIL1 to GILn, compensation scan lines GCL1 to GCLn, write scan lines GWL1 to GWLn, black scan lines GBL1 to GBLn, first emission control lines EML11 to EML1n, second emission control lines EML21 to EML2n, and data lines DL1 to DLm. Each of the plurality of pixels PX may be electrically connected to four scan lines and two emission control lines. In an embodiment, for example, Figure 1As shown in , the first row of pixels may be connected to the first initialization scan line GIL1, the first compensation scan line GCL1, the first write scan line GWL1, the first black scan line GBL1, the first-first emission control line EML11, and the second-first emission control line EML21. In addition, the second row of pixels may be connected to the second initialization scan line GIL2, the second compensation scan line GCL2, the second write scan line GWL2, the second black scan line GBL2, the first-second emission control line EML12, and the second-second emission control line EML22. However, it is not limited thereto, and the number of scan lines and emission control lines connected to each pixel PX may be changed.

[0039] Each of the plurality of pixels PX includes a light emitting element ED (see Figure 2A ) and a pixel circuit unit PXC (refer to Figure 2A ). The pixel circuit unit PXC may include one or more transistors and one or more capacitors. The scan driver 300 and the light emitting driver 350 may be directly disposed in the non-display area NDA of the display panel DP by the same process as the transistors of the pixel circuit unit PXC.

[0040] Each of the plurality of pixels PX receives the first driving voltage ELVDD, the second driving voltage ELVSS, and the first and second initialization voltages VINT and AINT from the voltage generator 400. Alternatively, each of the plurality of pixels PX may additionally receive a reference voltage Vref from the voltage generator 400.

[0041] Figure 2A is a circuit diagram of a pixel according to an embodiment of the present disclosure, and Figure 2B is a timing diagram for explaining the operation of a pixel according to an embodiment of the present disclosure.

[0042] Figure 1 The pixels PX shown in FIG. 1 and FIG. 2 may have the same configuration. Figure 2A The configuration of one pixel PXij among the pixels PX will be described, and description of the configurations of the remaining pixels will be omitted, where i is a natural number greater than or equal to 1 and less than or equal to m, and j is a natural number greater than or equal to 1 and less than or equal to n.

[0043] Reference Figure 2A , the pixel PXij is connected to Figure 1The j-th initialization scan line GILj among the initialization scan lines GIL1 to GILn, the j-th compensation scan line GCLj among the compensation scan lines GCL1 to GCLn, the j-th write scan line GWLj among the write scan lines GWL1 to GWLn, and the j-th black scan line GBLj among the black scan lines GBL1 to GBLn are shown in FIG. In addition, the pixel PXij is connected to Figure 1 The pixel PXij is connected to the first-jth emission control line EML1j among the first emission control lines EML11 to EML1n, and to the second-jth emission control line EML2j among the second emission control lines EML21 to EML2n.

[0044] Reference Figure 2A , the pixel PXij according to the embodiment includes a pixel circuit unit PXC and a light emitting element ED. In the embodiment of the present disclosure, the pixel circuit unit PXC may include nine transistors and two capacitors. Hereinafter, the nine transistors are referred to as a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, and a ninth transistor T9, and the two capacitors are referred to as a first capacitor C1 and a second capacitor C2.

[0045] In this embodiment, each of the first to ninth transistors T1 to T9 is a P-type transistor having a low temperature polysilicon ("LTPS") semiconductor layer. Alternatively, each of the first to ninth transistors T1 to T9 may be an N-type transistor. In another case, at least one of the first to ninth transistors T1 to T9 may be an N-type transistor, and the remaining transistors may be P-type transistors. At least one of the first to ninth transistors T1 to T9 may be a transistor having an oxide semiconductor layer. In an embodiment, for example, some of the first to ninth transistors T1 to T9 may be oxide semiconductor transistors, and the remaining transistors may be LTPS transistors.

[0046] The circuit configuration of the pixel PXij according to the present disclosure is not limited to Figure 2A The circuit configuration shown in . Figure 2A The pixel PXij shown in FIG. 1 is merely exemplary, and various changes and modifications may be made to the circuit configuration of the pixel PXij.

[0047] The jth initialization scan line GILj supplies the jth initialization scan signal GIj to the pixel PXij. The jth write scan line GWLj supplies the jth write scan signal GWj to the pixel PXij, and the jth compensation scan line GCLj supplies the jth compensation scan signal GCj to the pixel PXij. The first-jth emission control line EML1j supplies the first-jth emission control signal EM1j to the pixel PXij, the second-jth emission control line EML2j supplies the second-jth emission control signal EM2j to the pixel PXij, and the i-th data line DLi transmits the i-th data voltage Vdata to the pixel PXij. The i-th data voltage Vdata may have a value similar to that input to the display device DD (refer to Figure 1 )'s voltage level corresponding to the image data DATA.

[0048] The pixel PXij may be connected to a first driving voltage line VL1 , a second driving voltage line VL2 , a first initialization voltage line VIL1 , a second initialization voltage line VIL2 , a reference voltage line VRL, and a bias voltage line VBL.

[0049] The first driving voltage line VL1 will Figure 1 The first driving voltage ELVDD supplied by the voltage generator 400 shown in FIG. 1 is transmitted to the pixel PXij, and the second driving voltage line VL2 transmits the second driving voltage ELVSS supplied from the voltage generator 400 to the pixel PXij. The first initialization voltage line VIL1 and the second initialization voltage line VIL2 receive the first initialization voltage VINT and the second initialization voltage AINT from the voltage generator 400, and transmit the first initialization voltage VINT and the second initialization voltage AINT to the pixel PXij. The reference voltage line VRL receives the reference voltage Vref from the voltage generator 400 and transmits the reference voltage Vref to the pixel PXij. The bias voltage line VBL receives the reference voltage Vref from the voltage generator 400 (refer to FIG. 1 ). Figure 1 ) receives the bias voltage Vbias and transmits the bias voltage Vbias to the pixel PXij.

[0050] Each of the first to ninth transistors T1 to T9 may include an input electrode (or source electrode), an output electrode (or drain electrode), and a control electrode (or gate electrode). In this specification, for convenience, the input electrode, the output electrode, and the control electrode may be referred to as the first electrode, the second electrode, and the third electrode.

[0051] The first transistor T1 (or, referred to as the driving transistor T1) may be provided between the first driving voltage line VL1 and the light emitting element ED. Specifically, the first transistor T1 includes a first electrode electrically connected to the first driving voltage line VL1, a second electrode electrically connected to the light emitting element ED, and a third electrode connected to the first node N1. The first transistor T1 may receive the first driving voltage ELVDD through the first driving voltage line VL1. The first electrode of the first transistor T1 (see Figure 4 The first electrode S1 in FIG. 1 may be connected to the first driving voltage line VL1 via the eighth transistor T8, and the second electrode of the first transistor T1 (see FIG. 14 ) may be connected to the first driving voltage line VL1 via the eighth transistor T8. Figure 4 The second electrode D1 in the transistor can be electrically connected to the anode of the light emitting element ED via the sixth transistor T6.

[0052] The second transistor T2 may be connected between the i-th data line DLi and the second node N2. Specifically, the second transistor T2 includes a first electrode connected to the i-th data line DLi, a second electrode connected to the second node N2, and a third electrode receiving the j-th write scan signal GWj through the j-th write scan line GWLj. Figure 2B ), the second transistor T2 is turned on in response to the jth write scan signal GWj supplied to the jth write scan line GWLj. The i-th data line DLi and the second node N2 may be electrically connected through the turned-on second transistor T2, and the i-th data voltage Vdata applied to the i-th data line DLi may be applied to the second node N2 through the turned-on second transistor T2. The data write period AP7 may be referred to as the seventh effective period AP7.

[0053] The first capacitor C1 is connected between the first node N1 and the second node N2, and the second capacitor C2 is connected between the second node N2 and the first driving voltage line VL1. The first capacitor C1 includes a first electrode electrically connected to the first node N1 and a second electrode electrically connected to the second node N2. The second capacitor C2 includes a first electrode electrically connected to the first driving voltage line VL1 and a second electrode electrically connected to the second node N2.

[0054] The third transistor T3 is connected to the second electrode of the first transistor T1 and the third electrode of the first transistor T1 (see Figure 4 Specifically, the third transistor T3 includes a first electrode electrically connected to the second electrode of the first transistor T1, a second electrode electrically connected to the first node N1, and a third electrode receiving the jth compensation scan signal GCj through the jth compensation scan line GCLj. In the compensation periods AP4, AP5, and AP6 (refer to Figure 2B), the third transistor T3 is turned on in response to the jth compensation scan signal GCj supplied to the jth compensation scan line GCLj. During the compensation periods AP4, AP5 and AP6, the first transistor T1 may be diode-connected through the turned-on third transistor T3. In this embodiment, the compensation periods AP4, AP5 and AP6 include a fourth effective period AP4, a fifth effective period AP5 and a sixth effective period AP6.

[0055] The fourth transistor T4 (or, referred to as the first initialization transistor T4) is electrically connected between the first node N1 and the first initialization voltage line VIL1. Specifically, the fourth transistor T4 includes a first electrode electrically connected to the first node N1, a second electrode electrically connected to the first initialization voltage line VIL1, and a third electrode receiving the jth initialization scan signal GIj through the jth initialization scan line GILj. The first initialization voltage VINT may be applied to the first initialization voltage line VIL1. During the initialization periods AP1, AP2, and AP3 (refer to Figure 2B ), the fourth transistor T4 is turned on in response to the jth initialization scan signal GIj supplied to the jth initialization scan line GILj. During the initialization periods AP1, AP2, and AP3, the first node N1 may be initialized to the first initialization voltage VINT by the turned-on fourth transistor T4. In this embodiment, the initialization periods AP1, AP2, and AP3 include a first effective period AP1, a second effective period AP2, and a third effective period AP3.

[0056] The fifth transistor T5 may be electrically connected between the second node N2 and the reference voltage line VRL. The reference voltage line VRL may be connected from Figure 1 The voltage generator 400 shown in receives the reference voltage Vref, and can supply the reference voltage Vref to the pixel PXij. The reference voltage Vref can have a voltage level lower than the voltage level of the first driving voltage ELVDD. The fifth transistor T5 includes a first electrode connected to the reference voltage line VRL, a second electrode electrically connected to the second node N2, and a third electrode receiving the jth compensation scan signal GCj through the jth compensation scan line GCLj. During the compensation periods AP4, AP5 and AP6, the fifth transistor T5 is turned on in response to the jth compensation scan signal GCj provided to the jth compensation scan line GCLj. The reference voltage line VRL and the second node N2 are electrically connected through the turned-on fifth transistor T5. That is, during the compensation periods AP4, AP5 and AP6, the reference voltage Vref can be applied to the second node N2.

[0057] In an embodiment of the present disclosure, the third electrode of the third transistor T3 and the third electrode of the fifth transistor T5 are commonly connected to the j-th compensation scan line GCLj. However, the present disclosure is not limited thereto. That is, in another embodiment, the third electrode of the third transistor T3 and the third electrode of the fifth transistor T5 may be connected to different scan lines and may receive different scan signals.

[0058] The sixth transistor T6 (or, referred to as the first light emission control transistor T6) is connected between the second electrode of the first transistor T1 and the anode of the light emitting element ED. Specifically, the sixth transistor T6 includes a first electrode connected to the second electrode of the first transistor T1, a second electrode electrically connected to the anode of the light emitting element ED, and a third electrode electrically connected to the second-jth light emission control line EML2j. In the second non-light emitting period NEP2 (refer to Figure 2B ), the sixth transistor T6 may be turned on by the second to jth light emitting control signal EM2j supplied to the second to jth light emitting control line EML2j.

[0059] The seventh transistor T7 (or, referred to as the second initialization transistor T7) is connected between the second initialization voltage line VIL2 and the anode of the light emitting element ED. The seventh transistor T7 includes a first electrode connected to the anode of the light emitting element ED, a second electrode connected to the second initialization voltage line VIL2, and a third electrode receiving the jth black scan signal GBj (or, referred to as the initialization control signal GBj) through the jth black scan line GBLj. The second initialization voltage AINT can be applied to the second initialization voltage line VIL2. In an embodiment of the present disclosure, the second initialization voltage AINT has a voltage level different from the voltage level of the first initialization voltage VINT. During the black period AP8 (refer to Figure 2B ), the seventh transistor T7 is turned on in response to the jth black scan signal GBj provided to the jth black scan line GBLj. During the black period AP8, the anode of the light emitting element ED may be initialized to the second initialization voltage AINT by the turned-on seventh transistor T7. Alternatively, the third electrode of the seventh transistor T7 may be connected to the (j+1)th write scan line and may receive the (j+1)th write scan signal as the jth black scan signal GBj. The black period AP8 may be referred to as the eighth effective period AP8.

[0060] The eighth transistor T8 may be electrically connected between the first transistor T1 and the first driving voltage line VL1. Specifically, the eighth transistor T8 includes a first electrode electrically connected to the first driving voltage line VL1, a second electrode electrically connected to the first electrode of the first transistor T1, and a third electrode receiving the first to j-th emission control signal EM1j through the first to j-th emission control line EML1j. In the first non-emission period NEP1 (refer to Figure 2B ), the eighth transistor T8 may be turned on by the first to j-th light emitting control signals EM1j supplied to the first to j-th light emitting control lines EML1j.

[0061] The ninth transistor T9 may be electrically connected between the first transistor T1 and the bias voltage line VBL. Specifically, the ninth transistor T9 includes a first electrode electrically connected to the bias voltage line VBL, a second electrode electrically connected to the first electrode of the first transistor T1, and a third electrode receiving the jth black scan signal GBj through the jth black scan line GBLj. During the black period AP8, the ninth transistor T9 is turned on in response to the jth black scan signal GBj provided to the jth black scan line GBLj. During the black period AP8, the bias voltage Vbias may be applied to the first electrode of the first transistor T1 through the turned-on ninth transistor T9.

[0062] The light emitting element ED may be electrically connected between the sixth transistor T6 and the second driving voltage line VL2. The anode of the light emitting element ED is connected to the second electrode of the sixth transistor T6, and the cathode of the light emitting element ED is connected to the second driving voltage line VL2. The second driving voltage ELVSS may be applied to the second driving voltage line VL2. The second driving voltage ELVSS has a level lower than that of the first driving voltage ELVDD. Therefore, the light emitting element ED may emit light according to a voltage corresponding to the difference between the voltage of the signal transmitted through the sixth transistor T6 and the second driving voltage ELVSS.

[0063] Despite Figure 2B Only the jth initialization scan signal GIj, the jth compensation scan signal GCj, the jth write scan signal GWj and the jth black scan signal GBj, the first to jth light-emitting control signal EM1j and the second to jth light-emitting control signal EM2j are shown, and the remaining scan signals and the remaining light-emitting control signals also operate similarly, and therefore a detailed description thereof will be omitted.

[0064] Reference Figure 2A and Figure 2B, the first-jth light emitting control signal EM1j includes a first non-light emitting period NEP1, and the second-jth light emitting control signal EM2j includes a second non-light emitting period NEP2. In an embodiment of the present disclosure, the first non-light emitting period NEP1 and the second non-light emitting period NEP2 may overlap with each other. The duration of the second non-light emitting period NEP2 may be greater than the duration of the first non-light emitting period NEP1. The first non-light emitting period NEP1 may be defined as a non-effective period (or a high level period) of the first-jth light emitting control signal EM1j, and the second non-light emitting period NEP2 may be defined as a non-effective period (or a high level period) of the second-jth light emitting control signal EM2j. The low level period of the second-jth light emitting control signal EM2j may be defined as a light emitting period.

[0065] The jth initialization scan signal GIj may have a first effective period AP1, a second effective period AP2, and a third effective period AP3 (i.e., a low level period) during the second non-light emitting period NEP2. The jth initialization scan signal GIj is supplied to the fourth transistor T4 through the jth initialization scan line GILj, and the fourth transistor T4 is turned on during the first effective period AP1, the second effective period AP2, and the third effective period AP3 in which the jth initialization scan signal GIj is activated. During the first effective period AP1, the second effective period AP2, and the third effective period AP3, the potential (i.e., the voltage) of the first node N1 may be initialized to the first initialization voltage VINT by the turned-on fourth transistor T4. That is, since the jth initialization scan signal GIj includes three effective periods AP1, AP2, and AP3, the first node N1 may be initialized three times within the second non-light emitting period NEP2. Each of the first effective period AP1, the second effective period AP2, and the third effective period AP3 may be defined as an initialization period.

[0066] Among the jth initialization scan signal GIj, the jth compensation scan signal GCj, the jth write scan signal GWj and the jth black scan signal GBj, the jth compensation scan signal GCj may have fourth, fifth and sixth effective periods AP4, AP5 and AP6 during the second non-emission period NEP2.

[0067] When the j-th compensation scan signal GCj is supplied to the third transistor T3 and the fifth transistor T5 through the j-th compensation scan line GCLj, the third transistor T3 and the fifth transistor T5 are turned on in the fourth effective period AP4, the fifth effective period AP5 and the sixth effective period AP6. The first transistor T1 is connected in a diode manner through the turned-on third transistor T3 and is forward biased. Then, the compensation voltage "ELVDD-Vth" obtained by subtracting the threshold voltage (Vth) of the first transistor T1 from the first driving voltage ELVDD can be applied to the first node N1. That is, the potential of the first node N1 can be compensated by the compensation voltage "ELVDD-Vth" in the fourth effective period AP4, the fifth effective period AP5 and the sixth effective period AP6. During the fourth effective period AP4, the fifth effective period AP5 and the sixth effective period AP6, the reference voltage Vref is applied to the second node N2 through the turned-on fifth transistor T5.

[0068] The fourth effective period AP4, the fifth effective period AP5 and the sixth effective period AP6 can be defined as compensation periods. The duration of each of the fourth effective period AP4, the fifth effective period AP5 and the sixth effective period AP6 can be equal to the duration of each of the first effective period AP1, the second effective period AP2 and the third effective period AP3.

[0069] Among the jth initialization scan signal GIj, the jth compensation scan signal GCj, the jth write scan signal GWj and the jth black scan signal GBj, the jth write scan signal GWj can have a seventh effective period AP7 during the second non-luminous period NEP2, and the jth black scan signal GBj can have an eighth effective period AP8 during the second non-luminous period NEP2.

[0070] The j-th write scan signal GWj is supplied to the second transistor T2 through the j-th write scan line GWLj, and the second transistor T2 is turned on in the seventh effective period AP7. The i-th data voltage Vdata can be applied to the second node N2 through the turned-on second transistor T2. Then, the potential of the second node N2 changes from the first drive voltage ELVDD to the i-th data voltage Vdata. The potential of the first node N1 is also changed by the coupling of the first capacitor C1. The seventh effective period AP7 can be called a data write period.

[0071] The j-th black scan signal GBj is supplied to the seventh transistor T7 and the ninth transistor T9 through the j-th black scan line GBLj, and the seventh transistor T7 and the ninth transistor T9 are turned on during the eighth effective period AP8. During the eighth effective period AP8, the second initialization voltage AINT may be applied to the anode of the light emitting element ED through the turned-on seventh transistor T7. Then, the anode of the light emitting element ED may be initialized to the second initialization voltage AINT. In addition, during the eighth effective period AP8, the bias voltage Vbias may be applied to the first electrode of the first transistor T1 through the turned-on ninth transistor T9.

[0072] The eighth effective period AP8 may be referred to as a black period. The eighth effective period AP8 may include a plurality of sub-effective periods SAP8. In an embodiment of the present disclosure, Figure 2B 2 shows a case where the eighth effective period AP8 includes three sub-effective periods SAP8. However, the number of sub-effective periods SAP8 is not limited thereto.

[0073] In an embodiment of the present disclosure, each of the sub-effective periods SAP8 has the same duration as the seventh effective period AP7. In addition, the duration of each of the first effective period AP1 to the sixth effective period SP6 may be greater than or equal to the duration of each of the seventh effective period AP7 and the eighth effective period AP8. Figure 2B An example is shown in which the duration of each of the first effective period AP1 to the sixth effective period AP6 is twice the duration of the seventh effective period AP7, but the present disclosure is not limited thereto. Alternatively, the duration of each of the first effective period AP1 to the sixth effective period AP6 may be three or four times the duration of the seventh effective period AP7.

[0074] Figure 3A is a timing diagram for explaining a display device operating at a first driving frequency in a variable frequency mode according to an embodiment of the present disclosure, and Figure 3B is a timing diagram for explaining a display device operating at a second driving frequency in a variable frequency mode according to an embodiment of the present disclosure.

[0075] Reference Figure 1 , Figure 3A and Figure 3B , also refer to Figure 2A The display device DD may operate in a normal frequency mode (or, a first mode) in which the driving frequency is fixed (or does not change), or may operate in a variable frequency mode (or, a second mode) in which the driving frequency varies. In the variable frequency mode, the driving frequency may vary according to the frame rate. Figure 3A shows a case where the display device DD operates at a first driving frequency in a variable frequency mode, and Figure 3B A situation in which the display device DD operates at a second driving frequency in a variable frequency mode is shown. In an embodiment of the present disclosure, the first driving frequency may be the highest driving frequency at which the display device DD can operate. In an embodiment, for example, the first driving frequency may be 240 Hz or 480 Hz. The first driving frequency may be referred to as a reference frequency or a maximum frequency. The second driving frequency may be a frequency lower than the first driving frequency. In an embodiment of the present disclosure, the second driving frequency may be a frequency corresponding to one of the compensation frequencies preset in the panel driver PDD (e.g., the drive controller 100).

[0076] like Figure 1 and Figure 3A As shown in , when the display device DD operates at a first driving frequency in a variable frequency mode, the scan signals GIj, GCj, GWj and GBj and the light emitting control signals EM1j and EM2j may be activated within the first drive frame DF1. In an embodiment of the present disclosure, an effective period in which each of the scan signals GIj, GCj, GWj and GBj and the light emitting control signals EM1j and EM2j is activated may be defined as a low level period, and an ineffective period in which each of the scan signals GIj, GCj, GWj and GBj and the light emitting control signals EM1j and EM2j is disabled may be defined as a high level period. In an embodiment of the present disclosure, the first drive frame DF1 may include a first write frame WF1. The first write frame WF1 may include a first cycle interval CYP1 and a second cycle interval CYP2.

[0077] Among the scan signals GIj, GCj, GWj and GBj, the scan signals GIj, GCj and GWj can be activated only in the first cycle interval CYP1, and can be kept in a disabled state in the second cycle interval CYP2. In an embodiment of the present disclosure, the jth black scan signal GBj and the light emitting control signals EM1j and EM2j can be activated in the first cycle interval CYP1 and the second cycle interval CYP2. The jth initialization scan signal GIj, the jth compensation scan signal GCj and the jth write scan signal GWj can be activated only in the first cycle interval CYP1. That is, the jth black scan signal GBj, the first-jth light emitting control signal EM1j and the second-jth light emitting control signal EM2j are activated in units of one cycle interval, and the jth initialization scan signal GIj, the jth compensation scan signal GCj and the jth write scan signal GWj are activated in units of one first write frame WF1. Therefore, the frequencies of the jth black scan signal GBj, the first-jth emission control signal EM1j, and the second-jth emission control signal EM2j may be greater than the frequencies of the jth initialization scan signal GIj, the jth compensation scan signal GCj, and the jth write scan signal GWj.

[0078] like Figure 1 and Figure 3B As shown in , the display device DD can operate at a second driving frequency different from the first driving frequency in a variable frequency mode. In an embodiment of the present disclosure, the second driving frequency may be lower than the first driving frequency. In an embodiment, for example, the second driving frequency may be about 48 Hz or about 96 Hz. When the display device DD operates at the second driving frequency, the scanning signals GIj, GCj, GWj and GBj and the light emitting control signals EM1j and EM2j may be activated within the second driving frame DF2.

[0079] In an embodiment of the present disclosure, the second drive frame DF2 may include a second write frame WF2 and at least one hold frame HF2. The duration of the second write frame WF2 may be equal to the duration of the first write frame WF1. The duration of the hold frame HF2 may be equal to the duration of the second write frame WF2. The number of hold frames HF2 included in the second drive frame DF2 may vary according to the size of the second drive frequency.

[0080] Among the scanning signals GIj, GCj, GWj and GBj, the scanning signals GIj, GCj and GWj may be activated only in the second writing frame WF2, and may be maintained in a disabled state in the holding frame HF2. The second writing frame WF2 may include a first cycle interval CYP1 and a second cycle interval CYP2. The holding frame HF2 may include a first holding cycle interval HCYP1 and a second holding cycle interval HCYP2. In an embodiment of the present disclosure, each of the first holding cycle interval HCYP1 and the second holding cycle interval HCYP2 may have the same duration as the first cycle interval CYP1 and the second cycle interval CYP2.

[0081] Among the scan signals GIj, GCj, GWj and GBj, the scan signals GIj, GCj and GWj may be activated only in the first cycle interval CYP1 of the second write frame WF2, and may be kept in a disabled state in the second cycle interval CYP2. The jth black scan signal GBj and the light emitting control signals EM1j and EM2j may be activated in the second write frame WF2 and the hold frame HF2. That is, the jth black scan signal GBj, the first-jth light emitting control signal EM1j and the second-jth light emitting control signal EM2j are activated in units of one cycle interval, and the jth initialization scan signal GIj, the jth compensation scan signal GCj and the jth write scan signal GWj are activated in units of the second write frame WF2. Therefore, the frequencies of the jth black scan signal GBj, the first-jth light emitting control signal EM1j and the second-jth light emitting control signal EM2j may be greater than the frequencies of the jth initialization scan signal GIj, the jth compensation scan signal GCj and the jth write scan signal GWj.

[0082] Figure 4 is a cross-sectional view of a display panel according to an embodiment of the present disclosure. Specifically, Figure 4 Show Figure 2A . The cross-sectional structure of a portion AA of a pixel PXij is shown in FIG.

[0083] Reference Figure 4 , the display panel DP may include a base layer BL, a circuit layer DP_CL and an element layer DP_ED.

[0084] The base layer BL may include a synthetic resin layer. The synthetic resin layer may include a thermosetting resin. Specifically, the synthetic resin layer may be a polyimide-based resin layer, and its material is not particularly limited. The synthetic resin layer may include at least one of an acrylate-based resin, a methacrylate-based resin, a polyisoprene-based resin, a vinyl resin, an epoxy-based resin, a polyurethane-based resin, a cellulose-based resin, a siloxane-based resin, a polyamide-based resin, and a perylene-based resin. In addition, the base layer BL may include a glass substrate, a metal substrate, or an organic / inorganic composite substrate.

[0085] At least one inorganic layer may be disposed on the upper surface of the base layer BL. The inorganic layer may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon oxynitride, zirconium oxide, and hafnium oxide. The inorganic layer may be formed of a plurality of inorganic layers. The plurality of inorganic layers may constitute a barrier layer and / or a buffer layer. The barrier layer and the buffer layer may be selectively disposed.

[0086] The barrier layer prevents foreign matter from penetrating from the outside. The barrier layer may include a silicon oxide layer and a silicon nitride layer. A plurality of silicon oxide layers and a plurality of silicon nitride layers may be provided. The silicon oxide layers and the silicon nitride layers may be alternately stacked on top of each other.

[0087] The buffer layer may be disposed on the barrier layer. The buffer layer improves the coupling force between the base layer BL and the semiconductor pattern and / or the conductive pattern. The buffer layer may include a silicon oxide layer and a silicon nitride layer. The silicon oxide layer and the silicon nitride layer may be alternately stacked on top of each other. The barrier layer and the buffer layer may be omitted.

[0088] The circuit layer DP_CL is disposed on the base layer BL. The circuit layer DP_CL includes first to third semiconductor patterns disposed on the base layer BL. The first to third semiconductor patterns may include silicon semiconductors. The first to third semiconductor patterns may include polycrystalline silicon. However, not limited thereto, in another embodiment, the first to third semiconductor patterns may include amorphous silicon or oxide semiconductors.

[0089] The first to third semiconductor patterns have different electrical characteristics depending on whether the first to third semiconductor patterns are doped. Each of the first to third semiconductor patterns may include a doped region and an undoped region. The doped region may be doped with an N-type dopant or a P-type dopant. The P-type transistor includes a doped region doped with a P-type dopant, and the N-type transistor includes a doped region doped with an N-type dopant.

[0090] The doped region has a higher conductivity than that of the undoped region and is substantially used as an electrode or a signal line. The undoped region substantially corresponds to a channel portion of a transistor. In other words, one portion of each of the first to third semiconductor patterns may be a channel portion of a transistor, another portion of each of the first to third semiconductor patterns may be a source or drain of the transistor, and another portion may be a connection signal line (or, a connection electrode).

[0091] like Figure 4 As shown in, the first electrode S1, the channel portion A1, and the second electrode D1 of the first transistor T1 are formed by a first semiconductor pattern. The first electrode S1 and the second electrode D1 of the first transistor T1 extend from the channel portion A1 in opposite directions. The first electrode S2, the channel portion A2, and the second electrode D2 of the second transistor T2 are formed by a second semiconductor pattern. The first electrode S2 and the second electrode D2 of the second transistor T2 extend from the channel portion A2 in opposite directions. The first electrode S3, the channel portion A3, and the second electrode D3 of the third transistor T3 are formed by a third semiconductor pattern. The first electrode S3 and the second electrode D3 of the third transistor T3 extend from the channel portion A3 in opposite directions. The first electrode S3 of the third transistor T3 and the second electrode D1 of the first transistor T1 may be formed integrally with each other (i.e., provided integrally).

[0092] The first insulating layer 10 (or the gate insulating layer 10) is disposed on the base layer BL. In a plan view, the first insulating layer 10 overlaps with a plurality of pixels PX in common and covers the first semiconductor pattern to the third semiconductor pattern. The first insulating layer 10 may be an inorganic layer and / or an organic layer, and may have a single-layer structure or a multi-layer structure. The first insulating layer 10 may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon oxynitride, zirconium oxide, and hafnium oxide. In the present embodiment, the first insulating layer 10 may be a single silicon oxide layer. Not only the first insulating layer 10 but also the insulating layer of the circuit layer DP_CL to be described below may be an inorganic layer and / or an organic layer, and may have a single-layer structure or a multi-layer structure. The inorganic layer may include at least one of the above materials.

[0093] The third electrode G1 of the first transistor T1, the third electrode G2 of the second transistor T2, and the third electrode G3 of the third transistor T3 are disposed on the first insulating layer 10. In a plan view, the third electrode G1 of the first transistor T1 overlaps with the channel portion A1 of the first transistor T1, the third electrode G2 of the second transistor T2 overlaps with the channel portion A2 of the second transistor T2, and the third electrode G3 of the third transistor T3 overlaps with the channel portion A3 of the third transistor T3.

[0094] The first capacitor electrode C1-1 of the first capacitor C1 and the third capacitor electrode C2-1 of the second capacitor C2 are additionally disposed on the first insulating layer 10. The first capacitor electrode C1-1 may extend from the third electrode G1 of the first transistor T1 and may be integrally formed with the third electrode G1 of the first transistor T1. The third capacitor electrode C2-1 may be spaced apart from the first capacitor electrode C1-1. The third electrode G1 of the first transistor T1, the first capacitor electrode C1-1, and the third capacitor electrode C2-1 may be Figure 5A The first capacitor electrode C1-1 and the third capacitor electrode C2-1 may not overlap with each other in a plan view (ie, may be spaced apart from each other).

[0095] A second insulating layer 20 covering the third electrode G1 of the first transistor T1, the third electrode G2 of the second transistor T2, the third electrode G3 of the third transistor T3, the first capacitor electrode C1-1, and the third capacitor electrode C2-1 is disposed on the first insulating layer 10. The second insulating layer 20 overlaps the plurality of pixels PX in common in a plan view. The second insulating layer 20 may be an inorganic layer and / or an organic layer, and may have a single-layer structure or a multi-layer structure. In the present embodiment, the second insulating layer 20 may be a single silicon oxide layer.

[0096] The second capacitor electrode C1-2 of the first capacitor C1 and the fourth capacitor electrode C2-2 of the second capacitor C2 may be disposed on the second insulating layer 20. The second capacitor electrode C1-2 faces the first capacitor electrode C1-1, and the second insulating layer 20 is between the second capacitor electrode C1-2 and the first capacitor electrode C1-1 to form the first capacitor C1. The fourth capacitor electrode C2-2 faces the third capacitor electrode C2-1, and the second insulating layer 20 is between the fourth capacitor electrode C2-2 and the third capacitor electrode C2-1 to form the second capacitor C2. The second capacitor electrode C1-2 and the fourth capacitor electrode C2-2 may be Figure 5B The second capacitor electrode C1-2 and the fourth capacitor electrode C2-2 may not overlap with each other in a plan view (ie, may be spaced apart from each other).

[0097] The third insulating layer 30 covering the second capacitor electrode C1-2 and the fourth capacitor electrode C2-2 is disposed on the second insulating layer 20. In this embodiment, the third insulating layer 30 may be a single silicon oxide layer.

[0098] The first bridging electrode BE1 and the second bridging electrode BE2 are disposed on the third insulating layer 30. The first bridging electrode BE1 may be an electrode connecting the third electrode G1 of the first transistor T1 (i.e., the first capacitor electrode C1-1 of the first capacitor C1) and the second electrode D3 of the third transistor T3. The first bridging electrode BE1 is connected to the third electrode G1 of the first transistor T1 (i.e., the first capacitor electrode C1-1 of the first capacitor C1) through a contact hole penetrating the second insulating layer 20 and the third insulating layer 30. In addition, the first bridging electrode BE1 is connected to the second electrode D3 of the third transistor T3 through a contact hole penetrating the first insulating layer 10, the second insulating layer 20, and the third insulating layer 30. Although Figure 4 Not shown, but Figure 4 The two second bridge electrodes BE2 shown in FIG. 1 are electrically connected to each other. Figure 4 The two fourth capacitor electrodes C2 - 2 shown in are electrically connected to each other.

[0099] The second bridging electrode BE2 may be an electrode that connects the second capacitor electrode C1-2 and the third capacitor electrode C2-1 and connects the third capacitor electrode C2-1 and the second electrode D2 of the second transistor T2. The second bridging electrode BE2 is connected to the second capacitor electrode C1-2 through a contact hole penetrating the third insulating layer 30, and is connected to the third capacitor electrode C2-1 through a contact hole penetrating the second insulating layer 20 and the third insulating layer 30. In addition, the second bridging electrode BE2 is connected to the third capacitor electrode C2-1 through a contact hole penetrating the second insulating layer 20 and the third insulating layer 30, and is connected to the second electrode D2 of the second transistor T2 through a contact hole penetrating the first insulating layer 10, the second insulating layer 20, and the third insulating layer 30.

[0100] A first connection electrode CE1 and a second connection electrode CE2 are additionally disposed on the third insulating layer 30. The first connection electrode CE1 is an electrode for connecting the fourth capacitor electrode C2-2 to the first driving voltage line VL1, and the second connection electrode CE2 is an electrode for connecting the first electrode S2 of the second transistor T2 to the data line (i.e., the i-th data line DLi).

[0101] The first link electrode CE1 is connected to the fourth capacitor electrode C2 - 2 through a contact hole penetrating the third insulating layer 30 , and the second link electrode CE2 is connected to the first electrode S2 of the second transistor T2 through a contact hole penetrating the first, second and third insulating layers 10 , 20 and 30 .

[0102] The first and second bridge electrodes BE1 and BE2 and the first and second connection electrodes CE1 and CE2 may be Figure 5C A portion of the first data pattern layer 140 is shown in FIG.

[0103] The fourth insulating layer 40 is provided to cover the first and second bridging electrodes BE1 and BE2 and the first and second connection electrodes CE1 and CE2. The first driving voltage line VL1, the i-th data line DLi, and the shielding electrode SSE may be provided on the fourth insulating layer 40. The shielding electrode SSE may be integrally formed with the first driving voltage line VL1 (i.e., integrally provided). The first driving voltage line VL1 and the shielding electrode SSE may be spaced apart from the i-th data line DLi.

[0104] The first driving voltage line VL1 is connected to the first link electrode CE1 through a contact hole formed through the fourth insulating layer 40 , and the i th data line DLi is connected to the second link electrode CE2 through a contact hole formed through the fourth insulating layer 40 .

[0105] In a plan view, the shielding electrode SSE may be disposed above the first bridge electrode BE1 and the second bridge electrode BE2 and may overlap the first bridge electrode BE1 and the second bridge electrode BE2. Figure 2A The first node N1 shown in FIG. 1 corresponds to the first node N1, and the second bridge electrode BE2 can be connected to Figure 2A The first node N1 and the second node N2 may correspond to the second-jth light emitting control signal EM2j (refer to Figure 2B ) has a floating state in a low level period (i.e., a light emitting period) of the first node N1 and the second node N2. When the first node N1 and the second node N2 are in a floating state, the potentials (i.e., voltages) of the first node N1 and the second node N2 may be easily oscillated by an environmental signal (e.g., a data signal applied to an adjacent data line (e.g., the (i+1)th data line)). However, since the first bridging electrode BE1 and the second bridging electrode BE2 are covered by the shielding electrode SSE, the shielding electrode SSE can block the influence of the environmental signal on the first node N1 and the second node N2.

[0106] The first driving voltage line VL1, the i-th data line DLi, and the shielding electrode SSE may be Figure 5D A portion of the second data pattern layer 150 is shown in FIG.

[0107] A fifth insulating layer 50 covering the first driving voltage line VL1, the i-th data line DLi and the shielding electrode SSE is disposed on the fourth insulating layer 40. In this embodiment, the fifth insulating layer 50 may include a silicon oxide layer and a silicon nitride layer. The fifth insulating layer 50 may include a plurality of silicon oxide layers and a plurality of silicon nitride layers alternately stacked on each other.

[0108] The element layer DP_ED is disposed on the circuit layer DP_CL. The element layer DP_ED may include a light emitting element ED and a pixel defining layer PDL. The light emitting element ED includes an anode AE, an emission layer EL, and a cathode CCE.

[0109] The pixel defining layer PDL may include an opening OP defined therein to correspond to the light emitting element ED. The opening OP exposes at least a portion of the anode AE ​​of the light emitting element ED. The opening OP of the pixel defining layer PDL may define an emission area PXA. In an embodiment, for example, a plurality of pixels PX (refer to Figure 1 ) can be set on the display panel DP (refer to Figure 1 ). A region in which a plurality of pixels PX are disposed may be defined as a pixel region, and one pixel region may include an emission region PXA and a non-emission region NPXA adjacent to the emission region PXA. The non-emission region NPXA may surround the emission region PXA.

[0110] The emission layer EL is arranged to correspond to the opening OP defined in the pixel defining layer PDL. Although the present embodiment only shows a patterned emission layer EL, the present disclosure is not limited thereto. In another embodiment, a common emission layer for a plurality of pixels PX may be provided in common. In this case, the common emission layer may generate white light or blue light.

[0111] The cathode CCE is provided on the emission layer EL. The cathode CCE for a plurality of pixels PX is provided in common.

[0112] The display panel DP may further include an encapsulation layer that seals the element layer DP_ED. The encapsulation layer may include at least one organic layer and at least one inorganic layer. The inorganic layer may include an inorganic material and may protect the element layer DP_ED from moisture / oxygen. The inorganic layer may include a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer, but is not particularly limited thereto. The organic layer may include an organic material and may protect the element layer DP_ED from foreign matter such as dust particles.

[0113] FIG. 5A to FIG. 5F is a plan view showing the layout of layers stacked in a display panel. Specifically, Figure 5A is a plan view showing a semiconductor pattern layer and a first gate pattern layer provided on a base layer BL, and Figure 5B is a plan view showing a second gate pattern layer disposed on the first gate pattern layer. Figure 5C is a plan view showing a first data pattern layer disposed on a second gate pattern layer.

[0114] Figure 5D and Figure 5Eis a plan view showing a second data pattern layer disposed on the first data pattern layer.

[0115] Fig. 5F is a plan view showing an anode electrode layer disposed on the second data pattern layer. As used herein, a "plan view" is a view in the thickness direction of the base layer BL (ie, a direction perpendicular to the first direction DR1 and the second direction DR2).

[0116] Reference Figure 5A , the semiconductor patterns and the conductive patterns may be repeatedly arranged on the base layer BL according to a predetermined rule. Figures 5A to 5E Three pixel circuit units PXC are shown (refer to Figure 2A )’s floor plan.

[0117] Reference Figure 4 and Figure 5A , a semiconductor pattern layer 110 is shown. The semiconductor pattern layer 110 may be disposed on the base layer BL. The semiconductor pattern layer 110 may include a silicon semiconductor. In an embodiment, for example, the silicon semiconductor may include amorphous silicon or polycrystalline silicon. In an embodiment, for example, the semiconductor pattern layer 110 may include low temperature polycrystalline silicon (LTPS).

[0118] The semiconductor pattern layer 110 includes transistors (ie, first to ninth transistors T1 to T9 (refer to Figure 2A )) of a semiconductor pattern.

[0119] The first insulating layer 10 may be disposed on the semiconductor pattern layer 110, and the first gate pattern layer 120 may be disposed on the first insulating layer 10. The first gate pattern layer 120 may be a layer formed by patterning the first gate metal layer. The first gate pattern layer 120 may include a metal, an alloy, a metal nitride, a conductive metal oxide, or a transparent conductive material. In an embodiment, for example, the first gate pattern layer 120 may include silver (Ag), a silver-containing alloy, molybdenum (Mo), a molybdenum-containing alloy, aluminum (Al), an aluminum-containing alloy, aluminum nitride ("AlN"), tungsten (W), tungsten nitride ("WN"), copper (Cu), indium tin oxide ("ITO"), or indium zinc oxide ("IZO"), but is not particularly limited thereto.

[0120] The first gate pattern layer 120 may include third electrodes of transistors (ie, first to ninth transistors T1 to T9) included in each pixel circuit unit PXC. The first to ninth transistors T1 to T9 may be provided in each pixel circuit unit PXC through the first gate pattern layer 120 and the semiconductor pattern layer 110.

[0121] The first gate pattern layer 120 may further include a first capacitor electrode C1 - 1 of a first capacitor C1 and a third capacitor electrode C2 - 1 of a second capacitor C2 included in each pixel circuit unit PXC.

[0122] Reference Figure 4 and Figure 5B , the second insulating layer 20 may be disposed on the first insulating layer 10 to cover the first gate pattern layer 120. The second gate pattern layer 130 may be disposed on the second insulating layer 20. The second gate pattern layer 130 may be a layer formed by patterning the second gate metal layer. The second gate pattern layer 130 may include a metal, an alloy, a metal nitride, a conductive metal oxide, or a transparent conductive material.

[0123] The second gate pattern layer 130 may include a second capacitor electrode C1-2 of the first capacitor C1 and a fourth capacitor electrode C2-2 of the second capacitor C2. The first capacitor C1 and the second capacitor C2 may be provided in each pixel circuit unit PXC through the first gate pattern layer 120 and the second gate pattern layer 130.

[0124] Reference Figure 4 and Figure 5C , the third insulating layer 30 may be disposed on the second insulating layer 20 to cover the second gate pattern layer 130. The first data pattern layer 140 may be disposed on the third insulating layer 30. The first data pattern layer 140 may be a layer formed by patterning the first data metal layer. The first data pattern layer 140 may include a metal, an alloy, a metal nitride, a conductive metal oxide, or a transparent conductive material.

[0125] The first data pattern layer 140 may include Figure 2A The first data pattern layer 140 may further include scanning lines GWLj, GCLj, GILj and GBLj, emission control lines EML1j and EML2j, a horizontal reference voltage line H-VRL, a first initialization voltage line VIL1 and a second initialization voltage line VIL2, a bias voltage line VBL, and a first horizontal voltage line VL1-1. Figure 4 The first and second bridge electrodes BE1 and BE2 and the first and second connection electrodes CE1 and CE2 are shown in FIG.

[0126] The first bridge electrode BE1 may be an electrode connecting the third electrode G1 of the first transistor T1 (i.e., the first capacitor electrode C1-1 of the first capacitor C1) and the second electrode D3 of the third transistor T3. The first bridge electrode BE1 is connected to the third electrode G1 of the first transistor T1 (i.e., the first capacitor electrode C1-1 of the first capacitor C1) through a contact hole penetrating the second insulating layer 20 and the third insulating layer 30. In addition, the first bridge electrode BE1 is connected to the second electrode D3 of the third transistor T3 through a contact hole penetrating the first insulating layer 10, the second insulating layer 20, and the third insulating layer 30.

[0127] The second bridging electrode BE2 may be an electrode that connects the second capacitor electrode C1-2 of the first capacitor C1 and the third capacitor electrode C2-1 of the second capacitor C2 and connects the third capacitor electrode C2-1 of the second capacitor C2 and the second electrode D2 of the second transistor T2. The second bridging electrode BE2 is connected to the second capacitor electrode C1-2 of the first capacitor C1 through a contact hole penetrating the third insulating layer 30, and is connected to the third capacitor electrode C2-1 of the second capacitor C2 through a contact hole penetrating the second insulating layer 20 and the third insulating layer 30. In addition, the second bridging electrode BE2 is connected to the third capacitor electrode C2-1 of the second capacitor C2 through a contact hole penetrating the second insulating layer 20 and the third insulating layer 30, and is connected to the second electrode D2 of the second transistor T2 through a contact hole penetrating the first insulating layer 10, the second insulating layer 20, and the third insulating layer 30.

[0128] Reference Figure 4 , Figure 5D and Figure 5E , the fourth insulating layer 40 may be disposed on the third insulating layer 30 to cover the first data pattern layer 140. The second data pattern layer 150 may be disposed on the fourth insulating layer 40. The second data pattern layer 150 may be a layer formed by patterning the second data metal layer. The second data pattern layer 150 may include, for example, a metal, an alloy, a metal nitride, a conductive metal oxide, or a transparent conductive material.

[0129] The second data pattern layer 150 may include data lines DLi-1, DLi, and DLi+1, first vertical voltage lines VL1-2, a vertical reference voltage line V-VRL, and a second driving voltage line VL2.

[0130] The second data pattern layer 150 may further include a shielding electrode SSE extending from the first vertical voltage line VL1-2. The shielding electrode SSE may extend from the first vertical voltage line VL1-2 and may be integrally formed with the first vertical voltage line VL1-2. In a plan view, the shielding electrode SSE may extend from the first vertical voltage line VL1-2 to overlap the first bridge electrode BE1 and the second bridge electrode BE2 of the first data pattern layer 140.

[0131] Since the first bridge electrode BE1 and the second bridge electrode BE2 are covered by the shielding electrode SSE, the shielding electrode SSE can block the influence of the environmental signal on the first node N1 and the second node N2.

[0132] Reference Figure 4 and Fig. 5F , the fifth insulating layer 50 may be disposed on the fourth insulating layer 40 to cover the second data pattern layer 150. The anode electrode layer 160 may be disposed on the fifth insulating layer 50. The anode electrode layer 160 may include, for example, metal, alloy, metal nitride, conductive metal oxide, or transparent conductive material.

[0133] The anode electrode layer 160 may include a first anode R-AE of a first light emitting element, a second anode G-AE of a second light emitting element, and a third anode B-AE of a third light emitting element. The first light emitting element outputs a first color light (e.g., red light), the second light emitting element outputs a second color light (e.g., green light), and the third light emitting element outputs a third color light (e.g., blue light). Figure 2A The light emitting element ED shown in the figure may be one of the first to third light emitting elements. Each of the first anode R-AE, the second anode G-AE, and the third anode B-AE may be connected to the corresponding pixel circuit unit PXC ( Figure 2A ).

[0134] The first light emitting element further includes a first emission layer R-EL disposed on the first anode R-AE, the second light emitting element further includes a second emission layer G-EL disposed on the second anode G-AE, and the third light emitting element further includes a third emission layer B-EL disposed on the third anode B-AE.

[0135] Figure 5G is a plan view of a display panel according to an embodiment of the present disclosure.

[0136] Reference Figure 5G The display panel DPa according to the embodiment of the present disclosure may include a first shielding electrode SSE1, a second shielding electrode SSE2, and a third shielding electrode SSE3. The first shielding electrode SSE1 may have Figure 5E and Fig. 5FThe shield electrode SSE has the same shape as shown in FIG.

[0137] The display panel DPa may further include a first-first vertical voltage line VL1-2a, a first-second vertical voltage line VL1-2b, and a first-third vertical voltage line VL1-2c. The first-first vertical voltage line VL1-2a, the first-second vertical voltage line VL1-2b, and the first-third vertical voltage line VL1-2c may be parallel to each other and may be spaced apart from each other by a predetermined gap.

[0138] In a plan view, the first shielding electrode SSE1 may be integrally formed with the first-first vertical voltage line VL1-2a and may overlap with at least one of the first emission layer R-EL, the second emission layer G-EL, and the third emission layer B-EL (e.g., the second emission layer G-EL). Figure 4 In a plan view, the second shielding electrode SSE2 may be integrally formed with the first-second vertical voltage line VL1-2b and may not overlap with the first emission layer R-EL, the second emission layer G-EL, and the third emission layer B-EL. In a plan view, the third shielding electrode SSE3 may be integrally formed with the first-third vertical voltage line VL1-2c and may not overlap with the first emission layer R-EL, the second emission layer G-EL, and the third emission layer B-EL. In a plan view, the second shielding electrode SSE2 and the third shielding electrode SSE3 may be integrally formed with the first-third vertical voltage line VL1-2c and may not overlap with the first emission layer R-EL, the second emission layer G-EL, and the third emission layer B-EL. Figure 4 The non-emitting area NPXA shown in FIG. overlaps.

[0139] In a plan view, the first shielding electrode SSE1 may have a width W1 greater than each of the width W2 of the second shielding electrode SSE2 and the width W3 of the third shielding electrode SSE3. The width W2 of the second shielding electrode SSE2 and the width W3 of the third shielding electrode SSE3 may be equal to each other or may be different from each other.

[0140] When the width W2 of the second shielding electrode SSE2 and the width W3 of the third shielding electrode SSE3 are each smaller than the width W1 of the first shielding electrode SSE1, the shielding performance may be reduced. However, the light transmittance in the non-emission area NPXA may be increased.

[0141] In which the optical sensor is arranged in the display device DD (refer to Figure 1) on the rear surface of the display panel DPa to sense light, when the widths of the shielding electrodes SSE1, SSE2, and SSE3 increase, the transmittance may decrease. When the transmittance decreases, the sensing sensitivity of the optical sensor may decrease. Therefore, in an embodiment of the present disclosure, each of the widths W2 and W3 of the second shielding electrode SSE2 and the third shielding electrode SSE3 located in the non-emission area NPXA can be adjusted to be smaller than the width W1 of the first shielding electrode SSE1 located in the emission area PXA.

[0142] Figure 6 is a circuit diagram of a pixel according to another embodiment of the present disclosure.

[0143] Reference Figure 6 , pixel PXij_a is connected to Figure 1 The j-th initialization scan line GILj among the initialization scan lines GIL1 to GILn, the j-th compensation scan line GCLj among the compensation scan lines GCL1 to GCLn, the j-th write scan line GWLj among the write scan lines GWL1 to GWLn, and the j-th black scan line GBLj among the black scan lines GBL1 to GBLn are shown in FIG. In addition, the pixel PXij_a is connected to Figure 1 The pixel PXij_a is connected to the first-jth emission control line EML1j among the first emission control lines EML11 to EML1n, and to the second-jth emission control line EML2j among the second emission control lines EML21 to EML2n.

[0144] Reference Figure 6 , the pixel PXij_a according to the embodiment includes a pixel circuit unit PXCa and a light emitting element ED. In the embodiment of the present disclosure, the pixel circuit unit PXCa may include ten transistors and two capacitors. Hereinafter, the ten transistors are referred to as a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5a, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a ninth transistor T9 and a tenth transistor T10, and the two capacitors are referred to as a first capacitor C1 and a second capacitor C2.

[0145] In this embodiment, each of the first to tenth transistors T1 to T10 is a P-type transistor having a low temperature polycrystalline silicon (LTPS) semiconductor layer. Alternatively, each of the first to tenth transistors T1 to T10 may be an N-type transistor. In another case, at least one of the first to tenth transistors T1 to T10 may be an N-type transistor, and the remaining transistors may be P-type transistors. At least one of the first to tenth transistors T1 to T10 may be a transistor having an oxide semiconductor layer. In an embodiment, for example, some of the first to tenth transistors T1 to T10 may be oxide semiconductor transistors, and the remaining transistors may be LTPS transistors.

[0146] The circuit configuration of the pixel PXij_a according to the present disclosure is almost the same as Figure 2A The circuit configuration of the pixel PXij shown in FIG. 1 is the same, and therefore repeated description will be omitted.

[0147] The pixel PXij_a may be connected to a first driving voltage line VL1, a second driving voltage line VL2, a first initialization voltage line VIL1, a second initialization voltage line VIL2, and a bias voltage line VBL. That is, Figure 6 The pixel PXij_a shown in FIG. 1 is connected to five voltage lines VL1, VL2, VIL1, VIL2 and VBL, and Figure 2A The pixel PXij shown in FIG is connected to six voltage lines VL1, VL2, VIL1, VIL2, VRL and VBL. When the number of voltage lines connected to the pixel PXij_a is reduced, the space in which the elements of the pixel circuit unit PXCa are disposed can be further ensured, and the overall light transmittance of the display panel can be increased.

[0148] The fifth transistor T5a may be electrically connected between the second node N2 and the first driving voltage line VL1. The fifth transistor T5a includes a first electrode connected to the first driving voltage line VL1, a second electrode electrically connected to the second node N2, and a third electrode receiving the jth compensation scan signal GCj through the jth compensation scan line GCLj. Figure 2B ), the fifth transistor T5a is turned on in response to the jth compensation scan signal GCj supplied to the jth compensation scan line GCLj. The first driving voltage line VL1 and the second node N2 are electrically connected through the turned-on fifth transistor T5a. That is, during the compensation periods AP4, AP5, and AP6, the first driving voltage ELVDD may be applied to the second node N2.

[0149] The tenth transistor T10 may be electrically connected between the first transistor T1 and the first driving voltage line VL1. Specifically, the tenth transistor T10 includes a first electrode electrically connected to the first driving voltage line VL1, a second electrode electrically connected to the first electrode of the first transistor T1, and a third electrode receiving the jth compensation scan signal GCj through the jth compensation scan line GCLj. During the compensation periods AP4, AP5, and AP6, the tenth transistor T10 is turned on in response to the jth compensation scan signal GCj provided to the jth compensation scan line GCLj. The first driving voltage line VL1 and the first electrode of the first transistor T1 are electrically connected through the turned-on tenth transistor T10. That is, during the compensation periods AP4, AP5, and AP6, the first driving voltage ELVDD may be applied to the first electrode of the first transistor T1.

[0150] In an embodiment of the present disclosure, the second initialization voltage line VIL2 may include: a second-first initialization voltage line VIL2-G (refer to Fig.8D ), connected to the pixel PX (refer to Figure 1 ) among the first pixel outputting the first color light (e.g., red light), the second pixel outputting the second color light (e.g., green light), and the third pixel outputting the third color light (e.g., blue light); and the second-second initialization voltage line VIL2-RB (reference Fig.8D ), connected to the remaining pixels. In an embodiment, for example, the second-first initialization voltage line VIL2-G may be connected to the second pixel, and the second-first initialization voltage may be applied to the second pixel, and the second-second initialization voltage line VIL2-RB may be connected to the first pixel and the third pixel, and the second-second initialization voltage may be applied to the first pixel and the third pixel. The second-first initialization voltage may have a voltage level different from that of the second-second initialization voltage. Since the voltage levels of the second initialization voltages for the respective pixels as described above are different from each other, the brightness difference between the pixels can be effectively improved.

[0151] Figure 7 is a cross-sectional view of a display panel according to another embodiment of the present disclosure. Specifically, Figure 7 Show Figure 6 The cross-sectional structure of part BB of the pixel PXij_a is shown in FIG. Figure 7 Among the components shown in Figure 4 The same components as those shown in FIG. 1 will be given the same reference numerals, and a detailed description thereof will be omitted.

[0152] Reference Figure 7 , the display panel DPb may include a base layer BL, a circuit layer DP_CLa and an element layer DP_ED.

[0153] The circuit layer DP_CLa is disposed on the base layer BL. The circuit layer DP_CLa includes a first semiconductor pattern, a second semiconductor pattern, and a third semiconductor pattern disposed on the base layer BL. The first semiconductor pattern to the third semiconductor pattern may include polycrystalline silicon. However, not limited thereto, in another embodiment, the first semiconductor pattern to the third semiconductor pattern may include amorphous silicon or an oxide semiconductor.

[0154] like Figure 7 As shown in , the first electrode S1, the channel portion A1, and the second electrode D1 of the first transistor T1 are formed by the first semiconductor pattern, the first electrode S2, the channel portion A2, and the second electrode D2 of the second transistor T2 are formed by the second semiconductor pattern, and the first electrode S3, the channel portion A3, and the second electrode D3 of the third transistor T3 are formed by the third semiconductor pattern. The first electrode S3 of the third transistor T3 may be connected to the second electrode D1 of the first transistor T1 and formed integrally (i.e., provided integrally).

[0155] The first insulating layer 10 (or, the gate insulating layer 10 ) is disposed on the base layer BL. In a plan view, the first insulating layer 10 overlaps the plurality of pixels PX in common and covers the first to third semiconductor patterns.

[0156] The third electrode G1 of the first transistor T1, the third electrode G2 of the second transistor T2, and the third electrode G3 of the third transistor T3 are disposed on the first insulating layer 10. The third electrode G1 of the first transistor T1 overlaps with the channel portion A1 of the first transistor T1, the third electrode G2 of the second transistor T2 overlaps with the channel portion A2 of the second transistor T2, and the third electrode G3 of the third transistor T3 overlaps with the channel portion A3 of the third transistor T3.

[0157] A first capacitor electrode C1-1 of the first capacitor C1 is additionally disposed on the first insulating layer 10. The first capacitor electrode C1-1 of the first capacitor C1 may extend from the third electrode G1 of the first transistor T1 and may be integrally formed with the third electrode G1 of the first transistor T1.

[0158] The third electrode G1 of the first transistor T1, the third electrode G2 of the second transistor T2, the third electrode G3 of the third transistor T3, and the first capacitor electrode C1-1 of the first capacitor C1 may be Fig. 8A A portion of the first gate pattern layer 120a.

[0159] The second insulating layer 20 covering the third electrode G1 of the first transistor T1 , the third electrode G2 of the second transistor T2 , the third electrode G3 of the third transistor T3 , and the first capacitor electrode C1 - 1 of the first capacitor C1 is disposed on the first insulating layer 10 .

[0160] The second capacitor electrode C1-2 of the first capacitor C1 and the third capacitor electrode C2-1 of the second capacitor C2 may be disposed on the second insulating layer 20. The second capacitor electrode C1-2 of the first capacitor C1 and the third capacitor electrode C2-1 of the second capacitor C2 may be integrally formed with each other.

[0161] The second capacitor electrode C1-2 of the first capacitor C1 faces the first capacitor electrode C1-1 of the first capacitor C1, and the second insulating layer 20 is between the second capacitor electrode C1-2 of the first capacitor C1 and the first capacitor electrode C1-1 of the first capacitor C1 to form the first capacitor C1. The second capacitor electrode C1-2 of the first capacitor C1 and the third capacitor electrode C2-1 of the second capacitor C2 may be Figure 8B In the embodiment of the present disclosure, in a plan view, the third capacitor electrode C2-1 of the second capacitor C2 may overlap the first capacitor electrode C1-1 of the first capacitor C1.

[0162] An additional insulating layer 25 covering the second capacitor electrode C1-2 of the first capacitor C1 is disposed on the second insulating layer 20. In this embodiment, the additional insulating layer 25 may be a single silicon oxide layer.

[0163] The fourth capacitor electrode C2-2 of the second capacitor C2 may be disposed on the additional insulating layer 25. The fourth capacitor electrode C2-2 of the second capacitor C2 faces the third capacitor electrode C2-1 of the second capacitor C2, and the additional insulating layer 25 is between the fourth capacitor electrode C2-2 of the second capacitor C2 and the third capacitor electrode C2-1 of the second capacitor C2 to form the second capacitor C2. The fourth capacitor electrode C2-2 of the second capacitor C2 may be Figure 8C A portion of the additional pattern layer 135a is shown in FIG. In an embodiment of the present disclosure, in a plan view, the fourth capacitor electrode C2-2 of the second capacitor C2 may overlap the second capacitor electrode C1-2 of the first capacitor C1.

[0164] The first bridge electrode BE1a and the second bridge electrode BE2a are disposed on the third insulating layer 30. The first bridge electrode BE1a may be an electrode connecting the first capacitor electrode C1-1 of the first capacitor C1 and the second electrode D3 of the third transistor T3, and the second bridge electrode BE2a may be an electrode connecting the second capacitor electrode C1-2 of the first capacitor C1 and the second electrode D2 of the second transistor T2. The first bridge electrode BE1a is connected to the first capacitor electrode C1-1 of the first capacitor C1 through a contact hole penetrating the second insulating layer 20, the additional insulating layer 25, and the third insulating layer 30, and is connected to the second electrode D3 of the third transistor T3 through a contact hole penetrating the first insulating layer 10, the second insulating layer 20, the additional insulating layer 25, and the third insulating layer 30. The second bridging electrode BE2a is connected to the second capacitor electrode C1-2 of the first capacitor C1 through a contact hole penetrating the additional insulating layer 25 and the third insulating layer 30, and is connected to the second electrode D2 of the second transistor T2 through a contact hole penetrating the first insulating layer 10, the second insulating layer 20, the additional insulating layer 25 and the third insulating layer 30.

[0165] A first connection electrode CE1a and a second connection electrode CE2a are additionally disposed on the third insulating layer 30. The first connection electrode CE1a is an electrode for connecting the fourth capacitor electrode C2-2 of the second capacitor C2 to the first driving voltage line VL1, and the second connection electrode CE2a is an electrode for connecting the first electrode S2 of the second transistor T2 to the data line (i.e., the i-th data line DLi).

[0166] The first connection electrode CE1a is connected to the fourth capacitor electrode C2-2 of the second capacitor C2 through a contact hole penetrating the third insulating layer 30, and the second connection electrode CE2a is connected to the first electrode S2 of the second transistor T2 through a contact hole penetrating the first insulating layer 10, the second insulating layer 20, the additional insulating layer 25 and the third insulating layer 30.

[0167] The first and second bridge electrodes BE1a and BE2a and the first and second connection electrodes CE1a and CE2a may be Fig.8D A portion of the first data pattern layer 140a is shown in FIG.

[0168] The fourth insulating layer 40 is disposed to cover the first and second bridging electrodes BE1a and BE2a and the first and second connecting electrodes CE1a and CE2a. The first driving voltage line VL1, the i-th data line DLi, and the shielding electrode SSEa may be disposed on the fourth insulating layer 40. The shielding electrode SSEa may be integrally formed with the first driving voltage line VL1. The first driving voltage line VL1 and the shielding electrode SSEa may be spaced apart from the i-th data line DLi. The first driving voltage line VL1, the i-th data line DLi, and the shielding electrode SSEa may be Fig. 8E A portion of the second data pattern layer 150a is shown in FIG.

[0169] The first driving voltage line VL1 is connected to the first link electrode CE1 a through a contact hole formed through the fourth insulating layer 40 , and the i th data line DLi is connected to the second link electrode CE2 a through a contact hole formed through the fourth insulating layer 40 .

[0170] The shielding electrode SSEa may be disposed on the first bridging electrode BE1a and the second bridging electrode BE2a, and may overlap the first capacitor electrode C1-1, the second capacitor electrode C1-2, the third capacitor electrode C2-1, and the fourth capacitor electrode C2-2, and the first transistor T1, the second transistor T2, and the third transistor T3. In a plan view, the shielding electrode SSEa may overlap the first connection electrode CE1a and the first bridging electrode BE1a and the second bridging electrode BE2a. In the present disclosure, the first bridging electrode BE1a may overlap Figure 6 The first node N1 shown in FIG. 1 corresponds to the first node N1, and the second bridge electrode BE2a can be connected to Figure 6 The first node N1 and the second node N2 may have a low level period (ie, a light emitting period) during the second-jth light emitting control signal EM2j (refer to Figure 2B ) is in a floating state. When the first node N1 and the second node N2 are in a floating state, the potentials of the first node N1 and the second node N2 may be easily oscillated by an environmental signal (e.g., a data signal applied to an adjacent data line (e.g., the (i+1)th data line)). However, the first bridging electrode BE1a and the second bridging electrode BE2a may be covered by the shielding electrode SSEa, and thus the shielding electrode SSEa may block the influence of the environmental signal on the first node N1 and the second node N2.

[0171] A fifth insulating layer 50 covering the first driving voltage line VL1 , the i th data line DLi, and the shielding electrode SSEa is disposed on the fourth insulating layer 40 .

[0172] The device layer DP_ED is disposed on the circuit layer DP_CLa. Figure 4A repeated description of the component layer DP_ED that is identical to the component layer DP_ED is given.

[0173] FIG. 8A to FIG. 8G is a plan view showing the layout of layers stacked in a display panel. Specifically, Fig. 8A is a plan view showing a semiconductor pattern layer and a first gate pattern layer provided on a base layer, and Figure 8B is a plan view showing a second gate pattern layer disposed on the first gate pattern layer. Figure 8C is a plan view showing an additional pattern layer disposed on the second gate pattern layer, and Fig.8D is a plan view showing a first data pattern layer disposed on an additional pattern layer. Fig. 8E and Fig.8F is a plan view showing a second data pattern layer disposed on the first data pattern layer. Figure 8G is a plan view showing an anode electrode layer provided on the second data pattern layer.

[0174] Reference Fig. 8A , the semiconductor patterns and the conductive patterns may be repeatedly arranged on the base layer BL according to a predetermined rule. FIG. 8A to FIG. 8G Three pixel circuit units PXCa are shown in FIG. Figure 6 )’s floor plan.

[0175] Reference Figure 7 and Fig. 8A , a semiconductor pattern layer 110a is shown. The semiconductor pattern layer 110a may be disposed on the base layer BL. The semiconductor pattern layer 110a may include low temperature polysilicon (LTPS).

[0176] The semiconductor pattern layer 110a is included in each pixel circuit unit PXCa (refer to Figure 6 ) included in the transistor (ie, the first transistor T1 to the tenth transistor T10 (refer to Figure 6 The first insulating layer 10 may be disposed on the semiconductor pattern layer 110 a , and the first gate pattern layer 120 a may be disposed on the first insulating layer 10 .

[0177] The first gate pattern layer 120a may include a third electrode of a transistor (ie, first to tenth transistors T1 to T10) included in each pixel circuit unit PXCa. The first to tenth transistors T1 to T10 may be provided in each pixel circuit unit PXCa through the first gate pattern layer 120a and the semiconductor pattern layer 110a.

[0178] The first gate pattern layer 120 a may further include a first capacitor electrode C1 - 1 of a first capacitor C1 included in each pixel circuit unit PXCa.

[0179] Reference Figure 7 and Figure 8B The second insulating layer 20 may be disposed on the first insulating layer 10 to cover the first gate pattern layer 120 a. The second gate pattern layer 130 a may be disposed on the second insulating layer 20 .

[0180] The second gate pattern layer 130a may include a second capacitor electrode C1-2 of the first capacitor C1 and a third capacitor electrode C2-1 of the second capacitor C2. The first capacitor C1 may be formed in each pixel circuit unit PXCa (refer to FIG. 1 ) by the first gate pattern layer 120a and the second gate pattern layer 130a. Figure 6 )middle.

[0181] Reference Figure 7 and Figure 8C , an additional insulating layer 25 may be disposed on the second insulating layer 20 to cover the second gate pattern layer 130a (refer to Figure 8B ). The additional pattern layer 135a may be disposed on the additional insulating layer 25. The additional pattern layer 135a may include a metal, an alloy, a metal nitride, a conductive metal oxide, or a transparent conductive material.

[0182] The additional pattern layer 135a may include a fourth capacitor electrode C2-2 of the second capacitor C2. The second capacitor C2 may be formed in each pixel circuit unit PXCa (refer to Figure 6 ). The additional pattern layer 135a may further include a plurality of repair lines RPL. The plurality of repair lines RPL may be provided to repair lines (eg, scan lines and emission control lines) provided on the display panel DPb.

[0183] Reference Figure 7 and Fig.8D , the additional insulating layer 25 may be disposed on the third insulating layer 30 to cover the additional pattern layer 135a (refer to Figure 8C ). The first data pattern layer 140 a may be disposed on the third insulating layer 30 .

[0184] The first data pattern layer 140a may include scan lines GWLj, GCLj, GILj, and GBLj (refer to Figure 6 ), light emitting control lines EML1j and EML2j (refer to Figure 6 ), a second-first initialization voltage line VIL2-G, a second-second initialization voltage line VIL2-RB and a bias voltage line VBL. The first data pattern layer 140a may further include Figure 7 Shown are first and second bridge electrodes BE1a and BE2a and first and second connection electrodes CE1a and CE2a.

[0185] The first bridge electrode BE1a may be an electrode connecting the first capacitor electrode C1-1 of the first capacitor C1 and the second electrode D3 of the third transistor T3, and the second bridge electrode BE2a may be an electrode connecting the second capacitor electrode C1-2 of the first capacitor C1 and the second electrode D2 of the second transistor T2. The first bridge electrode BE1a is connected to the first capacitor electrode C1-1 of the first capacitor C1 through a contact hole penetrating the second insulating layer 20, the additional insulating layer 25, and the third insulating layer 30, and is connected to the second electrode D2 of the third transistor T3 through a contact hole penetrating the first insulating layer 10, the second insulating layer 20, the additional insulating layer 25, and the third insulating layer 30. The second bridge electrode BE2a is connected to the second capacitor electrode C1-2 of the first capacitor C1 through a contact hole penetrating the additional insulating layer 25 and the third insulating layer 30, and is connected to the second electrode D2 of the second transistor T2 through a contact hole penetrating the first insulating layer 10, the second insulating layer 20, the additional insulating layer 25, and the third insulating layer 30.

[0186] Reference Figure 7 , Fig. 8E and Fig.8F , also refer to Fig.8D The fourth insulating layer 40 may be disposed on the third insulating layer 30 to cover the first data pattern layer 140 a. The second data pattern layer 150 a may be disposed on the fourth insulating layer 40 .

[0187] The second data pattern layer 150 a may include data lines DLi- 1 , DLi, and DLi+1, a first driving voltage line VL1 , and a second driving voltage line VL2 .

[0188] The second data pattern layer 150a may further include a shielding electrode SSEa extending from the first driving voltage line VL1. The shielding electrode SSEa may extend from the first driving voltage line VL1 and may be integrally formed (i.e., integrally provided) with the first driving voltage line VL1. In a plan view, the shielding electrode SSEa may extend from the first driving voltage line VL1 to overlap the first bridging electrode BE1a and the second bridging electrode BE2a of the first data pattern layer 140a.

[0189] Since the first bridge electrode BE1a and the second bridge electrode BE2a are covered by the shielding electrode SSEa, the shielding electrode SSEa can block the influence of the environmental signal on the first node N1 and the second node N2.

[0190] Reference Figure 7 and Figure 8G, the fifth insulating layer 50 may be disposed on the fourth insulating layer 40 to cover the second data pattern layer 150a. The anode electrode layer 160a may be disposed on the fifth insulating layer 50. The anode electrode layer 160a may include, for example, metal, alloy, conductive metal oxide, or transparent conductive material.

[0191] The anode electrode layer 160a may include a first anode R-AE of a first light emitting element, a second anode G-AE of a second light emitting element, and a third anode B-AE of a third light emitting element. The first light emitting element outputs a first color light (e.g., red light), the second light emitting element outputs a second color light (e.g., green light), and the third light emitting element outputs a third color light (e.g., blue light). Figure 6 The light emitting element ED shown in the figure may be one of the first to third light emitting elements. Each of the first anode R-AE, the second anode G-AE, and the third anode B-AE may be connected to the corresponding pixel circuit unit PXCa ( Figure 6 ).

[0192] The first light emitting element further includes a first emission layer R-EL disposed on the first anode R-AE, the second light emitting element further includes a second emission layer G-EL disposed on the second anode G-AE, and the third light emitting element further includes a third emission layer B-EL disposed on the third anode B-AE.

[0193] Fig. 9 is a plan view of a display panel according to an embodiment of the present disclosure, and Fig.10 is a cross-sectional view of a display panel according to another embodiment of the present disclosure. Fig. 9 and Fig.10 Among the components shown in Figure 7 and Figure 8G The same components as those shown in FIG. 1 will be given the same reference numerals, and a detailed description thereof will be omitted.

[0194] Reference Fig. 9 and Fig.10 The display panel DPc according to the embodiment of the present disclosure may include a first shielding electrode SSE1a, a second shielding electrode SSE2a, and a third shielding electrode SSE3a. Each of the first shielding electrode SSE1a, the second shielding electrode SSE2a, and the third shielding electrode SSE3a may have a width less than Fig. 8E and Figure 8G The area of ​​the shield electrode SSEa shown in .

[0195] The display panel DPc may further include first-first, second and third driving voltage lines VL1a, VL1b and VL1c. The first-first, second and third driving voltage lines VL1a, VL1b and VL1c may be parallel to each other and may be spaced apart from each other.

[0196] In a plan view, the first shielding electrode SSE1a may be integrally formed with the first-first driving voltage line VL1a, and may overlap with at least one of the first emission layer R-EL, the second emission layer G-EL, and the third emission layer B-EL (e.g., the second emission layer G-EL). Figure 7 In a plan view, the first shielding electrode SSE1a may include: Fig. 9 The first portion overlaps the emission area PXA and the second portion overlaps the non-emission area NPXA as shown in FIG. , and a width w1a of the second portion may be smaller than a width w2a of the first portion.

[0197] In a plan view, the second shielding electrode SSE2a may be integrally formed with the first-second driving voltage line VL1b and may not overlap with the first emission layer R-EL, the second emission layer G-EL, and the third emission layer B-EL. In a plan view, the third shielding electrode SSE3a may be integrally formed with the first-third driving voltage line VL1c and may not overlap with the first emission layer R-EL, the second emission layer G-EL, and the third emission layer B-EL. In a plan view, the second shielding electrode SSE2a and the third shielding electrode SSE3a may overlap with the non-emission area NPXA.

[0198] In a plan view, the area where the second shielding electrode SSE2a and the third shielding electrode SSE3a overlap with the non-emission area NPXA is larger than the area where the first shielding electrode SSE1a overlaps with the non-emission area NPXA. Therefore, in order to improve the transmittance, the area of ​​the second shielding electrode SSE2a and the third shielding electrode SSE3a can be designed to be smaller than the area of ​​the first shielding electrode SSE1a. Therefore, the transmittance in the non-emission area NPXA can be increased.

[0199] However, if Fig. 9 As shown in FIG. 1 , the first shielding electrode SSE1a, the second shielding electrode SSE2a, and the third shielding electrode SSE3a may be provided to cover the contact portions (i.e., contact holes) of the first and second bridge electrodes BE1a and BE2a and the first connection electrode CE1a. Figure 6) is in a floating state, the first shielding electrode SSE1a, the second shielding electrode SSE2a and the third shielding electrode SSE3a can perform a shielding function and thus are not affected by environmental signals.

[0200] According to the present disclosure, the display device includes a shielding electrode capable of shielding a first node and a second node of each pixel, thereby solving the problem of picture quality degradation caused by the influence of an environmental signal on the first node and the second node.

[0201] While the present disclosure has been described with reference to the embodiments thereof, it will be apparent to one of ordinary skill in the art that various changes and modifications can be made therein without departing from the spirit and scope of the present disclosure as set forth in the appended claims.

Claims

1. A display device, characterized in that: The display device comprises: A display panel includes a light emitting element and a pixel circuit unit connected to the light emitting element. Wherein, the pixel circuit unit comprises: a first transistor connected between the driving voltage line and the light emitting element, and configured to operate according to a potential of a first node; a second transistor connected between the data line and the second node; a first capacitor electrode electrically connected to the first node; a second capacitor electrode electrically connected to the second node, and the second capacitor electrode is configured to face the first capacitor electrode to form a first capacitor with the first capacitor electrode; a third capacitor electrode electrically connected to the second node; a fourth capacitor electrode electrically connected to the driving voltage line, and the fourth capacitor electrode is configured to face the third capacitor electrode to form a second capacitor with the third capacitor electrode; a bridging electrode configured to electrically connect the second capacitor electrode and the third capacitor electrode; and A shielding electrode is disposed on the bridge electrode, and the shielding electrode is configured to overlap with the bridge electrode in a plan view.

2. The display device according to claim 1, characterized in that The bridge electrode and the shielding electrode are disposed on different layers from each other.

3. The display device according to claim 2, characterized in that: The shielding electrode is electrically connected to the fourth capacitor electrode, and The shielding electrode and the driving voltage line are disposed on the same layer, and the shielding electrode extends from the driving voltage line.

4. The display device according to claim 1, characterized in that The bridge electrode is connected to the second capacitor electrode and the third capacitor electrode through a plurality of contact holes.

5. The display device according to claim 4, characterized in that: In the plan view, the shielding electrode is disposed to cover the plurality of contact holes.

6. The display device according to claim 1, characterized in that: The display panel further includes a connection electrode configured to connect the driving voltage line and the fourth capacitor electrode.

7. The display device according to claim 6, characterized in that: The bridge electrode and the connection electrode are provided on the same layer.

8. The display device according to claim 1, characterized in that: The display panel includes an emission area and a non-emission area, the emission area is configured to overlap with the emission layer of the light emitting element, the non-emission area is adjacent to the emission area, and Wherein, the shielding electrode comprises: A first shielding electrode configured to overlap the emitting region; and The second shielding electrode is configured to overlap the non-emitting area.

9. The display device according to claim 8, characterized in that: In the plan view, the second shielding electrode has a width smaller than a width of the first shielding electrode.

10. A display device, characterized in that: The display device comprises: A display panel includes a light emitting element and a pixel circuit unit connected to the light emitting element. Wherein, the pixel circuit unit comprises: a first transistor connected between the driving voltage line and the light emitting element, and configured to operate according to a potential of a first node; a second transistor connected between the data line and the second node; a first capacitor electrode connected to the first node; a second capacitor electrode and a third capacitor electrode connected to the second node, and the second capacitor electrode and the third capacitor electrode are configured to face the first capacitor electrode to form a first capacitor with the first capacitor electrode, wherein the second capacitor electrode and the third capacitor electrode are provided integrally with each other; a fourth capacitor electrode configured to face the third capacitor electrode to form a second capacitor with the third capacitor electrode, wherein the fourth capacitor electrode is connected to the driving voltage line; a bridge electrode configured to electrically connect the second capacitor electrode and the second transistor; and A shielding electrode is provided on the bridge electrode, and the shielding electrode is configured to partially overlap the second capacitor electrode and the second transistor in a plan view.

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