Grid-connected inverter overcurrent protection circuit and grid-connected inverter

Abstract

The embodiment of the utility model relates to the technical field of inverters, and relates to a grid-connected inverter overcurrent protection circuit and a grid-connected inverter, and the grid-connected inverter overcurrent protection circuit comprises a digital signal trigger module, an AND gate circuit and an overcurrent detection module. The over-current detection module is used for detecting the input current and the output current of each path of the inverter, and the over-current detection module generates a falling edge signal under the condition that any path of the input current or the output current is over-current; the first input end of the AND gate circuit is electrically connected with the output end of the overcurrent detection module; the digital signal triggering module is electrically connected with the output end of the AND gate circuit, and under the condition that the AND gate circuit outputs a falling edge signal, the digital signal triggering module outputs a driving wave sealing signal for turning off driving. The overcurrent protection circuit has the effect of reducing the response time of the overcurrent protection circuit.

Description

Technical Field

[0001] The present application relates to the technical field of inverters, and in particular to an overcurrent protection circuit for a grid-connected inverter and a grid-connected inverter. Background Art

[0002] The inverter overcurrent protection circuit is used to ensure the safe, reliable and stable operation of the inverter and prevent damage to the inverter caused by excessive current. Specifically, when the inverter output current exceeds the rated value, the overcurrent protection circuit will automatically cut off the power supply to protect the inverter from damage caused by excessive current; when the current exceeds the safe range, the overcurrent protection circuit can take timely measures according to the size of the current to prevent the occurrence of faults such as short circuit and overload, thereby protecting the stable operation of the power system, reducing the possibility of damage to the inverter due to overcurrent, and improving the service life and reliability of the inverter.

[0003] In the design of overcurrent protection circuit, each current is usually protected independently by adding a hysteresis comparator through an operational amplifier. The protection action and recovery action are generated by the hysteresis comparator, and the DSP is triggered to block the drive and restore the drive by setting the hysteresis interval.

[0004] However, the inventors have realized that in this overcurrent protection circuit, the control circuit design is complex and occupies more DSP resources. When an overcurrent occurs in a single path in each independent protection, the input and output drives cannot be cut off at the same time, resulting in a long response time. Summary of the invention

[0005] One or more embodiments of the present application provide a grid-connected inverter overcurrent protection circuit and a grid-connected inverter to solve or at least partially alleviate the problem of long response time of the overcurrent protection circuit in the related art.

[0006] In a first aspect of the present application, there is provided a grid-connected inverter overcurrent protection circuit, comprising a digital signal trigger module, an AND gate circuit and an overcurrent detection module;

[0007] The overcurrent detection module is used to detect the input current and output current of each path of the inverter. When an overcurrent occurs in any input current or output current, the overcurrent detection module generates a falling edge signal;

[0008] The first input terminal of the AND gate circuit is electrically connected to the output terminal of the overcurrent detection module;

[0009] The digital signal trigger module is electrically connected to the output end of the AND gate circuit. When the AND gate circuit outputs a falling edge signal, the digital signal trigger module outputs a driving wave envelope signal for shutting off the driving.

[0010] The above technical solution, the present application monitors the input and output currents of each inverter through an overcurrent detection module, and integrates them into a current signal. When an overcurrent occurs in a certain input or output of the inverter, the overcurrent detection module can capture and generate a falling edge signal. After being processed by the AND gate circuit, a falling edge signal is generated synchronously and output to the digital signal trigger module as an abnormal signal. Then, a driving wave blocking signal is generated by the digital signal trigger module to cut off the driving voltage, thereby ensuring the stable operation of the overcurrent protection circuit. This design eliminates the hysteresis circuit of the operational amplifier and reduces the number of DSP ports used. Through simple wave blocking logic, the input and output current protection circuits are integrated to achieve a rapid response to overcurrent conditions.

[0011] In one of the embodiments, the grid-connected inverter overcurrent protection circuit also includes a digital signal reset module, the output end of the digital signal reset module is electrically connected to the second input end of the AND gate circuit, and the digital signal reset module is used to receive a reset signal and transmit a reset protection signal to the AND gate circuit according to the reset signal.

[0012] In one embodiment, the digital signal reset module includes a first transistor, wherein the first end of the first transistor is used to receive the reset signal; the second end of the first transistor is electrically connected to a reference power supply; when the first end receives the reset signal, the first transistor is cut off, and the reset protection signal is generated at the third end of the first transistor and output to the AND gate circuit.

[0013] In one embodiment, the digital signal reset module further includes a first resistor, and two ends of the first resistor are respectively connected to the first end and the second end of the first transistor.

[0014] In one embodiment, the first transistor is a PNP transistor, the first end is a base, the second end is an emitter, and the third end is a collector.

[0015] In one of the embodiments, the grid-connected inverter overcurrent protection circuit also includes a drive enable module, the output end of the drive enable module is used to be electrically connected to the third input end of the AND gate circuit, so that the output end of the drive enable module outputs a drive protection signal to the AND gate circuit.

[0016] In one embodiment, the digital signal trigger module includes a second transistor, a first end of the second transistor is electrically connected to the output end of the gate circuit; a second end is grounded; and a third end is used to be electrically connected to a digital signal processor.

[0017] In one embodiment, the digital signal trigger module further includes a second resistor, one end of the second resistor is electrically connected to a reference power supply, and the other end of the second resistor is electrically connected to the third end of the second transistor.

[0018] In one embodiment, the second transistor is an NPN transistor, the first end is a base, the second end is an emitter, and the third end is a collector.

[0019] On the other hand, one or more embodiments of the present application also provide a grid-connected inverter, including an inverter and the grid-connected inverter overcurrent protection circuit as described above, wherein the input and output ends of the inverter are electrically connected to the grid-connected inverter overcurrent protection circuit.

[0020] The beneficial effects of the grid-connected inverter relative to the prior art are the same as those of the grid-connected inverter overcurrent protection circuit, which will not be described in detail here. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present application, rather than limiting the present application.

[0022] Figure 1 A system block diagram of an overcurrent protection circuit for a grid-connected inverter according to some embodiments of the present application.

[0023] Figure 2 A circuit diagram of an overcurrent protection circuit for a grid-connected inverter according to some embodiments of the present application.

[0024] Figure 3 Another system block diagram of a grid-connected inverter overcurrent protection circuit according to some embodiments of the present application. DETAILED DESCRIPTION

[0025] In order to make the purpose, technical solutions and advantages of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the accompanying drawings showing multiple embodiments of the present application. It should be understood that the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments described in the present application, all other embodiments obtained by ordinary technicians in this field without spending creative work will fall within the scope of protection of the present application.

[0026] Unless otherwise defined, all technical and scientific terms used in this application have the same meaning as those generally understood by technicians in the technical field of this application; the terms used in the specification of the application are only for the purpose of describing specific implementation methods, and are not intended to limit this application; the terms "including", "comprising", "having", "having", "containing", "including", etc. in the specification and claims of this application and the above-mentioned figure description are open-ended words. Therefore, "including", "comprising", "having" is a method or device with one or more steps or elements, for example, which has one or more steps or elements, but is not limited to having only these one or more elements. The terms "first", "second", etc. in the specification and claims of this application or the above-mentioned figures are used to distinguish different objects, rather than to describe a specific order or a primary and secondary relationship. In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of this application, unless otherwise specified, the meaning of "multiple" is two or more.

[0027] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", and "attached" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a direct connection, or an indirect connection through an intermediate medium, or it can be the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0028] Reference to "embodiment" in this application means that a particular feature, structure, or characteristic described in conjunction with the embodiment may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described in this application may be combined with other embodiments.

[0029] As mentioned above, it should be emphasized that when the term "includes / comprising" is used in this specification, it is used to clearly indicate the presence of the features, integers, steps or components, but does not exclude the presence or addition of one or more other features, integers, steps, components or groups of features, integers, steps, components. As used in this application, the singular forms "a", "an" and "the" also include plural forms, unless the context clearly indicates otherwise.

[0030] The words "a" and "an" in this specification may mean one, but may also have the same meaning as "at least one" or "one or more". The term "or" used in the claims means "and / or" unless it is clearly stated that it refers to only alternative solutions.

[0031] The term "and / or" in this application is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this application generally indicates that the associated objects before and after are in an "or" relationship.

[0032] Figure 1 A system block diagram of an overcurrent protection circuit for a grid-connected inverter according to some embodiments of the present application; Figure 2 A circuit diagram of an overcurrent protection circuit for a grid-connected inverter according to some embodiments of the present application.

[0033] like Figure 1 and Figure 2 As shown, one or more embodiments of the present application disclose a grid-connected inverter overcurrent protection circuit, including a digital signal trigger module, an AND gate circuit and an overcurrent detection module;

[0034] The overcurrent detection module is used to detect the input current and output current of each circuit of the inverter. When an overcurrent occurs in any input current or output current, the inverter generates an overcurrent signal (BlockInv) and generates a falling edge signal through the overcurrent detection module.

[0035] Specifically, overcurrent protection design is crucial to ensure the safety of inverter products and personnel. Overcurrent protection can be divided into DC overcurrent protection on the input side and AC overcurrent protection on the output side. When overcurrent occurs on the input or output side, the drive signal must be terminated in time through the overcurrent protection circuit to prevent the current from damaging the inverter components or causing harm to the human body.

[0036] In at least one embodiment, the inverter has multiple input and output functions, and each input and output may have overcurrent during operation. In this embodiment, the overcurrent detection module includes multiple current detection devices, and current detection devices are set in each input and output circuit of the inverter. When no overcurrent is detected, the current detection device outputs a normal high level; once the current detection device captures that the current of a certain path exceeds the preset threshold, that is, when an overcurrent condition occurs, the current detection device outputs a low level and generates a falling edge, that is, at this time, a falling edge is generated in the overcurrent detection module, and one output becomes a low level, thereby notifying the overcurrent protection circuit to achieve a rapid response to the overcurrent phenomenon.

[0037] The first input end of the AND gate circuit is electrically connected to the output end of the overcurrent detection module.

[0038] In at least one embodiment, the first input end of the AND gate circuit is electrically connected to the output end of the overcurrent detection module to receive a digital signal from the overcurrent detection module. When the overcurrent detection module does not detect an overcurrent condition, it outputs a normal high level, and the output end of the AND gate circuit synchronously outputs a high level. When the overcurrent detection module detects an overcurrent condition, the current detection module of the overcurrent path generates a falling edge, which is input to the AND gate circuit. When the input end of the AND gate circuit receives any falling edge, the output end of the AND gate circuit synchronously outputs a falling edge, that is, an abnormal signal, to notify the digital signal trigger module that an overcurrent phenomenon occurs in the inverter.

[0039] The digital signal trigger module is electrically connected to the output end of the AND gate circuit. When the AND gate circuit outputs a falling edge signal, the digital signal trigger module outputs a driving enveloping wave signal (PWM-OE) for shutting down the driving.

[0040] In at least one embodiment, the digital signal trigger module is a DSP trigger module, and its main function is to monitor the circuit with overcurrent in real time during the operation of the inverter. Once an overcurrent phenomenon is detected in any circuit, the AND gate circuit will generate an abnormal signal, triggering the digital signal trigger module to generate a drive wave sealing signal. This drive wave sealing signal is a high-level signal, which can stop the inverter from working and disconnect the connection with the power grid by turning off the drive voltage, thereby avoiding damage to the IGBT tube caused by large current. When the inverter is operating normally, the AND gate circuit will normally output a high-level signal, and the digital signal trigger module will not generate a drive wave sealing signal.

[0041] This embodiment uses an overcurrent detection module to monitor the input and output currents of the inverter and integrate them into a current signal. When an overcurrent occurs in a certain input or output of the inverter, the overcurrent detection module can capture and generate a falling edge signal. After being processed by the AND gate circuit, a falling edge signal is synchronously generated and output to the digital signal trigger module as an abnormal signal. Then, a driving wave blocking signal is generated by the digital signal trigger module to cut off the driving voltage to ensure the stable operation of the overcurrent protection circuit. This design eliminates the hysteresis circuit of the operational amplifier and reduces the number of DSP ports used. Through simple wave blocking logic, the input and output current protection circuits are integrated to achieve a rapid response to overcurrent conditions.

[0042] Figure 3 Another system block diagram of a grid-connected inverter overcurrent protection circuit according to some embodiments of the present application.

[0043] In some embodiments, Figure 3As shown, the grid-connected inverter overcurrent protection circuit also includes a digital signal reset module, the output end of the digital signal reset module is electrically connected to the second input end of the AND gate circuit, and the digital signal reset module is used to receive a reset signal (PWM-RESET) and transmit a reset protection signal to the AND gate circuit according to the reset signal.

[0044] In at least one embodiment, the grid-connected inverter overcurrent protection circuit also includes a digital signal reset module, which is responsible for generating a reset protection signal. In this embodiment, the input end of the digital signal reset module is electrically connected to a digital signal processor (DSP). When the digital signal processor is restarted or receives a reset instruction issued by a user, a DSP reset signal will be generated. The second input end of the AND gate circuit is electrically connected to the output end of the digital signal reset module, and its function is to generate a reset protection signal and output it to the AND gate circuit when receiving the reset signal. When the digital signal reset module does not input the DSP reset signal, its input end is a low level, and the digital signal reset module can normally generate a high level. When the digital signal reset module receives a high-level DSP reset signal, a falling edge signal will be generated and converted to a low level, thereby generating a reset protection signal. In addition, when the AND gate circuit receives a falling edge signal from any one of the overcurrent detection modules, or a falling edge signal generated by the digital signal reset module, a falling edge signal will be generated and output to the digital signal trigger module as an abnormal signal. The digital signal trigger module outputs a drive sealing signal to realize the shutdown drive, ensuring that the inverter can be shut down and connected to the grid when the DSP is reset, thereby protecting the inverter components from damage and ensuring the safety of operators.

[0045] In some embodiments, the digital signal reset module includes a first transistor, wherein the first end of the first transistor is used to receive the reset signal; the second end of the first transistor is electrically connected to a reference power supply; when the first end receives the reset signal, the first transistor is cut off, and the reset protection signal is generated at the third end of the first transistor and output to the AND gate circuit.

[0046] like Figure 2 As shown, for the sake of clear description, the first transistor is marked as Q1, the first end is marked as 1, the second end is marked as 2, and the third end is marked as 3, wherein the second end of the first transistor is electrically connected to a reference power supply, the reference voltage of the reference power supply is a DC voltage of 3.3V, the first end is electrically connected to a digital signal processor (DSP) for receiving a reset signal, and the third end is electrically connected to an AND gate circuit. When the first end receives the reset signal, the transistor is cut off, and the third end generates a low-level reset protection signal, thereby causing the gate circuit to output an abnormal signal, and outputting a drive sealing wave signal through the digital signal trigger module.

[0047] In some embodiments, the first transistor is a PNP transistor, the first end is a base, the second end is an emitter, and the third end is a collector.

[0048] In some embodiments, the digital signal reset module further includes a first resistor, and two ends of the first resistor are respectively connected to the first end and the second end of the first transistor.

[0049] The digital signal reset module also includes a first resistor, which is connected in parallel with the first end and the second end of the first transistor, and is used to cut off the first transistor when a high-level reset signal is input to the first end, and keep the first transistor turned on when the input to the first end is restored to a low-level signal.

[0050] like Figure 2 As shown, for the sake of clear description, the first resistor is marked as R1, and the first resistor is connected in parallel with the first end and the second end of the first transistor. When the digital signal reset module does not receive the DSP reset signal, the first transistor is in the on state, the third end normally outputs a high level, and the AND gate circuit has no abnormal signal output; when the digital signal reset module receives a high-level DSP reset signal, there is no conduction voltage drop between the second end and the third end, the second end is turned off, the third end generates a falling edge, and the output becomes a low level, that is, the third end generates a reset protection signal and transmits it to the AND gate circuit, and the AND gate circuit synchronously outputs a falling edge signal. After receiving this falling edge signal, the digital signal trigger module generates a low-level abnormal signal, and then outputs a high-level drive wave signal.

[0051] In some embodiments, the grid-connected inverter overcurrent protection circuit also includes a drive enable module, the output end of the drive enable module is used to be electrically connected to the third input end of the AND gate circuit, so that the output end of the drive enable module outputs a drive protection signal to the AND gate circuit.

[0052] like Figure 2 and Figure 3 As shown, the grid-connected inverter overcurrent protection circuit also includes a drive enable module, which is used to generate a drive enable signal (M-DriPWM-EN). When the drive enable signal changes from a high level to a low level, a falling edge signal is generated. The falling edge signal is transmitted to the AND gate circuit as a drive protection signal, which can make the output of the AND gate circuit change from a high level to a low level, thereby generating an abnormal signal of a falling edge, and transmitting it to the digital signal trigger module, thereby causing the digital signal trigger module to output a high-level drive wave signal.

[0053] In some embodiments, the digital signal trigger module includes a second transistor, a first end of the second transistor is electrically connected to the output end of the gate circuit; a second end is grounded; and a third end is used to be electrically connected to a digital signal processor.

[0054] like Figure 2 As shown, the first end of the second transistor is used to receive the abnormal signal from the AND gate circuit; when the first end receives the abnormal signal, the second transistor changes from the on state to the off state; the third end is used as an output end, which is electrically connected to the digital signal processor and connected to the reference voltage at the same time. When the second transistor is in the on state, the connection node between the third end and the digital signal processor is at a low level, and when the second transistor is in the off state, the connection node between the third end and the digital signal processor is at a high level, that is, the digital signal trigger module outputs a high-level driving sealing wave signal.

[0055] In some embodiments, the second transistor is an NPN transistor, the first end is a base, the second end is an emitter, and the third end is a collector.

[0056] The digital signal trigger module includes a second transistor. For a clear description, in the circuit, the second transistor is marked as Q2, the first end is marked as 4, the second end is marked as 5, and the third end is marked as 6. Under normal circumstances, that is, when the AND gate circuit does not output a low-level abnormal signal, the first end receives a high-level signal from the AND gate circuit, and the third end receives a reference voltage, so that the transistor is turned on. However, when the AND gate circuit does not output a low-level abnormal signal, the first end receives a low-level abnormal signal from the AND gate circuit, causing the transistor to be cut off. At this time, since the third end is electrically connected to the reference voltage, the connection node (i.e., the signal output node) between the third end and the digital signal processor generates a high-level drive wave signal to shut off the drive through the digital signal processor.

[0057] In some embodiments, the digital signal trigger module further includes a second resistor, one end of the second resistor is electrically connected to a reference power supply, and the other end of the second resistor is electrically connected to a third end of the second transistor.

[0058] For clear description, the second resistor is marked as R2. The second resistor is used as a pull-up resistor to connect to the reference voltage D3.3V. When the first end of the second transistor receives a low level, the second transistor is cut off, and the third end and the second end of the second transistor are disconnected. Since the third end is connected to the reference voltage through the second resistor, the third end outputs a high level at this time; when the first end of the second transistor receives a high level, the third end and the second end of the second transistor are turned on. Since the second end is grounded, the third end outputs a low level at this time.

[0059] In at least one embodiment, when the AND gate circuit continuously outputs a low-level abnormal signal, the digital signal trigger module receives the low-level signal from the AND gate circuit and continuously generates a drive envelope signal synchronously according to the low level to shut down the drive and protect the devices in the inverter circuit from damage.

[0060] One or more embodiments of the present application further discloses a grid-connected inverter, comprising an inverter and the grid-connected inverter overcurrent protection circuit as described above, wherein the input and output ends of the inverter are electrically connected to the grid-connected inverter overcurrent protection circuit.

[0061] The beneficial effects of the grid-connected inverter relative to the prior art are the same as those of the grid-connected inverter overcurrent protection circuit, which will not be described in detail here.

[0062] The above describes the basic principles, main features and advantages of the present application. Those skilled in the art should understand that the present application is not limited by the above embodiments, and the above embodiments and the specification only describe the principles of the present application. The present application may have various changes and improvements without departing from the spirit and scope of the present application, and these changes and improvements fall within the scope of the present application for which protection is sought. The scope of protection claimed by the present application is defined by the attached claims and their equivalents.

Claims

1. A grid-connected inverter overcurrent protection circuit, characterized in that: It includes a digital signal trigger module, an AND gate circuit and an overcurrent detection module; The overcurrent detection module is used to detect the input current and output current of each path of the inverter. When an overcurrent occurs in any input current or output current, the overcurrent detection module generates a falling edge signal; The first input terminal of the AND gate circuit is electrically connected to the output terminal of the overcurrent detection module; The digital signal trigger module is electrically connected to the output end of the AND gate circuit. When the AND gate circuit outputs a falling edge signal, the digital signal trigger module outputs a driving wave envelope signal for shutting off the driving.

2. The grid-connected inverter overcurrent protection circuit according to claim 1, characterized in that: It also includes a digital signal reset module, the output end of the digital signal reset module is electrically connected to the second input end of the AND gate circuit, the digital signal reset module is used to receive a reset signal, and transmit a reset protection signal to the AND gate circuit according to the reset signal.

3. The grid-connected inverter overcurrent protection circuit according to claim 2, characterized in that: The digital signal reset module includes a first transistor, wherein the first end of the first transistor is used to receive the reset signal; the second end of the first transistor is electrically connected to a reference power supply; when the first end receives the reset signal, the first transistor is cut off, and the reset protection signal is generated at the third end of the first transistor and output to the AND gate circuit.

4. The grid-connected inverter overcurrent protection circuit according to claim 3, characterized in that: The digital signal reset module further includes a first resistor, and two ends of the first resistor are respectively connected to the first end and the second end of the first transistor.

5. The grid-connected inverter overcurrent protection circuit according to claim 3, characterized in that: The first transistor is a PNP transistor, the first end is a base, the second end is an emitter, and the third end is a collector.

6. The grid-connected inverter overcurrent protection circuit according to claim 1, characterized in that: It also includes a driving enable module, the output end of the driving enable module is used to be electrically connected to the third input end of the AND gate circuit, so that the output end of the driving enable module outputs a driving protection signal to the AND gate circuit.

7. The grid-connected inverter overcurrent protection circuit according to claim 1 or 6, characterized in that: The digital signal trigger module comprises a second transistor, wherein a first end of the second transistor is electrically connected to the output end of the gate circuit; a second end is grounded; and a third end is used to be electrically connected to a digital signal processor.

8. The grid-connected inverter overcurrent protection circuit according to claim 7, characterized in that: The digital signal trigger module also includes a second resistor, one end of the second resistor is electrically connected to the reference power supply, and the other end of the second resistor is electrically connected to the third end of the second transistor.

9. The grid-connected inverter overcurrent protection circuit according to claim 7, characterized in that: The second transistor is an NPN transistor, the first end is a base, the second end is an emitter, and the third end is a collector.

10. A grid-connected inverter, characterized in that: It comprises an inverter and a grid-connected inverter overcurrent protection circuit as claimed in any one of claims 1 to 9, wherein the input end and the output end of the inverter are electrically connected to the grid-connected inverter overcurrent protection circuit.

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