Array substrate and display device

Abstract

The utility model discloses an array substrate and a display device. The array substrate comprises a plurality of gate metal layer wires, a plurality of source metal layer wires and a plurality of first via holes, the source electrode metal layer wire is wound at the blind hole for layer changing and is in lap joint with the gate electrode metal layer wire through a first via hole which is connected in parallel with the source electrode metal layer wire; wherein the number of the first via holes is at least two. According to the display device, the source electrode metal layer wires and the corresponding grid electrode metal layer wires are connected in parallel at the positions of the blind holes through the via hole pairs, in this way, even if one via hole pair has a lap joint problem, wire breakage cannot occur at the position, the problem of poor lap joint of the via holes is solved, and the reliability of the display device is improved.

Description

Technical Field

[0001] The utility model relates to the technical field of display screens, and in particular to an array substrate and a display device. Background Art

[0002] With the continuous development of display panels, liquid crystal displays using thin film transistors have been applied to various industries. Thin film transistor liquid crystal displays are the mainstream display devices on various notebook computers and desktop computers. Each liquid crystal pixel on this type of display is driven by a thin film transistor integrated behind the pixel. It is one of the best LCD color displays, and its display effect is close to that of CRT displays.

[0003] At present, there are various shapes of display screens on the market, such as the notch screen and water drop screen in the full screen that pursues screen-to-body ratio. The development idea of ​​this type of display screen is to dig a hole in the screen to place the front camera and hide the camera module in the panel. The in-plane hole technology came into being. It will enlarge the effective display area and increase the screen-to-body ratio of the display. For example, the blind hole screen that pursues function sacrifices part of the screen-to-body ratio in order to make a certain performance stronger.

[0004] However, existing blind hole screens have the problem of poor reliability of via connection, resulting in reduced display quality. Summary of the invention

[0005] The existing blind hole screen has unreliable via connection, which leads to a decrease in the display quality of the display screen.

[0006] In view of the above problems, an array substrate and a display device are proposed, in which the source metal layer wiring and the corresponding gate metal layer wiring are connected in parallel through multiple via pairs at the blind hole position. In this way, even if there is an overlap problem in one of the via pairs, it will not cause a break in the wire here, thereby solving the problem of poor via overlap and improving the reliability of the display device.

[0007] In a first aspect, an array substrate includes:

[0008] Multiple gate metal layer routing;

[0009] Multiple source metal layer routing;

[0010] a plurality of first via holes;

[0011] The source metal layer wiring is wound around the blind hole and changes layers and is overlapped with the gate metal layer wiring through the first via hole connected in parallel;

[0012] Wherein, the number of the first via holes is at least two.

[0013] In combination with the array substrate of the present utility model, in a first possible implementation manner, the source metal layer routing includes:

[0014] First source routing;

[0015] Second source routing;

[0016] The third source routing;

[0017] The first source electrode routing changes layers when passing through the blind hole, and is directly connected to the second source electrode routing and the third source electrode routing.

[0018] In combination with the first possible implementation manner of the utility model, in a second possible implementation manner, the gate metal layer routing includes:

[0019] Winding part;

[0020] a first gate connection portion;

[0021] a second gate connection portion;

[0022] The winding portion is wound when passing through the blind hole and is directly connected to the first gate connecting portion and the second gate connecting portion.

[0023] In combination with the second possible implementation manner of the utility model, in a third possible implementation manner, the second source electrode wiring is overlapped with the gate metal layer wiring through the first via hole connected in parallel.

[0024] In combination with the third possible implementation manner of the utility model, in a fourth possible implementation manner, the first via hole includes

[0025] a first pair of connecting holes;

[0026] a second pair of connecting holes;

[0027] The second source electrode wiring is respectively overlapped with the first end of the first connection hole pair and the first end of the second connection hole pair;

[0028] The second end of the first connection hole pair and the second end of the second connection hole pair are overlapped with the first gate connection portion respectively.

[0029] In combination with the first possible implementation manner of the utility model, in a fifth possible implementation manner, the third source electrode wiring is overlapped with the gate metal layer wiring through the first via hole connected in parallel.

[0030] In combination with the fifth possible implementation manner of the utility model, in a sixth possible implementation manner, the first via further includes:

[0031] a third pair of connecting holes;

[0032] a fourth pair of connecting holes;

[0033] The third source electrode wiring is overlapped with the first end of the third connection hole pair and the first end of the fourth connection hole pair respectively;

[0034] The second end of the third connection hole pair and the second end of the fourth connection hole pair are overlapped with the second gate connection portion respectively.

[0035] In a second aspect, a display device comprises the array substrate described in the first aspect.

[0036] An array substrate and a display device described in the utility model are implemented by connecting the source metal layer wiring and the corresponding gate metal layer wiring in parallel through multiple via pairs at the blind hole position. In this way, even if one of the via pairs has an overlap problem, it will not cause a break at this point, thus solving the problem of poor via overlap. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0038] Figure 1 is a schematic diagram of a blind hole display device;

[0039] Figure 2 A schematic diagram of a via-hole overlap structure at a blind hole of an existing array substrate;

[0040] Figure 3 It is a schematic diagram of the via-hole overlap structure at the blind hole of the array substrate in the utility model. DETAILED DESCRIPTION

[0041] The following will be combined with the drawings in the utility model to clearly and completely describe the technical solution in the utility model. Obviously, the described embodiments are only part of the embodiments of the utility model, not all of the embodiments. Based on the embodiments in the utility model, other embodiments obtained by ordinary technicians in this field without creative work are all within the scope of protection of the utility model.

[0042] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art in the technical field of the present invention. The terms used herein in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "and / or" used herein includes any and all combinations of one or more related listed items.

[0043] It should be noted that when an element is referred to as being "fixed to" or "disposed on" another element, it can be directly on the other element or indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or indirectly connected to the other element.

[0044] It should be understood that the orientation or position relationship indicated by terms such as "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside" and "outside" are based on the orientation or position relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0045] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0046] The existing blind hole 210 screen has unreliable via connection, which leads to a decrease in the display quality of the display screen.

[0047] In view of the above problems, an array substrate and a display device 200 are proposed.

[0048] Example 1

[0049] In a first aspect, an array substrate includes a plurality of gate metal layer routings 400, a plurality of source metal layer routings 100, and a plurality of first vias; the source metal layer routings 100 are wound around and changed layers at blind holes 210 and overlapped with the gate metal layer routings 400 through parallel first vias; wherein the number of the first vias is at least two.

[0050] like Figure 1 , Figure 1Schematic diagram of the blind via 210 display device 200; due to space limitations, the blind via 210 display device 200 adopts a via layer switching and wiring method to save wiring space.

[0051] like Figure 2 , Figure 2 The schematic diagram of the via overlap structure at the blind hole 210 of the existing array substrate is shown in FIG. The thick solid line is the gate signal line, and the thin solid line is the source signal line. The routing of the source signal line to the source signal line at the blind hole 210 is realized. This connection method uses a single pair of vias. When one of the vias has an overlap problem, it will cause a break here, and the source signal cannot be transmitted to the pixel above the via, which eventually leads to abnormal display.

[0052] In this embodiment, vias are connected in parallel to perform via fault tolerance setting. Specifically, Figure 3 , Figure 3 The schematic diagram of the via overlap structure of the array substrate at the blind hole 210 in the utility model shows that the source metal layer wiring 100 is overlapped with the gate metal layer wiring 400 through parallel vias after the layer change winding. By connecting the source metal layer wiring 100 and the corresponding gate metal layer wiring 400 in parallel through multiple via pairs at the blind hole 210, even if one of the via pairs has an overlap problem, it will not cause a break at this point, thus solving the problem of poor via overlap.

[0053] The source metal layer wiring 100 and the gate metal layer wiring 400 are arranged in a staggered manner, and each source metal layer wiring 100 is overlapped with the corresponding gate metal layer wiring 400 .

[0054] Specifically, the source metal layer routing 100 includes a first source routing 110 , a second source routing 120 , and a third source routing 130 ; the first source routing 110 changes layers when passing through the blind hole 210 , and is directly connected to the second source routing 120 and the third source routing 130 .

[0055] Specifically, the gate metal layer routing 400 includes a winding portion 410 , a first gate connection portion 420 , and a second gate connection portion 430 ; the winding portion 410 is wound when passing through the blind hole 210 , and is directly connected to the first gate connection portion 420 and the second gate connection portion 430 .

[0056] Specifically, the second source wiring 120 is overlapped with the gate metal layer wiring 400 through the parallel first vias.

[0057] Furthermore, the first via includes a first connection hole pair 310 and a second connection hole pair 320; the second source wiring 120 overlaps the first end of the first connection hole pair 310 and the first end of the second connection hole pair 320 respectively; the second end of the first connection hole pair 310 and the second end of the second connection hole pair 320 overlaps the first gate connection portion 420 respectively.

[0058] Similarly, the third source electrode routing is overlapped with the gate metal layer routing 400 through the first via hole in parallel. The first via hole also includes a third connection hole pair 330 and a fourth connection hole pair 340; the third source electrode routing is overlapped with the first end of the third connection hole pair 330 and the first end of the fourth connection hole pair 340 respectively; the second end of the third connection hole pair 330 and the second end of the fourth connection hole pair 340 are overlapped with the second gate connection portion 430 respectively.

[0059] In this embodiment, without increasing the space occupied, the number of vias is connected in parallel, thereby increasing the overlap tolerance of different layers and improving the quality of the product.

[0060] In a second aspect, a display device 200 comprises the array substrate of the first aspect.

[0061] An array substrate and a display device 200 described in the utility model are implemented by connecting the source metal layer wiring 100 and the corresponding gate metal layer wiring 400 in parallel through a plurality of via pairs at the blind hole 210. Thus, even if one of the via pairs has an overlap problem, it will not cause a break at this point, thus solving the problem of poor via overlap.

[0062] The above are only preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. An array substrate, characterized in that it comprises: Multiple gate metal layer routing; Multiple source metal layer routing; a plurality of first via holes; The source metal layer wiring is wound around the blind hole and changes layers and is overlapped with the gate metal layer wiring through the first via hole connected in parallel; Wherein, the number of the first via holes is at least two.

2. The array substrate according to claim 1, characterized in that: The source metal layer routing includes: First source routing; Second source routing; The third source routing; The first source electrode routing changes layers when passing through the blind hole, and is directly connected to the second source electrode routing and the third source electrode routing.

3. The array substrate according to claim 2, characterized in that: The gate metal layer routing includes: Winding part; a first gate connection; a second gate connection; The winding portion is wound when passing through the blind hole and is directly connected to the first gate connecting portion and the second gate connecting portion.

4. The array substrate according to claim 3, characterized in that: The second source electrode wiring is overlapped with the gate metal layer wiring through the first via hole connected in parallel.

5. The array substrate according to claim 4, characterized in that: The first via hole comprises a first pair of connecting holes; a second pair of connecting holes; The second source electrode wiring is respectively overlapped with the first end of the first connection hole pair and the first end of the second connection hole pair; The second end of the first connection hole pair and the second end of the second connection hole pair are overlapped with the first gate connection portion respectively.

6. The array substrate according to claim 3, characterized in that: The third source electrode wiring is overlapped with the gate metal layer wiring through the first via hole connected in parallel.

7. The array substrate according to claim 6, characterized in that: The first via hole further comprises: a third pair of connecting holes; a fourth pair of connecting holes; The third source electrode wiring is overlapped with the first end of the third connection hole pair and the first end of the fourth connection hole pair respectively; The second end of the third connection hole pair and the second end of the fourth connection hole pair are overlapped with the second gate connection portion respectively.

8. A display device, characterized in that: The invention comprises the array substrate according to any one of claims 1 to 7.

Images