Display device

Abstract

A display device is provided. The display device includes a display module including a display panel and an input sensor, and a circuit board including: a first signal line electrically connected to the display panel and having a portion extending in a first extension direction; a sensing line electrically connected to the input sensing unit and having a portion extending in a second extension direction; and a shielding layer between the first signal line and the sensing line and having a first opening and a second opening with the sensing line between the first opening and the second opening, in which a portion of each of the first opening and the second opening extends in a second extension direction, the sensing line crosses the first signal line between the first opening and the second opening, and wherein a distance between the first opening and the second opening is greater than or equal to a width of the sensing line. The display device can improve the quality of a high-frequency driving signal transmitted through a signal line and improve the accuracy and reliability of input sensing.

Description

[0001] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0052050 filed in the Korean Intellectual Property Office on April 20, 2023, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0002] An aspect of some embodiments of the present disclosure relates to a display device. Background Art

[0003] Generally, an electronic device that displays an image to a user (such as a smart phone, a digital camera, a laptop computer, a navigation device, or a smart TV) includes a display device for displaying the image. The display device generates an image and provides the generated image to the user through a display screen.

[0004] The display device includes a display panel for generating an image and an input sensing unit positioned on the display panel to sense an external input. The display panel includes a plurality of pixels for generating an image, and the input sensing unit includes a plurality of sensing electrodes for sensing the external input.

[0005] The circuit board is connected to the display panel and the input sensing unit. The circuit board has signal lines and sensing lines, the signal lines are connected to the display panel to transmit driving signals for driving pixels, and the sensing lines are connected to the input sensing unit to transmit driving signals for driving sensing electrodes or receive sensing signals from sensing electrodes.

[0006] The above information disclosed in this background section is only for enhancement of understanding of the background technology and therefore the information discussed in this background section does not necessarily constitute prior art. Utility Model Content

[0007] Embodiments of the present disclosure provide a display device capable of improving the quality of a high-frequency driving signal transmitted through a signal line and reducing noise induced in a sensing line to improve the reliability of input sensing.

[0008] According to some embodiments, a display device includes a display module and a circuit board, the display module includes a display panel and an input sensing unit, and the circuit board is connected to the display module. According to some embodiments, the circuit board includes: a first signal line electrically connected to the display panel and having at least a portion extending in a first extension direction; a sensing line electrically connected to the input sensing unit and having at least a portion extending in a second extension direction intersecting the first extension direction; and a shielding layer placed between the first signal line and the sensing line, and when viewed in a plan view, the shielding layer has a first opening and a second opening spaced apart from each other while placing the sensing line therebetween. According to some embodiments, at least a portion of each of the first opening and the second opening extends in the second extension direction, when viewed in a plan view, the sensing line crosses the first signal line between the first opening and the second opening, and when viewed in a plan view, the distance between the first opening and the second opening is greater than or substantially equal to the width of the sensing line.

[0009] According to some embodiments, when viewed in a plan view, a portion of the first signal line may be exposed from the shielding layer through each of the first opening and the second opening.

[0010] According to some embodiments, the circuit board may further include: a second signal line electrically connected to the display panel, spaced apart from the first signal line and extending parallel to the first signal line, and when viewed in a plan view, the second signal line crosses the sensing line between the first opening and the second opening.

[0011] According to some embodiments, the circuit board may further include: a ground line disposed between the first signal line and the second signal line and extending parallel to the first signal line, and when viewed in a plan view, a portion of the ground line is exposed from the shielding layer through each of the first opening and the second opening.

[0012] According to some embodiments, the circuit board may further include: a second signal line electrically connected to the display panel, spaced apart from the first signal line, and extending parallel to the first signal line, the shielding layer having a third opening and a fourth opening additionally defined in the shielding layer, the third opening and the fourth opening being arranged in a second extension direction from the first opening and the second opening, respectively, and spaced apart from each other while placing the sensing line between the third opening and the fourth opening, when viewed in a plan view, the second signal line crosses the sensing line between the third opening and the fourth opening, and when viewed in a plan view, a distance between the third opening and the fourth opening is greater than or substantially equal to a width of the sensing line.

[0013] According to some embodiments, the circuit board may further include: a ground line placed between the first signal line and the second signal line and extending parallel to the first signal line, and when viewed in a plan view, the ground line may be placed between the first opening and the third opening and between the second opening and the fourth opening.

[0014] According to some embodiments, the sensing line may include: a first portion extending in a second extension direction; and a second portion extending in a third extension direction, the third extension direction intersecting each of the first extension direction and the second extension direction, and each of the first opening and the second opening may include: a first opening area extending in the second extension direction; and a second opening area extending from the first opening area in the third extension direction.

[0015] According to some embodiments, the first portion may be disposed between a first opening region of the first opening and a first opening region of the second opening, and the second portion may be disposed between a second opening region of the first opening and a second opening region of the second opening.

[0016] According to some embodiments, the first signal line may transmit a high frequency signal.

[0017] According to some embodiments, a ground voltage may be applied to the shielding layer.

[0018] According to some embodiments, the circuit board may further include: a base layer under the first signal line; a first insulating layer disposed between the first signal line and the shielding layer; and a second insulating layer disposed between the shielding layer and the sensing line.

[0019] According to some embodiments, the circuit board may further include: a lower insulating layer disposed between the base layer and the first signal line; and a power line disposed between the base layer and the lower insulating layer.

[0020] According to some embodiments, a display device may include a display module and a circuit board, the display module including a display panel and an input sensing unit, and the circuit board is connected to the display module. According to some embodiments, the circuit board may include: a first signal line electrically connected to the display panel; a shielding layer on the first signal line and including a first extension area and a second extension area spaced apart from each other and a peripheral area surrounding the first extension area and the second extension area; and a sensing line on the shielding layer, electrically connected to the input sensing unit, and including a first sensing line and a second sensing line, the first sensing line having a portion overlapping the first extension area, and the second sensing line having a portion overlapping the second extension area. According to some embodiments, when viewed in a plan view, the first sensing line may cross the first signal line in an area overlapping the first extension area, and the second sensing line crosses the first signal line in an area overlapping the second extension area, and in an area where the first extension area overlaps the first sensing line, the width of the first extension area may be greater than or substantially equal to the width of the first sensing line.

[0021] According to some embodiments, the shielding layer may further include: a dummy extension region, which is spaced apart from the first extension region, extends parallel to the first extension region, and is surrounded by the peripheral region, and when viewed in a plan view, the dummy extension region may be in a non-overlapping state with the sensing line and cross the first signal line.

[0022] According to some embodiments, the shielding layer may further include a third extension region and a fourth extension region surrounded by the peripheral region, another portion of the first sensing line may overlap the third extension region, and another portion of the second sensing line may overlap the fourth extension region.

[0023] According to some embodiments, the circuit board may further include: a second signal line electrically connected to the display panel, spaced apart from the first signal line, and extending parallel to the first signal line, and when viewed in a plan view, the first sensing line may cross the second signal line in an area overlapping the third extension area, and the second sensing line crosses the second signal line in an area overlapping the fourth extension area.

[0024] According to some embodiments, the first signal line may have at least a portion extending in a first extension direction in an area overlapping with the shielding layer, the first sensing line may include a first portion extending in a second extension direction intersecting the first extension direction and a second portion extending from the first portion in a third extension direction intersecting each of the first extension direction and the second extension direction, and the first extension area may include a first area extending in the second extension direction and overlapping with the first portion and a second area extending from the first area in the third extension direction and overlapping with the second portion.

[0025] According to some embodiments, the shielding layer may further include: a dummy extension region, which is spaced apart from the first extension region, is in a non-overlapping state with the sensing line, and is surrounded by the peripheral region, and the dummy extension region may include a first dummy region extending in the second extension direction and a second dummy region extending from the first dummy region in a third extension direction.

[0026] According to some embodiments, the circuit board may further include: a ground line spaced apart from the first signal line and extending parallel to the first signal line.

[0027] According to some embodiments, a display device may include a display module and a circuit board, the display module being configured to provide an image and sense an external input, and the circuit board being connected to the display module. According to some embodiments, the circuit board may include: a first line electrically connected to the display module to transmit a high-frequency signal and having at least a portion extending in a first extension direction; a second line electrically connected to the display module and having at least a portion extending in a second extension direction intersecting the first extension direction; and a shielding layer disposed between the first line and the second line, and when viewed in a plan view, the shielding layer has a first opening and a second opening spaced apart from each other while the second line is disposed therebetween, wherein at least a portion of each of the first opening and the second opening extends in the second extension direction. According to some embodiments, when viewed in a plan view, the second line may cross the first line between the first opening and the second opening, and when viewed in a plan view, the distance between the first opening and the second opening may be greater than or substantially equal to the width of the second line. The display device may improve the quality of a high-frequency drive signal transmitted through the signal line, and may improve the accuracy and reliability of input sensing. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The above and other characteristics and features according to embodiments of the present disclosure will become more apparent by describing aspects of some embodiments according to embodiments of the present disclosure in more detail with reference to the accompanying drawings.

[0029] Figure 1 is a perspective view showing a display device according to some embodiments of the present disclosure.

[0030] Figure 2 is a cross-sectional view showing a display device according to some embodiments of the present disclosure.

[0031] Figure 3 is a cross-sectional view illustrating a display module according to some embodiments of the present disclosure.

[0032] Figure 4 is a plan view showing some components of a display device according to some embodiments of the present disclosure.

[0033] Figure 5 is a plan view illustrating an input sensing unit according to some embodiments of the present disclosure.

[0034] Fig. 6A is a plan view showing some components of a circuit board according to some embodiments of the present disclosure.

[0035] Figure 6B is a cross-sectional view showing a circuit board according to some embodiments of the present disclosure.

[0036] FIG. 6C to FIG. 6Eis a plan view showing some components of a circuit board according to some embodiments of the present disclosure.

[0037] Fig. 7A and Figure 7B is an enlarged plan view showing some components of a circuit board according to some embodiments of the present disclosure.

[0038] Fig. 8A and Figure 8B is an enlarged plan view showing some components of a circuit board according to some embodiments of the present disclosure.

[0039] 9A to 9C is an enlarged plan view showing some components according to some embodiments of the present disclosure.

[0040] Fig. 10A is an enlarged plan view showing some components of a circuit board according to a first comparative example.

[0041] Fig. 10B is an enlarged plan view showing some components of a circuit board according to a second comparative example. DETAILED DESCRIPTION

[0042] In the specification, the expression that a first component (or region, layer, part, portion, etc.) is "on", "connected to" or "coupled to" a second component means that the first component is directly on, directly connected to or directly coupled to the second component, or that a third component is placed between the first and second components.

[0043] The same reference numerals refer to the same components. In addition, in the drawings, the thickness, proportion and size of the components may be exaggerated to effectively describe the technical features. The expression "and / or" includes one or more combinations that the related components can define.

[0044] Although the terms "first", "second", etc. can be used to describe various components, these components should not be interpreted as being limited by these terms. These terms are only used to distinguish one component from another component. For example, without departing from the scope and spirit of the present disclosure, a first component may be referred to as a second component, and similarly, a second component may be referred to as a first component. The articles "one", "a (kind / person)", and "the (said)" are singular because they have a single referent, but the use of the singular form in the specification should not exclude the presence of more than one referent.

[0045] In addition, the terms "under", "beneath", "over", "above", etc. are used to describe the relationship between components shown in the drawings. The terms are relative and are described with reference to the directions shown in the drawings.

[0046] It will be understood that the terms “comprises,” “includes,” “has,” etc. specify the presence of features, quantities, steps, operations, elements or components, or a combination thereof, described in the specification, and do not exclude the possibility of the presence or addition of one or more other features, quantities, steps, operations, elements or components, or a combination thereof.

[0047] Unless otherwise defined, all terms (including technical terms and scientific terms) used in the specification have the same meaning as those generally understood by those skilled in the art to which the present disclosure belongs. In addition, terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning consistent with the meaning in the context of the relevant technology, and should not be interpreted in an idealized or overly formalized meaning unless explicitly defined herein.

[0048] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0049] Figure 1 is a perspective view of a display device DD according to some embodiments of the present disclosure.

[0050] The display device DD may have a rectangular shape having a longer side in a first direction DR1 and a shorter side in a second direction DR2 intersecting the first direction DR1 (e.g., when viewed in a plan view or a view perpendicular or normal to a display surface of the display device DD (e.g., when viewed from a third direction DR3)). However, embodiments according to the present disclosure are not limited thereto, and the display device DD may have various shapes such as a circle, an ellipse, or a polygon, and according to some embodiments, the display device DD may have rounded corners or vertices.

[0051] Hereinafter, a direction substantially perpendicular to a plane defined by the first direction DR1 and the second direction DR2 is defined as a third direction DR3. In addition, in the specification, "when viewed from above a plane" may mean "when viewed in the third direction DR3".

[0052] An upper surface of the display device DD may be defined as a display surface DS, and may have a plane defined by the first direction DR1 and the second direction DR2. An image IM generated by the display device DD may be provided to a user through the display surface DS.

[0053] The display surface DS may include a display area DA and a non-display area NDA around the display area DA (e.g., in the periphery of the display area DA or outside the display area DA). The display area DA is an area configured to display an image IM, and the non-display area NDA is an area where the image IM is not displayed. The non-display area NDA may be defined as an edge of the display device DD that surrounds the display area DA and is printed with a specific color.

[0054] The display device DD may be used for large electronic devices such as televisions, monitors, or external billboards. In addition, the display device DD may be used for small and medium-sized electronic devices such as personal computers, notebook computers, personal digital terminals, car navigation systems, game consoles, smart phones, tablet computers, or cameras. However, the above examples are provided for illustrative purposes only, and without departing from the concept of the present disclosure, the display device DD may be applied to any other electronic device having a display capability.

[0055] Figure 2 is a cross-sectional view of a display device DD according to some embodiments of the present disclosure. Figure 2 A cross section of the display device DD when viewed in a first direction DR1 is shown.

[0056] Reference Figure 2 , the display device DD may include a display panel DP, an input sensing unit (or input sensor or input sensing circuit or input sensing component) ISP, an anti-reflection layer RPL, a window WIN, a panel protection film PPF, and first to third adhesive layers AL1 to AL3. The display panel DP may be a flexible display panel. For example, the display panel DP may include a plurality of electronic components positioned on a flexible substrate.

[0057] The display panel DP according to some embodiments of the present disclosure may be an emissive display panel, and is not particularly limited thereto. For example, the display panel DP may be an organic light-emitting display panel or a quantum dot light-emitting display panel. The light-emitting layer of the organic light-emitting display layer may include an organic light-emitting material. The light-emitting layer of the quantum dot light-emitting display panel may include quantum dots, quantum rods, etc. In the following, the display panel DP is an organic light-emitting display panel.

[0058] The input sensing unit ISP may be positioned on the display panel DP. The input sensing unit ISP may include a plurality of sensors for sensing external input in a capacitive scheme. The input sensing unit ISP may be directly formed on the display panel DP when manufacturing the display device DD. However, the present disclosure is not limited thereto. The input sensing unit ISP is manufactured separately from the display panel DP and may be attached to the display panel DP by an adhesive layer.

[0059] The anti-reflection layer RPL may be positioned on the input sensing unit ISP. The anti-reflection layer RPL may reduce reflectivity of external light incident from the top surface of the display device DD to the display panel DP. The anti-reflection layer RPL may include a retarder and a polarizer.

[0060] The window WIN may be positioned on the anti-reflection layer RPL. The window WIN may protect the display panel DP, the input sensing unit ISP, and the anti-reflection layer RPL from external scratches and impacts.

[0061] The panel protection film PPF may be positioned under the display panel DP. The panel protection film PPF may protect the bottom surface of the display panel DP. The panel protection film PPF may include a flexible plastic material such as polyethylene terephthalate (PET).

[0062] The first adhesive layer AL1 may be disposed between the display panel DP and the panel protection film PPF to combine the display panel DP with the panel protection film PPF. The second adhesive layer AL2 may be disposed between the anti-reflection layer RPL and the input sensing unit ISP to combine the anti-reflection layer RPL and the input sensing unit ISP. The third adhesive layer AL3 may be disposed between the window WIN and the anti-reflection layer RPL to combine the window WIN with the anti-reflection layer RPL.

[0063] Figure 3 is a cross-sectional view of a display module DM according to some embodiments of the present disclosure. For example, Figure 3 A cross section of the display module DM when viewed in the first direction DR1 is shown.

[0064] Reference Figure 3 , the display module DM may include a display panel DP and an input sensing unit ISP.

[0065] The display panel DP may include a substrate SUB, a circuit element layer DP-CL positioned on the substrate SUB, a display element layer DP-OLED positioned on the circuit element layer DP-CL, and a thin film encapsulation layer TFE positioned on the display element layer DP-OLED.

[0066] The substrate SUB may include a display area DA and a non-display area NDA around the display area DA. The display element layer DP-OLED is positioned in the display area DA. The substrate SUB may include a flexible plastic material such as polyimide (PI).

[0067] A plurality of pixels may be positioned in the circuit element layer DP-CL and the display element layer DP-OLED. Each of the pixels may include a transistor positioned in the circuit element layer DP-CL and a light emitting element positioned in the display element layer DP-OLED and connected to the transistor.

[0068] The thin film encapsulation layer TFE may cover the display element layer DP-OLED. The thin film encapsulation layer TFE may include an inorganic layer, an organic layer, and an inorganic layer stacked sequentially. The inorganic layer includes an inorganic material and may protect the pixel from moisture / oxygen. The organic layer includes an organic material and may protect the pixel from foreign matter such as dust particles.

[0069] The input sensing unit ISP obtains coordinate information of the external input. The input sensing unit ISP may have a multi-layer structure. The input sensing unit ISP may include a single layer or multiple layers of conductive layers. The input sensing unit ISP may include a single layer or multiple layers of insulating layers. The input sensing unit ISP may detect the external input, for example, by capacitive means. According to an embodiment of the present disclosure, the operating method of the input sensing unit ISP is not particularly limited, and according to some embodiments of the present disclosure, the input sensing unit ISP may sense the external input by an electromagnetic induction method or a pressure sensing method.

[0070] Figure 4 is a plan view of some components of a display device DD according to some embodiments of the present disclosure.

[0071] Reference Figure 4 The display device DD may include a display panel DP, a scan driver SDV, a data driver DDV, an emission driver EDV, a plurality of first pads (also referred to as "pads") PD1, a circuit board PCB, a sensing controller S-IC, a plurality of first connection pads CPD1, a plurality of second connection pads CPD2, and a plurality of third connection pads CPD3.

[0072] The display panel DP may have a rectangular shape having longer sides extending in the first direction DR1 and shorter sides extending in the second direction DR2, but the shape of the display panel DP is not limited thereto. The display panel DP may include a display area DA and a non-display area NDA surrounding the display area DA.

[0073] The display panel DP may include a plurality of pixels PX, a plurality of scan lines SL1 to SLm, a plurality of data lines DL1 to DLn, a plurality of emission lines EL1 to ELm, first and second control lines CSL1 and CSL2, first and second power lines PL1 and PL2, and a power connection line CNL. In this case, 'm' and 'n' are natural numbers greater than 0.

[0074] The pixel PX may be positioned in the display area DA. The scan driver SDV and the emission driver EDV may be positioned in the non-display area NDA adjacent to the longer sides of the display panel DP, respectively. The data driver DDV may be positioned in the non-display area NDA adjacent to any one of the shorter sides of the display panel DP. When viewed in a plan view, the data driver DDV may be adjacent to the lower end of the display panel DP. The data driver DDV may be manufactured in the form of an integrated circuit chip and mounted on the display panel DP.

[0075] The scan lines SL1 to SLm may extend in the second direction DR2 and may be connected to the pixels PX and the scan driver SDV. The data lines DL1 to DLn may extend in the first direction DR1 and may be connected to the pixels PX and the data driver DDV. The emission lines EL1 to ELm may extend in the second direction DR2 and may be connected to the pixels PX and the emission driver EDV.

[0076] The first power line PL1 may extend in the first direction DR1 and may be positioned in the non-display area NDA. The first power line PL1 may be interposed between the display area DA and the emission driver EDV, but is not limited thereto and may be interposed between the display area DA and the scan driver SDV.

[0077] The power connection line CNL may extend in the second direction DR2 and may be arranged in the first direction DR1. The power connection line CNL may be connected to the first power line PL1 and the pixel PX. The first voltage may be applied to the pixel PX through the first power line PL1 and the power connection line CNL connected to each other.

[0078] The second power line PL2 may be positioned in the non-display area NDA. The second power line PL2 may extend along a longer side of the display panel DP and another shorter side of the display panel DP where the data driver DDV is not positioned. The second power line PL2 may be positioned outside the scan driver SDV and the emission driver EDV.

[0079] According to some embodiments, the second power line PL2 may extend toward the display area DA and may be connected to the pixel PX. A second voltage having a level lower than the first voltage may be applied to the pixel PX through the second power line PL2.

[0080] The first control line CSL1 may be connected to the scan driver SDV and may extend toward the lower end of the display panel DP when viewed in a plan view. The second control line CSL2 may be connected to the emission driver EDV and may extend toward the lower end of the display panel DP when viewed in a plan view. The data driver DDV may be interposed between the first control line CSL1 and the second control line CSL2.

[0081] The first pad PD1 may be positioned on the display panel DP. The first pad PD1 may be closer to the lower end of the display panel DP than the data driver DDV. The data driver DDV, the first power line PL1, the second power line PL2, the first control line CSL1, and the second control line CSL2 may be connected to the first pad PD1. The data lines DL1 to DLn may be connected to the data driver DDV, and the data driver DDV may be connected to the first pad PD1 corresponding to the data lines DL1 to DLn.

[0082] The circuit board PCB may be implemented in the form of a flexible circuit board, but the present disclosure is not limited thereto. The circuit board PCB may be implemented in a rigid type. The sensing controller S-IC may be manufactured in the form of an integrated circuit chip and mounted on the circuit board PCB.

[0083] The first connection pad CPD1, the second connection pad CPD2, and the third connection pad CPD3 may be positioned on the circuit board PCB. When viewed in a plan view, the first connection pad CPD1, the second connection pad CPD2, and the third connection pad CPD3 may be adjacent to an upper portion of the circuit board PCB. The upper portion of the circuit board PCB may face a lower portion of the display panel DP.

[0084] The first connection pad CPD1 may be disposed between the second connection pad CPD2 and the third connection pad CPD3. For example, the second connection pad CPD2 may be located on the left side of the first connection pad CPD1, and the third connection pad CPD3 may be located on the right side of the first connection pad CPD1.

[0085] The circuit board PCB can be connected to the display module DM (see Figure 2 ). The circuit board PCB may be connected to the display panel DP. Since the first connection pad CPD1 is connected to the first pad PD1, the circuit board PCB may be electrically connected to the display panel DP.

[0086] The circuit board PCB may include a first extension unit EXP1 extending in the second direction DR2 and a second extension unit EXP2 extending in the first direction DR1 from a specific portion of the first extension unit EXP1. The second extension unit EXP2 may extend in a direction away from the display panel DP. According to some embodiments, the second extension unit EXP2 may be connected to a system board positioned outside. The system board may control the overall operation of the display device DD.

[0087] The sensing controller S-IC may be positioned on the first extension unit EXP1. The sensing controller S-IC may be adjacent to the second extension unit EXP2. The first connection pad CPD1, the second connection pad CPD2, and the third connection pad CPD3 may be positioned on the first extension unit EXP1 and may be adjacent to an upper portion of the first extension unit EXP1 when viewed in a plan view.

[0088] A plurality of power lines PL, a plurality of control lines CSL_D, a plurality of signal lines SGL (or first lines), a plurality of sensing lines TL (second lines), and a plurality of sensing signal lines CSL_I may be positioned inside the circuit board PCB.

[0089] The signal line SGL, the power line PL, and the control line CSL_D may be positioned in the second extension unit EXP2 and may extend in the first direction DR1. The signal line SGL, the power line PL, and the control line CSL_D may be connected to the system board through the second extension unit EXP2.

[0090] The signal line SGL, the power line PL, and the control line CSL_D may be positioned in the first extension unit EXP1 while sequentially extending in the first direction DR1, the second direction DR2, and the first direction DR1, and respectively connected to the first connection pad CPD1. The signal line SGL, the power line PL, and the control line CSL_D may be connected to the first pad PD1 through the first connection pad CPD1, thereby being connected to the display panel DP.

[0091] The sensing signal line CSL_I may be positioned in the second extension unit EXP2 and may extend in the first direction DR1 to be connected to the sensing controller S-IC in the first extension unit EXP1.

[0092] The sensing line TL may be positioned in the first extension unit EXP1 and may extend in the first direction DR1, the second direction DR2, and the first direction DR1 sequentially to be connected to the second connection pad CPD2 or the third connection pad CPD3. The left sensing line among the sensing lines TL may be connected to the second connection pad CPD2, and the right sensing line among the sensing lines TL may be connected to the third connection pad CPD3. The sensing line TL may be connected to the input sensing unit ISP (see FIG. 1 ) through the second connection pad CPD2 or the third connection pad CPD3. Figure 2 According to some embodiments, the sensing line TL connected to the second connection pad CPD2 may be a transmission line that transmits a driving signal for driving the sensing electrode, and the sensing line TL connected to the third connection pad CPD3 may be a receiving line that receives a sensing signal from the sensing electrode, but the present disclosure is not limited thereto.

[0093] According to some embodiments, the sensing line TL connected to the third connection pad CPD3 may overlap with the signal line SGL. More specifically, when viewed on a plane, since the sensing line TL connected to the third connection pad CPD3 extends from the sensing controller S-IC positioned on the left side of the first extension unit EXP1 to the third connection pad CPD3 positioned on the right side of the first extension unit EXP1, the sensing line TL connected to the third connection pad CPD3 may cross the signal line SGL. When viewed in a plan view, an area formed on the circuit board PCB where the sensing line TL crosses the signal line SGL may be defined as an overlapping area OVA. At the same time, the sensing line TL connected to the second connection pad CPD2 may not overlap with the signal line SGL.

[0094] According to some embodiments, the shielding layer SDL is arranged to overlap with at least some of the sensing lines TL on the circuit board PCB. The shielding layer SDL may be positioned between the sensing lines TL and the signal lines SGL in the overlapping area OVA. A ground (or ground) voltage may be applied to the shielding layer SDL. Therefore, the shielding layer SDL may reduce the coupling phenomenon between the sensing lines TL and the signal lines SGL that are adjacent to or cross each other when viewed in a plan view.

[0095] Meanwhile, the shape of the shielding layer SDL is exemplary, and the shielding layer SDL may be arranged to overlap only some of the sensing lines TL outside the overlapping area OVA, or a plurality of shielding layers SDL may be arranged to be spaced apart from each other to overlap mutually different sensing lines TL. Fig. 6A A configuration of the sensing lines TL and the signal lines SGL crossing each other and the shielding layer SDL interposed between the sensing lines TL and the signal lines SGL, which is an enlarged view of the overlap area OVA, will be described in detail.

[0096] According to some embodiments, each of the sensing lines TL (e.g., receiving lines) connected to the third connection pad CPD3 may cross all of the signal lines SGL. However, the present disclosure is not limited thereto. The sensing lines TL connected to the third connection pad CPD3 may cross some of the signal lines SGL, and some of the sensing lines TL connected to the third connection pad CPD3 may cross the signal lines SGL.

[0097] The system board may include a timing controller for controlling the operation of the display panel DP. According to some embodiments, the second extension unit EXP2 may be connected to a voltage generator positioned outside. The timing controller may output a scan control signal, an image signal, and an emission control signal. The voltage generator may generate a first voltage and a second voltage.

[0098] The scan control signal and the emission control signal may be provided to the first control line CSL1 and the second control line CSL2 through the control line CSL_D, respectively. The scan control signal may be provided to the scan driver SDV through the first control line CSL1. The emission control signal may be provided to the emission driver EDV through the second control line CSL2. The image signal may be provided to the data driver DDV through the signal line SGL.

[0099] The scan driver SDV generates a plurality of scan signals in response to the scan control signal, and the scan signals can be applied to the pixels PX through the scan lines SL1 to SLm. The emission driver EDV generates a plurality of emission signals in response to the emission control signal, and the emission signals can be applied to the pixels PX through the emission lines EL1 to ELm.

[0100] The data driver DDV may generate a plurality of data voltages corresponding to the image signal. The data voltages may be applied to the pixels PX through the data lines DL1 to DLn. The first voltage and the second voltage may be provided to the first power line PL1 and the second power line PL2 through the power line PL.

[0101] The pixel PX may receive a data voltage in response to a scan signal. The pixel PX may display an image by emitting light having brightness corresponding to the data voltage in response to a light emission signal. The light emission time of the pixel PX may be controlled by the light emission signal.

[0102] The sensing controller S-IC can be connected to the input sensing unit ISP described below through the second connection pad CPD2 and the third connection pad CPD3 (see Figure 5 ) sensing electrode.

[0103] Figure 5 is a plan view of an input sensing unit ISP according to some embodiments of the present disclosure.

[0104] Reference Figure 4 and Figure 5 The input sensing unit ISP may include a plurality of sensing electrodes SE1 and SE2, a plurality of sensing lines SNL1 and SNL2, a plurality of second pads PD2, and a plurality of third pads PD3. The sensing electrodes SE1 and SE2, the sensing lines SNL1 and SNL2, the second pads PD2, and the third pads PD3 may be positioned on the thin film encapsulation layer TFE.

[0105] The plane area of ​​the input sensing unit ISP may include an active area AA and a non-active area NAA surrounding the active area AA. The active area AA may overlap the display area DA, and the non-active area NAA may overlap the non-display area NDA. The sensing electrodes SE1 and SE2 may be positioned in the active area AA, and the second pad PD2 and the third pad PD3 may be positioned in the non-active area NAA.

[0106] The sensing lines SNL1 and SNL2 may be connected to one end of the sensing electrodes SE1 and SE2 and may extend to the non-active area NAA to be connected to the second pad PD2 and the third pad PD3. The input sensing unit ISP may be connected to the circuit board PCB. According to some embodiments, the second pad PD2 may be connected to the second connection pad CPD2 positioned on the circuit board PCB, and the third pad PD3 may be connected to the third connection pad CPD3 positioned on the circuit board PCB. Some of the sensing lines TL positioned on the circuit board PCB may be connected to the input sensing unit ISP through the second connection pad CPD2, and the remaining lines of the sensing lines TL positioned on the circuit board PCB may be connected to the input sensing unit ISP through the third connection pad CPD3.

[0107] The sensing electrodes SE1 and SE2 may include a plurality of first sensing electrodes SE1 extending in the first direction DR1 and arranged in the second direction DR2 and a plurality of second sensing electrodes SE2 extending in the second direction DR2 and arranged in the first direction DR1. The second sensing electrodes SE2 may extend to be insulated from the first sensing electrodes SE1 while crossing the first sensing electrodes SE1.

[0108] The sensing lines SNL1 and SNL2 may include a plurality of first sensing lines SNL1 connected to the first sensing electrode SE1 and a plurality of second sensing lines SNL2 connected to the second sensing electrode SE2. The first sensing line SNL1 may be connected to the third pad PD3. The second sensing line SNL2 may be connected to the second pad PD2. Therefore, the transmission line of the sensing line TL placed on the circuit board PCB is connected to the second sensing line SNL2 placed in the input sensing unit ISP. The receiving line of the sensing line TL placed on the circuit board PCB may be connected to the first sensing line SNL1 placed in the input sensing unit ISP.

[0109] The first sensing electrode SE1 may be defined as an output sensing electrode, and the second sensing electrode SE2 may be defined as an input sensing electrode. The input sensing unit ISP may be driven in a mutual sensing mode. For example, the sensing controller S-IC may provide a driving signal to the input sensing unit ISP and receive a sensing signal from the input sensing unit ISP.

[0110] The driving signal may be applied to the second sensing electrode SE2 through the transmission line of the sensing line TL (e.g., the sensing line TL connected to the second connection pad CPD2) and the second sensing line SNL2. The sensing signal sensed by the first sensing electrode SE1 may be output through the first sensing line SNL1 and may be provided to the sensing controller S-IC through the reception line of the sensing line TL (e.g., the sensing line TL connected to the third connection pad CPD3).

[0111] The sensing controller S-IC may receive a control signal for generating a driving signal through the plurality of sensing signal lines CSL_I. In addition, the sensing controller S-IC may process the sensing signal and output the sensing signal through the plurality of sensing signal lines CSL_I.

[0112] Each of the first sensing electrodes SE1 may include a plurality of first sensing cells SP1 arranged in the first direction DR1 and a plurality of connection patterns CP connecting the first sensing cells SP1. Each of the connection patterns CP may be disposed between two first sensing cells SP1 adjacent to each other in the first direction DR1 to connect the two first sensing cells SP1 to each other.

[0113] Each of the second sensing electrodes SE2 may include a plurality of second sensing cells SP2 arranged in the second direction DR2 and a plurality of extension patterns EP extending from the second sensing cells SP2. Each of the extension patterns EP may be positioned between two second sensing cells SP2 adjacent to each other in the second direction DR2 and may extend from the two second sensing cells SP2.

[0114] The first sensing cells SP1 and the second sensing cells SP2 may have a mesh shape. The first sensing cells SP1 and the second sensing cells SP2 may be spaced apart from each other and may be alternately arranged. Capacitance may be formed by the first sensing cells SP1 and the second sensing cells SP2. The extension pattern EP may not overlap the connection pattern CP.

[0115] The first and second sensing cells SP1 and SP2 and the extension pattern EP may be positioned at the same layer. The connection pattern CP may be positioned at a layer different from that of the first and second sensing cells SP1 and SP2 and the extension pattern EP.

[0116] Fig. 6A is a plan view showing some components of a circuit board PCB according to some embodiments of the present disclosure. Figure 6B It is along Fig. 6A A cross-sectional view of a circuit board PCB according to some embodiments, cut along line II'. FIG. 6C to FIG. 6E PCB (see FIG. Fig. 6A )'s floor plan of some components.

[0117] Fig. 6A as well as FIG. 6C to FIG. 6E It is shown Figure 4 0 and an enlarged view of the overlapping area OVA and an area adjacent to the overlapping area OVA shown in FIG. Fig. 6A The signal line SGL, the sensing line TL and the shielding layer SDL on the circuit board PCB are shown. Figure 6C Only shown Fig. 6A The signal line SGL, Fig.6D Only shown Fig. 6A The sensing line TL, Fig. 6E Only shown Fig. 6A The shielding layer SDL.

[0118] Reference FIG. 6A to FIG. 6C, in the overlapping area OVA, each of the signal lines SGL may extend in a first extension direction and may be arranged in a direction perpendicular to the first extension direction. According to some embodiments, the first extension direction may be a direction parallel to the first direction DR1. In other words, in the overlapping area OVA, the signal line SGL may extend in the first direction DR1 and may be arranged in the second direction DR2. The following description will be made based on the first extension direction being a direction parallel to the first direction DR1.

[0119] According to some embodiments, the signal lines SGL may be arranged so that every two signal lines form a pair. The signal lines SGL may be arranged in such a manner that two signal lines are arranged adjacent to each other, and the distance between the two signal lines forming a pair may be narrower than the distance between two pairs of signal lines adjacent to each other but forming mutually different pairs. However, the present disclosure is not limited thereto, and all signal lines SGL may be arranged at a uniform distance. Even in this case, the signal lines SGL are considered to be arranged while every two signal lines adjacent to each other form a pair, and the distance between the two signal lines forming a pair is considered to be equal to the distance between the two pairs of signal lines adjacent to each other but forming mutually different pairs.

[0120] In the present specification, each of the two signal lines forming any pair of signal lines SGL may be defined as a first signal line SGL1, and two signal lines forming another pair of signal lines adjacent to the pair of signal lines may be defined as a second signal line SGL2. For example, the first signal line SGL1 may correspond to the i-th pair of signal lines (i.e., the 2i-1-th signal line and the 2i-th signal line) in the signal lines SGL, and the second signal line SGL2 may correspond to the i+1-th pair of signal lines (i.e., the 2i+1-th signal line and the 2i+2-th signal line). In this case, 'i' is a natural number greater than 0.

[0121] Fig. 6A and Figure 6C It is shown that 10 signal lines SGL are positioned in the overlap area OVA and intersect the sensing lines TL when viewed in a plan view. Fig. 6A and Figure 6C The number of signal lines SGL positioned in the overlap area OVA is shown, but embodiments according to the present disclosure are not limited to any embodiment.

[0122] like Figure 6B As shown in , a circuit board PCB according to some embodiments may include a base layer BL, a lower insulating layer IL_B positioned on the base layer BL, a first insulating layer IL1 and a second insulating layer IL2 sequentially stacked on the lower insulating layer IL_B, and a cover layer CVL positioned on the second insulating layer IL2.

[0123] Each of the base layer BL, the lower insulating layer IL_B, the first insulating layer IL1, the second insulating layer IL2, and the cover layer CVL may include an insulating material. Each of the base layer BL, the lower insulating layer IL_B, the first insulating layer IL1, the second insulating layer IL2, and the cover layer CVL may include an organic insulating material, and the organic insulating material may include a polymer material such as polyimide (PI), polyethylene terephthalate (PET), and polyethylene terephthalate. For example, each of the base layer BL, the lower insulating layer IL_B, the first insulating layer IL1, the second insulating layer IL2, and the cover layer CVL may include polyimide (PI).

[0124] According to some embodiments, the signal line SGL may be positioned on the lower insulating layer IL_B and covered by the first insulating layer IL1 .

[0125] Reference Fig. 6A , Figure 6B and Fig.6D , in the overlapping area OVA, the sensing lines TL may extend in the second extension direction, respectively, and may be arranged in a direction perpendicular to the second extension direction. The second extension direction may be a direction intersecting the first extension direction along which the signal line SGL extends. According to some embodiments, the second extension direction may be a direction perpendicular to the first extension direction and parallel to the second direction DR2. In other words, in the overlapping area OVA, each of the sensing lines TL may extend in the second direction DR2, and may be arranged in the first direction DR1. However, the present disclosure is not limited thereto, and the second extension direction is not perpendicular to the first extension direction, and may be a direction intersecting the first extension direction.

[0126] In the present specification, two sensing lines TL located adjacent to each other among the sensing lines TL may be defined as a first sensing line TL1 and a second sensing line TL2, respectively. For example, the first sensing line TL1 may correspond to the jth sensing line among the sensing lines TL, and the second sensing line TL2 may correspond to the j+1th sensing line among the sensing lines TL. In this case, 'j' is a natural number greater than 0.

[0127] According to some embodiments, the sensing lines TL may be arranged at a uniform distance. In other words, all the sensing lines TL have an equal distance between adjacent sensing lines TL. However, the present disclosure is not limited thereto, and the sensing lines TL may be arranged at different distances depending on the position. Alternatively, a plurality of sensing lines TL form a group, and the sensing lines may be arranged at a uniform distance within a group, and the group may be arranged at a wider distance.

[0128] Fig. 6A and Fig.6D It is shown that six sensing lines TL are placed in the overlapping area OVA and cross the signal lines SGL. Fig. 6A and Fig.6D The number of sensing lines TL positioned in the overlap area OVA is illustrated, and embodiments according to the present disclosure are not limited to any embodiment.

[0129] According to some embodiments, the sensing line TL may be positioned on the signal line SGL. The sensing line TL may be positioned on the second insulating layer IL2 to be covered by the cover layer CVL.

[0130] Reference Fig. 6A , Figure 6B and Fig. 6E , an opening OP having a specific pattern may be defined in the overlapping area OVA of the shielding layer SDL. Each of the openings OP defined in the shielding layer SDL may extend in the second extension direction and may be arranged in a direction perpendicular to the second extension direction. According to some embodiments, each of the openings OP may extend in the second direction DR2 and may be arranged in the first direction DR1.

[0131] In the present specification, two of the openings OP positioned adjacent to each other may be respectively defined as a first opening OP1 and a second opening OP2. For example, the first opening OP1 may correspond to the kth opening of the openings OP, and the second opening OP2 may correspond to the k+1th opening of the openings OP. In this case, 'k' is a natural number greater than 0.

[0132] Since the openings OP having a specific pattern are defined in the shielding layer SDL, the shielding layer SDL may include an extension area EA arranged to be spaced apart from each other and a peripheral area SA surrounding the extension area EA. The extension area EA may be defined as an area between adjacent openings OP. Corresponding to the extension direction and arrangement direction of the openings OP, the extension area EA may also be arranged in a direction perpendicular to the second extension direction while extending in the second extension direction. According to some embodiments, each of the extension areas EA may extend in the second direction DR2 and may be arranged in the first direction DR1. The following description will be based on the second extension direction being a direction parallel to the second direction DR2.

[0133] When viewed in a plan view, the opening OP may have a rectangular shape having longer sides extending in the second direction DR2. Therefore, when viewed in a plan view, each of the extension areas EA may also have a rectangular shape having longer sides extending in the second direction DR2.

[0134] According to some embodiments of the present disclosure, a dummy opening OP-D having a specific pattern may be further defined in the shielding layer SDL outside the overlapping area OVA. According to some embodiments, the dummy opening OP-D may be defined to have a pattern similar to that of the opening OP. More specifically, the dummy opening OP-D may be spaced apart from the opening OP in the first direction DR1, and the dummy opening OP-D may extend in the second direction DR2 and may be arranged in the first direction DR1.

[0135] When dummy openings OP-D having a specific pattern are further defined in the shielding layer SDL, the shielding layer SDL may further include dummy extension areas EA-D arranged to be spaced apart from each other and surrounded by the peripheral area SA. The dummy extension area EA-D may be defined as an area between adjacent dummy openings OP-D or an area between adjacent dummy openings OP-D and the opening OP.

[0136] The shielding layer SDL according to some embodiments may be positioned between the signal line SGL and the sensing line TL. The shielding layer SDL may be positioned on the first insulating layer IL1 and covered by the second insulating layer IL2.

[0137] Reference FIG. 6A to FIG. 6E , when viewed in a plan view, the sensing line TL positioned in the overlapping area OVA may be positioned in each space between adjacent openings OP. Hereinafter, a pair of first openings OP1 and a second opening OP2 of the opening OP, an extension area (hereinafter, referred to as extension area EAp) defined by the pair of first openings OP1 and the second opening OP2, and a sensing line (hereinafter, referred to as "sensing line TLp") positioned between the pair of first openings OP1 and the second opening OP2 will be representatively described, which is commonly applied to all sensing lines TL positioned in the overlapping area OVA.

[0138] When viewed in a plan view, a portion of the sensing line TLp may be disposed between the first opening OP1 and the second opening OP2, and the sensing line TLp may not overlap the first opening OP1 and the second opening OP2, respectively. When viewed in a plan view, a portion of the sensing line TLp may overlap an extension area EAp defined by the first opening OP1 and the second opening OP2 of the shielding layer SDL.

[0139] According to some embodiments, when viewed in a plan view, a distance d between the first opening OP1 and the second opening OP2 may be greater than or substantially equal to a width Wt of the sensing line TLp in the first direction DR1. The spacing distance d between the first opening OP1 and the second opening OP2 is the same as a width Ws of the extension area EAP in the first direction DR1. Therefore, the width Ws of the extension area EAP in the first direction DR1 may also be greater than or substantially equal to a width Wt of the sensing line TL in the first direction DR1. In the specification, the meaning of “substantially equal” may include a case where a difference is generated due to a process error in a process of forming the sensing line TL and / or forming the opening OP in the shielding layer SDL.

[0140] Fig. 6A It is shown that the distance d between the first opening OP1 and the second opening OP2 (ie, the width Ws of the extended area EAp) is equal to the width Wt of the sensing line TLP.

[0141] When viewed in a plan view, the sensing line TLp may cross the signal line SGL between the first opening OP1 and the second opening OP2 . In other words, when viewed in a plan view, the sensing line TLp may cross the signal line SGL in a region overlapping the extension area EA.

[0142] According to some embodiments, when viewed in a plan view, each of the first opening OP1 and the second opening OP2 may intersect all signal lines SGL positioned in the overlapping area OVA. Specifically, when viewed in a plan view, each of the first opening OP1 and the second opening OP2 may extend continuously to intersect all signal lines SGL positioned in the overlapping area OVA. Therefore, each of the signal lines SGL is partially exposed from the shielding layer SDL through the first opening OP1, and another portion may be exposed from the shielding layer SDL through the second opening OP2.

[0143] In the present specification, the extension area of ​​the extension area EA overlapping the first sensing line TL1 may be defined as the first extension area EA1, and the extension area of ​​the extension area EA overlapping the second sensing line TL2 may be defined as the second extension area EA2. For example, the first extension area EA1 may correspond to the jth extension area overlapping the jth sensing line, and the second extension area EA2 may correspond to the j+1th extension area overlapping the j+1th sensing line.

[0144] According to some embodiments, when viewed from the bottom of the circuit board PCB, since the shielding layer SDL covers the sensing line TL, the sensing line TL may not include any portion directly facing the signal line SGL without placing a separate shielding layer SDL between the sensing line TL and the signal line SGL. Therefore, the influence of the high-frequency signal transmitted through the signal line SGL can be reduced. In other words, the noise generated in the sensing line TL can also be reduced by reducing the coupling phenomenon between the sensing line TL and the signal line SGL.

[0145] In addition, according to some embodiments, the area of ​​the region where the signal line SGL and the shielding layer SDL face each other can be reduced by forming an opening OP in the shielding layer SDL. Therefore, by reducing the phenomenon that the characteristic impedance value of the signal line SGL decreases compared to the target value, the signal line SGL can have a characteristic impedance value close to the target value. In this case, since the opening OP of the shielding layer SDL is formed not to overlap with the sensing line TL, the signal line SGL can have a suitable characteristic impedance value and reduce the noise generated in the sensing line TL. Therefore, the quality of the high-frequency drive signal transmitted through the signal line SGL can be improved, and the accuracy and reliability of the input sensing can be improved. The details will be described later with Table 1.

[0146] Fig. 6A , Fig.6D and Fig. 6E It is shown that the sensing lines TL have the same width and are arranged at a uniform distance, so the openings OP also have equal widths and are arranged at a uniform distance. However, the present disclosure is not limited thereto, and the sensing lines TL may be designed to have different widths according to the positions, and the openings OP may also be arranged at different distances from each other according to the widths of the sensing lines TL adjacent to each other. Alternatively, the sensing lines TL may be arranged at different distances according to the positions, and the openings OP may also have different widths according to the intervals between the sensing lines TL adjacent to each other.

[0147] According to some embodiments, when viewed in a plan view, each of the dummy extension areas EA-D may be in a non-overlapping state with the sensing line TL. In other words, when viewed in a plan view, the sensing line TL may not be positioned between adjacent dummy openings OP-D or between adjacent dummy openings OP-D and the opening OP.

[0148] When viewed in a plan view, each of the dummy openings OP-D may cross at least some of the signal lines SGL passing through the overlap area OVA. Fig. 6AIt is shown that the dummy openings OP-D intersect all the signal lines SGL passing through the overlap area OVA when viewed in a plan view. However, the present disclosure is not limited thereto, and each of the dummy openings OP-D may extend to intersect only some of the signal lines SGL passing through the overlap area OVA.

[0149] According to some embodiments, the area of ​​the region of the signal line SGL facing the shielding layer SDL may be controlled by the length and / or width of each of the dummy openings OP-D so that the signal line SGL may have a suitable characteristic impedance value.

[0150] Meanwhile, according to some embodiments of the present disclosure, due to a process error occurring in a process of forming the sensing lines TL and / or forming the openings in the shielding layer SDL, some of the sensing lines TL may be formed to overlap adjacent openings.

[0151] like Figure 6B As shown in , according to some embodiments, the power line PWL may be positioned on the circuit board PCB. According to some embodiments, the power line PWL may be positioned under the signal line SGL in the overlapping area OVA. The power line PWL may be positioned on the base layer BL to be covered by the lower insulating layer IL_B. Figure 6B The power line PWL can correspond to Figure 4 , but the present disclosure is not limited thereto. For example, the power line PWL may correspond to a power line for providing a voltage to the display module DM (see Figure 2 ) of any of the various lines.

[0152] Hereinafter, various embodiments of the circuit board PCB will be described. In addition, the description of the circuit board according to various embodiments will be described while focusing on mutually different components of the circuit board PCB, and the same components will be assigned reference numerals.

[0153] Fig. 7A and Figure 7B is an enlarged plan view of some components of a circuit board PCBa according to some embodiments of the present disclosure. Fig. 7A Shown with Fig. 6A The corresponding floor plan.

[0154] Reference Fig. 7A and Figure 7B According to some embodiments, the signal line SGL, the sensing line TL, the shielding layer SDL, and the ground line GRL may be positioned in the overlapping area OVA of the circuit board PCBa. Fig. 6A Compared with the circuit board PCB shown in FIG. 1 , the ground line GRL passing through the overlapping area OVA can be further positioned Fig. 7A The circuit board PCBa shown in FIG.

[0155] Figure 7B A plane of a signal line SGL and a ground line GRL positioned on the lower insulating layer IL_B is shown. According to some embodiments, the ground line GRL may be positioned on the same layer as the signal line SGL. The ground line GRL may include two first sub-ground lines GRL1 and second sub-ground lines GRL2, the two first sub-ground lines GRL1 being positioned on opposite sides of the signal line SGL in the overlapped area OVA and spaced apart from each other in the second direction DR2, and each of the second sub-ground lines GRL2 being positioned between different pairs of the signal lines SGL.

[0156] According to some embodiments, the plane shapes of the sensing line TL and the shielding layer SDL positioned in the overlap area OVA may correspond to Fig.6D and Fig. 6E , so its detailed description will be omitted.

[0157] According to some embodiments, when viewed in a plan view, the sensing lines TL positioned in the overlapped area OVA may cross the second sub-ground line GRL2. In other words, when viewed in a plan view, each of the sensing lines TL positioned in the overlapped area OVA may cross the second sub-ground line GRL2 in an area overlapping the corresponding extension area EA.

[0158] When viewed in a plan view, the first opening OP1 and the second opening OP2 may intersect all of the second sub-ground lines GRL2 positioned in the overlapped area OVA. Therefore, each of the second sub-ground lines GRL2 is partially exposed from the shielding layer SDL through the first opening OP1, and another portion may be exposed from the shielding layer SDL through the second opening OP2.

[0159] When viewed in a plan view, the first sub-ground line GRL1 may overlap with the peripheral area SA of the shielding layer SDL. In other words, when viewed in a plan view, since the first sub-ground line GRL1 is in a non-overlapping state with the opening OP of the shielding layer SDL, the first sub-ground line GRL1 may not be exposed from the shielding layer SDL.

[0160] According to some embodiments, the noise generation caused by the coupling phenomenon between the signal lines SGL can be reduced by setting the second sub-ground line GRL2 between the adjacent signal lines SGL. In addition, by setting the first sub-ground line GRL1 on both sides of the signal line SGL, the noise generation caused by the coupling phenomenon between the signal line SGL and other adjacent wirings can be reduced.

[0161] Fig. 8A and Figure 8B is an enlarged plan view of some components of the circuit board PCBb according to some embodiments of the present disclosure. Fig. 8A Shown with Fig. 6AThe corresponding floor plan. Fig. 8A The signal line SGL, the sensing line TL and the shielding layer SDL′ positioned in the overlapping area OVA are shown. Figure 8B Shows Fig. 8A According to some embodiments, the planar shapes of the signal line SGL and the sensing line TL positioned in the overlap area OVA may correspond to Figure 6C and Fig.6D , so its detailed description will be omitted.

[0162] Reference Fig. 8A and Figure 8B , an opening OP' having a specific pattern may be defined in the shielding layer SDL'. According to some embodiments, in the overlapping area OVA, the opening OP' defined in the shielding layer SDL' may extend in the second extension direction, and may be arranged in a direction perpendicular to the second extension direction and the second extension direction, respectively. According to some embodiments, the second extension direction may be a direction parallel to the second direction DR2. In other words, each of the openings OP' may extend in the second direction DR2, and may be arranged in the first direction DR1 and the second direction DR2, respectively. The following description will be made based on the second extension direction being a direction parallel to the second direction DR2.

[0163] According to some embodiments, two openings in the opening OP' that are positioned adjacent to each other in the first direction DR1 may be defined as a first opening OP1' and a second opening OP2', respectively. Openings in the opening OP' that are adjacent to each other in the second direction DR2 from the first opening OP1' and the second opening OP2' may be defined as a third opening OP3' and a fourth opening OP4', respectively. For example, the first opening OP1' may correspond to an opening placed in the kth row and the lth column of the opening OP', and the second opening OP2' may correspond to an opening placed in the k+1th row and the lth column of the opening OP'. The third opening OP3' may correspond to an opening positioned in the kth row and the l+1th column of the opening OP', and the fourth opening OP4' may correspond to an opening positioned in the k+1th row and the l+1th column of the opening OP'. In this case, 'k' and 'l' are natural numbers greater than 0.

[0164] According to some embodiments, each of the distance d1 between the first opening OP1′ and the second opening OP2′ and the distance d2 between the third opening OP3′ and the fourth opening OP4′ may be greater than or substantially equal to the width Wt of the corresponding sensing line TL in the first direction DR1 (see FIG. 2 ). Fig.6D ).

[0165] Since the opening OP' having a specific pattern is defined in the shielding layer SDL', the shielding layer SDL' may include an extension area EA', an intersection area CA, and a peripheral area SA surrounding the extension area EA' and the intersection area CA, which are spaced apart from each other, each of the intersection areas CA being intersecting with the extension area EA' while being placed between the extension areas EA'.

[0166] According to some embodiments, the extension area EA' may be defined as an area between adjacent openings OP' in the first direction DR1. In other words, the extension area EA' may be defined as an area between the first opening OP1' and the second opening OP2' (or between the third opening OP3' and the fourth opening OP4'). Each of the extension areas EA' may extend in the second direction DR2 and may be arranged in the first direction DR1 and the second direction DR2, respectively.

[0167] The intersection area CA extends in the first direction DR1 and may be positioned between the opening OP' located in the lth column and the opening OP' located in the l+1th column. In other words, the intersection area CA may be positioned between the first opening OP1' and the third opening OP3' and between the second opening OP2' and the fourth opening OP4'. Each of the intersection areas CA may extend in the first direction DR1 and may be arranged in the second direction DR2.

[0168] According to some embodiments, when viewed in a plan view, the first signal line SGL1 may cross the first opening OP1' and the second opening OP2', respectively, and when viewed in a plan view, the second signal line SGL2 may cross the third opening OP3' and the fourth opening OP4', respectively. Therefore, when viewed in a plan view, a portion of each of the first signal lines SGL1 may be partially exposed from the shielding layer SDL' through the first opening OP1', and another portion of each of the first signal lines SGL1 may be partially exposed from the shielding layer SDL' through the second opening OP2'. A portion of each of the second signal lines SGL2 may be partially exposed from the shielding layer SDL' through the third opening OP3', and another portion of each of the second signal lines SGL2 may be partially exposed from the shielding layer SDL' through the fourth opening OP4'.

[0169] The first signal line SGL1 may cross the corresponding sensing line TL between the first and second openings OP1 ′ and OP2 ′ when viewed in a plan view, and the second signal line SGL2 may cross the corresponding sensing line TL between the third and fourth openings OP3 ′ and OP4 ′ when viewed in a plan view.

[0170] Fig. 8AIt is shown that one opening OP' or one extension area EA' crosses two signal lines SGL when viewed in a plan view and one opening OP' or one extension area EA' may extend while crossing various numbers of signal lines SGL.

[0171] According to some embodiments of the present disclosure, a dummy opening OP-D' having a specific pattern may be further defined in the shielding layer SDL' outside the overlapping area OVA. According to some embodiments, the dummy opening OP-D' may be defined to have a pattern similar to that of the opening OP'. More specifically, the dummy opening OP-D' may be spaced apart from the opening OP' in the first direction DR1, and each of the dummy openings OP-D' may extend in the second direction DR2 and may be arranged in the first direction DR1 and the second direction DR2.

[0172] According to some embodiments, two dummy openings located adjacent to each other in the second direction DR2 among the dummy openings OP-D' may be defined as a first dummy opening OP1-D' ​​and a second dummy opening OP2-D', respectively. For example, the first dummy opening OP1-D' ​​may correspond to a dummy opening placed in the mth row and the nth column, and the second dummy opening OP2-D' may correspond to a dummy opening placed in the mth row and the n+1th column. In this case, 'm' and 'n' are natural numbers greater than 0.

[0173] When the dummy opening OP-D' having a specific pattern is further defined in the shielding layer SDL', the shielding layer SDL' may further include dummy extension areas EA-D' arranged to be spaced apart from each other and dummy intersection areas CA-D extending from the intersection area CA and intersecting the dummy extension areas EA-D' between the dummy extension areas EA-D'. The dummy extension areas EA-D' and the dummy intersection areas CA-D may be surrounded by the peripheral area SA.

[0174] According to some embodiments, when viewed in a plan view, each of the dummy extension areas EA-D' may be in a non-overlapping state with the sensing line TL. In other words, when viewed in a plan view, the sensing line TL is not placed between adjacent dummy openings OP-D' or between adjacent dummy openings OP-D' and opening OP'.

[0175] When viewed in a plan view, each of the first signal lines SGL1 may cross the first dummy opening OP1-D', and when viewed in a plan view, each of the second signal lines SGL2 may cross the second dummy opening OP2-D'. Therefore, each of the first signal lines SGL1 may be partially exposed from the shielding layer SDL' through the first dummy opening OP1-D', and each of the second signal lines SGL2 may be partially exposed from the shielding layer SDL' through the second dummy opening OP2-D'.

[0176] Fig. 8A It is shown that the dummy opening OP-D′ or the dummy extension area EA-D′ crosses two signal lines SGL when viewed in a plan view and the dummy opening OP-D′ or the dummy extension area EA-D′ may extend to cross various numbers of signal lines SGL.

[0177] Meanwhile, according to some embodiments of the present disclosure, the circuit board PCBb may also include the above reference Figure 7B The ground line GRL described above. Figure 7B , Fig. 8A and Figure 8B , the ground line GRL may include a first sub-ground line GRL1 and a second sub-ground line GRL2.

[0178] According to some embodiments, the second sub-ground line GRL2 may be arranged to overlap the intersection areas CA, respectively. The second sub-ground line GRL2 may be placed between the first opening OP1' and the third opening OP3' and between the second opening OP2' and the fourth opening OP4'. Therefore, when viewed in a plan view, the second sub-ground line GRL2 may be covered by the shielding layer SDL'.

[0179] However, the embodiments according to the present disclosure are not limited thereto, and when viewed in a plan view, the second sub-grounding line GRL2 may be arranged to intersect with the opening OP' to be exposed from the shielding layer SDL' through the opening OP', and only some of the second sub-grounding lines GRL2 may be arranged to overlap with the intersection area CA, and the remaining grounding lines of the second sub-grounding lines GRL2 may be arranged to intersect with the opening OP'.

[0180] 9A to 9C is an enlarged plan view of some components of a circuit board PCBc according to some embodiments of the present disclosure. Fig.9A Shown with Fig. 6A The corresponding floor plan. Fig.9A The signal line SGL, the sensing line TLc, and the shielding layer SDL positioned in the overlapping area OVA are shown. Fig. 9B It is shown in Fig.9A The sensing line TLc, Fig. 9C It is shown in Fig.9A According to some embodiments, since the planar shape of the signal line SGL positioned in the overlap area OVA may correspond to Figure 6C , so its details will be omitted.

[0181] Refer to 9A to 9C, each of the sensing lines TLc positioned in the overlapping area OVA may include a first portion P1 extending in the second extension direction and a second portion P2 extending from the first portion P1 in a third extension direction. The third extension direction may be a direction intersecting the first extension direction and the second extension direction. According to some embodiments, the second extension direction may be a direction parallel to the second direction DR2, and the third extension direction may be a direction parallel to a fourth direction DR4, and the fourth direction DR4 is defined as a direction intersecting the first direction DR1 and the second direction DR2. In other words, according to some embodiments, each of the sensing lines TLc may include a portion bent in the overlapping area OVA. The following description will be made based on the second extension direction being a direction parallel to the second direction DR2 and the third extension direction being a direction parallel to the fourth direction DR4.

[0182] Each of the openings OP” may include a first opening area OA1 extending in the second direction DR2 and a second opening area OA2 extending from the first opening area OA1 in the fourth direction DR4. The first opening area OA1 of each of the first opening OP1” and the second opening OP2” may extend in parallel along the first portion P1 of the corresponding sensing line TLc, and the second opening area OA2 of each of the first opening OP1” and the second opening OP2” may extend along the second portion P2 of the corresponding sensing line TLc.

[0183] Therefore, each of the extended areas EA" of the shielding layer SDL" may include a first area A1 extending in the second direction DR2 and a second area A2 extending from the first area A1 in the fourth direction DR4. The first area A1 may overlap with the first portion P1 of the corresponding sensing line TLc, and the second area A2 may overlap with the second portion P2 of the corresponding sensing line TLc.

[0184] According to some embodiments, when viewed in a plan view, each of the sensing lines TLc may cross a portion of the signal lines SGL in the first portion P1, and may cross a remaining portion of the signal lines SGL in the second portion P2. For example, the first portion P1 of the sensing line TLc may cross each of the first signal lines SGL1, and the second portion P2 of the sensing line TLc may cross each of the second signal lines SGL2. In addition, the first signal line SGL1 may be partially exposed from the shielding layer SDL" through the first opening area OA1 of each of the first opening OP1" and the second opening OP2", and the second signal line SGL2 may be partially exposed from the shielding layer SDL" through the second opening area OA2 of each of the first opening OP1" and the second opening OP2".

[0185] According to some embodiments of the present disclosure, the dummy opening OP-D" may be further defined in the shielding layer SDL", and the dummy opening OP-D" may be defined as having a pattern similar to the pattern of the opening OP" outside the overlapping area OVA. Each of the dummy openings OP-D" may include a first dummy opening area OA1-D extending in the second direction DR2 and a second dummy opening area OA2-D extending from the first dummy opening area OA1-D in the fourth direction DR4.

[0186] When the dummy opening OP-D" is further defined in the shielding layer SDL", the shielding layer SDL" may also include dummy extension areas EA-D". Spaced apart from each other and surrounded by the peripheral area SA. Each of the dummy extension areas EA-D" may include a first dummy area A1-D extending in the second direction DR2 and a second dummy area A2-D extending from the first dummy area A1-D in the fourth direction DR4.

[0187] Fig. 10A 1 is an enlarged plan view of some components of the circuit board PCB-1 according to the first comparative example. Fig. 10A , the signal line SGL- 1 , the sensing line TL- 1 , and the shielding layer SDL- 1 are shown in the overlapping area OVA- 1 . Fig. 10A Six signal lines SGL- 1 and six sensing lines TL- 1 are shown crossing each other when viewed in a plan view.

[0188] Reference Fig. 10A , the opening OP-1 may be defined in the shielding layer SDL-1 to have a grid-shaped pattern. The shielding layer SDL-1 may include a first grid line MSL1 extending in a fourth direction DR4 and a second grid line MSL2 extending in a fifth direction DR5, and the grid-shaped pattern may be formed by the first grid line MSL1 and the second grid line MSL2. The fourth direction DR4 is defined as a direction crossing the first direction DR1 and the second direction DR2, and the fifth direction DR5 is defined as a direction perpendicular to the fourth direction DR4. The opening OP-1 may be defined by the first grid line MSL1 and the second grid line MSL2.

[0189] The signal line SGL- 1 may extend in the first direction DR1 . When viewed in a plan view, the signal line SGL- 1 may cross the mesh lines MSL1 and MSL2 .

[0190] The sensing line TL-1 may extend in the second direction DR2. When viewed in a plan view, the sensing line TL-1 may cross the mesh lines MSL1 and MSL2.

[0191] Fig. 10B1 is an enlarged plan view of some components of the circuit board PCB-2 according to the second comparative example. Fig. 10B , the signal line SGL- 2 , the sensing line TL- 2 , and the shielding layer SDL- 2 are shown in the overlapping area OVA- 2 . Fig. 10B Six signal lines SGL- 2 and six sensing lines TL- 2 are shown crossing each other when viewed in a plan view.

[0192] Reference Fig. 10B , the shielding layer SDL-2 may be implemented as a through electrode without defining an opening in the overlapping area OVA-2 and without having a separate pattern. In other words, in the overlapping area OVA-2, all the signal lines SGL-2 and the sensing lines TL-2 may overlap with the shielding layer SDL-2, and when viewed in a plan view, the signal lines SGL-2 may be covered by the shielding layer SDL-2. Fig. 10B In FIG. 1 , the signal line SGL- 2 is shown as a dotted line.

[0193] Table 1 shows that in the case of the first comparative example, the second comparative example, and the present embodiment, the coupling voltage (mV) generated from the sensing line and the characteristic impedance (Ω) of the signal line are measured and shown. In each of the first comparative example, the second comparative example, and the present embodiment, a shielding layer having a different shape is applied. In the first comparative example, as Fig. 10A As shown in , the shielding layer SDL-1 has a mesh-shaped pattern in a region where the signal line SGL-1 and the sensing line TL-1 overlap each other. Fig. 10B As shown in , the shielding layer SDL-2 is provided as a through electrode in a region where the signal line SGL-2 and the sensing line TL-2 overlap each other. Fig. 6A As shown in FIG. 1 , the shielding layer SDL includes an extension area EA extending side by side along the sensing line TL, and the extension area EA includes an opening OP positioned between the sensing lines TL in an area where the signal line SGL and the sensing line TL overlap each other. Fig. 6A , Fig. 10A and Fig. 10B To describe the measurement results values ​​in Table 1.

[0194] Table 1

[0195] Coupling voltage [mV] Characteristic impedance [Ω] First comparison example 21 95 Second comparison example 0.5 75 This embodiment 2.2 86

[0196] The coupling voltage (mV) generated in the sensing line is caused by a coupling phenomenon due to the crossing of the sensing line with the signal line transmitting a high-frequency signal, and the first comparative example, the second comparative example and the present embodiment are compared with each other in terms of noise caused in the sensing line.

[0197] Referring to the results of Table 1, the coupling voltage increases in the order of the second comparative example, the present embodiment, and the first comparative example.

[0198] In the second comparative example, since the shielding layer SDL-2 is disposed to overlap the sensing line TL-2 and the signal line SGL-2 within the overlapping area OVA-2, a coupling voltage generated in the sensing line TL-2 due to a high-frequency signal transmitted to the signal line SGL-2 can be low. In other words, in the second comparative example, a smaller amount of noise can be generated in a driving signal transmitted or received by the sensing line TL-2.

[0199] Meanwhile, in the first comparative example, since the opening OP-1 of the shielding layer SDL-1 overlaps some of the signal lines SGL-1 and some of the sensing lines TL-1 in the overlapping area OVA-1, the high-frequency signal transmitted to the signal line SGL-1 may generate a high coupling voltage in the sensing line TL-1 through the opening OP-1. In other words, in the first comparative example, a large amount of noise may be generated in the driving signal transmitted or received through the sensing line TL-1.

[0200] According to some embodiments, the shielding layer SDL may be arranged to overlap with the sensing line TL within the overlapping area OVA, and some of the signal lines SGL may be exposed through the opening OP. Therefore, according to some embodiments, the coupling voltage generated in the sensing line TL due to the high-frequency signal transmitted through the signal line SGL may be higher than the coupling voltage of the second comparative example and lower than the coupling voltage of the first comparative example. According to some embodiments, a coupling voltage reduced by about 90% compared to the first comparative example may be generated in the sensing line TL. In other words, according to some embodiments, it can be confirmed that the sensing line TL of the present embodiment generates more noise than the second comparative example, but generates less noise than the first comparative example.

[0201] When the coupling voltage generated in the sensing line is 12mV or less, the error rate of the input sensing of the final product can have a small level, thereby maintaining a high level of accuracy and reliability. According to some embodiments, it can be appreciated that the coupling voltage generated in the sensing line TL of the present embodiment satisfies the condition of 12mV or less, thereby showing higher accuracy and reliability of input sensing.

[0202] In the circuit board used for this measurement, the target value of the characteristic impedance of the signal line is 100 (Ω). The characteristic impedance is measured with respect to the signal line according to the first comparative example, the second comparative example, and the present embodiment, and the first comparative example, the second comparative example, and the present embodiment are measured in consideration of the degree of approaching the appropriate characteristic impedance (the degree of reduction from the target value).

[0203] The impedance of the signal line becomes a function of resistance, conductance, capacitance, and inductance, as shown in Equation 1 below.

[0204] Equation 1

[0205]

[0206] In this case, Z o is the characteristic impedance of the signal line, R is the resistance, G is the conductance, ω is the radian frequency (i.e., 2πf), and j is L is the inductance and C is the capacitance of the signal line.

[0207] At high frequencies, the characteristic impedance is preferably determined by capacitance and inductance, and Equation 1 is abbreviated to Equation 2 below.

[0208] Equation 2

[0209]

[0210] In Equation 2, since inductance is proportional to magnetic field strength and capacitance is proportional to electric field strength, the characteristic impedance can be expressed as In this case, 'H' represents the strength of the magnetic field and 'E' represents the strength of the electric field. Therefore, the characteristic impedance is inversely proportional to the strength of the electric field.

[0211] Referring to the results of Table 1, according to the first comparative example, the signal line SGL-1 has a characteristic impedance reduced by 5% from the characteristic impedance of the target value. According to the second comparative example, the signal line SGL-2 has a characteristic impedance reduced by 25% from the characteristic impedance of the target value. According to some embodiments, the signal line SGL has a characteristic impedance reduced by 14% from the characteristic impedance of the target value. The degree of reduction of the characteristic impedance increases in the order of the first comparative example, the present embodiment, and the second comparative example.

[0212] In the first comparative example, since a relatively large portion of the signal line SGL-1 overlaps the opening OP-1 of the shielding layer SDL-1, the intensity of the electric field formed between the signal line SGL-1 and the shielding layer SDL-1 may be low. Therefore, it can be recognized that the signal line SGL-1 according to the first comparative example has a characteristic impedance in which the degree of reduction from the target value is small.

[0213] Meanwhile, in the second comparative example, since the signal line SGL-2 overlaps the shielding layer SDL-2 in all regions, the intensity of the electric field formed between the signal line SGL-2 and the shielding layer SDL-2 may be large. Therefore, it can be recognized that the signal line SGL-2 according to the second comparative example has a characteristic impedance in which the degree of reduction from the target value is large.

[0214] According to some embodiments, compared with the case where the shielding layer SDL-1 has a grid-shaped pattern, the portion where the signal line SGL overlaps the opening OP of the shielding layer SDL may be small. Therefore, the intensity of the electric field formed between the signal line SGL and the shielding layer SDL may be higher than that of the first comparative example but lower than that of the second comparative example. Therefore, it can be appreciated that the signal line SGL according to the present embodiment has a reduction degree from the target value that is greater than that of the first comparative example but less than that of the second comparative example.

[0215] When the characteristic impedance of the signal line is reduced by 15% or less from the target value, the high-frequency drive signal transmitted through the signal line is modified to a small extent in the final product. Therefore, higher quality can be maintained. According to some embodiments, the reduction degree of the characteristic impedance of the signal line SGL satisfies the condition of 15% or less. Therefore, it can be appreciated that, according to some embodiments, the high-frequency drive signal transmitted through the signal line SGL can have higher quality.

[0216] Therefore, as shown in Table 1, since the signal line SGL-1 according to the first comparative example has a characteristic impedance closer to the target value, the driving signal received through the signal line SGL-1 shows excellent quality. However, since noise is generated in a large amount in the sensing line TL-1, the accuracy of input sensing may be reduced. In contrast, in the second comparative example, since less noise is generated in the sensing line TL-2, the accuracy of input sensing can be improved. However, since the signal line SGL-2 shows a characteristic impedance having a large difference from the target value, the quality of the driving signal received through the signal line SGL-2 may be deteriorated.

[0217] On the contrary, according to some embodiments, it can be appreciated that the signal line SGL has a characteristic impedance within a suitable range, and the coupling voltage generated in the sensing line TL also falls within a range that does not affect the input sensing accuracy. Therefore, according to some embodiments, it can be appreciated that the quality of the driving signal received through the sensing line TL can be improved, while also improving the accuracy of the input sensing.

[0218] As described above, according to some embodiments, a shielding layer may be formed between a signal line and a sensing line and an opening having a specific pattern may be provided in the shielding layer so that the signal line has an impedance having suitable characteristics. In addition, since the coupling degree between the signal line and the sensing line adjacent to each other can be reduced, the noise generated in the sensing line is reduced. Therefore, the quality of the high-frequency drive signal transmitted through the signal line can be relatively improved, and the accuracy and reliability of the input sensing can be relatively improved.

[0219] Although aspects of some embodiments of the present disclosure have been described for illustrative purposes, it will be understood by those skilled in the art that various modifications and substitutions are possible without departing from the scope and spirit of the utility model disclosed in the appended claims. Therefore, the technical scope of the present disclosure is not limited to the detailed description of this specification, but should be defined by the claims and their equivalents.

[0220] Although aspects of some embodiments of the present disclosure have been described with reference to the embodiments thereof, it will be apparent to those skilled in the art that various changes and modifications may be made thereto without departing from the spirit and scope of the present disclosure as set forth in the claims and their equivalents.

Claims

1. A display device, characterized in that: The display device comprises: A display module including a display panel and an input sensing unit; and A circuit board connected to the display module, Wherein, the circuit board comprises: a first signal line electrically connected to the display panel and having at least a portion extending in a first extension direction; a sensing line electrically connected to the input sensing unit and having at least a portion extending in a second extending direction intersecting the first extending direction; and a shielding layer disposed between the first signal line and the sensing line and having a first opening and a second opening spaced apart from each other in a plane while interposing the sensing line therebetween, wherein at least a portion of each of the first opening and the second opening extends in the second extension direction, Wherein, in the plane, the sensing line crosses the first signal line between the first opening and the second opening, and Wherein, in the plane, a distance between the first opening and the second opening is greater than or equal to a width of the sensing line.

2. The display device according to claim 1, characterized in that In the plane, a portion of the first signal line is exposed from the shielding layer through each of the first opening and the second opening.

3. The display device according to claim 1, characterized in that The circuit board also includes: a second signal line electrically connected to the display panel, spaced apart from the first signal line, and extending parallel to the first signal line, and Wherein, in the plane, the second signal line crosses the sensing line between the first opening and the second opening.

4. The display device according to claim 3, characterized in that: The circuit board also includes: a ground line disposed between the first signal line and the second signal line and extending parallel to the first signal line, and Wherein, in the plane, a portion of the ground line is exposed from the shielding layer through each of the first opening and the second opening.

5. The display device according to claim 1, characterized in that The circuit board also includes: a second signal line electrically connected to the display panel, spaced apart from the first signal line, and extending parallel to the first signal line, wherein the shielding layer has a third opening and a fourth opening additionally defined in the shielding layer, the third opening and the fourth opening being arranged from the first opening and the second opening in the second extension direction, respectively, and being spaced apart from each other while placing the sensing line between the third opening and the fourth opening, Wherein, in the plane, the second signal line crosses the sensing line between the third opening and the fourth opening, and Wherein, in the plane, a distance between the third opening and the fourth opening is greater than or equal to a width of the sensing line.

6. The display device according to claim 5, characterized in that: The circuit board also includes: a ground line disposed between the first signal line and the second signal line and extending parallel to the first signal line, and Wherein, in the plane, the ground line is placed between the first opening and the third opening and between the second opening and the fourth opening.

7. The display device according to claim 1, characterized in that: The sensing line comprises: a first portion extending in the second extension direction; and a second portion extending in a third extension direction intersecting each of the first extension direction and the second extension direction, and Wherein, each of the first opening and the second opening comprises: A first opening region extending in the second extension direction; and A second opening region extends from the first opening region in the third extension direction.

8. The display device according to claim 7, characterized in that: The first portion is disposed between the first opening region of the first opening and the first opening region of the second opening, and The second portion is disposed between the second opening region of the first opening and the second opening region of the second opening.

9. The display device according to claim 1, characterized in that: The circuit board also includes: A substrate layer, below the first signal line; a first insulating layer disposed between the first signal line and the shielding layer; and The second insulating layer is disposed between the shielding layer and the sensing line.

10. The display device according to claim 9, characterized in that: The circuit board also includes: a lower insulating layer disposed between the base layer and the first signal line; and The electric field line is disposed between the base layer and the lower insulating layer.

11. A display device, characterized in that: The display device comprises: A display module including a display panel and an input sensing unit; and A circuit board connected to the display module, Wherein, the circuit board also includes: A first signal line electrically connected to the display panel; a shielding layer on the first signal line and including a first extension region and a second extension region spaced apart from each other and a peripheral region surrounding the first extension region and the second extension region; and a sensing line, on the shielding layer, electrically connected to the input sensing unit and comprising a first sensing line and a second sensing line, the first sensing line having a portion overlapping the first extension area, the second sensing line having a portion overlapping the second extension area, wherein, in a plane, the first sensing line crosses the first signal line in a region overlapping the first extension region, and the second sensing line crosses the first signal line in a region overlapping the second extension region, and In an area where the first extension area overlaps with the first sensing line, a width of the first extension area is greater than or equal to a width of the first sensing line.

12. The display device according to claim 11, characterized in that: The shielding layer also includes: a dummy extension region, spaced apart from the first extension region, extending parallel to the first extension region, and surrounded by the peripheral region, and Wherein, in the plane, the dummy extension area is in a non-overlapping state with the sensing line and crosses the first signal line.

13. The display device according to claim 11, characterized in that The shielding layer further includes a third extension region and a fourth extension region surrounded by the peripheral region, another portion of the first sensing line overlaps the third extension region, and another portion of the second sensing line overlaps the fourth extension region.

14. The display device according to claim 13, characterized in that: The circuit board also includes: a second signal line electrically connected to the display panel, spaced apart from the first signal line, and extending parallel to the first signal line, and Wherein, in the plane, the first sensing line crosses the second signal line in a region overlapping the third extension region, and the second sensing line crosses the second signal line in a region overlapping the fourth extension region.

15. The display device according to claim 11, characterized in that: The first signal line has at least a portion extending in a first extension direction in a region overlapping with the shielding layer, Wherein, the first sensing line comprises: a first portion extending in a second extension direction intersecting the first extension direction; and a second portion extending from the first portion in a third extension direction intersecting each of the first extension direction and the second extension direction, and Wherein, the first extension area includes: a first region extending in the second extending direction and overlapping the first portion; and a second region extending from the first region in the third extending direction and overlapping the second portion.

16. The display device according to claim 15, characterized in that: The shielding layer also includes: a dummy extension region, which is spaced apart from the first extension region, is in a non-overlapping state with the sensing line, and is surrounded by the peripheral region, and The dummy extension region includes a first dummy region extending in the second extension direction and a second dummy region extending from the first dummy region in the third extension direction.

17. The display device according to claim 11, characterized in that: The circuit board also includes: The ground line is spaced apart from the first signal line and extends parallel to the first signal line.

18. A display device, characterized in that: The display device comprises: a display module configured to provide an image and sense an external input; and A circuit board connected to the display module, Wherein, the circuit board also includes: a first line electrically connected to the display module to transmit a high-frequency signal and having at least a portion extending in a first extension direction; a second line electrically connected to the display module and having at least a portion extending in a second extending direction intersecting the first extending direction; and a shielding layer disposed between the first wire and the second wire and having a first opening and a second opening spaced apart from each other in a plane while interposing the second wire therebetween, wherein at least a portion of each of the first opening and the second opening extends in the second extension direction, wherein, in the plane, the second line intersects the first line between the first opening and the second opening, and In the plane, a distance between the first opening and the second opening is greater than or equal to a width of the second line.

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