Display device

Abstract

Disclosed is a display device including: a display panel including a light emitting element layer; a light conversion panel on the display panel; and a filling layer between the display panel and the light conversion panel, in which the light conversion panel includes: a light control layer including a separation pattern and a plurality of light controllers spaced apart from each other by the separation pattern; and a curing control layer under the partition pattern. The display device has relatively improved light extraction efficiency.

Description

[0001] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0056160, filed on Apr. 28, 2023, the contents of which are hereby incorporated by reference in their entirety. Technical Field

[0002] Aspects of some embodiments of the present disclosure relate herein to a display device and a method for manufacturing the display device. Background Art

[0003] Various multimedia display devices such as televisions, mobile phones, tablet computers, and game consoles include a display panel and a light conversion panel to provide image information to users.

[0004] The display panels each include a light emitting element and a pixel circuit for driving the light emitting element. The light conversion panels each include a light controller using quantum dots, and source light provided from the light emitting element of the display panel can be converted by the light controller to be provided as light having various colors.

[0005] The display panel and the light conversion panel may be combined with each other through a filling layer. It is necessary to study the filling layer for reducing light loss until the source light provided from the display panel reaches the light conversion panel.

[0006] The above information disclosed in this background section is only for enhancement of understanding of the background technology and therefore, the information discussed in this background section does not necessarily constitute prior art. Utility Model Content

[0007] Aspects of some embodiments of the present disclosure relate to a display device and a method for manufacturing the display device, for example, to a display device including a filling layer and a method for manufacturing the display device.

[0008] An object of some embodiments of the present disclosure is to provide a display device including a filling layer having a structure capable of reducing light loss to relatively improve light extraction efficiency and color reproducibility.

[0009] Some embodiments of the present disclosure also aim to provide a method for manufacturing a display device, which has relatively improved process properties and mass productivity.

[0010] According to some embodiments of the present disclosure, a display device includes: a display panel including a light emitting element layer; a light conversion panel on the display panel; and a filling layer between the display panel and the light conversion panel. According to some embodiments, the light conversion panel includes: a light control layer including a partition pattern and a plurality of light controllers spaced apart from each other by the partition pattern; and a curing control layer below the partition pattern.

[0011] According to some embodiments, the separation pattern and the curing control layer may overlap each other on a plane.

[0012] According to some embodiments, the filling layer may include a filling portion overlapping the plurality of light controllers on a plane and a void overlapping the separation pattern on a plane, and the filling portion may have a refractive index greater than that of the void.

[0013] According to some embodiments, the cure control layer may include a cure delay material.

[0014] According to some embodiments, the filling layer may include: a filling portion overlapping the plurality of light controllers in a plane; and a void overlapping the separation pattern in a plane, and the void may have a shape having a curvature in a cross section.

[0015] According to some embodiments, the filling layer may include: a filling portion overlapping the plurality of light controllers in a plane; and a void overlapping the separation pattern in a plane, and the void may have an elliptical shape in a cross section.

[0016] According to some embodiments, the curing control layer may have a top surface adjacent to the separation pattern and a bottom surface adjacent to the filling layer, and the bottom surface of the curing control layer may include an uneven structure.

[0017] According to some embodiments, the filling layer may include: a filling portion overlapping the plurality of light controllers on a plane; and a void overlapping the partition pattern on a plane. According to some embodiments, the void may have a top surface adjacent to the curing control layer and a bottom surface adjacent to the display panel, and the top surface of the void may have an area smaller than that of the bottom surface of the void on a plane.

[0018] According to some embodiments, the curing control layer may include a curing delay material, and the curing control layer may have a top surface adjacent to the separation pattern and a bottom surface adjacent to the filling layer. According to some embodiments, the bottom surface of the curing control layer may include an uneven structure.

[0019] According to some embodiments, the filling layer may include: a filling portion overlapping the plurality of light controllers on a plane; and a void overlapping the partition pattern on a plane. According to some embodiments, the void may have a top surface adjacent to the curing control layer and a bottom surface adjacent to the display panel, and the top surface of the void may have an area smaller than that of the bottom surface of the void on a plane.

[0020] According to some embodiments of the present disclosure, a method for manufacturing a display device includes: preparing a light conversion panel; bonding a display panel to the light conversion panel with a filling material between the display panel and the light conversion panel; and curing the filling material. According to some embodiments, the step of preparing the light conversion panel includes: forming a color filter layer on a base layer; forming a light control layer on the color filter layer, the light control layer including a separation pattern and a plurality of light controllers spaced apart from each other by the separation pattern; and forming a cured control layer on the separation pattern.

[0021] According to some embodiments, the step of curing the filling material may include an operation of curing and shrinking the filling material on the plurality of light controllers, and not curing the filling material on the separation pattern.

[0022] According to some embodiments, the step of curing the filling material may include an operation of forming a filling portion overlapping the plurality of light controllers on a plane and a gap overlapping the separation pattern on a plane.

[0023] According to some embodiments, the cure control layer may include a cure delay material that delays the cure of the filling material.

[0024] According to some embodiments, the step of solidifying the filling material may include an operation of forming a void overlapping the separation pattern in a plane, and the void may have a shape having a curvature in a cross section.

[0025] According to some embodiments, the void may have an elliptical shape in cross-section.

[0026] According to some embodiments, the curing control layer may include an uneven structure on a surface thereof adjacent to the filling material.

[0027] According to some embodiments, the step of curing the filling material may include an operation of forming a filling portion overlapping the plurality of light controllers on a plane and a void overlapping the partition pattern on a plane. According to some embodiments, the void may have a top surface adjacent to the curing control layer and a bottom surface adjacent to the display panel, and the top surface of the void may have an area formed smaller than an area of ​​the bottom surface of the void on a plane.

[0028] According to some embodiments, bonding the display panel to the light conversion panel may include applying a filling material.

[0029] According to some embodiments, in the step of forming the curing control layer, the curing control layer may be formed by a photolithography process.

[0030] According to some embodiments of the present invention, the curing control layer can suppress the flow of the filling material to adjust the curing and form a gap in the filling layer, and the light emitted from the display panel traveling toward the side surface can be totally reflected at the boundary of the gap to travel toward the light conversion panel. That is, the side loss can be reduced to relatively improve the light extraction efficiency of the display device. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The accompanying drawings are included to provide a further understanding of the utility model concept, and are incorporated in and constitute a part of this specification. The accompanying drawings illustrate embodiments of the utility model concept and, together with the description, are used to explain the principles of the utility model concept. In the accompanying drawings:

[0032] Figure 1A is a perspective view of a display device according to some embodiments of the present disclosure;

[0033] Figure 1B is a cross-sectional view of a display device according to some embodiments of the present disclosure;

[0034] Figure 2 is a plan view of a display panel according to some embodiments of the present disclosure;

[0035] Figure 3 is an equivalent circuit diagram of a pixel according to some embodiments of the present disclosure;

[0036] Figure 4 is an enlarged plan view of a display area according to some embodiments of the present disclosure;

[0037] Figures 5 to 7 are cross-sectional views of a portion of a display device according to some embodiments of the present disclosure;

[0038] Fig. 8A and Figure 8B are cross-sectional views of emission layers according to some embodiments of the present disclosure;

[0039] Fig.9A and Fig. 9B are flowcharts of methods for manufacturing a display device according to some embodiments of the present disclosure; and

[0040] Figures 10 to 13 Each is a cross-sectional view illustrating operations of a method for manufacturing a display device according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0041] The utility model can be modified in various forms, and its specific embodiments will be shown in the drawings and described in detail herein. The utility model concept should not be interpreted as being limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that the present disclosure will be thorough and complete, and will fully convey the scope of the utility model concept to those skilled in the art.

[0042] As used herein, the singular forms are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0043] It will also be understood that when terms such as “including” and “having” are used herein, it indicates the presence of the stated features, numbers, steps, operations, elements, parts or combinations thereof, but does not preclude the presence or addition of one or more other features, numbers, steps, operations, elements, parts or combinations thereof.

[0044] It will be understood that when an element (or region, layer, portion, etc.) is referred to as being "on," "connected to" or "coupled to" another element, the element (or region, layer, portion, etc.) can be directly positioned on, directly connected to or coupled to the other element, or a third intervening element can be positioned between the elements.

[0045] In addition, terms such as "below", "under", "on", and "over" are used to explain the relationship of elements shown in the drawings. These terms are relative concepts and are explained based on the directions shown in the drawings.

[0046] In the present disclosure, when a component is referred to as being “positioned above” another component, the component will be oriented above or below the other component.

[0047] As used herein, "directly positioned" may mean that there are no additional layers, films, regions, plates, etc. between a component such as a layer, film, region, plate, etc. and another component. For example, "directly positioned" may mean positioning two layers or two components without additional components such as adhesive components.

[0048] The term "and / or" used herein includes one or more combinations that may be defined by the relevant elements.

[0049] It will be understood that although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, without departing from the teachings of the present invention, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0050] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those commonly understood by ordinary technicians in the field to which the utility model belongs. It will also be understood that, unless so clearly defined herein, terms such as those defined in general dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant field, and will not be interpreted in an idealized or overly formal meaning.

[0051] The same reference numerals always represent the same elements. In addition, in the drawings, in order to effectively describe the technical contents, the thickness, ratio and size of the elements are exaggerated.

[0052] Hereinafter, a display device and a method for manufacturing the display device according to some embodiments of the present disclosure will be described in more detail with reference to the accompanying drawings.

[0053] Figure 1A is a perspective view of a display device DD according to some embodiments of the present disclosure. Figure 1B is a cross-sectional view of a display device DD according to some embodiments of the present disclosure.

[0054] Reference Figure 1A , the display device DD may display an image through the display surface DD-IS. The display surface DD-IS may be parallel to a plane defined by the first direction DR1 and the second direction DR2. The top surface of a member positioned at the uppermost side of the display device DD in the third direction DR3 may be defined as the display surface DD-IS.

[0055] The third direction DR3 may indicate a normal direction or a vertical direction of the display surface DD-IS (ie, a thickness direction of the display device DD). A front surface (or top surface) and a rear surface (or bottom surface) of each of the layers or units to be described below may be defined based on the third direction DR3.

[0056] The display device DD may include a display area DA and a non-display area NDA. The unit pixel PXU is positioned in the display area DA, and the unit pixel PXU is not positioned in the non-display area NDA. The non-display area NDA may be defined along the edge of the display surface DD-IS. The non-display area NDA may surround the display area DA. According to some embodiments of the present disclosure, the non-display area NDA may be omitted or positioned only at one side of the display area DA. Although Figure 1A A flat panel display device DD is shown as an example, but the display device DD may have a curved shape, may be foldable, may be rollable, or may be slidable from a housing.

[0057] Figure 1AThe unit pixel PXU shown in FIG. 1 may define pixel rows and pixel columns. Each of the unit pixels PXU is a minimum repeating unit, and the unit pixel PXU may include at least one pixel. The unit pixel PXU may include a plurality of pixels providing light having different colors from each other.

[0058] Reference Figure 1B , the display device DD may include a display panel DP and a light conversion panel OP facing the display panel DP and spaced apart from the display panel DP. The display panel DP may be referred to as a lower display substrate, and the light conversion panel OP may be referred to as an upper display substrate. A cell gap (e.g., a set or predetermined cell gap) may be provided between the display panel DP and the light conversion panel OP. The cell gap may be maintained by a sealing member SLM that combines the display panel DP and the light conversion panel OP with each other. The sealing member SLM may include an adhesive resin and an inorganic filler mixed in the adhesive resin. The sealing member SLM may also include other additives. The additives may include an amine curing agent and a photoinitiator. The additives may also include a silane additive and an acrylic additive. The sealing member SLM may include an inorganic material such as glass frit.

[0059] In each of the display panel DP and the light conversion panel OP, a display area DA and a non-display area NDA may be defined to substantially correspond to the display area DA and the non-display area NDA of the display device DD, respectively. Hereinafter, the display area DA of the display device DD may mean the display area DA of each of the display panel DP and the light conversion panel OP, and the non-display area NDA of the display device DD may mean the non-display area NDA of each of the display panel DP and the light conversion panel OP.

[0060] Figure 2 is a plan view of a display panel DP according to some embodiments of the present disclosure.

[0061] Figure 2 The arrangement relationship of the signal lines GL1 to GLm and DL1 to DLn and the pixels PX11 to PXmn is shown in a plan view. The signal lines GL1 to GLm and DL1 to DLn may include a plurality of gate lines GL1 to GLm and a plurality of data lines DL1 to DLn.

[0062] Each of the pixels PX11 to PXmn may be connected to a corresponding gate line among a plurality of gate lines GL1 to GLm and a corresponding data line among a plurality of data lines DL1 to DLn. Each of the pixels PX11 to PXmn may include a pixel driving circuit and a light emitting element. According to the configuration of the pixel driving circuit of the pixels PX11 to PXmn, more types of signal lines may be provided in the display panel DP. For example, each of the gate lines GL1 to GLm may include a corresponding scan line SCLi (see Figure 3 ) and the corresponding sensing line SSLi (see Figure 3 ).

[0063] The gate driver circuit GDC may be integrated in the display panel DP by an oxide semiconductor gate driver circuit (OSG) or an amorphous silicon gate driver circuit (ASG) process. The gate driver circuit GDC connected to the gate lines GL1 to GLm may be positioned at one side of the non-display area NDA in the first direction DR1. A pad (also referred to as a "pad" or "pad") PD connected to the ends of the plurality of data lines DL1 to DLn may be positioned at one side of the non-display area NDA in the second direction DR2.

[0064] Figure 3 is an equivalent circuit diagram of a pixel PXij according to some embodiments of the present disclosure.

[0065] Figure 3 A pixel PXij connected to the i-th scan line SCLi, the i-th sensing line SSLi, the j-th data line DLj, and the j-th reference line RLj is shown as an example. The pixel PXij may include a pixel circuit PC and a light-emitting element OLED connected to the pixel circuit PC. The pixel circuit PC may include a plurality of transistors T1, T2, and T3 and a capacitor Cst. The plurality of transistors T1, T2, and T3 may be formed by a low-temperature polycrystalline silicon (LTPS) process or a low-temperature polycrystalline oxide (LTPO) process. In the following, the plurality of transistors T1, T2, and T3 are explained as n-type transistors, but at least one transistor may be implemented as a p-type transistor.

[0066] According to some embodiments, a pixel circuit PC including a first transistor T1, a second transistor T2, a third transistor T3 and a capacitor Cst is shown as an example, but the pixel circuit PC is not limited thereto. The first transistor T1 may be a driving transistor, the second transistor T2 may be a switching transistor, and the third transistor T3 may be a sensing transistor. The pixel circuit PC may further include an additional transistor or may further include an additional capacitor.

[0067] The light emitting element OLED may be an organic light emitting element or an inorganic light emitting element including an anode (first electrode) and a cathode (second electrode). The anode of the light emitting element OLED may receive a first voltage ELVDD through a first transistor T1, and the cathode of the light emitting element OLED may receive a second voltage ELVSS. The light emitting element OLED may receive the first voltage ELVDD and the second voltage ELVSS to emit light.

[0068] The first transistor T1 may include a drain D1 receiving the first voltage ELVDD, a source S1 connected to the anode of the light emitting element OLED, and a gate G1 connected to the capacitor Cst. The first transistor T1 may control a driving current flowing from the first voltage ELVDD through the light emitting element OLED corresponding to the value of the voltage stored in the capacitor Cst.

[0069] The second transistor T2 may include a drain D2 connected to the jth data line DLj, a source S2 connected to the capacitor Cst, and a gate G2 receiving the i-th first scan signal SCi. The j-th data line DLj may receive the data voltage Vd. The second transistor T2 may transmit the data voltage Vd to the first transistor T1 in response to the i-th first scan signal SCi.

[0070] The third transistor T3 may include a source S3 connected to the jth reference line RLj, a drain D3 connected to the anode of the light emitting element OLED, and a gate G3 receiving the i-th second scan signal SSi. The jth reference line RLj may receive a reference voltage Vr. The third transistor T3 may initialize the capacitor Cst and the anode of the light emitting element OLED.

[0071] The capacitor Cst may store a voltage corresponding to a difference between a voltage transmitted from the second transistor T2 and the first voltage ELVDD. The capacitor Cst may be connected to the gate G1 of the first transistor T1 and the anode of the light emitting element OLED.

[0072] The pixel circuit PC according to some embodiments is not limited to having Figure 3 For example, according to some embodiments, the pixel circuit PC may have additional components or fewer components without departing from the spirit and scope of the embodiments according to the present disclosure.

[0073] Figure 4 is an enlarged plan view of a display area DA according to some embodiments of the present disclosure.

[0074] like Figure 4 As shown in , the unit pixel PXU may be aligned in each of the first direction DR1 and the second direction DR2. According to some embodiments, the unit pixel PXU may include a first pixel, a second pixel, and a third pixel that emit light having different colors. The first pixel, the second pixel, and the third pixel may output red light, green light, and blue light, respectively. Figure 4A first pixel region PXA-R, a second pixel region PXA-G, and a third pixel region PXA-B are shown, which represent a first pixel, a second pixel, and a third pixel, respectively. The first pixel region PXA-R may be a region in which light generated from the first pixel is provided to the outside, the second pixel region PXA-G may be a region in which light generated from the second pixel is provided to the outside, and the third pixel region PXA-B may be a region in which light generated from the third pixel is provided to the outside.

[0075] The peripheral area NPXA may be arranged to have a shape surrounding the first pixel area PXA-R, the second pixel area PXA-G, and the third pixel area PXA-B. The peripheral area NPXA may also be positioned between the first pixel area PXA-R, the second pixel area PXA-G, and the third pixel area PXA-B. The peripheral area NPXA may set a boundary of each of the first to third pixel areas PXA-R, PXA-G, and PXA-B, and prevent mixing of colors between the first to third pixel areas PXA-R, PXA-G, and PXA-B.

[0076] Reference Figure 4 , the first pixel region PXA-R and the third pixel region PXA-B may be positioned in the same row, and the second pixel region PXA-G may be positioned in a row different from the first pixel region PXA-R and the third pixel region PXA-B. The second pixel region PXA-G may have the largest area, and the third pixel region PXA-B may have the smallest area. However, embodiments of the present disclosure are not limited thereto. According to some embodiments, each of the first pixel region PXA-R, the second pixel region PXA-G, and the third pixel region PXA-B is shown as having a substantially square shape. However, this shape is an example, and embodiments according to the present disclosure are not limited thereto.

[0077] Figures 5 to 7 are cross-sectional views of portions of display devices DD, DD-a, and DD-b, respectively, according to some embodiments of the present disclosure. Fig. 8A and Figure 8B are cross-sectional views of emission layers EMLa and EMLb, respectively, according to some embodiments of the present disclosure.

[0078] Figures 5 to 7 Both show Figure 4 These cross sections are examples, and the embodiments according to the present disclosure are not limited thereto. Figures 5 to 7 Examples of cross sections of the first to third pixel regions PXA-R, PXA-G, and PXA-B are each shown.

[0079] The display panel DP may include a first base layer BS1, a circuit layer CL, a light emitting element layer EDL, and a thin film encapsulation layer TFE. The circuit layer CL may be positioned on the first base layer BS1. The light emitting element layer EDL may be positioned on the circuit layer CL. The thin film encapsulation layer TFE may be positioned on the light emitting element layer EDL and seal the light emitting element layer EDL.

[0080] The first base layer BS1 may include a glass or synthetic resin layer. The synthetic resin layer may include a thermosetting resin. Specifically, the synthetic resin layer may be a polyimide resin layer, and its material is not specifically limited. The synthetic resin layer may include at least one of acrylic resin, methacrylic resin, polyisoprene, vinyl resin, epoxy resin, urethane resin, cellulose resin, siloxane resin, polyamide resin and perylene resin. In addition, the first base layer BS1 may include a glass substrate, a metal substrate, an organic / inorganic composite material substrate, etc.

[0081] The circuit layer CL may be positioned on the first base layer BS1. The circuit layer CL may include an insulating layer, a semiconductor pattern, a conductive pattern, a signal line, etc. The insulating layer, the semiconductor layer, and the conductive layer may be formed on the first base layer BS1 by coating, deposition, etc., and then, the insulating layer, the semiconductor layer, and the conductive layer may be selectively patterned by performing a photolithography process multiple times. Therefore, the semiconductor pattern, the conductive pattern, and the signal line may be positioned on the circuit layer CL. The circuit layer CL may include a transistor, a buffer layer, and a plurality of insulating layers.

[0082] The light emitting element layer EDL may be positioned on the circuit layer CL, and include a light emitting element OLED and a pixel defining layer PDL.

[0083] The light emitting element OLED may include a first electrode EL1, a second electrode EL2 facing the first electrode EL1, and an emission layer EML positioned between the first electrode EL1 and the second electrode EL2. The emission layer EML included in the light emitting element OLED may include an organic light emitting material or a quantum dot as a light emitting material. The light emitting element OLED may further include a hole transport region HTR and / or an electron transport region ETR. Meanwhile, according to some embodiments, the light emitting element OLED may further include a cover layer positioned at an upper portion of the second electrode EL2.

[0084] The pixel defining film PDL may be positioned on the circuit layer CL and cover a portion of the first electrode EL1. An emission opening portion OH may be defined in the pixel defining film PDL. The emission opening portion OH of the pixel defining film PDL exposes at least a portion of the first electrode EL1. Each of the first to third emission areas EA1, EA2, and EA3 may be defined to correspond to a portion of the first electrode EL1 exposed by the emission opening portion OH of the pixel defining film PDL. The first emission area EA1, the second emission area EA2, and the third emission area EA3 may correspond to the first pixel area PXA-R, the second pixel area PXA-G, and the third pixel area PXA-B, respectively. Areas other than the first to third emission areas EA1, EA2, and EA3 may be defined as non-emission areas.

[0085] In the present disclosure, two components "corresponding" to each other means that when viewed in the thickness direction (e.g., the third direction DR3) of each of the display devices DD, DD-a, and DD-b (or when viewed in a plan view), the two components overlap each other and are not limited to having the same area. The first emission area to the third emission area EA1, EA2, and EA3 may overlap with the first pixel area to the third pixel area PXA-R, PXA-G, and PXA-B, respectively. When viewed in a plan view, the areas of the first pixel area to the third pixel area PXA-R, PXA-G, and PXA-B may be respectively larger than the areas of the first emission area to the third emission area EA1, EA2, and EA3 divided by the pixel defining film PDL. However, this is merely an example, and according to the embodiments of the present disclosure, it is not limited thereto. The areas of the first pixel area to the third pixel area PXA-R, PXA-G, and PXA-B may be substantially the same as the areas of the first emission area to the third emission area EA1, EA2, and EA3 divided by the pixel defining film PDL, respectively.

[0086] The first electrode EL1 may be positioned on the circuit layer CL. The first electrode EL1 may be an anode or a cathode. The first electrode EL1 may also be a pixel electrode. The first electrode EL1 may be a transmissive electrode, a transflective electrode, or a reflective electrode.

[0087] The hole transport region HTR may be positioned on the first electrode EL1. The hole transport region HTR may be commonly positioned in the first to third emission regions EA1, EA2, and EA3 and the non-emission region. A common layer like the hole transport region HTR may be arranged with Figure 4, a plurality of unit pixels PXU in the display area DA shown in FIG. are overlapped. However, the embodiments according to the present disclosure are not limited thereto, and the hole transport region HTR may be arranged to be separated to correspond to each of the first to third emission regions EA1, EA2, and EA3. The hole transport region HTR may include at least one of a hole transport layer, a hole injection layer, and an electron blocking layer.

[0088] The emission layer EML may be positioned on the hole transport region HTR. The emission layer EML may be commonly positioned in the first to third emission regions EA1, EA2, and EA3 and the non-emission region. The emission layer EML may be arranged to overlap the entire hole transport region HTR and the electron transport region ETR. However, the embodiments of the present disclosure are not limited thereto, and according to some embodiments, the emission layer EML may be positioned within the emission opening portion OH. That is, the emission layer EML may be arranged to be separated to correspond to each of the first to third emission regions EA1, EA2, and EA3 divided by the pixel defining film PDL.

[0089] The emission layer EML may generate source light. According to some embodiments, the emission layer EML may emit blue light. In the display devices DD, DD-a, and DD-b according to some embodiments, blue light may be source light. Meanwhile, when the emission layer EML is arranged to be separated to correspond to each of the first to third emission areas EA1, EA2, and EA3, the emission layer EML may all emit blue light, or may emit light having different wavelength regions in the first to third emission areas EA1, EA2, and EA3, respectively.

[0090] The emission layer EML may have a single layer made of a single material or a single layer made of multiple different materials, or may have a multilayer structure having multiple layers made of multiple different materials. The emission layer EML may include a fluorescent material or a phosphorescent material. In the light-emitting element according to some embodiments, the emission layer EML may include a light-emitting material such as an organic light-emitting material, an organic metal complex, or a quantum dot.

[0091] Fig. 8A and Figure 8B The emission layer EML (see Figures 5 to 7 ) is a cross-sectional view of an example of a case with a multilayer structure.

[0092] Reference Fig. 8A The emission layer EMLa may include a first emission layer EM1, a charge generation layer CGL, and a second emission layer EM2 sequentially stacked in the third direction DR3. The first emission layer EM1 and the second emission layer EM2 may emit light having different colors from each other. For example, the first emission layer EM1 may emit blue light, and the second emission layer EM2 may emit green light.

[0093] The charge generation layer CGL may be positioned between the first emission layer EM1 and the second emission layer EM2. The charge generation layer CGL may supply electrons or holes to each of the first emission layer EM1 and the second emission layer EM2 to relatively improve emission efficiency.

[0094] Reference Figure 8B The emission layer EMLb may include a first emission layer EM1a, a first charge generation layer CGLa, a second emission layer EM2a, a second charge generation layer CGLb, and a third emission layer EM3a sequentially stacked in the third direction DR3.

[0095] One of the first emission layer EM1a, the second emission layer EM2a, and the third emission layer EM3a may emit light having a different color from the other two. For example, the first emission layer EM1a and the third emission layer EM3a may emit light having the same color, and the second emission layer EM2a may emit light having a different color from the light generated in the first emission layer EM1a. For example, the first emission layer EM1a and the third emission layer EM3a may emit blue light, and the second emission layer EM2a may emit green light.

[0096] The first charge generation layer CGLa may be positioned between the first emission layer EM1a and the second emission layer EM2a. The second charge generation layer CGLb may be positioned between the second emission layer EM2a and the third emission layer EM3a. The first charge generation layer CGLa may supply electrons or holes to each of the first emission layer EM1a and the second emission layer EM2a to relatively improve the emission efficiency. In addition, the second charge generation layer CGLb may supply electrons or holes to each of the second emission layer EM2a and the third emission layer EM3a to relatively improve the emission efficiency.

[0097] Reference Figures 5 to 7 , the electron transport region ETR may be positioned on the emission layer EML. The electron transport region ETR may include at least one of an electron injection layer, an electron transport layer, and a hole blocking layer. The electron transport region ETR may be arranged as a common layer so as to overlap with the entire first to third emission regions EA1, EA2, and EA3 and the pixel defining film PDL. However, according to the embodiments of the present disclosure, it is not limited thereto, and the electron transport region ETR may be arranged to be separated to correspond to each of the first to third emission regions EA1, EA2, and EA3.

[0098] The second electrode EL2 may be positioned on the electron transport region ETR. The second electrode EL2 may be a common electrode. The second electrode EL2 may be a cathode or an anode, but is not limited thereto according to the embodiments of the present disclosure. For example, when the first electrode EL1 is an anode, the second electrode EL2 may be a cathode, and when the first electrode EL1 is a cathode, the second electrode EL2 may be an anode. The second electrode EL2 may be a transmissive electrode, a transflective electrode, or a reflective electrode.

[0099] The thin film encapsulation layer TFE may be positioned on the second electrode EL2. Optionally, when the light emitting element OLED includes a cover layer, the thin film encapsulation layer TFE may be positioned on the cover layer. The thin film encapsulation layer TFE may be used to protect the light emitting element layer EDL from moisture and oxygen, and prevent foreign matter such as dust from being introduced into the light emitting element layer EDL.

[0100] The thin film encapsulation layer TFE may include at least one inorganic film INL1 or INL2. The inorganic film INL1 or INL2 may include at least one of silicon nitride, silicon oxynitride, silicon oxide, titanium oxide, and aluminum oxide. The thin film encapsulation layer TFE may include at least one organic film OL. The organic film OL may include an organic polymer material formed of an acrylic resin or the like. However, these materials are examples and embodiments according to the present disclosure are not limited thereto.

[0101] The light conversion panel OP may be positioned on the display panel DP. The light conversion panel OP may include a second base layer BS2, a color filter layer CFL, a low refractive layer LR, a light control layer CCL, and a cover layer CAP. The color filter layer CFL may be positioned below the second base layer BS2. The low refractive layer LR may be positioned below the color filter layer CFL. The light control layer CCL may be positioned below the low refractive layer LR. The cover layer CAP may be positioned below the light control layer CCL.

[0102] The second base layer BS2 may be a member providing a base surface on which the color filter layer CFL and the like are positioned. The second base layer BS2 may include a glass or synthetic resin layer. The synthetic resin layer may include a thermosetting resin. Specifically, the synthetic resin layer may be a polyimide resin layer, and its material is not specifically limited. The synthetic resin layer may include at least one of acrylic resin, methacrylic resin, polyisoprene, vinyl resin, epoxy resin, urethane resin, cellulose resin, siloxane resin, polyamide resin and perylene resin. In addition, the second base layer BS2 may include a glass substrate, a metal substrate, an organic / inorganic composite material substrate, etc.

[0103] The color filter layer CFL is positioned below the second base layer BS2. The color filter layer CFL may include color filters CF1, CF2, and CF3. The color filter layer CFL may include a first color filter CF1 through which light of a second color passes, a second color filter CF2 through which light of a third color passes, and a third color filter CF3 through which light of a first color passes. For example, the first color filter CF1 may be a red color filter, the second color filter CF2 may be a green color filter, and the third color filter CF3 may be a blue color filter. Meanwhile, the first color filter CF1 and the second color filter CF2 may be yellow color filters. The first color filter CF1 and the second color filter CF2 may be provided as one body without being separated from each other.

[0104] The first color filter CF1 may allow only light within a partial wavelength range of light having the second color (i.e., light within the centroid wavelength range) to pass therethrough to improve color purity. The second color filter CF2 may allow only light within a partial wavelength range of light having the third color (i.e., light within the centroid wavelength range) to pass therethrough to improve color purity. The third color filter CF3 may allow only light within a partial wavelength range of light having the first color (i.e., light within the centroid wavelength range) to pass therethrough to improve color purity.

[0105] Each of the color filters CF1, CF2, and CF3 may include a polymer photosensitive resin and a pigment or dye. The first color filter CF1 may include a red pigment or a red dye, the second color filter CF2 may include a green pigment or a green dye, and the third color filter CF3 may include a blue pigment or a blue dye. Meanwhile, the third color filter CF3 may not include a pigment or a dye according to the embodiments of the present disclosure. The third color filter CF3 may include a polymer photosensitive resin but not a pigment or a dye. The third color filter CF3 may be transparent. The third color filter CF3 may include a transparent photosensitive resin.

[0106] The first to third color filters CF1, CF2, and CF3 may be arranged to correspond to the first pixel region PXA-R, the second pixel region PXA-G, and the third pixel region PXA-B, respectively. In addition, the first to third color filters CF1, CF2, and CF3 may be arranged to correspond to the first to third light controllers CCP1, CCP2, and CCP3, respectively.

[0107] A plurality of color filters CF1, CF2, and CF3 that allow light having different colors to pass therethrough may be arranged to overlap each other at a position corresponding to the peripheral area NPXA positioned between the pixel areas PXA-R, PXA-G, and PXA-B. A plurality of color filters CF1, CF2, and CF3 may be arranged to overlap each other in a third direction DR3 that is a thickness direction. The region in which the plurality of color filters CF1, CF2, and CF3 are arranged to overlap each other may define a boundary between adjacent pixel areas PXA-R, PXA-G, and PXA-B.

[0108] When viewed in a plan view, the area of ​​the portion where only the first color filter CF1 is positioned may be smaller than the area of ​​the first light controller CCP1. When viewed in a plan view, the area of ​​the portion where only the second color filter CF2 is positioned may be smaller than the area of ​​the second light controller CCP2. When viewed in a plan view, the area of ​​the portion where only the third color filter CF3 is positioned may be smaller than the area of ​​the third light controller CCP3. Therefore, the area of ​​the first pixel region PXA-R may be smaller than the area of ​​the first light controller CCP1, the area of ​​the second pixel region PXA-G may be smaller than the area of ​​the second light controller CCP2, and the area of ​​the third pixel region PXA-B may be smaller than the area of ​​the third light controller CCP3.

[0109] Unlike shown, the color filter layer CFL may include a light blocking portion defining a boundary between adjacent color filters CF1, CF2, and CF3. The light blocking portion may be provided as a blue color filter, or may include an organic light blocking material or an inorganic light blocking material including a black pigment or a black dye.

[0110] The low refractive layer LR may be positioned below the color filter layer CFL. The low refractive layer LR may be positioned on the light control layer CCL. The low refractive layer LR may also be positioned between the light control layer CCL and the color filter layer CFL to relatively improve the light extraction efficiency or perform the function of the optical functional layer (such as preventing reflected light from entering the light control layer CCL). The low refractive layer LR may be a layer having a lower refractive index than an adjacent layer. For example, the refractive index of the low refractive layer LR may be about 1.45 or less.

[0111] The low refractive layer LR may include at least one inorganic layer. For example, the low refractive layer LR may be manufactured by including silicon nitride, aluminum nitride, zirconium nitride, titanium nitride, hafnium nitride, tantalum nitride, silicon oxide, aluminum oxide, titanium oxide, tin oxide, cerium oxide or silicon oxynitride, or a metal film with light transmittance. However, the embodiments of the present disclosure are not limited thereto, and the low refractive layer LR may include an organic film. For example, the low refractive layer LR may be manufactured by including a polymer resin, inorganic particles, etc.

[0112] The light control layer CCL may be positioned below the low refractive layer LR. The light control layer CCL may include a partition pattern BMP and light controllers CCP1, CCP2, and CCP3. The partition pattern BMP may overlap with the peripheral area NPXA in a plan view. The light controllers CCP1, CCP2, and CCP3 included in the light control layer CCL may be arranged to be spaced apart from each other. The light controllers CCP1, CCP2, and CCP3 may be arranged to be spaced apart from each other by the partition pattern BMP. The light controllers CCP1, CCP2, and CCP3 may be positioned in opening portions BW-OH1, BW-OH2, and BW-OH3 defined in the partition pattern BMP, respectively. However, according to embodiments of the present disclosure, it is not limited thereto, and the edge of each of the light controllers CCP1, CCP2, and CCP3 may have at least a portion overlapping with the partition pattern BMP.

[0113] The separation pattern BMP may include a material having a transmittance less than or equal to a certain value (e.g., a set value or a predetermined value). For example, the separation pattern BMP may include a light-blocking material and may include a black colorant. The separation pattern BMP may include a black dye or a black pigment mixed in a matrix resin. In the separation pattern BMP, for example, the black colorant may include carbon black, or may include a metal such as chromium or an oxide thereof. The separation pattern BMP may include, for example, at least one of propylene glycol methyl ether acetate, 3-methoxybutyl acetate, an acrylate monomer, an acrylic monomer, an organic pigment, and an acrylate.

[0114] Each of the light controllers CCP1, CCP2 and CCP3 may be a portion that converts the wavelength of the source light supplied from the light emitting element layer EDL or allows the supplied source light to pass therethrough without converting the wavelength of the light. The light controllers CCP1, CCP2 and CCP3 may be formed by an inkjet process. A liquid ink composition may be supplied to each of the opening portions BW-OH1, BW-OH2 and BW-OH3, and the supplied liquid ink composition may be polymerized by a thermal curing process or a photocuring process to form the light controllers CCP1, CCP2 and CCP3. That is, the opening portions BW-OH1, BW-OH2 and BW-OH3 may have shapes corresponding to the shapes of the light controllers CCP1, CCP2 and CCP3, respectively.

[0115] The light control layer CCL may include a first light controller CCP1, a second light controller CCP2, and a third light controller CCP3, the first light controller CCP1 including a first quantum dot that converts light having a first color supplied from the light emitting element OLED into light having a second color, the second light controller CCP2 including a second quantum dot that converts light having a first color into light having a third color, and the third light controller CCP3 allowing light having a first color to pass through. The first light controller CCP1 may provide red light as light having a second color, and the second light controller CCP2 may provide green light as light having a first color. The third light controller CCP3 may provide blue light by allowing blue light as light having a first color supplied from the light emitting element OLED to pass through it. For example, the first quantum dot may be a red quantum dot, and the second quantum dot may be a green quantum dot.

[0116] Quantum dots refer to crystals of semiconductor compounds. When the band gap is adjusted by adjusting the size of the quantum dots or adjusting the ratio of elements in the quantum dots, light with various wavelength ranges can be obtained. For example, a quantum dot can have a diameter of about 1nm to about 10nm. Therefore, a light-emitting element that emits light with several wavelengths can be realized by using quantum dots with different sizes or using quantum dots with different ratios of elements in the quantum dots. Specifically, quantum dots can be implemented to emit red light, green light or blue light. Quantum dots can also be configured to combine light with various colors to emit white light.

[0117] Quantum dots can be synthesized by wet chemical process, metal organic chemical vapor deposition, molecular beam epitaxy or similar operations. The wet chemical process is a method of mixing an organic solution and a precursor material and then growing quantum dot particle crystals. When the crystal grows, the organic solvent can naturally coordinate on the surface of the quantum dot crystal to act as a dispersant, and the growth of the crystal can be controlled. Therefore, in the wet chemical process, the growth of quantum dot particle crystals can be controlled by a process that is easier and less expensive to manufacture than a vapor deposition process such as metal organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE).

[0118] The quantum dot may have a single structure or a dual core-shell structure, wherein the concentration of each element contained in the quantum dot is uniform. For example, the material contained in the core and the material contained in the shell may be different from each other. The shell of the quantum dot may be used as a protective layer for preventing chemical deformation of the core to maintain semiconductor properties and / or as a charged layer for imparting electrophoretic properties to the quantum dot. The shell may be a single-layer shell or a multi-layer shell. The core / shell structure may have a concentration gradient in which the concentration of the element present in the shell gradually decreases toward the core.

[0119] The core of the quantum dot can be selected from Group II-VI compounds, Group III-VI compounds, Group I-III-VI compounds, Group III-V compounds, Group III-II-V compounds, Group IV-VI compounds, Group IV elements, Group IV compounds, and combinations thereof.

[0120] The II-VI compound may be selected from the group consisting of binary compounds, ternary compounds and quaternary compounds, the binary compound being selected from the group consisting of CdSe, CdTe, CdS, ZnS, ZnSe, ZnTe, ZnO, HgS, HgSe, HgTe, MgSe, MgS and mixtures thereof, the ternary compound being selected from the group consisting of CdSeS, CdSeTe, CdSTe, ZnSeS, ZnSeTe, ZnSTe, HgSeS, HgSeTe, HgSTe, The invention also includes a group consisting of CdZnS, CdZnSe, CdZnTe, CdHgS, CdHgSe, CdHgTe, HgZnS, HgZnSe, HgZnTe, MgZnSe, MgZnS and mixtures thereof; and a quaternary compound selected from the group consisting of HgZnTeS, CdZnSeS, CdZnSeTe, CdZnSTe, CdHgSeS, CdHgSeTe, CdHgSTe, HgZnSeS, HgZnSeTe and mixtures thereof.

[0121] The III-VI compounds may include compounds such as In 2 S 3 andIn 2 Se 3 Binary compounds such as InGaS 3 and InGaSe 3 ternary compounds or any combination thereof.

[0122] The I-III-VI group compounds may be selected from ternary compounds and quaternary compounds (such as AgInGaS 2 and CuInGaS 2 ), the ternary compound is selected from AgInS, AgInS 2 、CuInS、CuInS 2 、AgGaS 2 、CuGaS 2 、CuGaO 2 、AgGaO 2 、AgAlO 2 and mixtures thereof.

[0123] The III-V compound may be selected from the group consisting of a binary compound, a ternary compound, and a quaternary compound, wherein the binary compound is selected from the group consisting of GaN, GaP, GaAs, GaSb, AlN, AlP, AlAs, AlSb, InN, InP, InAs, InSb, and mixtures thereof, the ternary compound is selected from the group consisting of GaNP, GaNAs, GaNSb, GaPAs, GaPSb, AlNP, AlNAs, AlNSb, AlPAs, AlPSb, InGaP, InAlP, InNP, InNAs, InNSb, InPAs, InPSb, and mixtures thereof, and the quaternary compound is selected from the group consisting of GaAlNP, GaAlNAs, GaAlNSb, GaAlPAs, GaAlPSb, GaInNP, GaInNAs, GaInNSb, GaInPAs, GaInPSb, InAlNP, InAlNAs, InAlNSb, InAlPAs, InAlPSb, and mixtures thereof. At the same time, the III-V compound may also include a Group II metal. For example, the III-II-V group compound may be selected from InZnP and the like.

[0124] The IV-VI compound may be selected from the group consisting of binary compounds, ternary compounds and quaternary compounds, the binary compound being selected from the group consisting of SnS, SnSe, SnTe, PbS, PbSe, PbTe and mixtures thereof, the ternary compound being selected from the group consisting of SnSeS, SnSeTe, SnSTe, PbSeS, PbSeTe, PbSTe, SnPbS, SnPbSe, SnPbTe and mixtures thereof, the quaternary compound being selected from the group consisting of SnPbSSe, SnPbSeTe, SnPbSTe and mixtures thereof. The IV group element may be selected from the group consisting of Si, Ge and mixtures thereof. The IV group compound may be a binary compound selected from the group consisting of SiC, SiGe and mixtures thereof.

[0125] The Group IV element or compound may include a single element material such as Si or Ge, a binary compound such as SiC or SiGe, or any combination thereof.

[0126] Here, each of the elements included in the multi-element compound such as the binary compound, the ternary compound, and the quaternary compound may be present in the particle at a uniform concentration or a non-uniform concentration. That is, each of the aforementioned chemical formulas means the type of element included in the compound, and the element ratio in the compound may be different. For example, AgInGaS 2 Can mean AgIn x Ga 1-x S 2 (x is a real number from about 0 to about 1).

[0127] The shell of a quantum dot may include a metal oxide, a non-metal oxide, a semiconductor compound, or a combination thereof.

[0128] For example, metal or non-metal oxides may include SiO 2 、Al 2 O 3 、TiO 2 、ZnO、MnO、Mn 2 O 3 , Mn 3 O 4 , CuO, FeO, Fe 2 O 3 , Fe 3 O 4 , CoO, Co 3 O 4 and NiO binary compounds, or such as MgAl 2 O 4 、CoFe 2 O 4 、NiFe 2 O 4 and CoMn 2 O 4 ternary compound, but the embodiments according to the present disclosure are not limited thereto.

[0129] In addition, examples of semiconductor compounds may include CdS, CdSe, CdTe, ZnS, ZnSe, ZnTe, ZnSeS, ZnTeS, GaAs, GaP, GaSb, HgS, HgSe, HgTe, InAs, InP, InGaP, InSb, AlAs, AlP, and AlSb, but embodiments according to the present disclosure are not limited thereto.

[0130] The quantum dot may have a full width at half maximum (FWHM) of about 45 nm or less (preferably, about 40 nm or less, more preferably, about 30 nm or less) in the emission wavelength spectrum, and within this range, color purity or color reproducibility may be relatively improved. In addition, since the light emitted by the quantum dot is emitted in all directions, the wide viewing angle may be relatively improved.

[0131] The shape of the quantum dot is a shape commonly used in the related art and is not particularly limited. However, more specifically, quantum dots of nanoparticles, nanotubes, nanowires, nanofibers, nanosheets, etc. in the form of spheres, pyramids, multi-arms or cubes can be used.

[0132] As described above, the color of light emitted by quantum dots can be adjusted according to the particle size, and therefore, quantum dots can have various emission colors such as blue, red, and green. As the particle size of quantum dots is smaller, quantum dots can emit light with a shorter wavelength range. For example, in quantum dots having the same core, the particle size of quantum dots emitting green light can be smaller than the particle size of quantum dots emitting red light. In addition, in quantum dots having the same core, the particle size of quantum dots emitting blue light can be smaller than the particle size of quantum dots emitting green light. However, according to the embodiments of the present disclosure, it is not limited thereto, and in quantum dots having the same core, the particle size can be adjusted according to the material forming the shell, the shell thickness, etc. At the same time, when quantum dots have various emission colors such as blue, red, and green, quantum dots with different emission colors can be different from each other in terms of core materials.

[0133] The light control layer CCL may further include a scatterer. The first light controller CCP1 may include first quantum dots and a scatterer, the second light controller CCP2 may include second quantum dots and a scatterer, and the third light controller CCP3 may include a scatterer but no quantum dots.

[0134] The scatterers may be inorganic particles. For example, the scatterers may include TiO 2 、ZnO、Al 2 O 3 、SiO 2 and hollow silica. The scatterer may include TiO 2 、ZnO、Al 2 O 3 、SiO 2 and hollow silica, or may be selected from TiO 2 、ZnO、Al 2 O 3 、SiO 2 and a mixture of two or more materials in hollow silica.

[0135] Each of the first light controller CCP1, the second light controller CCP2, and the third light controller CCP3 may further include a matrix resin in which quantum dots and scatterers are dispersed. According to some embodiments, the first light controller CCP1 may include first quantum dots and scatterers dispersed in the matrix resin, the second light controller CCP2 may include second quantum dots and scatterers dispersed in the matrix resin, and the third light controller CCP3 may include scatterers dispersed in the matrix resin.

[0136] The matrix resin is a medium in which quantum dots and scatterers are dispersed, and may be composed of various resin compositions that may generally be referred to as adhesives. For example, the matrix resin may be an acrylic resin, a urethane resin, a silicone resin, an epoxy resin, etc. The matrix resin may be a transparent resin.

[0137] The cover layer CAP may be positioned below the light control layer CCL. The cover layer CAP may be used to prevent moisture and / or oxygen penetration. The cover layer CAP may be positioned below the light controllers CCP1, CCP2, and CCP3 to prevent the light controllers CCP1, CCP2, and CCP3 from being exposed to moisture / oxygen. In addition, the cover layer CAP may not only cover the light controllers CCP1, CCP2, and CCP3, but may also cover the separation pattern BMP.

[0138] The cover layer CAP may include at least one inorganic layer. That is, the cover layer CAP may include an inorganic material. For example, the cover layer CAP may include silicon nitride, aluminum nitride, zirconium nitride, titanium nitride, hafnium nitride, tantalum nitride, silicon oxide, aluminum oxide, titanium oxide, tin oxide, cerium oxide and silicon oxynitride, or a metal film with light transmittance, etc. However, the embodiments of the present disclosure are not limited thereto. At the same time, the cover layer CAP may also include an organic film. The cover layer CAP may be composed of a single layer or multiple layers.

[0139] The light conversion panel OP according to some embodiments of the present disclosure further includes each of the curing control layers CRC, CRC-a, and CRC-b. The curing control layers CRC, CRC-a, and CRC-b may represent a layer for adjusting the filler material FM (see FIG. 1 ) to be described later. Fig.11 ) of the cured layer. For example, the curing control layers CRC, CRC-a and CRC-b can chemically inhibit the start of curing to delay the curing of the peripheral part, or can physically inhibit the flow of the material to regulate the curing. Alternatively, the curing can be regulated chemically and physically at the same time. This content will be described in detail later.

[0140] Each of the curing control layers CRC, CRC-a, and CRC-b may be positioned under the separation pattern BMP. Figures 5 to 7 It is shown that each of the curing control layers CRC, CRC-a, and CRC-b is positioned directly under the cover layer CAP, which is positioned under the partition pattern BMP, but the cover layer CAP may be omitted. When the cover layer CAP is omitted, each of the curing control layers CRC, CRC-a, and CRC-b may be positioned directly under the partition pattern BMP.

[0141] Each of the curing control layers CRC, CRC-a, and CRC-b may be positioned to overlap the partition pattern BMP in a plan view. In a plan view, each of the curing control layers CRC, CRC-a, and CRC-b may be positioned between the first pixel region to the third pixel region PXA-R, PXA-G, and PXA-B. Each of the curing control layers CRC, CRC-a, and CRC-b may have an area substantially the same as that of the partition pattern BMP. However, the embodiments of the present disclosure are not limited thereto, and the area of ​​each of the curing control layers CRC, CRC-a, and CRC-b may also be smaller than the area of ​​the partition pattern BMP.

[0142] Each of the curing control layers CRC, CRC-a, and CRC-b may be positioned at the lowermost side of the light conversion panel OP and between the first to third pixel regions PXA-R, PXA-G, and PXA-B in a plan view in order to adjust the filler material FM (see FIG. 1 ) arranged to couple the display panel DP and the light conversion panel OP to each other. Fig.11 ) solidification. When adjusting the filler material FM (see Fig.11 ), each of the voids VD, VD-a, and VD-b may be disposed between the first to third pixel regions PXA-R, PXA-G, and PXA-B in the filling layer FL in a plan view. Each of the voids VD, VD-a, and VD-b may be evacuated or filled with air to have a low refractive property compared to the peripheral portion, and thus, total reflection of light may be caused at the boundary of each of the voids VD, VD-a, and VD-b. The voids VD, VD-a, and VD-b will be described in detail later.

[0143] The curing control layers CRC, CRC-a and CRC-b may include an organic substance. For example, the curing control layers CRC, CRC-a and CRC-b may include photosensitive polyimide (PSPI). However, the materials of the curing control layers CRC, CRC-a and CRC-b are not limited thereto.

[0144] Reference Figure 5 , the curing control layer CRC may include a curing delay material. The curing delay material may mean a material that inhibits the filling material FM (see Fig.11 ) in order to delay the curing of the filling material. Since the curing control layer CRC includes the curing delaying material, the start of curing of the filling material at a position adjacent to the curing control layer CRC can be suppressed, so that the curing of the filling material at a position adjacent to the curing control layer CRC is delayed compared to the filling material at a position not adjacent to the curing control layer CRC.

[0145] For example, when the filling material is an epoxy-based material, the curing delay material may include an amine group (NH3 The amine group can first react with H as an ion initiator of epoxy filling material. + The ions react with the moisture remaining in the bonding of the display panel DP and the light conversion panel OP, so that the curing of the filling material is delayed. In addition, when the filling material is a silicon-based material, the curing delay material may include a silane-based (SH 4 Due to the Si-H bond of the silane group, the vinyl group of the silicon-based filling material can be opened to delay the curing of the filling material. However, the curing delay material according to some embodiments of the present disclosure is not limited thereto, as long as the material can inhibit the use of the filling material FM (see Fig.11 ) material begins to cure, so as to delay the curing of the filling material.

[0146] Since the curing control layer CRC includes the curing delay material, the curing control layer CRC may adjust the filling material FM (see FIG. 1 ) formed to combine the display panel DP and the light conversion panel OP with each other. Fig.11 ) solidification. When the filling material FM (see Fig.11 ) is cured and shrinks, the delay rate at the peripheral portion of the curing control layer CRC can be relatively low. That is, the curing can be chemically adjusted.

[0147] Therefore, in a plan view, a void VD may be provided in the filling layer FL between the first to third pixel regions PXA-R, PXA-G, and PXA-B. The void VD may be evacuated or filled with air to have a low refractive property compared to the peripheral portion, and thus, total reflection of light may be caused at the boundary of the void VD.

[0148] Reference Figure 6 , the curing control layer CRC-a may include an uneven structure. The curing control layer CRC-a may have a top surface adjacent to the separation pattern BMP and a bottom surface adjacent to the filling layer FL. The curing control layer CRC-a may include an uneven structure on the bottom surface.

[0149] Since the curing control layer CRC-a includes an uneven structure on the bottom surface, the curing control layer CRC-a may adjust the filler material FM (see FIG. 1 ) formed to combine the display panel DP and the light conversion panel OP with each other. Fig.11 ) solidification. When the filling material FM (see Fig.11 ) solidifies and shrinks, the flow rate of the filling material at the peripheral portion of the uneven structure can be lower than the flow rate at the opposite side. That is, the solidification can be physically adjusted.

[0150] Therefore, in a plan view, the void VD-a may be provided in the filling layer FL between the first to third pixel regions PXA-R, PXA-G, and PXA-B. The void VD-a may be evacuated or filled with air to have a low refractive property compared to the peripheral portion, and thus, total reflection of light may be caused at the boundary of the void VD-a.

[0151] Reference Figure 7 The curing control layer CRC-b may include a curing delay material and also include an uneven structure on the bottom surface. The curing control layer CRC-b may be as described above with reference to Figure 5 The curing is chemically regulated as described, and at the same time as above with reference to Figure 6 The curing is regulated physically as described.

[0152] Each of the display devices DD, DD-a, and DD-b includes a filling layer FL positioned between the display panel DP and the light conversion panel OP. The filling layer FL may be filled between the display panel DP and the light conversion panel OP. The filling layer FL may be used as a buffer between the display panel DP and the light conversion panel OP. The filling layer FL may perform an impact absorption function, etc., and may increase the rigidity of the display devices DD, DD-a, and DD-b.

[0153] The source light supplied from the display panel DP may reach the light conversion panel OP through the filling layer FL. The light emitting element OLED of the display panel DP may emit light in all directions. Therefore, when the light emitted from the light emitting element OLED travels toward the partition pattern BMP positioned between the first pixel region to the third pixel region PXA-R, PXA-G and PXA-B or between other adjacent pixel regions PXA-R, PXA-G and PXA-B, side losses may occur. In other words, the light extraction efficiency and color reproducibility of the light emitted to the outside of the display devices DD, DD-a and DD-b may be reduced.

[0154] Reference Figures 5 to 7 , the filling layer FL according to some embodiments of the present disclosure may include a filling part FP and each of the voids VD, VD-a, and VD-b.

[0155] The filling portion FP may overlap with the first to third pixel regions PXA-R, PXA-G, and PXA-B in a plan view, and overlap with the plurality of light controllers CCP1, CCP2, and CCP3. Here, the term "overlap" does not mean that the area of ​​the filling portion FP is the same as the area of ​​each of the first to third pixel regions PXA-R, PXA-G, and PXA-B or the area of ​​each of the plurality of light controllers CCP1, CCP2, and CCP3 in a plan view, and may be intended to indicate a positional relationship in which the filling portion FP is positioned in a plan view.

[0156] The filling part FP may be formed of a filling resin including a polymer resin. For example, the filling part FP may include a resin including an epoxy-based resin, a silicon-based resin, an acrylic-based resin, or the like.

[0157] The filling layer FL may include each of the voids VD, VD-a, and VD-b at a position where the filling layer FL overlaps the separation pattern BMP on a plan view. Here, the term "overlapping" does not mean that the area of ​​each of the voids VD, VD-a, and VD-b is the same as the area of ​​the separation pattern BMP on a plan view, and may be intended to indicate a positional relationship in which each of the voids VD, VD-a, and VD-b is positioned on a plan view. That is, on a plan view, each of the voids VD, VD-a, and VD-b may be positioned in the peripheral area NPXA between the first to third pixel regions PXA-R, PXA-G, and PXA-B.

[0158] The voids VD, VD-a and VD-b may mean empty spaces, and each of the voids VD, VD-a and VD-b is a partial space left when the filling layer FL is solidified and shrunk without being filled with the filling material FM to be described later. The voids VD, VD-a and VD-b may be evacuated or filled with air to have low refractive properties compared to the peripheral part. For example, the voids VD, VD-a and VD-b may have a refractive index of about 1.0, and the filling portion FP as the peripheral part may have a refractive index of about 1.6.

[0159] Therefore, the light emitted from the display panel DP traveling toward the side surface can be totally reflected at the boundary of each of the gaps VD, VD-a, and VD-b to travel toward the light conversion panel OP. That is, the side loss can be reduced to relatively improve the light extraction efficiency of the display devices DD, DD-a, and DD-b.

[0160] Reference Figure 5 , the shape of the void VD in the case where the curing control layer CRC includes a curing delay material is shown as an example. Since the curing control layer CRC includes the curing delay material, the start of curing of the filling material located between the first to third pixel regions PXA-R, PXA-G, and PXA-B at a position adjacent to the curing control layer CRC can be suppressed. That is, the curing of the filling material can be delayed compared to the filling material located at a position not adjacent to the curing control layer CRC in the first to third pixel regions PXA-R, PXA-G, and PXA-B.

[0161] When the filling material at a position not adjacent to the curing control layer CRC is first cured and shrunk, a gap VD may be provided between the first to third pixel regions PXA-R, PXA-G, and PXA-B. Figure 5 As shown in , the void VD may have a shape having curvature in a cross-sectional view. For example, the void VD may have an elliptical shape or a convex lens shape in a cross-sectional view, etc. However, the shape of the void VD is not limited thereto, and may vary according to conditions such as the type of curing delay material, the concentration of the filling material, the type, the curing temperature or time, etc.

[0162] Reference Figure 6 , the shape of the void VD-a in the case where the curing control layer CRC-a includes an uneven structure on its bottom surface is shown as an example. Since the curing control layer CRC-a includes an uneven structure on its bottom surface, when the filling material is cured and shrinks, the flow rate of the filling material at the peripheral portion of the uneven structure may be lower than the flow rate at the opposite side. Here, the peripheral portion of the uneven structure may mean a portion adjacent to the uneven structure, and the opposite side may mean a portion spaced apart from the uneven structure and adjacent to the display panel DP.

[0163] When the flow of the filling material is physically adjusted due to the uneven structure, the gap VD-a may be provided between the first to third pixel regions PXA-R, PXA-G, and PXA-B. Figure 6 As shown in , the void VD-a may have a substantially trapezoidal shape in a cross-sectional view. The void VD-a may have a top surface adjacent to the curing control layer CRC-a and a bottom surface adjacent to the display panel DP. The top surface of the void VD-a may correspond to the upper side of the trapezoid, and the bottom surface of the void VD-a may correspond to the lower side of the trapezoid. The width of the upper side of the trapezoid may be smaller than the width of the lower side of the trapezoid. In a plan view, the area of ​​the top surface of the void VD-a may be smaller than the area of ​​its bottom surface.

[0164] Reference Figure 7 , as an example, shows the shape of the void VD-b in the case where the curing control layer CRC-b includes a curing delay material and also includes an uneven structure on its bottom surface. Figure 6 Compared with the case described above, since the curing control layer CRC-b includes the curing delay material, the curing of the filling material adjacent to the curing control layer CRC-b can be delayed. Therefore, the width of the upper side of the void VD-b having a trapezoidal shape is greater than that of the case having the same uneven structure but not including the curing delay material. Figure 6 In a plan view, the area of ​​the top surface of the void VD-b may be smaller than the area of ​​the bottom surface thereof.

[0165] Fig.9Aand Fig. 9B Each of them is a flow chart of a method for manufacturing a display device according to some embodiments of the present disclosure. Figures 10 to 13 Each is a cross-sectional view illustrating operations of a method for manufacturing a display device according to some embodiments of the present disclosure.

[0166] Reference Fig.9A , a method for manufacturing a display device includes: preparing a light conversion panel (S100); bonding a display panel to the light conversion panel with a filling material between the display panel and the light conversion panel (S200); and curing the filling material (S300).

[0167] Reference Fig. 9B , the step (S100) of preparing the light conversion panel includes: forming a color filter layer on the base layer (S110); forming a light control layer on the color filter layer (S120); and forming a curing control layer (S130).

[0168] Fig.10 An example of a step (S100) of preparing an optical conversion panel OP is shown. The optical conversion panel OP may be prepared by forming a color filter layer CFL on a second base layer BS2; forming an optical control layer CCL including a partition pattern BMP and a plurality of optical controllers CCP1, CCP2, and CCP3 arranged to be spaced apart from each other by the partition pattern BMP on the color filter layer CFL; and forming a curing control layer CRC on the partition pattern BMP. Fig.10 The second base layer BS2 is shown positioned at the upper side and the light control layer CCL is positioned at the lower side so as to be oriented in the same direction as the lower Figures 11 to 13 The direction is consistent.

[0169] Each of the color filters CF1, CF2, and CF3 of the color filter layer CFL may be formed on the second base layer BS2 by a photolithography process, and the above-mentioned reference numerals may be formed on the second base layer BS2. Figures 5 to 7 The same or similar contents as described apply to the color filter layer CFL.

[0170] The step (S100) of preparing the light conversion panel may further include: forming a low refractive layer LR on the color filter layer CFL. The low refractive layer LR may be formed by chemical vapor deposition (CVD), or may be formed by applying an organic substance. Figures 5 to 7 The same or similar contents described may be applied to the low refractive layer LR. Meanwhile, the step of forming the low refractive layer LR may be omitted as needed.

[0171] The step ( S120 ) of forming the light-controlling layer may include forming separation patterns BMP and forming light controllers CCP1 , CCP2 , and CCP3 .

[0172] The separation pattern BMP of the light control layer CCL may be formed in the peripheral area NPXA of the color filter layer CFL. Fig.10 As shown in FIG. 1 , in the case where the light conversion panel OP includes a low refractive layer LR, a separation pattern BMP may be formed in the peripheral area NPXA of the low refractive layer LR. The separation pattern BMP may be formed by a photolithography process, and the above reference Figures 5 to 7 The same or similar contents described may be applied to the separation pattern BMP.

[0173] The light controllers CCP1, CCP2, and CCP3 of the light control layer CCL may be formed in the opening portions BW-OH1, BW-OH2, and BW-OH3 defined in the partition pattern BMP, respectively. However, the embodiment according to the present disclosure is not limited thereto, and the edge of each of the light controllers CCP1, CCP2, and CCP3 may be formed to have at least a portion overlapping the partition pattern BMP. The light controllers CCP1, CCP2, and CCP3 may be formed by polymerizing a liquid ink composition via thermal curing or photocuring, the liquid ink composition being provided by an inkjet process, and the above reference Figures 5 to 7 The same or similar contents described may be applied to the light controllers CCP1, CCP2 and CCP3.

[0174] The step (S100) of preparing the light conversion panel OP may further include: forming a cover layer CAP on the light control layer CCL. The cover layer CAP may be formed by chemical vapor deposition (CVD), and the above reference Figures 5 to 7 The same or similar contents described above may be applied to the cover layer CAP. Meanwhile, the step of forming the cover layer CAP may be omitted as needed.

[0175] A curing control layer CRC may be formed on the partition pattern BMP. The curing control layer CRC may include the curing delay material as described above. The curing control layer CRC may be formed by a photolithography process. Figure 6 and Figure 7 The curing control layers CRC-a and CRC-b in the embodiment of the present invention each include an uneven structure on its bottom surface. Figure 5 The same or similar contents described may be applied to the curing control layer CRC.

[0176] Fig.11 An example of a step ( S200 ) of bonding the display panel DP to the light conversion panel OP with the filling material FM between the display panel DP and the light conversion panel OP is shown.

[0177] The filling material FM may be applied in a liquid state and uniformly dispersed through the step of bonding the light conversion panel OP and the display panel DP to each other. Fig.11 As shown in FIG. 1 , the filling material FM may be entirely dispersed between the light conversion panel OP and the display panel DP, and entirely dispersed in the first to third pixel regions PXA-R, PXA-G, and PXA-B and the peripheral region NPXA.

[0178] Fig.12 An example of the step ( S300 ) of curing the filling material FM is shown.

[0179] The filling material FM applied in a liquid state may be changed into a solid state through a curing process. For example, a thermal curing process may be applied as the curing process, but the curing process is not limited thereto.

[0180] Since the curing control layer CRC includes the curing delay material, the start of curing of the filling material FM located between the first to third pixel regions PXA-R, PXA-G, and PXA-B at a position adjacent to the curing control layer CRC can be suppressed. That is, the curing of the filling material FM at a position adjacent to the curing control layer CRC can be delayed compared to the filling material FM located at a position not adjacent to the curing control layer CRC in the first to third pixel regions PXA-R, PXA-G, and PXA-B.

[0181] The curing of the filling material FM at a location not adjacent to the curing control layer CRC may start first, and the filling material FM may shrink. Fig.12 , the direction along which the filling material FM at the position corresponding to each of the first to third pixel regions PXA-R, PXA-G, and PXA-B is solidified and shrunk is schematically shown by arrows. That is, the filling material FM may shrink around the portion that is first solidified.

[0182] Fig.13 An example of a display device DD in which a filling layer FL including a filling part FP and a void VD is formed after the filling material FM is cured is shown.

[0183] When the filler material FM is regulated by the curing control layer CRC (see Fig.12 ) when the curing rate is less than 0.05, the filling layer FL may be formed by including the filling portion FP and the gap VD positioned between the first to third pixel regions PXA-R, PXA-G, and PXA-B. Figure 5 The same or similar contents described may be applied to the filling part FP and the void VD.

[0184] According to the foregoing description, the display device according to some embodiments of the present disclosure may include a filling layer having a structure capable of reducing light loss, thereby relatively improving light extraction efficiency and color reproducibility of the display device.

[0185] In addition, the method for manufacturing a display device according to some embodiments of the present disclosure may adjust a curing rate when bonding a display panel and a light conversion panel to each other to cure a filling material, thereby relatively improving process properties and mass productivity.

[0186] Although the embodiments of the present invention have been described, it is understood that the present invention should not be limited to these embodiments, but a person skilled in the art may make various changes and modifications within the spirit and scope of the present invention as claimed.

[0187] Therefore, the technical scope of the present invention is not limited to the contents described in the detailed description of the specification, but should be determined by the appended claims and their equivalents.

Claims

1. A display device, characterized in that: The display device comprises: A display panel including a light emitting element layer; a light conversion panel on the display panel; and A filling layer, between the display panel and the light conversion panel, The light conversion panel includes: a light control layer including a separation pattern and a plurality of light controllers spaced apart from each other by the separation pattern; and a curing control layer under the separation pattern.

2. The display device according to claim 1, characterized in that The partition pattern and the curing controlling layer overlap each other in a plan view.

3. The display device according to claim 1, characterized in that The filling layer comprises: a filling portion overlapping the plurality of light controllers in a plan view; and a gap, overlapping the partition pattern in plan view, The filling portion has a refractive index greater than that of the gap.

4. The display device according to claim 1, characterized in that The cure control layer includes a cure delay material.

5. The display device according to claim 4, characterized in that: The filling layer comprises: a filling portion overlapping the plurality of light controllers in a plan view; and a gap, overlapping the partition pattern in plan view, The gap has a shape with curvature in cross section.

6. The display device according to claim 4, characterized in that: The filling layer comprises: a filling portion overlapping the plurality of light controllers in a plan view; and a gap, overlapping the partition pattern in plan view, The gap has an elliptical shape in cross section.

7. The display device according to claim 1, characterized in that The curing control layer has a top surface adjacent to the separation pattern and a bottom surface adjacent to the filling layer, Wherein, the bottom surface of the solidification control layer includes an uneven structure.

8. The display device according to claim 7, characterized in that: The filling layer comprises: a filling portion overlapping the plurality of light controllers in a plan view; and a gap, overlapping the partition pattern in plan view, wherein the gap has a top surface adjacent to the curing control layer and a bottom surface adjacent to the display panel, Wherein, in a plan view, the top surface of the gap has an area smaller than an area of ​​the bottom surface of the gap.

9. The display device according to claim 1, characterized in that: The curing control layer includes a curing delay material, and The curing control layer has a top surface adjacent to the separation pattern and a bottom surface adjacent to the filling layer, Wherein, the bottom surface of the solidification control layer includes an uneven structure.

10. The display device according to claim 9, characterized in that: The filling layer comprises: a filling portion overlapping the plurality of light controllers in a plan view; and a gap, overlapping the partition pattern in plan view, wherein the gap has a top surface adjacent to the curing control layer and a bottom surface adjacent to the display panel, Wherein, in a plan view, the top surface of the gap has an area smaller than an area of ​​the bottom surface of the gap.

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