Multifunctional test platform for 3DX medium-wave transmitter power amplifier

Abstract

A multifunctional test platform for a 3DX medium-wave transmitter power amplifier is characterized in that a test mother board and a dummy load are fixed in a cabinet, a control panel provides an excitation signal source interface and two slot interfaces of the test mother board, a control button and a fault indicating lamp are installed on the control panel, control signals are input, and fault indication is displayed; the test mother board comprises a large-step power amplifier module slot, a binary power amplifier module slot, a high-voltage power supply port, a driving power supply port, a direct-current power supply port, a low-voltage power supply port, an excitation signal input port, a radio frequency output port, an efficiency coil, a filter circuit, an interface circuit and a decoding circuit; the device is divided into a high-voltage power supply part, a low-voltage power supply part, an excitation signal part, a radio frequency output part, a control signal part and a fault output part.

Description

Technical Field

[0001] The invention belongs to the technical field of medium wave transmission, and in particular relates to a testing circuit technology. Background Art

[0002] The 3DX medium wave transmitter uses a large number of integrated circuits and SMD components, which are more efficient and have clearer status parameter indications. It has become the world's mainstream model. Due to its high integration, the maintenance requirements of this transmitter are higher, and it is also very difficult to troubleshoot and repair the cause of the fault.

[0003] The 3DX50 medium wave transmitter produced by Gatesair in the United States uses 4 modulation encoders to control the switches of 64 identical large-step power amplifier modules and 4 binary power amplifier modules at the RF level. The power amplifier modules work in a high voltage and high current state. As time goes by, the damage rate gradually increases. There is no platform on the market to test the power amplifier modules of 3DX medium wave transmitters separately. In order to determine whether it is normal after maintenance, we can only rely on the online test of the transmitter, which increases the probability of transmitter damage. In severe cases, the transmitter motherboard is short-circuited and the RF transformer magnetic ring bursts, causing irreversible damage to the transmitter.

[0004] The large step amplifier module and binary amplifier module under test have common signal source and low voltage power supply interface, but the high voltage power supply and control signal interface definitions are different. The volume of the tester cannot be made as large as the transmitter. It is necessary to integrate the functions of the original amplifier motherboard and the filter board into a PCB board, and simplify the interface functions not related to the test. Therefore, the size of the tester motherboard is smaller and more integrated. Summary of the invention

[0005] In order to solve the technical problems that there is no 3DX medium wave transmitter power amplifier tester in China, and the large step power amplifier and binary power amplifier interface are incompatible, a technical solution of power supply filtering, RF output, and external interface concentrated on a motherboard is adopted, which realizes a high degree of integration. It can work safely under different voltage levels such as full voltage and half voltage, provide full circuit test points and fault indications, and has the technical effects of more convenient operation, clearer fault indication, and more complete protection function. The maintenance work is more comprehensive and accurate, eliminating the possibility of transmitter damage caused by the test module and reducing dependence on imported equipment.

[0006] The platform includes a cabinet and a control panel. The test motherboard and the dummy load are fixed inside the cabinet. The control panel provides an excitation signal source interface and two slot interfaces of the test motherboard. Control buttons and fault indicator lights are installed on the control panel to input control signals and display fault indications.

[0007] The test motherboard includes a large-step power amplifier module slot, a binary power amplifier module slot, a high-voltage power supply port, a drive power supply port, a DC power supply port, a low-voltage power supply port, an excitation signal input port, a RF output port, an efficiency coil, a filter circuit, an interface circuit, and a decoding circuit. It is divided into a high-voltage power supply part, a low-voltage power supply part, an excitation signal part, a RF output part, a control signal part, and a fault output part.

[0008] The large-step power amplifier module and the binary power amplifier module are inserted into the corresponding slots; the 300V input high-voltage power supply port and the 205V input drive power supply port belong to the high-voltage power supply part; the positive and negative 12V input DC power supply port and the 5V input low-voltage power supply port belong to the low-voltage power supply part, and the excitation signal source sends two excitation signals with a phase difference of 180° to the two excitation signal input ports, and drives the corresponding power amplifier modules through the two slots to control the 300V power switch with the excitation frequency, which belongs to the excitation signal part; the field effect tubes of the power amplifier module form two groups of bridges that are alternately turned on, and the distributed capacitance in the circuit is offset by the efficiency coil to form a pulse waveform of the same frequency at the RF output port, which is sent to the dummy load through the coupling transformer, which belongs to the RF output part; the TTL control signal is input from the interface circuit through the control button to adjust the excitation input and RF output, which belongs to the control signal part; the fault signal outputs a group of TTL fault signals from the interface circuit, which are sent to the decoding circuit to control the fault indicator light and display the fault type, which belongs to the fault output part.

[0009] The 205V driving power supply is sent to the large step power amplifier module or the binary power amplifier module through two slots, and is used for internal voltage inversion of the power amplifier module and rectified into 10V and 7.2V for use in the amplification and driving circuits.

[0010] The positive and negative 12V DC power supplies are sent to the large step amplifier module or the binary amplifier module through two slots. The positive 12V is used for the interlock detection circuit and the +5.5V voltage regulator is used for the logic device, and the negative 12V is used for the temperature detection circuit.

[0011] The efficiency coil uses 68 microhenry inductors L51 to L53 and 39 microhenry inductors L54 to L60. After the inductors L51 to L54 are connected in series, the inductors L55 to L57 are connected in series, and the inductors L58 to L60 are connected in series, they are connected in parallel with each other and bridged between the two RF output ports.

[0012] The dummy load input ports RF OUT A and RF OUT B are connected to the two RF output ports of the test motherboard, corresponding to the primary of the coupling transformer. One end of the secondary is grounded, and the other end is connected to three sets of two-in-one microstrip resistors through an adjustable inductor to adjust the impedance.

[0013] The two slots use 72-way push-in card edge connectors, the high-voltage power supply port and RF output port use pure copper gold-plated banana head terminals, the interface circuit uses 8-bit screw terminals, the drive power supply port and DC power supply port use screw terminals, and the excitation signal input port uses an elbow BNC RF coaxial connector to receive external excitation signals through a 50-ohm coaxial cable.

[0014] The first 5 bits of the interface circuit correspond to the PA RESET reset signal, LSB binary low-bit turn-on signal, MID binary middle-bit turn-on signal, PA / MSB ON binary high-bit turn-on signal / large-step turn-on signal, and interlock control signal of the control signal in turn, which are independently generated by the control button. The PA RESET reset signal clears the fault indication of the power amplifier module, the LSB binary low-bit turn-on signal turns on the low bit, the MID binary middle-bit turn-on signal turns on the middle bit, the PA / MSB ON large-step turn-on signal turns on the large-step power amplifier module or turns on the high bit of the binary power amplifier module, and the interlock signal interlocks the test motherboard with the power amplifier module to form a loop, providing installation protection for the power amplifier module. The last 3 bits of the interface circuit correspond to the fault signals DS1, DS2, and DS3 in turn, forming a group of control signals.

[0015] Fault signals DS1, DS2, and DS3 are input into the decoding circuit, and the code definitions are as follows: 010-INTERLOCK FAULT interlock fault, 110-PA / MSB FAULT power amplifier / high-order binary module fault signal, 001-MID FAULT mid-order binary module fault signal, 101-LSB FAULT low-order binary module fault signal, 011-TEMP FAULT over-temperature fault, 111-RESET reset signal enable, which controls the on and off of red LED6 to LED11, corresponding to INTERLOCK FAULT interlock fault indication, PA / MSB FAULT fault indication, MID FAULT mid-order binary fault indication, LSB FAULT low-order binary fault indication, TEMP FAULT over-temperature fault indication, and controls the on and off of green LED11, corresponding to the RESET reset indication.

[0016] Pins 1, 2, 3, 4, 5, 6, 9, 10, 11, 12, 13, and 14 of the large-step power amplifier module slot input a 300V DC power supply, pins 17 to 22 are connected to the J9 port, pins 25 to 30 are connected to the J10 port, pins 33 and 34 input a 205V drive power supply, pins 37, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56, 58, 60, 62, 64, 66, 68, 69, and 72 are grounded, pins 39 and 41 receive interlock signals INTERLOCK 1 and INTERLOCK 2 respectively, pins 47 and 49 input positive and negative 12V respectively, pins 51, 53, and 55 output fault signals DS1, DS2, and DS3 respectively, pin 57 receives the PA ON large-step opening signal, pin 63 receives the PA RESET reset signal, and pins 71 and 72 receive the excitation signal Bridge respectively. A. Bridge B.

[0017] Pins 1, 2, 3, 4, 5, 6, 9, 10, 11, 12, 13, and 14 of the binary power amplifier module slot input 300V DC power supply, pins 17 to 22 are connected to the J9 port, pins 25 to 30 are connected to the J10 port, pins 33 and 34 input 205V drive power supply, pins 37, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56, 58, 60, 62, 64, 66, 68, 69, and 72 are grounded, pins 39 and 41 output interlock signals INTERLOCK 1 and INTERLOCK 2 respectively, pins 47 and 49 input positive and negative 12V respectively, pins 51, 53, and 55 output fault signals DS1, DS2, and DS3 respectively, and pin 57 receives PA ON is the MSB binary high-bit turn-on signal, pin 59 receives the MID binary middle-bit turn-on signal, pin 61 receives the LSB binary low-bit turn-on signal, pin 63 receives the PA RESET reset signal, and pins 71 and 72 receive the excitation signals Bridge A and Bridge B respectively. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 This is the schematic diagram of the power amplifier circuit to be tested. Figure 2 It is a three-dimensional diagram of the platform. Figure 3 This is the functional architecture diagram of the test motherboard. Figure 4 This is the platform circuit schematic. Figure 5 is the slot and output circuit diagram, Figure 6 It is the input and output interface circuit diagram. Figure 7 This is the circuit diagram of the decoding indicator light. Figure 8 This is the schematic diagram of the dummy load. Fig. 9 This is the test circuit schematic. Implementation

[0019] The technical solution of the present invention is described in detail below with reference to the accompanying drawings.

[0020] Take the 3DX50 amplifier module as an example, it is a Class D switching amplifier. 8 field effect MOS tubes are connected in parallel into 4 groups, which is a full four-sided bridge configuration. Each amplifier is divided into bridge A and bridge B, and each amplifier bridge is composed of two pairs of MOSFETs in series. Each pair of MOSFETs is driven alternately into the cutoff and saturation states, like a switch. The excitation bridge signals sent to the two pairs of MOSFETs are 180 degrees out of phase. When the upper group is turned on, the lower group is turned off. The output level switches alternately between ground and +VDC power supply voltage at the carrier frequency rate, such as Figure 1 shown.

[0021] Use computer-aided design (CAD) software to complete the PCB design, simulation verification, and physical design of the test platform circuit, including layout, routing, layout, and DFM inspection, and export Gerber files for board making. Purchase components according to the BOM table and complete installation and welding, connect each circuit according to the platform architecture, use network analyzers, oscilloscopes, and multimeters to measure waveforms and values, and adjust the excitation signal, power supply, and dummy load impedance.

[0022] The control panel provides an excitation signal source interface and two slot interfaces for the test motherboard. Five control buttons and seven fault indicators are installed on the control panel to input control signals and display fault indications. The test motherboard and dummy load are fixed inside the cabinet, such as Figure 2 shown.

[0023] The test motherboard consists of a large step amplifier module slot, a binary module slot, an efficiency coil, and a filter circuit. The signal path includes a high-voltage power supply part, a low-voltage power supply part, an excitation signal part, a RF output part, a control signal part, and a fault output part, such as Figure 3 shown.

[0024] The 300V high-voltage power supply inputs the 205V driving power supply input driving power supply port J12, and is sent to the large-step power amplifier module through the power amplifier module slot J1, or is sent to the binary power amplifier module through the binary module slot J2, and is used for internal inverter voltage of the power amplifier module and rectified into 10V and 7.2V for use in the amplification and driving circuits.

[0025] The positive and negative 12V DC power supply is input into the DC power supply port J13 and sent to the power amplifier module through the power amplifier module slot J1. The positive 12V is used for the interlock detection circuit and the +5.5V voltage regulator is used for the logic device, and the negative 12V is used for the temperature detection circuit.

[0026] The excitation signal source uses a DSS arbitrary waveform signal generator to generate two 8Vp-p, 585kHz excitation signals A and B with a phase difference of 180°. They are sent to the excitation signal input ports RF1 and RF2 of the test motherboard through BNC RF coaxial cables, respectively, to drive four groups of eight MOSFET field effect tubes, control the 300V power switch at a frequency of 585kHz, alternately turn on bridge A and bridge B, and offset the distributed capacitance in the circuit through the efficiency coil, forming a 585kHz, 600Vp-p pulse waveform between the RF output ports J9 and J10, and sent to the dummy load through the coupling transformer T1 to be converted into heat, such as Figure 4 shown.

[0027] The RF output ports J9 and J10 use 10mm diameter pure copper gold-plated banana plug terminals, J1 and J2 use EDAC's 746-072-520-201 double-sided 72-way push-in card edge connector, and the amplifier signal input slots J1 and J2 are output from the J9 and J10 ports through the efficiency coil. Figure 5 shown.

[0028] Pins 1, 2, 3, 4, 5, 6, 9, 10, 11, 12, 13, and 14 of the J1 slot input a 300V DC power supply, pins 17 to 22 are connected to the J9 port, pins 25 to 30 are connected to the J10 port, pins 33 and 34 input a 205V drive power supply, pins 37, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56, 58, 60, 62, 64, 66, 68, 69, and 72 are grounded, pins 39 and 41 receive interlock signals INTERLOCK 1 and INTERLOCK 2 respectively, pins 47 and 49 input positive and negative 12V respectively, pins 51, 53, and 55 output fault signals DS1, DS2, and DS3 respectively, pin 57 receives the PA ON large step opening signal, pin 63 receives the PA RESET reset signal, and pins 71 and 72 receive the excitation signals Bridge A and Bridge B respectively. B.

[0029] Pins 1, 2, 3, 4, 5, 6, 9, 10, 11, 12, 13, and 14 of the J2 slot input a 300V DC power supply, pins 17 to 22 are connected to the J9 port, pins 25 to 30 are connected to the J10 port, pins 33 and 34 input a 205V drive power supply, pins 37, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56, 58, 60, 62, 64, 66, 68, 69, and 72 are grounded, pins 39 and 41 output interlock signals INTERLOCK 1 and INTERLOCK 2 respectively, pins 47 and 49 input positive and negative 12V respectively, pins 51, 53, and 55 output fault signals DS1, DS2, and DS3 respectively, and pin 57 receives PA ON is the MSB binary high-bit turn-on signal, pin 59 receives the MID binary middle-bit turn-on signal, pin 61 receives the LSB binary low-bit turn-on signal, pin 63 receives the PA RESET reset signal, and pins 71 and 72 receive the excitation signals Bridge A and Bridge B respectively.

[0030] Inductors L51 to L53 are 68 microhenries, and inductors L54 to L60 are 39 microhenries. These 10 inductors constitute the efficiency coil of the RF output part. Inductors L51 to L54 are connected in series, inductors L55 to L57 are connected in series, and inductors L58 to L60 are connected in series, and then connected in parallel to ports J9 and J10.

[0031] The interface circuit J4 uses an 8-bit screw terminal. The first 5 bits correspond to the control signal PA RESET reset signal, LSB binary low-bit open signal, MID binary middle-bit open signal, PA / MSB ON binary high-bit open signal / large step open signal, and interlock control signal. The last 3 bits correspond to the fault signals DS1, DS2, and DS3. The control button generates a set of TTL control signals and sends them to the interface circuit J4. If there is a fault, a three-bit coded TTL fault code signal is sent from the interface circuit J4 to the fault output circuit, such as Figure 6 shown.

[0032] Fault signals DS1, DS2, and DS3 are input into the 74HC138N 38 decoder, and the output red LED6 to LED11 correspond to INTERLOCK FAULT for interlock fault indication, PA / MSB FAULT for fault indication, MID FAULT for mid-bit binary fault indication, LSB FAULT for low-bit binary fault indication, and TEMP FAULT for over-temperature fault indication, and the output green LED11 corresponds to RESET reset indication, such as Figure 7 shown.

[0033] The code definitions are as follows: 010-INTERLOCK FAULT interlock fault, 110-PA / MSB FAULT power amplifier / high-order binary module fault signal, 001-MID FAULT mid-order binary module fault signal, 101-LSB FAULT low-order binary module fault signal, 011-TEMP FAULT over-temperature fault, 111-RESET reset signal enable.

[0034] The high-voltage power supply port J11 uses a 10mm diameter pure copper gold-plated banana head terminal, the drive power supply port J12 uses a screw terminal, and the DC power supply port J13 uses a screw terminal. After filtering, it supplies power to the two slots.

[0035] The excitation signal input ports RF1 and RF2 use elbow BNC RF coaxial connectors to receive the excitation signals Bridge A and Bridge B generated by the external DDS through 50-ohm coaxial cables and distribute them to two slots.

[0036] The RF OUT A and RF OUT B of the dummy load correspond to the RF output ports J9 and J10 of the test motherboard, and are connected to the primary of the dummy load transformer T1. One end of the secondary is grounded, and the other end is adjusted through the 0-25uH adjustable inductor L1 to adjust the impedance. Three sets of two-in-one microstrip resistors are connected. The model of a single microstrip resistor is RM800-50, with a resistance of 50Ω and a power of 800W. After the six resistors are connected in series and parallel, the resistance is 33.3Ω and the power capacity is 4800W. Figure 8 shown.

[0037] After the power amplifier module is inserted into J1, 300V, 205V, positive and negative 12V power supplies and Bridge A, Bridge B excitation signals are input into the large-step power amplifier module through J1. The cable interlock forms a loop with the power amplifier module cable interlock circuit through J1 to provide installation protection for the power amplifier module. The reset signal RESET clears the fault indication of the power amplifier module through J1. The PA ON large-step opening signal turns on the large-step power amplifier module through J1. After the binary power amplifier module is inserted into J2, the working process is similar. The MSB binary high-bit opening signal, the MID binary middle-bit opening signal, and the LSB binary low-bit opening signal respectively turn on the binary power amplifier module through J2. Fig. 9 shown.

[0038] The above are embodiments of the present invention and do not limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention are included in the protection scope of the present invention.

Claims

1. A 3DX medium wave transmitter power amplifier multifunctional test platform, characterized in that: include: The cabinet and control panel, the test motherboard and the dummy load are fixed inside the cabinet, the control panel provides an excitation signal source interface and two slot interfaces of the test motherboard, the control button and the fault indicator light are installed on the control panel, the control signal is input, and the fault indication is displayed; the test motherboard includes a large step amplifier module slot, a binary amplifier module slot, a high-voltage power supply port, a drive power supply port, a DC power supply port, a low-voltage power supply port, an excitation signal input port, a radio frequency output port, an efficiency coil, a filtering circuit, an interface circuit, and a decoding circuit, which are divided into a high-voltage power supply part, a low-voltage power supply part, an excitation signal part, a radio frequency output part, a control signal part, and a fault output part.

2. The 3DX medium wave transmitter power amplifier multifunctional test platform according to claim 1, characterized in that: Also includes: The large-step power amplifier module and the binary power amplifier module are inserted into the corresponding slots; the 300V input high-voltage power supply port and the 205V input drive power supply port belong to the high-voltage power supply part; the positive and negative 12V input DC power supply port and the 5V input low-voltage power supply port belong to the low-voltage power supply part, and the excitation signal source sends two excitation signals with a phase difference of 180° to the two excitation signal input ports, and drives the corresponding power amplifier modules through the two slots to control the 300V power switch with the excitation frequency, which belongs to the excitation signal part; the field effect tubes of the power amplifier module form two groups of bridges that are alternately turned on, and the distributed capacitance in the circuit is offset by the efficiency coil, forming a pulse waveform of the same frequency at the RF output port, and sent to the dummy load through the coupling transformer, which belongs to the RF output part; Input TTL control signal from the interface circuit through the control button to adjust the excitation input and RF output, which belongs to the control signal part; The fault signal outputs a set of TTL fault signals from the interface circuit and sends them to the decoding circuit to control the fault indicator light and display the fault type, which belongs to the fault output part.

3. The 3DX medium wave transmitter power amplifier multifunctional test platform according to claim 2 is characterized in that: The 205V input drive power supply port includes two slots, which send the supply voltage to the large step power amplifier module or the binary power amplifier module, which is used for internal voltage inversion of the power amplifier module and rectified into 10V and 7.2V for use in the amplification and driving circuits; the positive and negative 12V input DC power supply port includes two slots, which send the supply current to the large step power amplifier module or the binary power amplifier module, the positive 12V is used for the interlocking detection circuit and the +5.5V voltage regulator is used for the logic device, and the negative 12V is used for the temperature detection circuit.

4. The 3DX medium wave transmitter power amplifier multifunctional test platform according to claim 2, characterized in that: The efficiency coil uses 68 microhenry inductors L51 to L53 and 39 microhenry inductors L54 to L60. The inductors L51 to L54, L55 to L57, and L58 to L60 are connected in series and then connected in parallel to each other and bridged between the two RF output ports.

5. The 3DX medium wave transmitter power amplifier multifunctional test platform according to claim 2, characterized in that: The two input ports of the dummy load are connected to the two RF output ports of the test motherboard, corresponding to the primary of the coupling transformer, one end of the secondary is grounded, and the other end is connected to three groups of two-in-one microstrip resistors through an adjustable inductor to adjust the impedance.

6. The 3DX medium wave transmitter power amplifier multifunctional test platform according to claim 2, characterized in that: The two slots use 72-way push-in card edge connectors, the high-voltage power supply port and the RF output port use pure copper gold-plated banana head terminals, the interface circuit uses 8-bit screw terminals, the drive power supply port and the DC power supply port use screw terminals, and the excitation signal input port uses an elbow BNC RF coaxial connector to receive external excitation signals through a 50-ohm coaxial cable.

7. The 3DX medium wave transmitter power amplifier multifunctional test platform according to claim 6, characterized in that: The interface circuit comprises: a PA RESET reset signal, an LSB binary low-bit turn-on signal, a MID binary middle-bit turn-on signal, a PA / MSB ON binary high-bit turn-on signal / a large-step turn-on signal, and an interlocking control signal, the first five bits of which correspond in sequence to a control signal, and are independently generated by a control button; the PA RESET reset signal clears the fault indication of the power amplifier module; the LSB binary low-bit turn-on signal turns on the low bit; the MID binary middle-bit turn-on signal turns on the middle bit; the PA / MSB ON large-step turn-on signal turns on the large-step power amplifier module or turns on the high bit of the binary power amplifier module; and the interlocking signal interlocks the test motherboard with the power amplifier module to form a loop, thereby providing installation protection for the power amplifier module; and the last three bits correspond in sequence to fault signals DS1, DS2, and DS3, thereby forming a group of control signals.

8. The 3DX medium wave transmitter power amplifier multifunctional test platform according to claim 6, characterized in that: The fault signals DS1, DS2, and DS3 are input into the decoding circuit, and the code definitions are as follows: 010-INTERLOCK FAULT interlocking fault, 110-PA / MSB FAULT power amplifier / high-order binary module fault signal, 001-MID FAULT mid-order binary module fault signal, 101-LSB FAULT low-order binary module fault signal, 011-TEMP FAULT over-temperature fault, and 111-RESET reset signal enable, which controls the on and off of red LEDs 6 to LED 11, corresponding to the INTERLOCK FAULT interlocking fault indication, PA / MSB FAULT fault indication, MID FAULT mid-order binary fault indication, LSB FAULT low-order binary fault indication, and TEMP FAULT over-temperature fault indication, and controls the on and off of the green LED 11, corresponding to the RESET reset indication.

9. The 3DX medium wave transmitter power amplifier multifunctional test platform according to claim 1, characterized in that: The large-step power amplifier module slot includes: pins 1, 2, 3, 4, 5, 6, 9, 10, 11, 12, 13, and 14 input a 300V DC power supply, pins 17 to 22 are connected to a J9 port, pins 25 to 30 are connected to a J10 port, pins 33 and 34 input a 205V drive power supply, pins 37, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56, 58, 60, 62, 64, 66, 68, 69, and 72 are grounded, pins 39 and 41 receive interlocking signals INTERLOCK 1 and INTERLOCK 2 respectively, pins 47 and 49 input positive and negative 12V respectively, pins 51, 53, and 55 output fault signals DS1, DS2, and DS3 respectively, pin 57 receives a PA ON large-step opening signal, and pin 63 receives a PA RESET reset signal, pins 71 and 72 receive excitation signals Bridge A and Bridge B respectively.

10. The 3DX medium wave transmitter power amplifier multifunctional test platform according to claim 1, characterized in that: The binary power amplifier module slot includes: pins 1, 2, 3, 4, 5, 6, 9, 10, 11, 12, 13, and 14 input a 300V DC power supply, pins 17 to 22 are connected to a J9 port, pins 25 to 30 are connected to a J10 port, pins 33 and 34 input a 205V drive power supply, pins 37, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56, 58, 60, 62, 64, 66, 68, 69, and 72 are grounded, pins 39 and 41 output interlock signals INTERLOCK 1 and INTERLOCK 2 respectively, pins 47 and 49 input positive and negative 12V respectively, pins 51, 53, and 55 output fault signals DS1, DS2, and DS3 respectively, and pin 57 receives a PA ON is the MSB binary high-bit turn-on signal, pin 59 receives the MID binary middle-bit turn-on signal, pin 61 receives the LSB binary low-bit turn-on signal, pin 63 receives the PA RESET reset signal, and pins 71 and 72 receive the excitation signals Bridge A and Bridge B respectively.

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