Display panel and display device

Abstract

The embodiment of the utility model provides a display panel and a display device, relates to the technical field of display, and aims to reduce the production cycle of the display panel. The display panel comprises a substrate and a driving circuit layer. The driving circuit layer comprises a plurality of pixel driving circuits, a plurality of data write-in signal lines and a plurality of data leads. The data lead comprises a first lead section located on the first wiring metal layer and a second lead section located on the second wiring metal layer. And the first lead section is electrically connected with one data write-in signal line located in the edge area and one end of the second lead section. The second lead segment extends from the middle area to the binding area. The semiconductor layer includes a first conductive portion including a second pole of the first reset transistor. The second gate metal layer includes a first shielding portion. The orthographic projection of the first shielding part on the substrate, the orthographic projection of the first conductive part on the substrate and the orthographic projection of the first lead section on the substrate are overlapped. The display panel is used for displaying images.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] Organic Light Emitting Diode (OLED) display devices have become one of the most competitive and promising display devices due to their advantages such as self-luminescence, fast response speed, high brightness, full viewing angle, and flexible display. Utility Model Content

[0003] An object of the embodiments of the present disclosure is to provide a display panel and a display device, which are used to reduce the production cycle and cost of the display panel and improve the production efficiency of the display panel.

[0004] To achieve the above objectives, the embodiments of the present disclosure provide the following technical solutions:

[0005] In one aspect, a display panel is provided. The display panel includes a display area and a binding area, wherein the binding area is located on one side of the display area. The display area includes a middle area and two edge areas, wherein the middle area is located between the two edge areas along a first direction. The display panel includes a substrate and a drive circuit layer, wherein the drive circuit layer is located on one side of the substrate. The drive circuit layer includes: a plurality of pixel drive circuits, a plurality of data write signal lines, and a plurality of data leads. A plurality of pixel drive circuits are arranged in a plurality of rows and columns in the display area. The pixel drive circuit includes a drive transistor and a first reset transistor. The control electrode of the drive transistor is electrically connected to a first node, the first electrode of the drive transistor is electrically connected to a second node, and the second electrode of the drive transistor is electrically connected to a third node. A first reset transistor, wherein the control electrode of the first reset transistor is electrically connected to a first reset signal line, the first electrode of the first reset transistor is electrically connected to a first initialization signal line, and the second electrode of the first reset transistor is electrically connected to the first node. A plurality of data write signal lines are located in the display area, and the plurality of data write signal lines are arranged along the first direction and extend along the second direction, wherein the second direction intersects the first direction. A data write signal line connects a column of the pixel driving circuits. A plurality of data leads, the data leads include a first lead segment and a second lead segment, one end of the first lead segment is electrically connected to a data write signal line located in the edge region, and the other end of the first lead segment is electrically connected to one end of the second lead segment. The first lead segment extends along a first direction, the second lead segment extends along a second direction, and the second lead segment extends from the middle region to the binding region. In a direction away from the substrate, the driving circuit layer includes a semiconductor layer, a first gate metal layer, a second gate metal layer, a first routing metal layer, and a second routing metal layer. The semiconductor layer includes a first conductive portion, the first conductive portion includes a second electrode of a first reset transistor. The second gate metal layer includes a first shielding portion, the first shielding portion is configured to have a constant voltage signal. The first routing metal layer includes the first lead segment. The second routing metal layer includes the data write signal line and the second lead segment. The orthographic projection of the first shielding portion on the base substrate, the orthographic projection of the first conductive portion on the base substrate, and the orthographic projection of the first lead segment on the base substrate overlap.

[0006] In the above-mentioned display panel, the data writing signal line and the data lead are divided into the space of the first wiring metal layer and the second wiring metal layer, which can reduce two drawing processes compared to the display panel provided with the third wiring metal layer. Therefore, the cost of the display panel can be reduced, the production cycle of the display panel can be shortened, and the production efficiency of the display panel can be improved. In addition, the first shielding part with a constant voltage signal can be used to isolate the first conductive part and the first lead segment, improve the voltage jump at the position of the first conductive part when the data writing signal transmitted by the first lead segment jumps, indirectly improve the stability of the control electrode of the driving transistor, and help optimize the brightness uniformity of the display panel.

[0007] In some embodiments, the second gate metal layer further includes the first initialization signal line, and the first reset signal line is connected to the first shielding portion.

[0008] In some embodiments, the first initialization signal line includes a first auxiliary portion protruding toward the first reset transistor, and the orthographic projection of the first auxiliary portion on the base substrate, the orthographic projection of the first conductive portion on the base substrate, and the orthographic projection of the first lead segment on the base substrate overlap. The first auxiliary portion is multiplexed as the first shielding portion.

[0009] In some embodiments, the pixel driving circuit further includes a compensation transistor, the control electrode of the compensation transistor is electrically connected to the second scanning signal line, the first electrode of the compensation transistor is electrically connected to the third node, and the second electrode of the compensation transistor is electrically connected to the first node. The compensation transistor is a dual-gate transistor, and the control electrode of the compensation transistor includes a first control electrode and a second control electrode. The semiconductor layer further includes: a first channel portion of the compensation transistor, a second channel portion of the compensation transistor, and a second conductive portion, one end of the second conductive portion is connected to the first channel portion, and the other end of the second conductive portion is connected to the second channel portion. The first initialization signal line further includes a second auxiliary portion protruding toward the driving transistor, and the orthographic projection of the second auxiliary portion on the base substrate at least partially overlaps with the orthographic projection of the second conductive portion on the base substrate.

[0010] In some embodiments, an orthographic projection of the second conductive portion on the base substrate is located within a boundary of an orthographic projection of the second auxiliary portion on the base substrate.

[0011] In some embodiments, the second conductive portion includes a first sub-portion, a second sub-portion and a third sub-portion, wherein the first sub-portion, the second sub-portion and the third sub-portion intersect at the same point, wherein the first sub-portion is electrically connected to the first channel portion, the second sub-portion is electrically connected to the second channel portion, and the third sub-portion is located on a side of the second sub-portion away from the second channel portion.

[0012] In some embodiments, the pixel driving circuit further includes a data write transistor and a second reset transistor. The control electrode of the data write transistor is connected to the first scan signal line, the first electrode of the data write transistor is electrically connected to the data write signal line, and the second electrode of the data write transistor is electrically connected to the second node. The control electrode of the second reset transistor is electrically connected to the first scan signal line, the first electrode of the second reset transistor is electrically connected to the second initialization signal line, and the second electrode of the second reset transistor is electrically connected to the fourth node. Along the first direction, the control electrode of the data write transistor and the control electrode of the second reset transistor overlap.

[0013] In some embodiments, the pixel driving circuit further includes a first light emission control transistor and a second light emission control transistor. The control electrode of the first light emission control transistor is electrically connected to the first enable signal line, the first electrode of the first light emission control transistor is electrically connected to the first power signal line, and the second electrode of the first light emission control transistor is electrically connected to the second node. The control electrode of the second light emission control transistor is electrically connected to the second enable signal line, the first electrode of the second light emission control transistor is electrically connected to the third node, and the second electrode of the second light emission control transistor is electrically connected to the fourth node.

[0014] In some embodiments, the pixel driving circuit further includes a storage capacitor and a first capacitor. The first plate of the storage capacitor is electrically connected to the first node, and the second plate of the storage capacitor is electrically connected to the first power signal line. The first plate of the first capacitor is electrically connected to the second node, and the first plate of the first capacitor is electrically connected to the first power signal line.

[0015] In some embodiments, the pixel driving circuit includes a data writing transistor and a first light emission control transistor. The semiconductor layer includes a third conductive portion, and the third conductive portion includes a first electrode of the driving transistor, a second electrode of the first light emission control transistor, and a second electrode of the data writing transistor. The second gate metal layer also includes a fourth conductive portion, one end of the fourth conductive portion is electrically connected to the second electrode plate of the storage capacitor, and the other end of the fourth conductive portion is electrically connected to the first electrode of the first light emission control transistor. The orthographic projection of the fourth conductive portion on the substrate at least partially overlaps with the orthographic projection of the third conductive portion on the substrate. The third conductive portion is multiplexed as the first electrode plate of the first capacitor, and the fourth conductive portion is multiplexed as the second electrode plate of the first capacitor.

[0016] In some embodiments, along the second direction, the third conductive portion is away from a side of the channel portion of the first light emission control transistor and protrudes out of the channel portion of the driving transistor.

[0017] In some embodiments, along the first direction, two adjacent pixel driving circuits are symmetrical.

[0018] In some embodiments, along the first direction, the first electrode of the driving transistor in the nth pixel driving circuit is adjacent to the first electrode of the driving transistor in the n+1th pixel driving circuit, where n is a positive integer.

[0019] In some embodiments, the second plate of the storage capacitor of the nth pixel driving circuit is electrically connected to the second plate of the storage capacitor in the pixel driving circuit of the n+1th sub-pixel, where n is a positive integer.

[0020] In some embodiments, along the first direction, the second reset transistor in the n+1th pixel driving circuit is arranged adjacent to the second reset transistor in the n+2th pixel driving circuit, and the first electrode of the second reset transistor in the n+1th pixel driving circuit is reused as the first electrode of the second reset transistor in the n+2th pixel driving circuit.

[0021] In some embodiments, the first routing metal layer further includes a plurality of first virtual lead segments, the first virtual lead segments correspond to the first lead segments one by one, and along the first direction, the first lead segments and the first virtual lead segments are spaced apart.

[0022] In some embodiments, the second routing metal layer further includes a plurality of second virtual lead segments, the second virtual lead segments correspond to the second lead segments one by one, and along the first direction, the second lead segments and the second virtual lead segments are arranged at intervals.

[0023] In some embodiments, the display panel further includes a bottom shielding layer, the bottom shielding layer is located between the base substrate and the pixel driving circuit, and the orthographic projection of the bottom shielding layer on the base substrate covers the orthographic projection of the driving transistor on the base substrate.

[0024] In some embodiments, the display panel further comprises a light emitting device layer, which is located on a side of the driving circuit layer away from the base substrate. The light emitting device layer comprises a plurality of light emitting devices, which are electrically connected to the pixel driving circuit.

[0025] In another aspect, a display device is provided, comprising: a display panel as described in any one of the above embodiments.

[0026] The above-mentioned display device has the same structure and beneficial technical effects as the display panels provided in some of the above-mentioned embodiments, which will not be described in detail here. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the technical solutions in the present disclosure, the following briefly introduces the drawings required to be used in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can also be obtained based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams, and are not limitations on the actual size of the product involved in the embodiments of the present disclosure, the actual process of the method, the actual timing of the signal, etc.

[0028] Figure 1 is a structural diagram of a display device according to some embodiments;

[0029] Figure 2 is a structural diagram of a display panel according to some embodiments;

[0030] Figure 3 is a cross-sectional view of a display panel according to some embodiments;

[0031] Figure 4 is a circuit diagram of a pixel driving circuit according to some embodiments;

[0032] Figure 5 is a circuit diagram of a pixel driving circuit according to some other embodiments;

[0033] Figure 6 is a timing diagram of a pixel driving circuit according to some embodiments;

[0034] Figure 7 is a circuit diagram of a pixel driving circuit according to some further embodiments;

[0035] Figure 8 is a film layer structure diagram of multiple pixel driving circuits according to some embodiments;

[0036] Fig. 9 is a film layer structure diagram of a plurality of pixel driving circuits according to some other embodiments;

[0037] Fig.10 for Fig. 9 Structural diagram of the semiconductor layer in the middle;

[0038] Fig.11 is a structural diagram of a semiconductor layer according to some embodiments;

[0039] Fig.12 for Fig. 9 A structural diagram of the first gate metal layer;

[0040] Fig.13 for Fig. 9 A structural diagram of the second gate metal layer;

[0041] Fig.14 for Fig. 9 A structural diagram of a middle semiconductor layer, a first gate metal layer, and a second gate metal layer;

[0042] Fig.15 for Fig. 9 The structural diagram of the first routing metal layer in the figure;

[0043] Fig.16 for Fig. 9 A structural diagram of a middle semiconductor layer, a first gate metal layer, a second gate metal layer and a first wiring metal layer;

[0044] Fig.17 for Fig. 9 The structural diagram of the second routing metal layer;

[0045] Fig.18 is a film layer structure diagram of a plurality of pixel driving circuits according to some other embodiments;

[0046] Fig.19 for Fig.18 Structural diagram of the middle and bottom shielding layers. DETAILED DESCRIPTION

[0047] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present disclosure.

[0048] Unless the context requires otherwise, throughout the specification and claims, the term "comprise" and other forms thereof, such as the third person singular form "comprises" and the present participle form "comprising", are to be interpreted as open, inclusive, that is, "including, but not limited to". In the description of the specification, the terms "some embodiments", "example", or "some examples" and the like are intended to indicate that specific features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0049] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0050] When describing some embodiments, the expression "connection" and its derivatives may be used. The term "connection" should be understood in a broad sense. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected or indirectly connected through an intermediate medium. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0051] “At least one of A, B, and C” has the same meaning as “at least one of A, B, or C” and both include the following combinations of A, B, and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B, and C.

[0052] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0053] As used herein, the term "if" is optionally interpreted to mean "when" or "upon...", depending on the context. Similarly, the phrases "if it is determined that ..." or "if [stated condition or event] is detected" are optionally interpreted to mean "upon determining that ..." or "in response to determining that ...", depending on the context.

[0054] The use of "adapted to" or "configured to" herein is meant to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0055] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0056] As used herein, "about," "substantially," or "approximately" includes the stated value and an average value that is within an acceptable range of variation from the particular value as determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0057] As used herein, "parallel", "perpendicular", and "equal" include the situations described and situations similar to the situations described, and the range of the similar situations is within the acceptable deviation range, wherein the acceptable deviation range is determined by a person of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximate parallelism, wherein the acceptable deviation range of approximate parallelism may be, for example, a deviation within 5°; "perpendicular" includes absolute perpendicularity and approximate perpendicularity, wherein the acceptable deviation range of approximate perpendicularity may also be, for example, a deviation within 5°. "Equal" includes absolute equality and approximate equality, wherein the acceptable deviation range of approximate equality may be, for example, the difference between the two equalities is less than or equal to 5% of either one.

[0058] It will be understood that when a layer or an element is referred to as being on another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may be present between the layer or element and the other layer or substrate.

[0059] Exemplary embodiments are described herein with reference to cross-sectional views and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of the layers and the area of ​​the regions are exaggerated for clarity. Therefore, variations in the shapes relative to the drawings due to, for example, manufacturing techniques and / or tolerances are conceivable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shapes of the regions of the device, and are not intended to limit the scope of the exemplary embodiments.

[0060] In the circuit provided by the embodiments of the present disclosure, the first node, the second node, the third node and the fourth node do not represent actually existing components, but represent the junction points of related electrical connections in the circuit diagram, that is, these nodes are nodes formed by the equivalent junction points of related electrical connections in the circuit diagram.

[0061] Figure 1 is a structural diagram of a display device according to some embodiments. Figure 1 As shown, some embodiments of the present disclosure provide a display device 200 , which includes a display panel 100 .

[0062] Exemplarily, the display device 200 also includes a frame and other electronic accessories.

[0063] Exemplarily, the display device 200 may be an electroluminescent display device or a photoluminescent display device. When the display device is an electroluminescent display device, the electroluminescent display device may be an organic light emitting diode (OLED) or a quantum dot electroluminescent display device (QLED). When the display device is a photoluminescent display device, the photoluminescent display device may be a quantum dot photoluminescent display device.

[0064] Exemplarily, the display device 200 can be any display device that displays images, whether in motion (e.g., video) or fixed (e.g., still images), and whether text or images. More specifically, it is expected that the display device of the embodiments described can be implemented in or associated with a variety of electronic devices, such as (but not limited to) mobile phones, wireless devices, personal data assistants (PDAs), handheld or portable computers, GPS receivers / navigators, cameras, MP4 video players, camcorders, game consoles, watches, clocks, calculators, television monitors, flat panel displays, computer monitors, automotive displays (e.g., odometer displays, etc.), navigators, cockpit controls and / or displays, displays of camera views (e.g., displays of rear-view cameras in vehicles), electronic photographs, electronic billboards or signs, projectors, architectural structures, packaging, and aesthetic structures (e.g., displays of images of a piece of jewelry), etc.

[0065] Figure 2 is a structural diagram of a display panel according to some embodiments.

[0066] like Figure 2As shown, some embodiments of the present disclosure provide a display panel 100, and the display panel 100 includes a display area (full name in English: Active Area, abbreviated as AA area; also called effective display area) AA.

[0067] The display panel 100 may include a plurality of sub-pixels P, and the plurality of sub-pixels P are disposed in the display area AA, wherein the plurality of sub-pixels may be arranged in an array.

[0068] The sub-pixel P is the smallest unit for displaying images on the display panel 100. The multiple sub-pixels P may include red sub-pixels, blue sub-pixels and green sub-pixels. By adjusting the brightness (grayscale) of sub-pixels of different colors, multiple colors can be displayed through color combination and superposition, thereby realizing full-color display of the display panel 100.

[0069] In some other examples, the display panel 100 may further include a white sub-pixel.

[0070] In some examples, the display area AA includes a middle area AA1 and two edge areas AA2 , and along the first direction X, the middle area AA1 is located between the two edge areas AA2 .

[0071] Exemplarily, along the first direction X, the widths of the two edge regions AA2 of the display area AA are the same or approximately the same.

[0072] Figure 3 is a cross-sectional view of a display panel according to some embodiments.

[0073] like Figure 3 As shown, each sub-pixel P may include a light emitting device O and a pixel driving circuit Q for driving the light emitting device O.

[0074] In addition, the display panel 100 may further include a plurality of signal lines. The plurality of signal lines may be electrically connected to the pixel driving circuit Q to provide the pixel driving circuit Q with the signals required by the pixel driving circuit Q. The plurality of signal lines electrically connected to the pixel driving circuit Q will be described in detail below in terms of their functions and layout in the display panel 100.

[0075] Combination Figure 2 and Figure 3 As shown, the display panel 100 includes a base substrate 10, a driving circuit layer 20 and a light emitting device layer 30. The driving circuit layer 20 is located between the base substrate 10 and the light emitting device layer 30.

[0076] In some examples, the substrate 10 may be a flexible substrate. Exemplarily, the material of the substrate 10 may be an organic material. For example, the material of the substrate 10 may be any one of polyimide (PI), polycarbonate (PC), or polyvinyl chloride (PVC).

[0077] In some other examples, the substrate 10 may be a rigid substrate, for example, a glass substrate or a PMMA (Polymethyl methacrylate) substrate.

[0078] In some examples, the light emitting device layer 30 includes a plurality of light emitting devices O, and the plurality of light emitting devices O are electrically connected to a plurality of pixel driving circuits Q.

[0079] In some examples, the plurality of pixel driving circuits Q and the plurality of light emitting devices O may be electrically connected in a one-to-one correspondence. In other examples, one pixel driving circuit Q may be electrically connected to a plurality of light emitting devices O, or a plurality of pixel driving circuits Q may be electrically connected to one light emitting device O.

[0080] Below, the present disclosure takes the electrical connection between a pixel driving circuit Q and a light-emitting device O as an example to schematically illustrate the structure of the display panel 100 .

[0081] In some examples, the light-emitting device O includes an anode layer, a light-emitting layer, and a cathode layer stacked in sequence. In some examples, an electron transport layer is further provided between the cathode layer and the light-emitting layer, and a hole transport layer is further provided between the anode layer and the light-emitting layer. Exemplarily, the light-emitting device O may be an OLED light-emitting device, but is not limited thereto. The embodiments of the present disclosure do not limit the type of light-emitting device, that is, the light-emitting device O may be any other light-emitting device (e.g., a light-emitting device that emits light by discharge), as long as they can emit light so that the display panel 100 can display a picture.

[0082] The driving circuit layer 20 further includes a plurality of pixel driving circuits Q, and the plurality of pixel driving circuits Q are arranged in a plurality of rows and columns in the display area AA. The pixel driving circuits Q arranged in a row along the first direction X are referred to as a pixel driving circuit row, and the pixel driving circuits Q arranged in a row along the second direction Y are referred to as a pixel driving circuit column.

[0083] The first direction X and the second direction Y intersect.

[0084] In some examples, the first direction X and the second direction Y may be approximately perpendicular, and the angle between the first direction X and the second direction Y is approximately equal to 90°. For example, the angle between the first direction X and the second direction Y may be 85°, 90°, or 95°.

[0085] The pixel driving circuit Q is distributed in the film layer of the driving circuit layer 20 . The specific distribution of the pixel driving circuit Q in the driving circuit layer 20 will be described in detail below.

[0086] For the convenience of explanation, the above-mentioned multiple pixel driving circuits Q are described in the present disclosure by taking a matrix arrangement as an example.

[0087] In some examples, the structure of the pixel driving circuit Q includes multiple types, which can be selected and set according to actual needs. For example, the structure of the sub-pixel driving circuit may include "2T1C", "6T1C", "7T1C", "6T2C", "7T2C" or "8T1C", etc. Here, "T" represents a thin film transistor, and the number in front of "T" represents the number of thin film transistors; "C" represents a storage capacitor C, and the number in front of "C" represents the number of storage capacitors C. The following is an introduction to the sub-pixel driving circuit of "7T1C" as an example.

[0088] Figure 4 is a circuit diagram of a pixel driving circuit according to some embodiments.

[0089] In some examples, such as Figure 4 As shown, the pixel driving circuit Q includes: a first reset transistor T1, a compensation transistor T2, a driving transistor T3, a data writing transistor T4, a first light emission control transistor T5, a second light emission control transistor T6, a second reset transistor T7 and a storage capacitor Cst.

[0090] The gate g1 of the first reset transistor T1 is electrically connected to the first reset signal line R1, the first electrode s1 of the first reset transistor T1 is electrically connected to the first initialization signal line Vinit1, and the second electrode d1 of the first reset transistor T1 is electrically connected to the first node N1. The first reset transistor T1 is configured to, under the control of the first reset signal received from the first reset signal line R1, transmit the first initialization signal received at the first initialization signal line Vinit1 to the first node N1 to reset the first node N1.

[0091] A gate g2 of the compensation transistor T2 is electrically connected to the second scanning signal line G2 , a first electrode s2 of the compensation transistor T2 is electrically connected to the first node N1 , and a second electrode d2 of the compensation transistor T2 is electrically connected to the third node N3 .

[0092] The gate g3 of the driving transistor T3 is electrically connected to the first node N1, the first electrode s3 of the driving transistor T3 is electrically connected to the second node N2, and the second electrode d3 of the driving transistor T3 is electrically connected to the third node N3.

[0093] A gate g4 of the data writing transistor T4 is electrically connected to the first scanning signal line G1 , a first electrode s4 of the data writing transistor T4 is electrically connected to the data writing signal line Data, and a second electrode d4 of the data writing transistor T4 is electrically connected to the second node N2 .

[0094] A gate g5 of the first light emission control transistor T5 is electrically connected to the first enable signal line EM1, a first electrode s5 of the first light emission control transistor T5 is electrically connected to the first power signal line VDD, and a second electrode d5 of the first light emission control transistor T5 is electrically connected to the second node N2.

[0095] The gate g6 of the second light emitting control transistor T6 is electrically connected to the first enable signal line EM1, the first electrode s6 of the second light emitting control transistor T6 is electrically connected to the third node N3, and the second electrode d6 of the second light emitting control transistor T6 is electrically connected to the fourth node N4. The fourth node in the pixel driving circuit Q can be the output terminal of the pixel driving circuit. That is, the fourth node N4 of the pixel driving circuit Q can be electrically connected to the light emitting device O. Exemplarily, the fourth node N4 of the pixel driving circuit Q can be electrically connected to the anode of the light emitting device O. In addition, the cathode of the light emitting device O can be electrically connected to the second power signal line VSS. The voltage of the first power signal provided by the first power signal line VDD is higher than the voltage of the second power signal provided by the second power signal line VSS.

[0096] The first light emitting control transistor T5 and the second light emitting control transistor T6 are configured to cooperate with the driving transistor T3 to transmit a driving signal to the light emitting device O under the control of the first enable signal from the first enable signal line EM1.

[0097] The gate g7 of the second reset transistor T7 is electrically connected to the second reset signal line R2, the first electrode s7 of the second reset transistor T7 is electrically connected to the second initialization signal line Vinit2, and the second electrode d7 of the second reset transistor T7 is electrically connected to the fourth node N4. The second reset transistor T7 is configured to: under the control of the second reset signal received from the second reset signal line R2, transmit the second initialization signal received from the second initialization signal line V2 to the fourth node N4, and reset the fourth node N4. Among them, the fourth node N4 is electrically connected to the light emitting device O, and resetting the fourth node N4 is equivalent to resetting the anode of the light emitting device O using the signal, thereby improving the stability of the light emitting device O.

[0098] The first plate Cst-1 of the storage capacitor Cst is electrically connected to the first node N1, and the second plate Cst-2 of the storage capacitor Cst is electrically connected to the first power signal line VDD.

[0099] In some examples, the compensation transistor T2 may be an N-type transistor, and the first reset transistor T1 , the driving transistor T3 , the data writing transistor T4 , the first emission control transistor T5 , the second emission control transistor T6 , and the second reset transistor T7 may be P-type transistors.

[0100] In some examples, the compensation transistor T2 may be an oxide transistor, which may be an N-type transistor, and the other transistors may be LTPS (Low Temperature Poly Silicon) transistors, which may be P-type transistors.

[0101] Among them, the N-type transistor is turned on when the gate receives a high voltage signal, and the P-type transistor is turned on when the gate receives a low voltage signal. It should be noted that the "high voltage signal" and "low voltage signal" mentioned above are popular terms. Generally speaking, the opening condition of the N-type transistor is that the gate-source voltage difference is greater than its threshold voltage, that is, the gate voltage of the N-type transistor is greater than the sum of its source voltage and its threshold voltage, and the threshold voltage of the N-type transistor is a positive value, then the gate voltage signal that turns on the N-type transistor is called a high voltage signal, and the opening condition of the P-type transistor is that the absolute value of the gate-source voltage difference is greater than its threshold voltage, and the threshold voltage of the P-type transistor is a negative value, that is, the gate voltage of the P-type transistor is less than the sum of its source voltage and its threshold voltage, then the gate voltage signal that turns on the P-type transistor is called a low voltage signal, wherein the voltage of the "high voltage signal" is greater than the voltage of the "low voltage signal".

[0102] In some other examples, the plurality of transistors may all be P-type transistors, and in some other examples, the plurality of transistors may all be N-type transistors.

[0103] in, Figure 4 The pixel driving circuit Q shown is illustrated by taking the first reset transistor T1 and the compensation transistor T2 as N-type transistors, and the other transistors as P-type transistors as an example. Such an arrangement can help reduce the risk of leakage of the compensation transistor T2 and the first reset transistor T1, and is more conducive to ensuring the stability of the voltage of the first node N1, that is, ensuring the stability of the control electrode g1 of the driving transistor T3.

[0104] Figure 5 is a circuit diagram of a pixel driving circuit according to some other embodiments.

[0105] In some embodiments, Figure 5As shown, the second scanning signal line G2 used to drive the n-th row of pixel driving circuits Q responds to the same signal terminal as the first reset signal line R1(n+m) of the n+m-th row of pixel driving circuits Q. In other words, the second scanning signal line G2 used to drive the n-th row of pixel driving circuits Q can be reused as the first reset signal line R1(n+m) of the subsequent m-th row of pixel driving circuits Q. Where n and m are both natural numbers, and n>m. Figure 5 In the figure, m=7 is taken as an example for illustration.

[0106] It can also be understood that the first reset signal line R1 for driving the n-th row pixel driving circuit Q responds to the same signal terminal as the second scanning signal line G2(nm) for the nm-th row pixel driving circuit Q. That is, the first reset transistor T1 of the n-th row pixel driving circuit Q can be driven by the second scanning signal line G2(nm) for driving the nm-th row pixel driving circuit Q. Based on this, the first reset signal line R1 for driving the n-th row pixel driving circuit Q is represented by the second scanning signal line G2(nm) below, and the second scanning signal line G2 is still represented as the second scanning signal line for driving the n-th row pixel driving circuit Q.

[0107] Therefore, when the second scanning signal line G2 drives the compensation transistor T2 of the pixel driving circuit Q in the nth row to turn on, the first reset transistor T1 of the pixel driving circuit Q in the mth row can also be turned on to reset the first node N1.

[0108] As set above, the second scanning signal line G2 and the first reset signal line R1 (second scanning signal line G2 (nm)) used to drive the nth row of pixel driving circuits Q respond to the same signal terminal, which can reduce the number of signal terminals in the display panel 100 and save space in the display panel 100.

[0109] In some examples, m=7. The first reset signal line R1 for driving the n-th row of pixel driving circuits Q responds to the same signal terminal as the second scan signal line G2(n-7) for the n-7-th row of pixel driving circuits Q. In other words, the first reset transistor T1 for the n-th row of pixel driving circuits Q can be driven by the second scan signal line G2(n-7) for driving the n-7-th row of pixel driving circuits Q. Figure 5 In the figure, G2(n-7) indicates the second scanning signal line G2 electrically connected to the first 7 rows of pixel driving circuits Q of the pixel driving circuit Q. In the following, the first reset signal line R1 is indicated by the second scanning signal line G2(n-7) of the pixel driving circuit Q of the n-7th row.

[0110] Based on this, when the second scanning signal line G2 (n-7) drives the compensation transistor T2 of the pixel driving circuit Q of the n-7th row to turn on, it can also drive the first reset transistor T1 of the pixel driving circuit Q of the nth row to turn on, and reset the first node N1. Further, it can ensure that the control electrode g3 (first node N1) of the driving transistor T3 is initialized before the compensation stage (data writing stage), thereby improving the stability of the driving transistor T3.

[0111] It is understandable that in other examples, m may be other natural numbers. For example, the pixel driving circuit Q in the nth row may be driven by the second scanning signal line G2 that drives the pixel driving circuit Q in the n-3th row.

[0112] Based on this, the first reset transistor T1 of the pixel driving circuit Q of the nth row can be driven by the second scanning signal line G2 (n-7) driving the pixel driving circuit Q of the n-7th row.

[0113] In some embodiments, Figure 5 As shown, the first scan signal line G1 can be multiplexed as the second reset signal line R2. When the first scan signal line G1 controls the data writing transistor T4 to turn on, the second reset transistor T7 can be controlled to turn on at the same time, and the second initialization signal received from the second initialization signal line V2 is transmitted to the fourth node N4, and the fourth node N4 is reset. That is, the anode of the light emitting device O is reset, and the stability of the light emitting device O is improved.

[0114] In some embodiments, Figure 5 As shown, the pixel driving circuit Q includes a first reset transistor T1, a compensation transistor T2, a driving transistor T3, a data writing transistor T4, a first light emission control transistor T5, a second light emission control transistor T6, a second reset transistor T7 and a storage capacitor Cst.

[0115] Figure 5 The first light emission control transistor T5 and the second light emission control transistor T6 in the pixel driving circuit Q shown in the figure may not be controlled by the same first enable signal line EM1. That is, the first light emission control transistor T5 and the second light emission control transistor T6 are controlled by two enable signal lines respectively.

[0116] Specifically, the control electrode g5 of the first light emission control transistor T5 is electrically connected to the first enable signal line EM1, and the control electrode g6 of the second light emission control transistor T6 is electrically connected to the second enable signal line EM2.

[0117] Based on this, two enable signal lines (first enable signal line EM1 and second enable signal line EM2) can be used to control two emission control transistors (first emission control transistor T5 and second emission control transistor T6) respectively. Further, the first emission control transistor T5 and the second emission control transistor T6 can be controlled to turn on in sequence.

[0118] Thus, it is equivalent to resetting the first power signal line pair and the second node N2 before the light emitting device O receives the driving signal to emit light, so that the voltage at the first electrode s3 position of the driving transistor T3 of the pixel driving circuit Q in a pixel driving circuit row remains consistent for a period of time. Thus, the problem of afterimage caused by TFT characteristic drift can be improved, and the display quality of the display panel 100 can be improved.

[0119] Figure 6 is a timing diagram of a pixel driving circuit according to some embodiments.

[0120] Combination Figure 5 and Figure 6 As shown, the driving process of the pixel driving circuit Q is as follows: one frame period includes an initialization phase t1, a data writing phase t2 and a light emitting phase t3.

[0121] Initialization stage t1: the first enable signal line transmitted by the first enable signal line is a high voltage signal, the second enable signal line transmitted by the second enable signal line is a high voltage signal, the first scan signal transmitted by the first scan signal line G1 is a high voltage signal, the second scan signal line G2 transmits the second scan signal as a high voltage signal line, and the first reset signal line R1 (the first 7 rows of pixel driving circuits Q are electrically connected) and the second scan signal line G2 transmits the first reset signal (second scan signal) as a low voltage signal.

[0122] At this time, the compensation transistor T2, the data writing transistor T4, the first light emission control transistor T5, the second light emission control transistor T6 and the second reset transistor T7 are in a closed state. The first reset transistor T1 is in an open state, and the first initialization signal transmitted by the first initialization signal line Vinit1 is transmitted to the first node N1 to reset the first node N1. At this time, the voltage at the first node N1 is the voltage V1 of the first initialization signal.

[0123] Data writing stage t2: the first enable signal line transmitted by the first enable signal line is a high voltage signal, the second enable signal line transmitted by the second enable signal line is a high voltage signal, and the first reset signal line R1 (the first 7 rows of pixel driving circuits Q are electrically connected to the second scan signal line G2) transmits a first reset signal (second scan signal) as a high voltage signal. In addition, the first scan signal transmitted by the first scan signal line G1 is a low voltage signal and the second scan signal transmitted by the second scan signal line G2 is a low voltage signal line.

[0124] At this time, the first reset transistor T1, the first light emission control transistor T5 and the second light emission control transistor T6 are in the off state. The data write transistor T4 and the compensation transistor T2 are in the on state. At this time, the data write signal line Data transmits the data write signal to the second node N2 through the data write transistor T4. That is, the voltage at the second node N2 is the voltage Vdata of the data write signal. Therefore, Vgs of the driving transistor T3 is V1-Vdata, Vgs<Vth, and the driving transistor T3 is in the on state.

[0125] Since the data write transistor T4, the driving transistor T3 and the compensation transistor T2 are all in the open state during this stage, the data write signal line Data transmits the data write signal which can be sequentially transmitted through the data write transistor T4, the driving transistor T3 and the compensation transistor T2 to the first node N1, and the first node N1 is compensated. The potential of the first node N1 gradually rises to Vdata+Vth, the driving transistor T3 is turned off, and the storage capacitor Cst completes the charging process.

[0126] Wherein, Vdata is the voltage value of the data writing signal provided by the data writing signal line Data, and Vth is the threshold voltage of the driving transistor T3 in the pixel driving circuit Q.

[0127] Furthermore, since the first scan signal line G1 can be multiplexed as the second reset signal line R2, during this stage, the second reset transistor T7 can receive the low voltage signal from the first scan signal line G1 and turn on, and transmit the second initialization signal received from the second initialization signal line V2 to the fourth node N4, and reset the fourth node N4. The fourth node N4 is electrically connected to the light emitting device O, and resetting the fourth node N4 is equivalent to resetting the anode of the light emitting device O using the signal, thereby improving the stability of the light emitting device O.

[0128] In the light-emitting stage t3: the first scanning signal transmitted by the first scanning signal line G1 is a high voltage signal, the second scanning signal transmitted by the second scanning signal line G2 is a high voltage signal line, and the first reset signal transmitted by the first reset signal line R1 (the second scanning signal line G2 (n-7)) is a high voltage signal. In addition, the first enable signal line transmitted by the first enable signal line is a low voltage signal, and the second enable signal line transmitted by the second enable signal line is a low voltage signal.

[0129] At this time, the first reset transistor T1, the compensation transistor T2, the data writing transistor T4 and the second reset transistor T7 are in the off state. The first light emission control transistor T5 and the second light emission control transistor T6 are turned on. In addition, the driving transistor T3 is continuously turned on in this stage.

[0130] Based on this, the constant voltage power signal provided by the first power signal line VDD can flow through the first light-emitting control transistor T5, the driving transistor T3, and the second light-emitting control transistor T6 in sequence to the anode of the light-emitting device O, and the cathode of the light-emitting device O can be electrically connected to the second power signal line VSS, thereby driving the light-emitting device O to emit light.

[0131] In addition, since the two light-emitting control transistors (the first light-emitting control transistor T5 and the second light-emitting control transistor T6) are controlled by two enable signal lines (the first enable signal line EM1 and the second enable signal line EM2), respectively, the falling edge of the first enable signal transmitted by the first enable signal line EM1 is earlier than the falling edge of the second enable signal transmitted by the second enable signal line EM2. Thus, the first light-emitting control transistor T5 and the second light-emitting control transistor T6 can be controlled to be turned on in sequence.

[0132] In the light-emitting stage t3: under the control of the first enable signal from the first enable signal line EM1, the first light-emitting control transistor T5 can be controlled to turn on first, and the first power signal line from the first power signal line VDD can be transmitted to the second node N2 (the first pole s3 of the driving transistor T3) via the first light-emitting control transistor T5. Furthermore, the first power signal line can be used to reset the second node N2, so that the voltage at the first pole s3 position of the driving transistor T3 of the pixel driving circuit Q in a pixel driving circuit row remains consistent for a period of time. After that, the first light-emitting control transistor T5 remains in the turned-on state, and under the control of the second enable signal from the second enable signal line EM2, the second light-emitting control transistor T6 is controlled to turn on, and cooperates with the driving transistor T3 to transmit the driving signal to the light-emitting device O.

[0133] Based on this, it is equivalent to using the first power signal line pair and the second node N2 to reset before the light emitting device O receives the driving signal to emit light, so that the voltage at the first electrode s3 position of the driving transistor T3 of the pixel driving circuit Q in a pixel driving circuit row remains consistent for a period of time. In this way, the problem of afterimage caused by TFT characteristic drift can be improved, and the display quality of the display panel 100 can be improved.

[0134] Figure 7 is a circuit diagram of a pixel driving circuit according to some further embodiments.

[0135] In some embodiments, Figure 7 As shown, the pixel driving circuit Q further includes a first capacitor C1, a first plate C1-1 of the first capacitor C1 is electrically connected to the first power signal line VDD, and a second plate C1-2 of the first capacitor C1 is electrically connected to the second node N2.

[0136] Figure 7 The pixel driving circuit Q shown in FIG. Figure 5 The difference of the pixel driving circuit Q shown is: Figure 7 In the pixel driving circuit Q shown, a first capacitor is connected in series between the second node N2 and the first power signal line VDD, and other components are the same.

[0137] The following will Figure 7 The driving process of the pixel driving circuit Q is introduced, where the 7 transistors in the pixel driving circuit Q are all P-type transistors.

[0138] Combination Figure 6 and Figure 7 As shown, Figure 7 The driving process of the pixel driving circuit Q shown is as follows: one frame period includes an initialization phase t1, a data writing phase t2 and a light emitting phase t3. Figure 7 The initialization phase t1 and the light emitting phase t3 of the driving process of the pixel driving circuit Q shown in FIG. Figure 5 The driving process of the pixel driving circuit Q shown is substantially the same and will not be described in detail herein.

[0139] and Figure 7 The driving process of the pixel driving circuit Q shown in FIG. Figure 5 The difference in the driving process of the pixel driving circuit Q shown is: Figure 7 The data writing phase t2 of the driving process of the pixel driving circuit Q shown in FIG. 1 includes not only the above Figure 5 The data writing phase t2 in the driving process of the pixel driving circuit Q shown in FIG. 1 also includes the following phases.

[0140] When the data write signal is transmitted to the second node N2, it is equivalent to transmitting the data write signal to the first capacitor C1. Based on this, the first capacitor C1 also synchronously stores the voltage of the data write signal in this stage.

[0141] In the sub-phase t21 after the data writing transistor T4 is turned off and before the compensation transistor T2 is turned off, the first capacitor C1 can be discharged to the first node N1 until the compensation transistor T2 is turned off. Thus, the writing time of the data writing signal can be indirectly extended, which is beneficial to improving the display uniformity of the display panel.

[0142] Figure 8 FIG. 1 is a film layer structure diagram of a plurality of pixel driving circuits according to some embodiments. Figure 8 The description is made by taking the two rows and four columns of pixel driving circuits Q in the display panel 100 as an example, but it does not mean that the display panel 100 includes only the pixel driving circuits Q in the illustrated number.

[0143] In some embodiments, in combination Figure 2 , Figure 6 and Figure 8 As shown, the driving circuit layer 20 includes a semiconductor layer POLY, a first gate metal layer Gate1, a first wiring metal layer SD1 and a second wiring metal layer SD2 stacked on the base substrate 10. The semiconductor layer POLY is located between the base substrate 10 and the first gate metal layer Gate1.

[0144] The driving circuit layer 20 also includes the above-mentioned plurality of signal lines electrically connected to the driving circuit Q. Exemplarily, the driving circuit layer 20 includes a plurality of first scanning signal lines G1, a plurality of second scanning signal lines G2, a plurality of first initialization signal lines Vinit1, a plurality of second initialization signal lines Vinit2, a plurality of first power signal lines VDD, a plurality of second power signal lines VSS, and a plurality of data writing signal lines Data.

[0145] The plurality of data writing signal lines Data are arranged along the first direction X and extend along the second direction Y. The data writing signal lines Data are configured to provide the pixel driving circuit Q with a data writing signal.

[0146] In some examples, a plurality of data writing signal lines Data may be located in the second wiring metal layer SD2 , a plurality of data writing signal lines Data are located in the display area AA, and a data writing signal line Data is connected to a column of sub-pixel driving circuits Q.

[0147] Among them, a part of the multiple data write signal lines Data is located in an edge area AA2, another part of the multiple data write signal lines Data is located in another edge area AA2, and another part of the multiple data write signal lines Data is located in the middle area AA1.

[0148] In some examples, the number of data write signal lines Data in the two edge areas AA2 may be the same. In other examples, the number of data write signal lines Data in the two edge areas AA2 may be different.

[0149] In some examples, the number of data write signal lines Data in an edge area AA2 may be the same as the number of data write signal lines Data in the middle area AA1. In other examples, the number of data write signal lines Data in an edge area AA2 may be different from the number of data write signal lines Data in the middle area AA1.

[0150] In some examples, the display panel further includes a binding area BB. The binding area BB is located on one side of the display area AA. The driving circuit layer 20 in the display panel 100 further includes a plurality of data leads L. The data lead L includes a first lead segment L1 and a second lead segment L2. The second lead segment L2 is located in the middle area AA1, and the second lead segment L2 extends along the second direction Y and extends to the binding area BB. In addition, the first lead segment L1 extends along the first direction X, one end of the first lead segment L1 is located in the edge area AA2, and the other end of the first lead segment L1 is located in the middle area AA2. One end of the first lead segment L1 can be electrically connected to a data write signal line Data located in the edge area AA2, and the other end of the first lead segment L1 can be electrically connected to one end of the second lead segment L2 located in the middle area AA1.

[0151] Based on this, the data write signal line Data in the edge area AA2 can be switched to the middle area AA1 using the first lead segment L1 of the data lead line L, and then extended to the binding area BB using the second lead segment L2 of the data lead line L. That is, the signal lines that need to be electrically connected to the binding area BB (the second lead segment L2 electrically connected to the data write signal line Data in the edge area AA2 and the data write signal line Data in the middle area AA1) can be concentrated in the display area AA at the position corresponding to the driver chip IC, which is conducive to achieving a narrow frame.

[0152] Therefore, the display panel 100 can implement the FIAA technology and arrange the data leads L in the display area AA, which can be beneficial to realize a narrow frame of the display panel 100 .

[0153] In some examples, the binding area BB includes a driver chip (English full name: Integrated Circuit, English abbreviation: IC).

[0154] However, since the data lead L is disposed in the display area AA, the orthographic projection of the data lead L on the base substrate 10 may easily overlap with the orthographic projection of some transistors in the pixel driving circuit Q on the base substrate 10, thus affecting the stability of the transistors.

[0155] Specifically, when the positive projection of the data lead L on the substrate 10 overlaps with the positive projection of the second electrode d1 of the first reset transistor T1 in the pixel driving circuit Q on the substrate 10. Since the data write signal can be a pulse signal. That is, the data write signal is a constantly changing, non-constant signal. Based on the effect of capacitive coupling, when the data write signal transmitted by the data lead L jumps, it will cause the potential of the second electrode d1 of the first reset transistor T1 to jump. Furthermore, it will also indirectly cause the potential of the control electrode g3 of the driving transistor T3 to change, affecting the stability of the driving transistor T3.

[0156] Based on this, a third wiring metal layer can be added to the driving circuit layer 20 to form a first lead segment L1 of the data lead L in the second wiring metal layer SD2 and a second lead segment of the data lead L in the third wiring metal layer. In this way, the spacing between each transistor in the pixel driving circuit Q and the data lead L is increased in the direction perpendicular to the substrate 10. This can improve the problem that the potential jump of the second electrode d1 of the first reset transistor T1 occurs when the data write signal transmitted by the data lead L jumps.

[0157] However, the inventors of the present disclosure have found through research that the method of adding a third wiring metal layer in the driving circuit layer 20 will result in an additional drawing process being required when manufacturing the display panel 100 to form the data writing signal line Data in the third wiring metal layer and the second lead segment L2 of the data lead L. In addition, since the third wiring metal layer is located on the side of the second wiring metal layer SD2 away from the first wiring metal layer SD1, in order to prevent the problem of short circuit between the third wiring metal layer and the second wiring metal layer, an insulating layer needs to be provided between the third wiring metal layer and the second wiring metal layer so that the third wiring metal layer and the second wiring metal layer are insulated from each other. The first lead segment L1 of the data lead L is formed in the second wiring metal layer SD2, and the first lead segment L1 and the second lead segment L2 of the data lead L need to be connected to each other, and then a via hole needs to be formed in the insulating layer between the third wiring metal layer and the second wiring metal layer, so that the first lead segment L1 of the data lead L located in the second wiring metal layer SD2 is connected to the second lead segment L2 of the data lead L located in the third wiring metal layer. That is, when manufacturing the display panel 100, another drawing process needs to be added to form a via hole in the insulating layer between the third wiring metal layer and the second wiring metal layer.

[0158] In summary, since the third wiring metal layer is added to the driving circuit layer 20, two more drawing processes are required when manufacturing the display panel 100. This will increase the cost of the display panel 100, increase the production cycle of the display panel 100, and reduce the production efficiency of the display panel 100.

[0159] Fig. 9 1 is a film layer structure diagram of multiple pixel driving circuits according to other embodiments. Fig.10 for Fig. 9 The structure of the semiconductor layer in Fig.11 is a structural diagram of a semiconductor layer according to some embodiments, Fig.12 for Fig. 9 The structure diagram of the first gate metal layer in Fig.13 for Fig. 9 The structure diagram of the second gate metal layer in Fig.14 for Fig. 9The structure diagram of the semiconductor layer, the first gate metal layer and the second gate metal layer, Fig.15 for Fig. 9 The structure diagram of the first routing metal layer in the figure. Fig.16 for Fig. 9 The structure diagram of the semiconductor layer, the first gate metal layer, the second gate metal layer and the first wiring metal layer, Fig.17 for Fig. 9 Structural diagram of the second routing metal layer.

[0160] in, Fig. 9 for Figure 8 The four pixel driving circuits Q in the lower middle are used as an example for illustration, so that the structure of each pixel driving circuit Q can be observed more clearly.

[0161] Based on the above problems, combined with Figure 8 to Figure 17 As shown, in the display panel 100 provided in the embodiment of the present disclosure, the driving circuit layer 20 includes a layer stacked on the base substrate 10 (such as Figure 3 The semiconductor layer POLY, the first gate metal layer Gate1, the second gate metal layer Gate2, the first wiring metal layer SD1 and the second wiring metal layer SD2 are formed on the substrate 10. The semiconductor layer POLY is located between the first gate metal layer Gate1 and the substrate 10.

[0162] The first wiring metal layer SD1 may include a first lead segment L1 of the data lead line L, and the second wiring metal layer SD2 may include a data write signal line Data and a second lead segment L2 of the data lead line L.

[0163] Based on this, the data writing signal line Data and the data lead line L are divided into the space of the first wiring metal layer SD1 and the second wiring metal layer SD2. Therefore, there is no need to add a third wiring metal layer in the driving circuit layer 20 in the display panel 100. Compared with the display panel 100 provided with the third wiring metal layer, the display panel 100 provided by the embodiment of the present disclosure can reduce two drawing processes. Therefore, the cost of the display panel 100 can be reduced, the production cycle of the display panel 100 can be shortened, and the production efficiency of the display panel 100 can be improved.

[0164] The above mainly introduces the method of moving the data lead L and the data write signal line Data downward to achieve the elimination of the need for a third wiring metal layer in the driving circuit layer, so as to reduce the cost of the display panel 100, shorten the production cycle of the display panel 100, and improve the production efficiency of the display panel 100. After the data lead L and the data write signal line Data are moved downward to the side of the base substrate 10, the spacing between the data lead L and the data write signal line Data and the transistors in the pixel driving circuit Q is reduced, which may easily affect the stability of the transistors. The following will introduce how to reduce the problem of crosstalk between the data lead L and the transistors in combination with the structures in multiple film layers in the driving circuit layer.

[0165] In some examples, such as Fig.10 As shown, the semiconductor layer POLY also includes the channel portion of each transistor in the pixel driving circuit Q. In addition, the semiconductor layer POLY also includes a first conductive portion U1, the first conductive portion U1 includes the second electrode d1 of the first reset transistor T1, and the first conductive portion U1 is connected to the channel portion a1 of the first reset transistor T1. In addition, the first conductive portion U1 may also include a second electrode d2 of the compensation transistor T2, so that the second electrode d1 of the first reset transistor T1 is connected to the second electrode d2 of the compensation transistor T2.

[0166] Exemplarily, in the case where the pixel driving circuit Q includes a first reset transistor T1, a compensation transistor T2, a driving transistor T3, a data writing transistor T4, a first light emission control transistor T5, a second light emission control transistor T6 and a second reset transistor T7: the semiconductor layer POLY includes: a first electrode s1, a second electrode d1 and a channel portion a1 of the first reset transistor T1, a first electrode s2, a second electrode d2 and a channel portion a2 of the compensation transistor T2, a first electrode s3, a second electrode d3 and a channel portion a3 of the driving transistor T3, a first electrode s4, a second electrode d4 and a channel portion a4 of the data writing transistor T4, a first electrode s5, a second electrode d5 and a channel portion a5 of the first light emission control transistor T5, a first electrode s6, a second electrode d6 and a channel portion a6 of the second light emission control transistor T6, and a first electrode s7, a second electrode d7 and a channel portion a7 of the second reset transistor T7.

[0167] It should be noted that, combined with Fig. 9 and Fig.10 As shown, the semiconductor layer POLY is on the base substrate 10 (such as Figure 3 The orthographic projection of the semiconductor layer POLY on the substrate 10 overlaps with the orthographic projection of the first gate metal layer Gate1 on the substrate 10. The portion of the semiconductor layer POLY covered by the first gate metal layer Gate1 constitutes the channel portion of each transistor, and the portion of the semiconductor layer POLY not covered by the first gate metal layer G1 is a conductive portion, constituting a portion of the first electrode or the second electrode of each transistor.

[0168] In some examples, such as Fig.10 As shown, the shape of the positive projection of the channel portion a3 of the driving transistor T3 on the base substrate 10 is an inverted "I" shape. At this time, the channel portion a3 of the driving transistor T3 extends along the first direction X. The channel portion a3 of the driving transistor T3 has a regular structure, which can facilitate the flexible arrangement of other transistors on the semiconductor layer POLY.

[0169] In other examples, such as Fig.11 As shown, the orthographic projection of the channel portion a3 of the driving transistor T3 on the substrate 10 is in the shape of a "J". The "J" shape can be understood as an Ω shape, or is similar to an Ω shape or a "J" shape, that is, the channel portion a3 of the driving transistor T3 includes a protruding structure. Such a configuration can facilitate the improvement of the stability of the driving transistor T3, so that it can meet the flow of a larger driving current, thereby improving the display quality of the display panel 100.

[0170] In some examples, the material of the semiconductor layer POLY may include amorphous silicon, single crystal silicon, or polycrystalline silicon semiconductor material.

[0171] In some examples, combined Fig. 9 and Fig.12 As shown, the first gate metal layer Gate1 is located on the semiconductor layer POLY away from the substrate 10 (eg Figure 3 That is, the first gate metal layer Gate1 is located between the semiconductor layer POLY and the second gate metal layer Gate2.

[0172] The first gate metal layer Gate1 may include control electrodes of each transistor in the pixel driving circuit Q. Exemplarily, when the pixel driving circuit Q includes a first reset transistor T1, a compensation transistor T2, a driving transistor T3, a data writing transistor T4, a first light emission control transistor T5, a second light emission control transistor T6, and a second reset transistor T7: the first gate metal layer Gate1 may include a control electrode g1 of the first reset transistor T1, a control electrode g2 of the compensation transistor T2, a control electrode g3 of the driving transistor T3, a control electrode g4 of the data writing transistor T4, a control electrode g5 of the first light emission control transistor T5, a control electrode g6 of the second light emission control transistor T6, and a control electrode g7 of the second reset transistor T7.

[0173] In addition, the first gate metal layer Gate1 can also be used to form a portion of signal lines. The portion of signal lines includes a plurality of first scan signal lines G1 and a plurality of second scan signal lines G2. The plurality of first scan signal lines G1 extend along the first direction X and are arranged along the second direction Y. Also, the plurality of second scan signal lines G1 extend along the first direction X and are arranged along the second direction Y.

[0174] In some examples, the first scan signal line G1 located on the first gate metal layer Gate1 may include a first portion G11 , and the first portion G11 of the first scan signal line G1 may be multiplexed as a control electrode g4 of the data writing transistor T4 .

[0175] Based on this, the first portion G11 of the first scanning signal line G1 is directly used as the control electrode g4 of the data writing transistor T4, and not only does it not need to separately set the control electrode g4 of the data writing transistor T4, but it also does not need to set a conductive portion for connecting the control electrode g4 of the data writing transistor T4 and the first description signal line G1. Therefore, the above arrangement can not only simplify the layout of the first gate metal layer Gate1, facilitate the flexible arrangement of other conductive portions on the first gate metal layer Gate1, but also help save resources.

[0176] In some examples, when the first scan signal line G1 is multiplexed as the second reset signal line, the first scan signal line G1 located on the first gate metal layer Gate1 may further include a second portion G12, and the second portion G12 of the first scan signal line G1 may be multiplexed as the control electrode g7 of the second reset transistor T7.

[0177] Based on this, the second portion G12 of the first scanning signal line G1 is directly used as the control electrode g7 of the second reset transistor T7, and not only does it not need to separately set the control electrode g7 of the second reset transistor T7, but it also does not need to set a conductive portion for connecting the control electrode g7 of the second reset transistor T7 and the first scanning signal line G1. Therefore, the above arrangement can not only simplify the layout of the first gate metal layer Gate1, facilitate the flexible arrangement of other conductive portions on the first gate metal layer Gate1, but also simplify the manufacturing process of the pixel driving circuit Q, which is conducive to saving resources.

[0178] In some examples, the second scan signal line Gate2 located on the first gate metal layer Gate1 may include a first portion G21 , and the first portion G21 of the second scan signal line Gate2 may be reused as a control electrode g2 of the compensation transistor T2 .

[0179] Based on this, the first portion G21 of the second scanning signal line Gate2 is directly used as the control electrode g2 of the compensation transistor T2, and not only does it not need to separately set the control electrode g2 of the compensation transistor T2, but it also does not need to set a conductive portion for connecting the control electrode g2 of the compensation transistor T2 and the second scanning signal line Gate2. Therefore, the above arrangement can not only simplify the layout of the first gate metal layer Gate1, facilitate the flexible arrangement of other conductive portions on the first gate metal layer Gate1, but also simplify the manufacturing process of the pixel driving circuit Q, which is conducive to saving resources.

[0180] In some examples, the second scan signal line G2(n-7) / first reset signal line R1 located on the first gate metal layer Gate1 can include a first portion R11, and the first portion R11 of the second scan signal line G2(n-7) / first reset signal line R1 can be reused as the control electrode g1 of the first reset transistor T1.

[0181] Based on this, the first part R11 of the second scanning signal line G2(n-7) / the first reset signal line R1 is directly used as the control electrode g1 of the first reset transistor T1, and not only does it not need to separately set the control electrode g1 of the first reset transistor T1, but it also does not need to set a conductive portion for connecting the control electrode g1 of the first reset transistor T1 and the second scanning signal line G2(n-7) / the first reset signal line R1. Therefore, the above arrangement can not only simplify the layout of the first gate metal layer Gate1, facilitate the flexible arrangement of other conductive portions on the first gate metal layer Gate1, but also simplify the manufacturing process of the pixel driving circuit Q, which is conducive to saving resources.

[0182] In some examples, the material of the first gate metal layer Gate1 includes a conductive metal, and the conductive metal may include at least one of aluminum, copper, and molybdenum, but the present disclosure is not limited thereto.

[0183] In some examples, a first gate insulating layer is disposed between the first semiconductor layer POLY1 and the first gate metal layer Gate1 , and the first gate insulating layer electrically insulates the first semiconductor layer POLY1 from the first gate metal layer Gate1 .

[0184] Exemplarily, the material of the first gate insulating layer includes any one of inorganic insulating materials such as silicon nitride, silicon oxynitride and silicon oxide. The material of the first gate insulating layer may also include silicon dioxide, but the present disclosure is not limited thereto.

[0185] In some examples, combined Fig. 9 , Fig.13 and Fig.14 As shown, the second gate metal layer Gate2 is located on a side of the first gate metal layer Gate1 away from the semiconductor layer POLY. That is, the second gate metal layer Gate2 is located between the first gate metal layer Gate1 and the first wiring metal layer SD1.

[0186] In some examples, the pixel driving circuit Q further includes a storage capacitor Cst. A first plate Cst-1 of the storage capacitor Cst is electrically connected to the first node N1, and a second plate Cst-2 of the storage capacitor Cst is electrically connected to the first power signal line VDD.

[0187] The first gate metal layer Gate1 further includes a first electrode plate Cst-1 of a storage capacitor Cst. The first electrode plate Cst-1 of the storage capacitor Cst may be disposed on the substrate 10 (eg Figure 3 The orthographic projection on the substrate 10 overlaps with the orthographic projection of the channel portion a3 of the driving transistor T3 on the substrate 10, so that the first plate of the storage capacitor Cst is reused as the control electrode g3 of the driving transistor T3.

[0188] The second gate metal layer Gate2 includes a second electrode plate Cst-2 of the storage capacitor Cst. The second electrode plate Cst-2 of the storage capacitor Cst is formed on the substrate 10 (eg Figure 3 The orthographic projection on the substrate 10 overlaps with the orthographic projection of the first electrode plate Cst-1 of the storage capacitor Cst on the substrate 10 to form the storage capacitor Cst.

[0189] Among them, the first electrode plate Cst-1 of the storage capacitor Cst located on the first gate metal layer Gate1 can be reused as the control electrode g3 of the driving transistor T3. Based on this, there is no need to separately set the control electrode g3 of the driving transistor T3, which can be beneficial to simplifying the manufacturing process of the pixel driving circuit Q. In addition, the first electrode plate Cst-1 of the storage capacitor Cst can be reused as the control electrode g3 of the driving transistor T3, and the first electrode plate Cst-1 of the storage capacitor Cst can be directly electrically connected to the control electrode g3 of the driving transistor T3 without separately setting a connecting portion, which can also be beneficial to the layout of the pixel driving circuit Q.

[0190] In addition, the second gate metal layer Gate2 can also be used to form a portion of signal lines. The portion of signal lines includes a plurality of first initialization signal lines Vinit1 and a plurality of second initialization signal lines Vinit2. The plurality of first initialization signal lines Vinit1 extend along the first direction X and are arranged along the second direction Y. Also, the plurality of second initialization signal lines Vinit2 extend along the first direction X and are arranged along the second direction Y.

[0191] In addition, since the second gate metal layer Gate2 is located between the semiconductor POLY and the first wiring metal layer SD1, a first shielding portion J1 may be provided on the second gate metal layer Gate2, wherein the first shielding portion J1 is configured to have a constant voltage signal.

[0192] Based on this, the orthographic projection of the first shielding portion J on the base substrate 10 may be arranged to partially overlap with the orthographic projection of the first conductive portion U1 on the base substrate 10 .

[0193] In some examples, the second gate metal layer Gate2 may be made of the same material as the first gate metal layer Gate1. It is understood that in other examples, the second gate metal layer Gate2 may be made of a different material than the first gate metal layer Gate1. The embodiments of the present disclosure are not limited thereto.

[0194] In some examples, a second gate insulating layer may be disposed between the second gate metal layer Gate2 and the first gate metal layer Gate1. The second gate insulating layer electrically insulates the second gate metal layer Gate2 from the first gate metal layer Gate1.

[0195] Exemplarily, the material of the second gate insulating layer includes any one of inorganic insulating materials such as silicon nitride, silicon oxynitride and silicon oxide. The material of the second gate insulating layer may also include silicon dioxide, but the present disclosure is not limited thereto.

[0196] In some examples, combined Fig. 9 , Fig.15 and Fig.16 As shown, the first wiring metal layer SD1 is located on a side of the second gate metal layer Gate2 away from the first gate metal layer Gate1. That is, the first wiring metal layer SD1 is located between the second gate metal layer Gate2 and the second wiring metal layer SD2.

[0197] Exemplarily, the material package of the first wiring metal layer SD1 may be a titanium (Ti)-aluminum (Al)-titanium (Ti) multi-layer composite material.

[0198] Exemplarily, a first planarization layer (PLN) is disposed between the first wiring metal layer SD1 and the second gate metal layer Gate2. The first planarization layer can electrically insulate the first wiring metal layer SD1 from the second gate metal layer Gate2.

[0199] Exemplarily, the material of the first planarization layer is generally an organic material. For example, the material of the first planarization layer may include at least one of polyimide (full name in English: Polyimide, English abbreviation: PI), acrylic polymer or silicon polymer.

[0200] In addition, the first routing metal layer SD1 can also be used to form a portion of signal lines. The portion of signal lines includes a first lead segment L1 of a plurality of data leads L, a plurality of first enable signal lines EM1, and a plurality of second enable signal lines EM2. The plurality of first enable signal lines EM1 extend along the first direction X and are arranged along the second direction Y. And the plurality of second enable signal lines EM2 extend along the first direction X and are arranged along the second direction Y.

[0201] In some embodiments, in combination Figure 8 , Fig. 9 and Fig.16 As shown, the first wiring metal layer SD1 further includes a plurality of first virtual lead segments 31 extending along the first direction X and arranged in the second direction Y. The first virtual lead segments 31 correspond to the first lead segments L1 one by one, and along the first direction X, the first virtual lead segments 31 are spaced apart from the first lead segments L1.

[0202] Based on this, multiple first virtual lead segments 31 can be used in conjunction with multiple first lead segments L1 to achieve uniform routing on the first routing metal layer SD1, thereby improving the uniformity of the first routing metal layer SD1 reflecting external ambient light, thereby improving the display effect of the display panel 100.

[0203] In some examples, the first dummy lead segment 31 may be configured to transmit a constant voltage signal. Exemplarily, the first dummy lead segment 31 may be electrically connected to the second power signal line VSS.

[0204] In some embodiments, the first routing metal layer SD1 further includes a plurality of connection portions.

[0205] The connecting portion includes a first connecting portion PAD1, which is used to connect the control electrode g3 of the driving transistor T3 located in the first gate metal layer Gate1 and the first conductive portion U1 located in the semiconductor layer POLY, so as to realize electrical connection among the control electrode g3 of the driving transistor T3, the second electrode d1 of the first reset transistor T1, and the second electrode d2 of the compensation transistor T2.

[0206] The first connection portion PAD1 may be connected to the first conductive portion U1 through a via hole, and the first connection portion PAD1 may be connected to the control electrode g3 of the driving transistor T3 through another via hole.

[0207] The connection portion also includes a second connection portion PAD2, which is used to connect the first initialization signal line Vinit1 located in the second gate metal layer Gate2 and the first electrode s1 of the first reset transistor T1 located in the semiconductor layer POLY, so as to realize the electrical connection between the first initialization signal line Vinit1 and the first electrode s1 of the first reset transistor T1.

[0208] The second connection portion PAD2 may be connected to the first initialization signal line Vinit1 through a via hole, and the second connection portion PAD2 may be connected to the first electrode s1 of the first reset transistor T1 through another via hole.

[0209] The connection portion may further include a third connection portion PAD3, and the third connection portion PAD3 may be used to connect the second plate Cst-2 of the storage capacitor Cst and the first power signal line VDD.

[0210] The third connection portion PAD3 may be connected to the second electrode plate Cst-2 of the storage capacitor Cst through a via hole, and the third connection portion PAD3 may also be connected to the first power signal line VDD through another via hole.

[0211] The connecting portion may also include a fourth connecting portion PAD4, which is used to connect the second electrode d6 of the second light-emitting control transistor T6, the second electrode d7 of the second reset transistor T7 and the anode of the light-emitting device, so as to realize that the second electrode d6 of the second light-emitting control transistor T6, the second electrode d7 of the second reset transistor T7 are electrically connected to the anode of the light-emitting device.

[0212] The fourth connection portion PAD4 may be connected to the second electrode d6 of the second light emitting control transistor T6 and the second electrode d7 of the second reset transistor T7 through a via hole, and the fourth connection portion PAD4 may also be connected to the anode of the light emitting device through another via hole.

[0213] The connection portion may also include a fifth connection portion PAD5, which is used to connect the first electrode s7 of the second reset transistor T7 located in the semiconductor layer POLY and the second initialization signal line Vinit2 located in the second gate metal layer Gate2 to achieve electrical connection between the first electrode s7 of the second reset transistor T7 and the second initialization signal line Vinit2.

[0214] The fifth connection portion PAD5 may be connected to the first electrode s7 of the second reset transistor T7 through a via hole, and the fifth connection portion PAD5 may also be connected to the second initialization signal line Vinit2 through another via hole.

[0215] The connection portion may also include a sixth connection portion PAD6, which is used to connect the first electrode s4 of the data write transistor T4 located in the semiconductor layer POLY and the first scanning signal line G1 located in the first gate metal layer Gate1 to achieve electrical connection between the first electrode s4 of the data write transistor T4 and the first scanning signal line G1.

[0216] In some examples, combined Figure 8 , Fig. 9 and Fig.17 As shown, the second wiring metal layer SD2 is located on a side of the first wiring metal layer SD1 away from the second gate metal layer Gate2.

[0217] In some examples, the material of the second wiring metal layer SD2 may be the same as that of the first wiring metal layer SD1. Alternatively, in other examples, the material of the second wiring metal layer SD2 may be different from that of the first wiring metal layer SD1. The embodiments of the present disclosure are not limited to this.

[0218] In some examples, a second planarization layer is disposed between the second routing metal layer SD2 and the first routing metal layer SD1 . The second planarization layer electrically insulates the second routing metal layer SD2 from the first routing metal layer SD1 .

[0219] Exemplarily, the material of the second planarization layer is generally an organic material. For example, the material of the second planarization layer may include at least one of polyimide (full name in English: Polyimide, English abbreviation: PI), acrylic-based polymer or silicon-based polymer.

[0220] In some embodiments, in combination Figure 8 and Fig. 9 As shown, the second routing metal layer SD2 further includes a plurality of second virtual lead segments 32, which extend along the second direction Y and are arranged in the first direction X. The second virtual lead segments 32 correspond to the second lead segments L2 one by one, and along the second direction Y, the second virtual lead segments 32 are spaced apart from the second lead segments L2.

[0221] Based on this, multiple second virtual lead segments 32 can be used in conjunction with multiple second lead segments L2 to achieve uniform routing on the second routing metal layer SD2 and improve the uniformity of the second routing metal layer SD2 reflecting external ambient light, thereby improving the display effect of the display panel 100.

[0222] In some examples, the second dummy lead segment 32 may be configured to transmit a constant voltage signal. Exemplarily, the second dummy lead segment 32 may be electrically connected to the second power signal line VSS.

[0223] In some examples, in the same data lead L, the orthographic projection of the first lead segment L1 on the base substrate 10 overlaps with the orthographic projection of the second lead segment L2 on the base substrate 10. Based on this, the first lead segment L1 and the second lead segment L2 can be connected by a punching process.

[0224] Furthermore, the width of the first part of the second lead segment L2 can be set to be greater than the width of the second part. The orthographic projection of the first part of the second lead segment L2 on the substrate 10 overlaps with the orthographic projection of the first lead segment L1 on the substrate 10, and the orthographic projection of the second part of the second lead segment L2 on the substrate 10 does not overlap with the orthographic projection of the first lead segment L1 on the substrate 10. Based on this, the area of ​​the overlapping region of the orthographic projection of the first lead segment L1 on the substrate 10 and the orthographic projection of the second lead segment L2 on the substrate 10 can be increased, thereby reducing the difficulty of the punching process, so that the first lead segment L1 and the second lead segment L2 can be connected through the punching process.

[0225] In some examples, the orthographic projection of the first lead segment L1 on the base substrate 10 overlaps with the orthographic projection of the data writing signal line Data on the base substrate 10. Based on this, the first lead segment L1 and the data writing signal line Data can be connected by a punching process.

[0226] In some embodiments, in combination Figure 2 , Figure 6 and Figure 8 As shown, the second lead segment L2 of the data lead L is located between two adjacent pixel driving circuits Q in the first direction X. That is, the second lead segment L2 of the data lead L is located in a region of the driving transistor T3 close to the edge of the pixel driving circuit Q in the first direction X, so that the second lead segment L2 of the data lead L is located on the substrate 10 (return Figure 3 The orthographic projection on the substrate 10 does not overlap with the orthographic projection of the driving transistor T3 on the substrate 10.

[0227] Thus, the data write signal transmitted by the second lead segment L2 of the data lead L can be prevented from being affected by the potential of each electrode of the driving transistor T3 when it jumps, which is beneficial to improving the stability of the driving transistor T3 in the pixel driving circuit Q, thereby helping to improve the brightness uniformity of the display panel 100.

[0228] Combination Figures 9 to 16 As shown, based on the above description of the structure of each film layer in the driving circuit layer 20, it can be known that the first conductive portion U1 in the semiconductor layer POLY includes the second electrode d1 of the first reset transistor T1, and the second gate metal layer Gate2 is provided with a first shielding portion J with a constant voltage signal. The first wiring metal layer SD1 is provided with a first lead segment L1 of the data lead L. That is, along the vertical substrate 10 (such as Figure 3 In the direction shown in FIG. 1 , the first shielding portion J is located between the first conductive portion U1 and the first lead segment.

[0229] Furthermore, it may be arranged that the orthographic projection of the first conductive portion U1 on the base substrate 10 , the orthographic projection of the first shielding portion J on the base substrate 10 , and the orthographic projection of the first lead segment L1 on the base substrate 10 overlap.

[0230] Based on this, the first shielding portion J with a constant voltage signal can be used to isolate the first conductive portion U1 and the first lead segment L1, so as to improve the voltage jump at the position of the first conductive portion U1 caused by the data write signal transmitted by the first lead segment L1. Since the second electrode d1 of the first reset transistor T1 and the control electrode g3 of the driving transistor T3 are both electrically connected to the first node. That is, the first conductive portion U1 will be electrically connected to the control electrode g3 of the driving transistor T3, thereby indirectly improving the stability of the control electrode g3 of the driving transistor T3, which is beneficial to optimizing the brightness uniformity of the display panel 100.

[0231] In some embodiments, in combination Figures 9 to 16As shown, the first reset transistor T1 and the compensation transistor T2 are located on the same side of the driving transistor T3 in the second direction Y. In the second direction Y, the control electrode g1 of the first reset transistor T1 is located on the side of the compensation transistor T2 away from the driving transistor T3, the first electrode s1 and the second electrode d1 of the first reset transistor T1 are both located between the control electrode g1 of the first reset transistor T1 and the driving transistor, and the second electrode d1 of the first reset transistor T1 is adjacent to the second electrode d2 of the compensation transistor T2.

[0232] Based on this, the second electrode d1 of the first reset transistor T1 can be conveniently connected to the second electrode d2 of the compensation transistor T2, so as to be conveniently electrically connected to the control electrode g3 of the driving transistor T3 in a subsequent synchronous manner.

[0233] In some examples, the second electrode d1 of the first reset transistor T1 is multiplexed as the second electrode d2 of the compensation transistor T2 .

[0234] Based on this, it is easy to realize that the second electrode d1 of the first reset transistor T1 can be connected to the second electrode d2 of the compensation transistor T2, and it is also beneficial to save the space of the semiconductor layer POLY.

[0235] In some embodiments, in combination Figures 9 to 16 As shown, the second gate metal layer Gate2 also includes a plurality of first initialization signal lines Vinit1. Since the first electrode s1 of the first reset transistor T1 is electrically connected to the first initialization signal line Vinit1, the first initialization signal line Vinit1 can be set between the control electrode g1 of the first reset transistor T1 and the first electrode s1 and the second electrode d1 of the first reset transistor T1.

[0236] Based on this, the distance between the first initialization signal line Vinit1 and the first electrode s1 of the first reset transistor T1 can be reduced, so as to facilitate electrical connection between the two.

[0237] In some embodiments, in combination Figures 9 to 16 As shown, since the first initialization signal transmitted by the first initialization signal line Vinit1 is a constant voltage signal, the first initialization signal line Vinit1 may be electrically connected to the first shielding portion J, so as to transmit the constant voltage signal to the first shielding portion J using the first initialization signal line.

[0238] Based on this, the first shielding part J can be provided with a constant voltage signal, so that the first shielding part J can be used to isolate the first lead segment L1 and the first conductive part U1, thereby improving the problem that the voltage of the first conductive part U1 jumps due to the data write signal transmitted by the first lead segment L1. In addition, there is no need to set up an independent constant voltage signal line in the driving circuit layer, which can save space in the driving circuit layer and save resources.

[0239] In some examples, the first initialization signal line Vinit1 is in the same layer as the first shielding portion J. The first initialization signal line Vinit1 and the first shielding portion J may be formed by one patterning process, so as to simplify the process of the pixel driving circuit Q.

[0240] It should be noted that "same layer" refers to a layer structure formed by using the same film-forming process to form a film layer for forming a specific pattern, and then using the same mask to form a layer structure through a single patterning process. Depending on the specific pattern, a single patterning process may include multiple exposure, development or etching processes, and the specific patterns in the formed layer structure may be continuous or discontinuous, and these specific patterns may also be at different heights or have different thicknesses.

[0241] In some embodiments, in combination Figures 9 to 16 As shown, the first initialization signal line Vinit1 may include a main body portion B1 and a first auxiliary portion F1, the first auxiliary portion F1 being located on a side of the main body portion B1 close to the first reset transistor T1. That is, the first auxiliary portion F1 is a protruding portion of the first initialization signal line Vinit1 toward the first reset transistor T1.

[0242] At this time, the first auxiliary portion F1 of the first initialization signal line Vinit1 is formed on the base substrate 10 (eg Figure 3 The orthographic projection of the first conductive portion U1 on the substrate 10 and the orthographic projection of the first lead segment L1 on the substrate 10 overlap.

[0243] Therefore, the first auxiliary part F1 of the first initialization signal line Vinit1 can be reused as the first shielding part J to isolate the first lead segment L1 from the first conductive part U1, thereby improving the problem of voltage jump of the first conductive part U1 caused by the data write signal transmitted by the first lead segment L1.

[0244] Furthermore, since the first auxiliary portion F1 of the first initialization signal line Vinit1 is reused as the first shielding portion J, there is no need to separately provide the first shielding portion J, and the manufacturing process of the display panel can be simplified.

[0245] In addition, since the orthographic projection of the body portion B1 of the first initialization signal line Vinit1 on the base substrate 10 at least partially overlaps with the orthographic projection of the first conductive portion U1 on the base substrate 10, the relative area between the first initialization signal line Vinit1 and the first conductive portion U1 can be increased, and the stability of the first conductive portion U1 can be further improved, so as to improve the stability of the driving transistor T3.

[0246] In some embodiments, in combination Figures 9 to 14As shown, the control electrode g2 of the compensation transistor T2 includes a first control electrode g1 and a second control electrode g2.

[0247] The channel portion a2 of the compensation transistor T2 includes: a first channel portion a21 and a second channel portion a22. The semiconductor layer POLY also includes a second conductive portion U2, which is located between the first channel portion a21 and the second channel portion a22 of the compensation transistor T2, one end of the second conductive portion U2 is connected to the first channel portion a21 of the compensation transistor T2, and the other end of the second conductive portion U2 is connected to the second channel portion a22 of the compensation transistor T2, so as to realize the connection of the first channel portion a21 and the second channel portion a22 of the compensation transistor T2 by using the second conductive portion U2.

[0248] It should be noted that, the first channel portion a21 of the compensation transistor T2 is opposite to the first control electrode g21 of the compensation transistor T2. That is, the orthographic projection of the first channel portion a21 of the compensation transistor T2 on the base substrate 10 and the orthographic projection of the first control electrode g21 of the compensation transistor T2 on the base substrate 10 overlap. And, the second channel portion a22 of the compensation transistor T2 is opposite to the second control electrode g22 of the compensation transistor T2. That is, the orthographic projection of the second channel portion a22 of the compensation transistor T2 on the base substrate 10 and the orthographic projection of the second control electrode g22 of the compensation transistor T2 on the base substrate 10 overlap.

[0249] As described above, the compensation transistor T2 can be a dual-gate transistor, which can improve the problem of leakage from the compensation transistor T2 to the first node N1, thereby improving the stability of the control electrode g3 of the driving transistor T3 and improving the brightness uniformity of the display panel 100.

[0250] In some embodiments, in combination Figures 9 to 14 As shown, in some examples, combined with Fig.13 and Fig.14 As shown, the first initialization signal line Vinit1 further includes a second auxiliary portion F2, and the second auxiliary portion F2 is located on the side of the main body portion B1 of the first initialization signal line Vinit1 close to the driving transistor. That is, the portion of the first initialization signal line Vinit that protrudes toward the driving transistor T3 is the second auxiliary portion F2. The orthographic projection of the second auxiliary portion F2 on the base substrate 10 at least partially overlaps with the orthographic projection of the second conductive portion U2 on the base substrate 10.

[0251] This is equivalent to setting the orthographic projection of the second auxiliary portion F2 on the base substrate 10 to at least partially overlap with the orthographic projection of the conductive portion (second conductive portion U2) between the first channel portion a21 and the second channel portion a22 of the compensation transistor T2 on the base substrate 10. Therefore, the second auxiliary portion F2 of the first initialization signal line Vinit1 can form a capacitor with the second conductive portion U2 between the first channel portion a21 and the second channel portion a22 of the compensation transistor T2.

[0252] Since the first initialization signal transmitted by the first initialization signal line Vinit1 is a constant voltage signal, it is convenient to improve the stability of the compensation transistor T2 and improve the leakage problem to the first node N1 through the compensation transistor T2. Furthermore, it is beneficial to improve the stability of the control electrode g3 of the driving transistor T3 and improve the brightness uniformity of the display panel 100.

[0253] The orthographic projection of the second auxiliary portion F2 on the base substrate 10 at least partially overlaps with the orthographic projection of the second conductive portion U2 on the base substrate 10 , which may include the following two situations.

[0254] The first type: the orthographic projection of the second auxiliary portion F2 on the base substrate 10 overlaps with the orthographic projection of a portion of the second conductive portion U2 on the base substrate 10. That is, the orthographic projection of a portion of the second conductive portion U2 on the base substrate 10 is located within the boundary of the orthographic projection of the second auxiliary portion F2 on the base substrate 10.

[0255] The second type: the orthographic projections of the second conductive portion U2 on the base substrate 10 are all located within the boundaries of the orthographic projections of the second auxiliary portion F2 on the base substrate 10 .

[0256] Regardless of any of the overlapping situations of the second auxiliary portion F2 and the second conductive portion U2 , a capacitor can be formed between the two, which can improve the stability of the compensation transistor T2 and alleviate the problem of leakage to the first node N1 through the compensation transistor T2 .

[0257] Compared with the first method, the second method can further increase the overlapping area of ​​the orthographic projection between the second conductive part U2 and the second auxiliary part F2, thereby increasing the capacitance formed between the second conductive part U2 and the second auxiliary part F2, so as to better improve the stability of the control electrode g3 of the driving transistor T3 and improve the brightness uniformity of the display panel 100.

[0258] In some embodiments, in combination Figures 9 to 14As shown, the second conductive part U2 includes a first sub-part U21 and a second sub-part U22. The first sub-part U21 protruding toward the first channel part a21 of the compensation transistor T2 in the second conductive part U2 can be electrically connected to the first channel part a21, and the second sub-part U22 protruding toward the second channel part a22 of the compensation transistor T2 in the second conductive part U2 can be electrically connected to the second channel part a22.

[0259] Based on this, the first channel portion a21 and the second channel portion a22 of the compensation transistor T2 are electrically connected by utilizing the second conductive portion U2.

[0260] In some examples, the second conductive portion U2 may include a third sub-portion U23 on the basis of the first sub-portion U21 and the second sub-portion U22. The first sub-portion U21, the second sub-portion U22 and the third sub-portion U23 intersect at the same point, and the third sub-portion U23 is located on the side of the second sub-portion U22 away from the second channel portion a22. The second conductive portion U2 consisting of the first sub-portion U21, the second sub-portion U22 and the third sub-portion U23 is formed on the substrate 10 (such as Figure 3 The shape of the orthographic projection on the surface is “├”.

[0261] Since the third sub-portion U23 is located on the side of the second sub-portion U22 away from the second channel portion a22, that is, the main body B1 of the first initialization signal line Vinit1 of the third sub-portion U23, the orthographic projection of the third sub-portion U23 on the base substrate 10 is located within the boundary of the orthographic projection of the second auxiliary portion F2 on the base substrate 10. This is equivalent to increasing the size of the second conductive portion U2 by using the third sub-portion U23, thereby increasing the facing area between the second conductive portion U2 and the second auxiliary portion F2, thereby increasing the capacitance of the capacitor formed between the second conductive portion U2 and the second auxiliary portion F2, so as to better improve the stability of the control electrode g3 of the driving transistor T3 and improve the brightness uniformity of the display panel 100.

[0262] In some embodiments, in combination Figures 9 to 16 As shown, the pixel driving circuit Q further includes a first light emitting control transistor T5 and a second light emitting control transistor T6, and the first light emitting control transistor T5 and the second light emitting control transistor T6 are located on the same side of the driving transistor T3.

[0263] Furthermore, along the first direction X, the first light emission control transistor T5 and the second light emission control transistor T6 overlap. In other words, the first light emission control transistor T5 and the second light emission control transistor T6 are arranged side by side along the first direction X. The first light emission control transistor T5 is closer to the first electrode s3 of the driving transistor T3 than the second light emission control transistor T6, and the second light emission control transistor T6 is closer to the second electrode d3 of the driving transistor T3 than the first light emission control transistor T5.

[0264] Based on this, the distance between the first light emission control transistor T5 and the first electrode s3 of the driving transistor T3 can be reduced, and the distance between the second light emission control transistor T6 and the second electrode d3 of the driving transistor T3 can be reduced, so as to facilitate the connection of the second electrode d5 of the first light emission control transistor T5 with the first electrode s3 of the driving transistor T3, and the connection of the first electrode s6 of the second light emission control transistor T6 with the second electrode d3 of the driving transistor T3.

[0265] In some embodiments, in combination Figures 9 to 16 As shown, the first routing metal layer SD1 further includes a first enable signal line EM1 and a second enable signal line EM2.

[0266] In the case where the first light emission control transistor T5 and the second light emission control transistor T6 are located on the same side of the driving transistor T3, along the second direction Y, the first enable signal line EM1 electrically connected to the first light emission control transistor T5 is located between the control electrode g5 of the first light emission control transistor T5 and the control electrode g6 of the second light emission control transistor T6 and the control electrode g3 of the driving transistor T3. That is, the first enable signal line EM1 is located on the side where the control electrode g5 of the first light emission control transistor T5 and the control electrode g6 of the second light emission control transistor T6 are close to the control electrode g3 of the driving transistor T3. In addition, the second enable signal line EM2 electrically connected to the second light emission control transistor T6 is set on the side where the control electrode g5 of the first light emission control transistor T5 and the control electrode g6 of the second light emission control transistor T6 are far away from the control electrode g3 of the driving transistor T3.

[0267] In other words, one of the first enable signal line EM1 and the second enable signal line EM2 can be set on one side of the control electrode g5 of the first light-emitting control transistor T5 and the control electrode g6 of the second light-emitting control transistor T6, and the other of the first enable signal line EM1 and the second enable signal line EM2 can be set on the other side of the control electrode g5 of the first light-emitting control transistor T5 and the control electrode g6 of the second light-emitting control transistor T6.

[0268] Thus, it is possible to utilize two enable signal lines to drive two light-emitting control transistors respectively, and it is also possible to fully utilize the space of the first wiring metal layer SD1 of the display panel to increase the spacing between the first enable signal line EM1 and the second enable signal line EM2 to avoid the conductive components in the first wiring metal layer SD1 layer located between the first enable signal line EM1 and the second enable signal line EM2.

[0269] In some embodiments, in combination Figures 9 to 16As shown, the first enable signal line EM1 includes a first portion and a second portion. In the second direction Y, the first portion is located between the control electrode g3 of the driving transistor T3 and the control electrode g6 of the second light-emitting control transistor T6, and the second portion is located between the control electrode g3 of the driving transistor T3 and the control electrode g5 of the first light-emitting control transistor T5.

[0270] A first portion of the first enable signal line EM1 can be arranged closer to the control electrode g3 of the driving transistor T3 than a second portion of the first enable signal line EM1, and at the same time, this portion of the first enable signal line EM1 and the second light-emitting control transistor T6 can be enlarged to prevent the positive projection of the first enable signal line EM1 on the substrate from overlapping with the positive projection of the second light-emitting control transistor T6 on the substrate, so as to prevent the subsequent electrical connection between the second light-emitting control transistor T6 and the second reset transistor T7 from being affected.

[0271] In some embodiments, in combination Figures 9 to 16 As shown, the second enable signal line EM2 further includes a second auxiliary portion F2 protruding toward the control electrode g6 of the second light emitting control transistor T6, and the second auxiliary portion F2 extends along the second direction Y.

[0272] Based on this, the second auxiliary part F2 can be used to move the second enable signal line EM to the side away from the driving transistor T3. In addition, the distance between the second enable signal line EM2 and the first light-emitting control transistor T5 can be increased. Thus, the conductive component between the first enable signal line EM1 and the second enable signal line EM2 in the first routing metal layer SD1 can be avoided.

[0273] In some embodiments, in combination Figures 9 to 14 As shown, based on the first scanning signal line G1 being multiplexed as the second reset signal line R2: the control electrode of the second reset transistor T7 is electrically connected to the first scanning signal line G1, and the control electrode g4 of the data writing transistor T4 is also electrically connected to the first scanning signal line G1.

[0274] Therefore, along the first direction X, the control electrode g4 of the data writing transistor T4 and the control electrode g7 of the second reset transistor T7 overlap.

[0275] The first scanning signal line G1 can be electrically connected to the control electrode g4 of the data writing transistor T4 and the control electrode g7 of the second reset transistor T7. No bending part / avoidance part is required on the first scanning signal line G1, so the film layer structure layout of the pixel driving circuit Q can be simplified.

[0276] In some embodiments, in combination Figures 9 to 14As shown, the semiconductor layer POLY includes a first electrode s1 of the driving transistor T3, a second electrode d5 of the first light-emitting control transistor T5, and a second electrode d4 of the data-writing transistor T4. The semiconductor layer POLY also includes a third conductive portion U3, and the third conductive portion U3 includes the first electrode s1 of the driving transistor T3, the second electrode d5 of the first light-emitting control transistor T5, and the second electrode d4 of the data-writing transistor T4, which are electrically connected. That is, the first electrode s1, the second electrode d5 of the first light-emitting control transistor T5, and the second electrode d4 of the data-writing transistor T4 are electrically connected to the second node N2 (as shown in FIG. 1 ). Figure 6 shown).

[0277] The second gate metal layer Gate2 further includes a fourth conductive portion U4, one end of which is electrically connected to the second electrode Cst-2 of the storage capacitor Cst, and the other end of which is electrically connected to the first electrode s5 of the first light-emitting control transistor T5. Subsequently, the fourth conductive portion U4 is electrically connected to the first power signal line VDD, so that the second electrode Cst-2 of the storage capacitor Cst and the first electrode s5 of the first light-emitting control transistor T5 are both electrically connected to the first power signal line VDD.

[0278] Since the first plate C1 - 1 of the first capacitor C1 is electrically connected to the second node N2 , the second plate C1 - 2 of the first capacitor C1 is electrically connected to the first electrode s5 of the first light emission control transistor T5 .

[0279] Therefore, the orthographic projection of the fourth conductive part U4 on the base substrate 10 is overlapped with the orthographic projection of the third conductive part U3 on the base substrate 10, so that the third conductive part U3 is reused as the first plate C1-1 of the first capacitor C1, and the fourth conductive part U4 is reused as the second plate C1-2 of the first capacitor C1.

[0280] Based on this, there is no need to separately manufacture the first electrode plate C1 - 1 and the second electrode plate C1 - 2 of the first capacitor C1 , which can simplify the manufacturing process of the pixel driving circuit Q in the display panel 100 .

[0281] In addition, since the fourth conductive portion U4 (the second plate C1-2 of the first capacitor C1) is electrically connected to the second plate Cst-2 of the storage capacitor Cst. It can be understood that the second plate C1-2 of the first capacitor C1 and the second plate Cst-2 of the storage capacitor Cst are a whole. In addition, the size of the second plate Cst-2 of the first capacitor C1 can be increased, and the capacitance of the first capacitor C1 can be increased. As a result, the discharge time of the first capacitor C1 to the first node N1 can be increased after the data write transistor T4 is turned off and in the extreme before the compensation transistor T2 is turned off. Therefore, the time for writing the data write signal can be further extended, which is beneficial to improving the display uniformity of the display panel.

[0282] In some examples, the fourth conductive portion U4 is disposed in the same layer as the second electrode plate Cst- 2 of the storage capacitor Cst.

[0283] Based on this, the fourth conductive portion U4 and the second electrode plate Cst- 2 of the storage capacitor Cst can be formed by using one patterning process, which can simplify the manufacturing process of the pixel driving circuit Q.

[0284] It should be noted that "same layer" refers to a layer structure formed by using the same film-forming process to form a film layer for forming a specific pattern, and then using the same mask to form a layer structure through a single patterning process. Depending on the specific pattern, a single patterning process may include multiple exposure, development or etching processes, and the specific patterns in the formed layer structure may be continuous or discontinuous, and these specific patterns may also be at different heights or have different thicknesses.

[0285] In some embodiments, Fig.10 and Fig.14 As shown, the third conductive portion U3 is close to the channel portion a5 of the first light emission control transistor T5 and is connected to the channel portion a5 of the first light emission control transistor T5. That is, the third conductive portion U3 extends along the second direction Y to the position of the channel portion a5 of the first light emission control transistor T5 and is connected to the channel portion a5 of the first light emission control transistor T5.

[0286] Thus, the length of the third conductive portion U3 along the second direction Y can be increased. Furthermore, the size of the first electrode plate C1 - 1 of the first capacitor C1 can be increased, thereby increasing the capacitance of the first capacitor C1 .

[0287] Based on this, the discharge time of the first capacitor C1 to the first node N1 can be increased after the data writing transistor T4 is turned off and before the compensation transistor T2 is turned off. Therefore, the writing time of the data writing signal can be further extended, which is beneficial to improve the display uniformity of the display panel.

[0288] In some embodiments, Fig.10 and Fig.14 As shown, the third conductive portion U3 is close to one side of the channel portion a3 of the driving transistor T3 and is connected to the channel portion a3 of the driving transistor T3. That is, it is equivalent to extending the third conductive portion U3 to the position of the channel portion a3 of the driving transistor T3 and connecting to the channel portion a3 of the driving transistor T3 to increase the size of the third conductive portion U3.

[0289] Thus, the size of the first electrode plate C1-1 of the first capacitor C1 can be increased, and the capacitance of the first capacitor C1 can be increased. Furthermore, the discharge time of the first capacitor C1 to the first node N1 can be increased after the data writing transistor T4 is turned off and before the compensation transistor T2 is turned off. Therefore, the writing time of the data writing signal can be further extended, which is beneficial to improve the display uniformity of the display panel.

[0290] In some embodiments, Fig.10 and Fig.14 As shown, the third conductive portion U3 is close to the channel portion a4 of the data writing transistor T4 and is connected to the channel portion a4 of the data writing transistor T4. That is, it is equivalent to extending the third conductive portion U3 to the position of the channel portion a4 of the data writing transistor T4 and connecting to the channel portion a4 of the data writing transistor T4 to increase the size of the third conductive portion U3.

[0291] Thus, the size of the first electrode plate C1-1 of the first capacitor C1 can be increased, and the capacitance of the first capacitor C1 can be increased. Furthermore, the discharge time of the first capacitor C1 to the first node N1 can be increased after the data writing transistor T4 is turned off and before the compensation transistor T2 is turned off. Therefore, the writing time of the data writing signal can be further extended, which is beneficial to improve the display uniformity of the display panel.

[0292] In some embodiments, Fig.10 and Fig.14 As shown, along the second direction Y, the third conductive portion U3 is away from the channel portion a5 of the first light emission control transistor T5 and protrudes from the channel portion a5 of the driving transistor T3.

[0293] This is equivalent to extending the third conductive portion U3 out of the channel portion a5 of the driving transistor T3 along the second direction Y, so as to maximize the length of the third conductive portion U3 within the space in the second direction Y of the semiconductor layer POLY.

[0294] Thus, the size of the first electrode plate C1-1 of the first capacitor C1 can be increased, and the capacitance of the first capacitor C1 can be increased. Furthermore, the discharge time of the first capacitor C1 to the first node N1 can be increased after the data writing transistor T4 is turned off and before the compensation transistor T2 is turned off. Therefore, the writing time of the data writing signal can be further extended, which is beneficial to improve the display uniformity of the display panel.

[0295] In some embodiments, Fig.13 and Fig.14 As shown, the fourth conductive portion U4 includes a fourth auxiliary portion F4 protruding toward the control electrode g5 of the first light-emitting control transistor T5. The fourth auxiliary portion F4 is formed on the substrate (eg Figure 3The orthographic projection on the first light emitting control transistor T5 at least partially overlaps with the second electrode d5 of the first light emitting control transistor T5.

[0296] Thus, the size of the second electrode plate C1-2 of the first capacitor C1 can be increased, and the capacitance of the first capacitor C1 can be increased. Furthermore, the discharge time of the first capacitor C1 to the first node N1 can be increased after the data writing transistor T4 is turned off and before the compensation transistor T2 is turned off. Therefore, the writing time of the data writing signal can be further extended, which is beneficial to improve the display uniformity of the display panel.

[0297] In some embodiments, Fig. 9 As shown, along the first direction X, two adjacent pixel driving circuits Q are symmetrical. Exemplarily, along the first direction X, two adjacent pixel driving circuits Q are mirror-symmetrical.

[0298] Based on this, the regularity of the pixel driving circuit Q in the display panel 100 can be improved, which facilitates the simplification of the layout of the pixel driving circuit Q in the display panel 100 .

[0299] In some embodiments, Figures 9 to 17 As shown, in the case where two adjacent pixel driving circuits Q are symmetrically arranged along the first direction X: the first electrode s3 of the driving transistor T3 of the nth pixel driving circuit Q can be arranged to be adjacent to the first electrode s3 of the driving transistor T3 in the n+1th pixel driving circuit Q along the first direction X. Wherein, n is a positive integer.

[0300] When the first electrodes s3 of the driving transistors T3 of two adjacent pixel driving circuits Q are adjacent to each other along the first direction X, the second electrode Cst-2 of the storage capacitor Cst located on the second gate metal layer Gate2 does not need to avoid the second electrode d3 of the driving transistor T3. Figure 3 The orthographic projection on the substrate 10 covers the orthographic projection of the first electrode s3 of the driving transistor T3 on the substrate 10.

[0301] Thus, the second plates Cst-2 of the storage capacitors Cst in two adjacent pixel driving circuits Q do not need to consider the problem of avoiding, and can directly fill the space between the second plates Cst-2 of the storage capacitors Cst of the two pixel driving circuits Q. That is, the horizontal space utilization rate of the driving circuit layer can be fully utilized, and the size of the second plate Cst-2 of the storage capacitor Cst can be increased, which is beneficial to increase the capacitance of the storage capacitor Cst and the first capacitor C1.

[0302] In some examples, n=1 is used as an example for description. In the first direction X, the first electrode s3 of the driving transistor T3 of the first pixel driving circuit Q is adjacent to the first electrode s3 of the driving transistor T3 in the second pixel driving circuit Q. Wherein n is a positive integer.

[0303] Thus, the second electrode d3 of the driving transistor T3 of the first pixel driving circuit Q is located at the side of the first pixel driving circuit Q away from the second pixel driving circuit Q. Also, the second electrode d3 of the driving transistor T3 in the second pixel driving circuit Q is located at the side of the second pixel driving circuit Q away from the first pixel driving circuit Q.

[0304] Based on this, the second electrode plate Cst-2 of the storage capacitor Cst can be formed on the substrate 10 (eg Figure 3 The orthographic projection on the substrate 10 covers the orthographic projection of the first electrode s3 of the driving transistor T3 on the substrate 10, and the second electrode plate Cst-2 of the storage capacitor Cst does not need to avoid the second electrode d3 of the driving transistor T3. That is, the second electrode plate Cst-2 of the storage capacitor Cst can directly cover the space between the second electrodes d3 of the driving transistors T3 of the two pixel driving circuits Q, making full use of the horizontal space utilization rate of the driving circuit layer.

[0305] In some embodiments, Figures 9 to 17 As shown, in the case where two adjacent pixel driving circuits Q are symmetrically arranged along the first direction X: the second plate Cst-2 of the storage capacitor Cst of the n-th pixel driving circuit Q can be electrically connected to the second plate Cst-2 of the storage capacitor Cst in the n+1-th pixel driving circuit Q. Wherein, n is a positive integer.

[0306] Based on this, the size of the second plate Cst-2 of the storage capacitor Cst in the pixel driving circuit Q can be increased. Therefore, the size of the second plate C1-2 of the first capacitor C1 can also be increased synchronously, and the capacitance of the first capacitor C1 can be increased. Furthermore, the discharge time of the first capacitor C1 to the first node N1 can be increased after the data writing transistor T4 is turned off and before the compensation transistor T2 is turned off. Therefore, the writing time of the data writing signal can also be further extended, which is beneficial to improve the display uniformity of the display panel.

[0307] In some examples, n=1 is used as an example for description. In the first direction X, the first electrode s3 of the driving transistor T3 of the first pixel driving circuit Q is adjacent to the first electrode s3 of the driving transistor T3 in the second pixel driving circuit Q. Wherein n is a positive integer.

[0308] Thus, the second plate Cst-2 of the storage capacitor Cst of the first pixel driving circuit Q is electrically connected to the second plate Cst-2 of the storage capacitor Cst of the second pixel driving circuit Q. Furthermore, it is equivalent to providing a third conductive portion U3 corresponding to the first pixel driving circuit Q, which is connected to the third conductive portion U3 corresponding to the second pixel driving circuit Q.

[0309] Based on this, the size of the second plate Cst-2 of the storage capacitor Cst and the size of the second plate C1-2 of the first capacitor C1 can be increased in the pixel driving circuit Q. Therefore, the writing time of the data writing signal can be further prolonged, which is beneficial to improving the display uniformity of the display panel.

[0310] In some embodiments, Figures 9 to 17 As shown, along the first direction X, the second reset transistor T7 and the second electrode d2 of the driving transistor T3 belong to the areas on both sides of the pixel driving circuit Q. On the basis that the first electrode s3 of the driving transistor T3 of the nth pixel driving circuit Q is adjacent to the first electrode s3 of the driving transistor T3 in the n+1th pixel driving circuit Q, the second reset transistor T7 in the n+1th pixel driving circuit Q can be arranged adjacent to the second reset transistor T7 in the n+2th pixel driving circuit Q. Wherein, n is a positive integer.

[0311] Further, the first electrode s7 of the second reset transistor T7 in the n+1th pixel driving circuit Q may be arranged adjacent to the first electrode s7 of the second reset transistor T7 in the n+2th pixel driving circuit Q.

[0312] Based on this, the first initialization signal line Vinit1 can be electrically connected to the first electrode s7 of the second reset transistor T7 in the n+1th pixel driving circuit Q and the first electrode s7 of the second reset transistor T7 in the n+2th pixel driving circuit Q. There is no need to provide a bending portion / avoidance portion on the first initialization signal line Vinit1, and the film layer structure layout of the pixel driving circuit Q can be simplified.

[0313] In some examples, the first electrode s7 of the second reset transistor T7 in the n+1th pixel driving circuit Q is multiplexed as the first electrode s7 of the second reset transistor T7 in the n+2th pixel driving circuit Q.

[0314] Based on this, there is no need to separately set the first electrode s7 of the second reset transistor T7 in the n+2 pixel driving circuit Q, which can simplify the manufacturing process of the pixel driving circuit Q in the display panel 100. In addition, since the first electrode s7 of the second reset transistor T7 in the n+1 pixel driving circuit Q is directly reused as the first electrode s7 of the second reset transistor T7 in the n+2 pixel driving circuit Q, the first initialization signal line Vinit1 is directly electrically connected to the first electrode s7 of the second reset transistor T7 in the n+1 pixel driving circuit Q, and can be electrically connected to the first electrode s7 of the second reset transistor T7 in the n+2 pixel driving circuit Q at the same time.

[0315] Therefore, the film structure of the pixel driving circuit Q can be simplified, which facilitates the simplification of the process of the pixel driving circuit Q.

[0316] Fig.18 is a film layer structure diagram of a plurality of pixel driving circuits according to some other embodiments, Fig.19 for Fig.18 The structure diagram of the middle and bottom shielding layer. Fig.18 The pixel driving circuit Q shown in FIG. Fig. 9 The difference between the pixel driving circuit Q shown is that the display panel 100 further includes a bottom shielding layer 40 .

[0317] In some embodiments, in combination Fig.18 and Fig.19 As shown, the display panel 100 further includes a bottom shield metal (BSM) 40, which is located on the base substrate 10 (eg Figure 3 The orthographic projection of the bottom shielding layer 40 on the base substrate 10 covers the orthographic projection of the driving transistor T3 on the base substrate 10 .

[0318] Based on this, the bottom shielding layer 40 can be used to shield the influence of static electricity on the driving transistor T3. In addition, the bottom shielding layer 40 can also serve as a light shielding layer to reduce the influence of external light incident from the side of the base substrate 10 on the semiconductor layer POLY, thereby improving the performance of the semiconductor layer POLY.

[0319] In some examples, the orthographic projection of the driving transistor T3 on the substrate 10 is located within the boundary of the orthographic projection of the bottom shielding layer 40 on the substrate 10 , and the bottom shielding layer 40 can completely cover the driving transistor T3 to shield the influence of static electricity on the driving transistor T3 .

[0320] In some examples, the bottom shielding layer 40 is configured to receive a first power signal, thereby reducing static electricity accumulation on the bottom shielding layer 40 .

[0321] In addition, two bottom shielding layers 40 corresponding to two adjacent pixel driving circuits Q may be electrically connected via a connecting portion, thereby reducing the impedance of the bottom shielding layer 40 .

[0322] The above is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any changes or substitutions that can be thought of by any person skilled in the art within the technical scope disclosed in the present disclosure should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A display panel, characterized in that: It includes a display area and a binding area, wherein the binding area is located at one side of the display area; the display area includes a middle area and two edge areas, and along a first direction, the middle area is located between the two edge areas; The display panel comprises: a substrate substrate; and, A driving circuit layer is located on one side of the base substrate; the driving circuit layer comprises: A plurality of pixel driving circuits are arranged in a plurality of rows and columns in the display area; the pixel driving circuits include a driving transistor and a first reset transistor; The control electrode of the driving transistor is electrically connected to the first node, the first electrode of the driving transistor is electrically connected to the second node, and the second electrode of the driving transistor is electrically connected to the third node; The control electrode of the first reset transistor is electrically connected to the first reset signal line, the first electrode of the first reset transistor is electrically connected to the first initialization signal line, and the second electrode of the first reset transistor is electrically connected to the first node; A plurality of data writing signal lines are located in the display area, and the plurality of data writing signal lines are arranged along the first direction and extend along a second direction, and the second direction intersects the first direction; one data writing signal line is connected to one column of the pixel driving circuits; A plurality of data leads, the data leads include a first lead segment and a second lead segment, one end of the first lead segment is electrically connected to a data write signal line located in the edge area, and the other end of the first lead segment is electrically connected to one end of the second lead segment; the first lead segment extends along a first direction, the second lead segment extends along a second direction, and the second lead segment extends from the middle area to the binding area; Along the direction away from the substrate, the driving circuit layer includes a semiconductor layer, a first gate metal layer, a second gate metal layer, a first routing metal layer and a second routing metal layer; The semiconductor layer includes a first conductive portion, which includes a second electrode of a first reset transistor; the second gate metal layer includes a first shielding portion, which is configured to have a constant voltage signal; the first routing metal layer includes the first lead segment; the second routing metal layer includes the data write signal line and the second lead segment; wherein the orthographic projection of the first shielding portion on the substrate, the orthographic projection of the first conductive portion on the substrate, and the orthographic projection of the first lead segment on the substrate overlap.

2. The display panel according to claim 1, characterized in that: The second gate metal layer further includes the first initialization signal line, and the first reset signal line is connected to the first shielding portion.

3. The display panel according to claim 2, characterized in that: The first initialization signal line includes a first auxiliary portion protruding toward the first reset transistor, and the orthographic projection of the first auxiliary portion on the base substrate, the orthographic projection of the first conductive portion on the base substrate, and the orthographic projection of the first lead segment on the base substrate overlap; the first auxiliary portion is multiplexed as the first shielding portion.

4. The display panel according to claim 1, characterized in that: The pixel driving circuit further includes: a compensation transistor, wherein a control electrode of the compensation transistor is electrically connected to the second scanning signal line, a first electrode of the compensation transistor is electrically connected to the third node, and a second electrode of the compensation transistor is electrically connected to the first node; The compensation transistor is a dual-gate transistor, and the control electrode of the compensation transistor includes a first control electrode and a second control electrode; The semiconductor layer further includes: a first channel portion of the compensation transistor, a second channel portion of the compensation transistor, and a second conductive portion, one end of the second conductive portion is connected to the first channel portion, and the other end of the second conductive portion is connected to the second channel portion; The first initialization signal line further includes a second auxiliary portion protruding toward the driving transistor, and an orthographic projection of the second auxiliary portion on the base substrate at least partially overlaps with an orthographic projection of the second conductive portion on the base substrate.

5. The display panel according to claim 4, characterized in that: The orthographic projection of the second conductive portion on the base substrate is located within the boundary of the orthographic projection of the second auxiliary portion on the base substrate.

6. The display panel according to claim 4 or 5, characterized in that: The second conductive portion includes a first sub-portion, a second sub-portion and a third sub-portion, and the first sub-portion, the second sub-portion and the third sub-portion intersect at the same point; wherein the first sub-portion is electrically connected to the first channel portion, the second sub-portion is electrically connected to the second channel portion, and the third sub-portion is located on a side of the second sub-portion away from the second channel portion.

7. The display panel according to claim 1, characterized in that: The pixel driving circuit further includes: a data writing transistor, wherein a control electrode of the data writing transistor is connected to the first scanning signal line, a first electrode of the data writing transistor is electrically connected to the data writing signal line, and a second electrode of the data writing transistor is electrically connected to the second node; a second reset transistor, wherein a control electrode of the second reset transistor is electrically connected to the first scanning signal line, a first electrode of the second reset transistor is electrically connected to the second initialization signal line, and a second electrode of the second reset transistor is electrically connected to a fourth node; Along the first direction, a control electrode of the data writing transistor overlaps with a control electrode of the second reset transistor.

8. The display panel according to claim 1, characterized in that: The pixel driving circuit also includes: a first light emission control transistor, wherein a control electrode of the first light emission control transistor is electrically connected to a first enable signal line, a first electrode of the first light emission control transistor is electrically connected to a first power supply signal line, and a second electrode of the first light emission control transistor is electrically connected to the second node; A second light emitting control transistor, wherein the control electrode of the second light emitting control transistor is electrically connected to the second enable signal line, the first electrode of the second light emitting control transistor is electrically connected to the third node, and the second electrode of the second light emitting control transistor is electrically connected to the fourth node.

9. The display panel according to claim 1, characterized in that: The pixel driving circuit further includes: a storage capacitor, wherein a first plate of the storage capacitor is electrically connected to the first node, and a second plate of the storage capacitor is electrically connected to a first power signal line; A first capacitor, wherein a first plate of the first capacitor is electrically connected to the second node, and the first plate of the first capacitor is electrically connected to a first power signal line.

10. The display panel according to claim 9, characterized in that: The pixel driving circuit includes a data writing transistor and a first light emitting control transistor; The semiconductor layer includes a third conductive portion, and the third conductive portion includes a first electrode of the driving transistor, a second electrode of the first light emission control transistor, and a second electrode of the data writing transistor; The second gate metal layer further includes a fourth conductive portion, one end of the fourth conductive portion is electrically connected to the second electrode of the storage capacitor, and the other end of the fourth conductive portion is electrically connected to the first electrode of the first light emission control transistor; The orthographic projection of the fourth conductive portion on the base substrate at least partially overlaps with the orthographic projection of the third conductive portion on the base substrate; The third conductive portion is multiplexed as the first plate of the first capacitor, and the fourth conductive portion is multiplexed as the second plate of the first capacitor.

11. The display panel according to claim 10, characterized in that: Along the second direction, the third conductive portion is away from a side of the channel portion of the first light emission control transistor and protrudes out of the channel portion of the driving transistor.

12. The display panel according to claim 1, characterized in that: Along the first direction, two adjacent pixel driving circuits are symmetrical.

13. The display panel according to claim 12, characterized in that: Along the first direction, the first electrode of the driving transistor in the nth pixel driving circuit is adjacent to the first electrode of the driving transistor in the (n+1)th pixel driving circuit; wherein n is a positive integer.

14. The display panel according to claim 12 or 13, characterized in that: The second plate of the storage capacitor of the nth pixel driving circuit is electrically connected to the second plate of the storage capacitor in the pixel driving circuit of the n+1th sub-pixel; wherein n is a positive integer.

15. The display panel according to claim 14, characterized in that: Along the first direction, the second reset transistor in the n+1th pixel driving circuit is arranged adjacent to the second reset transistor in the n+2th pixel driving circuit, and the first electrode of the second reset transistor in the n+1th pixel driving circuit is reused as the first electrode of the second reset transistor in the n+2th pixel driving circuit.

16. The display panel according to claim 1, characterized in that: The first routing metal layer further includes a plurality of first virtual lead segments, the first virtual lead segments correspond to the first lead segments one by one, and along the first direction, the first lead segments and the first virtual lead segments are arranged at intervals.

17. The display panel according to claim 1, characterized in that: The second routing metal layer further includes a plurality of second virtual lead segments, the second virtual lead segments correspond to the second lead segments one by one, and along the first direction, the second lead segments and the second virtual lead segments are arranged at intervals.

18. The display panel according to claim 1, characterized in that: It also includes a bottom shielding layer located between the base substrate and the pixel driving circuit, wherein the orthographic projection of the bottom shielding layer on the base substrate covers the orthographic projection of the driving transistor on the base substrate.

19. The display panel according to claim 1, characterized in that: Also includes: The light emitting device layer is located on a side of the driving circuit layer away from the base substrate; the light emitting device layer includes a plurality of light emitting devices, and the light emitting devices are electrically connected to the pixel driving circuit.

20. A display device, characterized in that: The invention comprises the display panel according to any one of claims 1 to 19.

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