Display device

Abstract

A display device is provided. The display device includes a substrate including a first pixel and a second pixel adjacent to each other in a first direction, the first pixel including a sub-pixel, and the second pixel including a sub-pixel; a first electrode and a second electrode over the substrate and extending in a first direction, the first electrode and the second electrode in the sub-pixel; a first insulating layer over the first electrode and the second electrode; a light emitting element over the first insulating layer between the first electrode and the second electrode; a bank layer over the first insulating layer and dividing a first emission region and a second emission region of one of the sub-pixels and dividing a sub-region of the first pixel and a sub-region of the second pixel; and a first connection electrode and a second connection electrode in the sub-pixel. The display device can prevent or reduce dark spot defects.

Description

Technical Field

[0001] The present disclosure relates to a display device. Background Art

[0002] As multimedia technology develops, the importance of display devices has been steadily increasing. In response to this, various types of display devices such as organic light emitting diode (OLED) displays, liquid crystal displays (LCDs), etc. have been used.

[0003] The display device is a device for displaying an image, and may include a display panel such as a light-emitting display panel or a liquid crystal display panel. The light-emitting display panel may include a light-emitting element, for example, a light-emitting diode (LED). The light-emitting diode may include an organic light-emitting diode (OLED) using an organic material as a light-emitting material and an inorganic light-emitting diode using an inorganic material as a light-emitting material. Utility Model Content

[0004] The utility model aims to provide a display device capable of preventing or reducing dark spot defects.

[0005] However, aspects of the present disclosure are not limited to the aspects set forth herein. The above and other aspects of the present disclosure will become more apparent to those skilled in the art to which the present disclosure pertains by referring to the detailed description of the present disclosure given below.

[0006] In one or more embodiments, a display device includes: a substrate including a first pixel and a second pixel adjacent to each other in a first direction, the first pixel including a sub-pixel, and the second pixel including a sub-pixel; a first electrode and a second electrode above the substrate and extending in the first direction, the first electrode and the second electrode being in the sub-pixel; a first insulating layer above the first electrode and the second electrode; a light-emitting element above the first insulating layer between the first electrode and the second electrode; a dam layer above the first insulating layer and dividing a first emission region and a second emission region of one of the sub-pixels, and dividing a sub-region of the first pixel and a sub-region of the second pixel; and a first connecting electrode and a second connecting electrode, in the sub-pixel, the first connecting electrode being connected to a first end of the light-emitting element, and the second connecting electrode being connected to a second end of the light-emitting element, wherein the dam layer is around the first emission region and sub-region of the sub-pixel of the first pixel and the second emission region of the sub-pixel of the second pixel.

[0007] In one or more embodiments, the embankment layer includes: a first extension portion and a second extension portion, which extend in a first direction and are spaced apart in a second direction intersecting the first direction; and a first connecting portion and a second connecting portion, which connect the first extension portion and the second extension portion and are spaced apart in the first direction.

[0008] In one or more embodiments, the first extension is on one side of a sub-pixel of the first pixel and the second pixel, and wherein the second extension is on the other side of the sub-pixel of the first pixel and the second pixel.

[0009] In one or more embodiments, the first connection portion is between the first emission region and the second emission region of the sub-pixel of the first pixel in the sub-pixel of the first pixel, and the first connection electrode of the sub-pixel of the first pixel does not overlap with the first connection portion, and wherein the second connection electrode of the sub-pixel of the first pixel overlaps with the first connection portion.

[0010] In one or more embodiments, the second connection portion is between the first emission region and the second emission region of the sub-pixel of the second pixel in the sub-pixel of the second pixel, the first connection electrode of the sub-pixel of the second pixel does not overlap with the second connection portion, and wherein the second connection electrode of the sub-pixel of the second pixel overlaps with the second connection portion.

[0011] In one or more embodiments, the first extension portion, the second extension portion, the first connection portion, and the second connection portion are around the second emission region and sub-region of the sub-pixel of the first pixel and the first emission region of the sub-pixel of the second pixel, and the sub-region of the sub-pixel of the first pixel is between the second emission region of the sub-pixel of the first pixel and the first emission region of the sub-pixel of the second pixel.

[0012] In one or more embodiments, the light emitting element is in sub-pixels of the first pixel and the second pixel and includes the first light emitting element and the second light emitting element, and the first light emitting element and the second light emitting element do not overlap with the first connection portion and the second connection portion of the bank layer.

[0013] In one or more embodiments, a display device includes: a substrate including a first sub-pixel and a second sub-pixel spaced apart from each other in a first direction; a dam layer above the substrate and dividing a first emission region and a second emission region of the first sub-pixel and a first emission region and a second emission region of the second sub-pixel; a first connecting electrode, a second connecting electrode, and a third connecting electrode, in the first sub-pixel and the second sub-pixel and extending across the first emission region and the second emission region; and a light emitting element above the substrate and between the first connecting electrode and the second connecting electrode and between the second connecting electrode and the third connecting electrode, respectively, wherein the first connecting electrode, the second connecting electrode, and the third connecting electrode cross and overlap with the dam layer.

[0014] In one or more embodiments, the embankment layer is around the first emission region of the first subpixel and the second emission region of the second subpixel, and in the first subpixel and the second subpixel, the light-emitting elements include the first light-emitting element and the second light-emitting element between the first connecting electrode and the second connecting electrode, and the third light-emitting element and the fourth light-emitting element between the second connecting electrode and the third connecting electrode, and the first light-emitting element and the fourth light-emitting element are in the first emission region, and wherein the second light-emitting element and the third light-emitting element are in the second emission region.

[0015] In one or more embodiments, the display device further includes: a sub-region between the first emission region of the first sub-pixel and the second emission region of the second sub-pixel, and not overlapping with the bank layer and the light-emitting element. The display device according to one or more embodiments may include emission regions of sub-pixels adjacent to each other in which a bank layer is positioned, thereby reducing or preventing driving defects of the sub-pixels even when there is a light-emitting element region in which no light-emitting element is positioned. In addition, even if a driving defect occurs in one sub-pixel, the possibility of recognizing a dark spot due to light emitted from an adjacent sub-pixel can be reduced or prevented.

[0016] However, aspects according to one or more embodiments of the present disclosure are not limited to the above-mentioned aspects, and various other aspects are included herein. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The above and other aspects of the present disclosure will become more apparent by describing in detail embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0018] Figure 1 is a schematic plan view of a display device according to one or more embodiments;

[0019] Figure 2 is a plan view showing the arrangement of a plurality of wirings included in a display device according to one or more embodiments;

[0020] Figure 3 is an equivalent circuit diagram of a sub-pixel according to one or more embodiments;

[0021] Figure 4 is a plan view showing a pixel of a display device according to one or more embodiments;

[0022] Figure 5 is a plan view showing electrodes of a display device according to one or more embodiments;

[0023] Figure 6 is a plan view showing connection electrodes of a display device according to one or more embodiments;

[0024] Figure 7is a schematic cross-sectional view of a display device according to one or more embodiments;

[0025] Figure 8 is a schematic perspective cross-sectional view of a light emitting element according to one or more embodiments;

[0026] Fig. 9 is a plan view schematically showing electrodes, a bank layer, and a light emitting element of a display device according to one or more embodiments;

[0027] Fig.10 is a plan view schematically showing a connection electrode, a bank layer, and a light emitting element of a display device according to one or more embodiments;

[0028] Fig.11 is a plan view showing a connection electrode and a current flow of a light emitting element of a display device according to one or more embodiments;

[0029] Fig.12 is a plan view showing a connection electrode and a current flow of a light emitting element of a display device according to one or more embodiments;

[0030] Fig.13 is a plan view showing a connection electrode, a bank layer, and a light emitting element of a display device according to one or more embodiments; and

[0031] Fig.14 is a plan view illustrating a connection electrode and a current flow of a light emitting element of a display device according to one or more embodiments. DETAILED DESCRIPTION

[0032] The present disclosure will now be described more fully hereinafter with reference to the accompanying drawings, in which embodiments of the present disclosure are shown. However, the present disclosure may be implemented in different forms and should not be construed as being limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that the present disclosure will be thorough and complete, and will fully convey the scope of the present disclosure to those skilled in the art.

[0033] It will also be understood that when a layer is referred to as being “on” another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may also be present. Like reference numerals refer to like components throughout the disclosure.

[0034] It will be understood that although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, without departing from the teachings of the present disclosure, the first element discussed below may be referred to as the second element. Similarly, the second element may also be referred to as the first element.

[0035] Each of the features of the various embodiments of the present disclosure can be combined in part or in whole or in combination with each other, and various interlocks and drives are technically possible. Each embodiment can be implemented independently of each other, or can be implemented together in association.

[0036] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0037] Figure 1 is a schematic plan view of a display device according to one or more embodiments.

[0038] Reference Figure 1 , the display device 10 displays a moving image or a still image. The display device 10 may refer to any electronic device that provides a display screen. For example, the display device 10 may include a television, a laptop computer, a monitor, an electronic billboard, an Internet of Things (IoT) device, a mobile phone, a smart phone, a tablet personal computer (PC), an electronic watch, a smart watch, a watch phone, a head-mounted display device, a mobile communication terminal, an electronic notebook, an electronic book, a portable multimedia player (PMP), a navigation device, a game console, and a digital camera, a video camera, etc.

[0039] The display device 10 includes a display panel for providing a display screen. Examples of the display panel may include an inorganic light emitting diode display panel, an organic light emitting display panel, a quantum dot light emitting display panel, a plasma display panel, a field emission display panel, etc. In the following description, an inorganic light emitting diode display panel is used as an example of the display device 10, but the present disclosure is not limited thereto. Any other display panel may be used as long as the technical concept of the present disclosure can be equally applied.

[0040] The shape of the display device 10 may be modified in various ways. For example, the display device 10 may have a shape such as a rectangle with a longer horizontal side, a rectangle with a longer vertical side, a square, a quadrilateral with rounded corners (vertices), other polygons, a circle, etc. The shape of the display area DPA of the display device 10 may also be similar to the overall shape of the display device 10. Figure 1 As shown in , the display device 10 has a rectangular shape having longer sides in the second direction DR2.

[0041] The display device 10 may include a display area DPA and a non-display area NDA around an edge or periphery of the display area DPA. In the display area DPA, an image may be displayed. In the non-display area NDA, no image is displayed. The display area DPA may be referred to as an active area, and the non-display area NDA may be referred to as an inactive area. The display area DPA may generally occupy most of the center (or central portion) of the display device 10.

[0042] The display area DPA may include a plurality of pixels PX. The plurality of pixels PX may be arranged in a matrix. For example, the plurality of pixels PX may be arranged along rows and columns of the matrix. When viewed from the top, the shape of each pixel PX may be, but is not limited to, a rectangle or a square. Each pixel may have a rhombus shape with sides inclined relative to a direction. The pixels PX may be arranged in a stripe or island pattern or The structure is arranged, but the present disclosure is not limited thereto. The arrangement structure may be referred to as an RGBG matrix structure (eg, Matrix structure or RGBG structure (for example, structure)). It is a registered trademark of Samsung Display Co., Ltd., Republic of Korea.

[0043] Each of the pixels PX may include at least one light emitting element that emits light of a corresponding wavelength band to express a color.

[0044] The non-display area NDA may be positioned around the display area DPA along an edge or periphery of the display area DPA. The non-display area NDA may completely or partially surround the display area DPA. The display area DPA may have a rectangular shape, and the non-display area NDA may be adjacent to four sides of the display area DPA. The non-display area NDA may form a frame of the display device 10. A line or circuit driver included in the display device 10 may be positioned in each of the non-display areas NDA, or an external device may be installed.

[0045] Figure 2 is a plan view showing the arrangement of a plurality of wirings included in a display device according to one or more embodiments.

[0046] Reference Figure 2 The display device 10 may include a plurality of scan lines SL (SL1, SL2, and SL3), a plurality of data lines DTL (DTL1, DTL2, and DTL3), an initialization voltage line VIL, and a plurality of voltage lines VL (VL1, VL2, VL3, and VL4). Figure 2 In the embodiment, other lines may be further positioned in the display device 10 .

[0047] The first scan line SL1 and the second scan line SL2 may extend in the first direction DR1. The first scan line SL1 and the second scan line SL2 may be positioned in a state where they are adjacent to each other, and may be spaced apart from other first scan lines SL1 and second scan lines SL2 in the second direction DR2. The first scan line SL1 and the second scan line SL2 may be connected to a scan line pad (also referred to as a "pad" or "pad") WPD_SC connected to a scan driver. The first scan line SL1 and the second scan line SL2 may extend from a pad area PDA positioned in a non-display area NDA to a display area DPA.

[0048] The third scan line SL3 may extend in the second direction DR2 and may be spaced apart from other third scan lines SL3 in the first direction DR1. One third scan line SL3 may be connected to one or more first scan lines SL1 or one or more second scan lines SL2. In one or more embodiments, the first scan line SL1 and the second scan line SL2 may be formed of a conductive layer positioned at a different layer from the third scan line SL3. The plurality of scan lines SL may have a grid structure in the entire display area DPA, but is not limited thereto.

[0049] In one or more embodiments, the term "connection" as used herein may not only mean that one component is connected to another component by physical contact, but also may mean that one component is connected to another component via another component. This may also be understood as a component (part) and another component (part) being connected to an integral component via another component. In addition, if one component is connected to another component, this may be interpreted as meaning an electrical connection via another component in addition to a direct connection of physical contact.

[0050] The data line DTL may extend in a first direction DR1. The data line DTL may include a first data line DTL1, a second data line DTL2, and a third data line DTL3, and one first data line DTL1, one second data line DTL2, and one third data line DTL3 form a group and are adjacent to each other. Each of the data lines DTL1, DTL2, and DTL3 may extend from a pad area PDA positioned in a non-display area NDA to a display area DPA. However, the present disclosure is not limited thereto, and a plurality of data lines DTL may also be spaced apart from each other at equal intervals (e.g., at substantially equal intervals) between a first voltage line VL1 and a second voltage line VL2 to be described later.

[0051] The initialization voltage line VIL may extend in the first direction DR1. The initialization voltage line VIL may be positioned between the data line DTL and the first and second scan lines SL1 and SL2. The initialization voltage line VIL may extend from the pad area PDA positioned in the non-display area VDA to the display area DPA.

[0052] The first voltage line VL1 and the second voltage line VL2 extend in the first direction DR1, and the third voltage line VL3 and the fourth voltage line VL4 extend in the second direction DR2. The first voltage line VL1 and the second voltage line VL2 may be alternately arranged along the second direction DR2, and the third voltage line VL3 and the fourth voltage line VL4 may be alternately arranged along the first direction DR1. The first voltage line VL1 and the second voltage line VL2 may extend in the first direction DR1 to pass through the display area DPA, some voltage lines of each of the third voltage line VL3 and the fourth voltage line VL4 may be positioned in the display area DPA, and the other voltage lines of each of the third voltage line VL3 and the fourth voltage line VL4 may be positioned in the non-display area NDA located on both sides of the display area DPA in the first direction DR1. The first voltage line VL1 and the second voltage line VL2 may be formed by a conductive layer positioned at a different layer from the third voltage line VL3 and the fourth voltage line VL4. The first voltage line VL1 may be connected to at least one third voltage line VL3 , the second voltage line VL2 may be connected to at least one fourth voltage line VL4 , and the plurality of voltage lines VL may have a mesh structure throughout the display area DPA However, the present disclosure is not limited thereto.

[0053] The first scan line SL1, the second scan line SL2, the data line DTL, the initialization voltage line VIL, the first voltage line VL1, and the second voltage line VL2 may be electrically connected to at least one wire pad WPD. Each wire pad WPD may be positioned in the non-display area NDA. In one or more embodiments, each of the wire pads WPD may be positioned in the pad area PDA located at the lower side of both sides of the display area DPA in the first direction DR1. The first scan line SL1 and the second scan line SL2 are connected to the scan line pad WPD_SC positioned in the pad area PDA, and the plurality of data lines DTL are respectively connected to different data line pads WPD_DT from each other. The initialization voltage line VIL is connected to the initialization line pad WPD_Vint, the first voltage line VL1 is connected to the first voltage line pad WPD_VL1, and the second voltage line VL2 is connected to the second voltage line pad WPD_VL2. An external device may be mounted on the wire pad WPD. The external device may be mounted on the wire pad WPD by applying an anisotropic conductive film, ultrasonic bonding, or the like. The drawings show that each of the wire pads WPD is positioned in the pad area PDA located at the lower side of the display area DPA, but is not limited thereto. Some of the plurality of wire pads WPD may be positioned in any one area of ​​the upper side or left and right sides of the display area DPA.

[0054] Each pixel PX or sub-pixel SPXn (n is an integer from 1 to 3) of the display device 10 (see Figure 4 ) includes a pixel driving circuit. The above-mentioned lines can apply driving signals to each pixel driving circuit while passing through each pixel PX or around each pixel PX. The pixel driving circuit may include transistors and capacitors. The number of transistors and capacitors in each pixel driving circuit may be modified differently. According to one or more embodiments, each sub-pixel SPXn of the display device 10 may have a 3T1C structure in which the pixel driving circuit includes three transistors and one capacitor. In the following, the pixel driving circuit will be described using the 3T1C structure, but the present disclosure is not limited thereto, and various other modified structures (such as a 2T1C structure, a 7T1C structure, and a 6T1C structure) may be applied.

[0055] Figure 3 is an equivalent circuit diagram of a sub-pixel according to one or more embodiments.

[0056] Reference Figure 3 , each sub-pixel SPX of the display device 10 according to one or more embodiments includes three transistors T1 , T2 , and T3 and one storage capacitor C1 in addition to at least one light emitting element ED.

[0057] The light emitting element ED may emit light according to the current supplied by the first transistor T1. The light emitting element ED may include a first electrode, a second electrode, and a first light emitting element ED1, a second light emitting element ED2, a third light emitting element ED3, and a fourth light emitting element ED4 positioned between the first electrode and the second electrode. The first light emitting element ED1, the second light emitting element ED2, the third light emitting element ED3, and the fourth light emitting element ED4 may be connected in series. The first light emitting element ED1, the second light emitting element ED2, the third light emitting element ED3, and the fourth light emitting element ED4 may receive a driving current and emit light. The amount of light emitted or the brightness of the light emitting element ED may be proportional to the size of the driving current. The light emitting element ED may be an organic light emitting diode (OLED) having an organic light emitting layer, a quantum dot light emitting diode (LED) including a quantum dot light emitting layer, a micro LED, or an inorganic LED having an inorganic semiconductor.

[0058] A first electrode of the first light emitting element ED1 may be connected to a source electrode of the first transistor T1, a drain electrode of the third transistor T3, and a second capacitor electrode of the storage capacitor C1. A second electrode of the first light emitting element ED1 may be connected to a first electrode of the second light emitting element ED2. The second light emitting element ED2, the third light emitting element ED3, and the fourth light emitting element ED4 may each be connected in series. A second electrode of the fourth light emitting element ED4 may be connected to a second voltage line VL2.

[0059] The first transistor T1 adjusts the current flowing from the first voltage line VL1 to which the first power voltage is applied to the light emitting element ED according to the voltage difference between the gate electrode and the source electrode of the first transistor T1. For example, the first transistor T1 may be a driving transistor for driving the light emitting element ED. The gate electrode of the first transistor T1 may be connected to the source electrode of the second transistor T2, the source electrode thereof may be connected to the first electrode of the light emitting element ED, and the drain electrode thereof may be connected to the first voltage line VL1 to which the first power voltage is applied.

[0060] The second transistor T2 is turned on by the scan signal of the first scan line SL1 to connect the data line DTL to the gate electrode of the first transistor T1. The gate electrode of the second transistor T2 may be connected to the first scan line SL1, its source electrode may be connected to the gate electrode of the first transistor T1, and its drain electrode may be connected to the data line DTL.

[0061] The third transistor T3 is turned on by the scan signal of the second scan line SL2 to connect the initialization voltage line VIL to one end of the light emitting element ED. The gate electrode of the third transistor T3 may be connected to the second scan line SL2, the drain electrode thereof may be connected to the initialization voltage line VIL, and the source electrode thereof may be connected to one end of the light emitting element ED or to the source electrode of the first transistor T1.

[0062] In one or more embodiments, the source electrode and the drain electrode of each of the transistors T1, T2, and T3 are not limited to the above description, and vice versa. In addition, each of the transistors T1, T2, and T3 may be formed by a thin film transistor. Figure 3 In the embodiment, each of the transistors T1, T2 and T3 has been described as being formed by an N-type metal oxide semiconductor field effect transistor (MOSFET), but is not limited thereto. For example, each of the transistors T1, T2 and T3 may be formed by a P-type MOSFET. Alternatively, some of the transistors T1, T2 and T3 may be formed by an N-type MOSFET, while the others may be formed by a P-type MOSFET.

[0063] The storage capacitor C1 is formed between the gate electrode and the source electrode of the first transistor T1. The storage capacitor C1 stores a voltage corresponding to a voltage difference between a gate voltage and a source voltage of the first transistor T1.

[0064] Hereinafter, the structure of one pixel PX of the display device 10 according to one or more embodiments will be described in detail with additional reference to other drawings.

[0065] Figure 4 is a plan view showing a pixel of a display device according to one or more embodiments.

[0066] Figure 4 A planar arrangement of electrodes RME ( RME1 and RME2 ), a bank layer BNL, and connection electrodes CTE ( CTE1 , CTE2 , CTE3 , CTE4 , and CTE5 ) positioned in each of the pixels PX1 and PX2 of the display device 10 is shown.

[0067] Reference Figure 4 , the display device 10 may include a first pixel PX1 and a second pixel PX2. Each of the first pixel PX1 and the second pixel PX2 may include a plurality of sub-pixels SPXn. For example, the first pixel PX1 may include a first sub-pixel SPX1, a second sub-pixel SPX2, and a third sub-pixel SPX3, and the second pixel PX2 may include a first sub-pixel SPX1, a second sub-pixel SPX2, and a third sub-pixel SPX3.

[0068] The first sub-pixel SPX1 of each of the first pixel PX1 and the second pixel PX2 may emit light of a first color, the second sub-pixel SPX2 of each of the first pixel PX1 and the second pixel PX2 may emit light of a second color, and the third sub-pixel SPX3 of each of the first pixel PX1 and the second pixel PX2 may emit light of a third color. For example, the first color may be blue, the second color may be green, and the third color may be red. However, the present disclosure is not limited thereto, and each sub-pixel SPXn may emit light of the same color. In one or more embodiments, each sub-pixel SPXn may emit blue light. In the accompanying drawings, it is shown that one pixel PX includes three sub-pixels SPXn, but the present disclosure is not limited thereto, and the pixel PX may include a greater number of sub-pixels SPXn.

[0069] Each sub-pixel SPXn of the display device 10 may include a first emission area EMA1, a second emission area EMA2, and a non-emission area. Each of the first emission area EMA1 and the second emission area EMA2 may be an area where a light emitting element ED is positioned to emit light of a specific wavelength range. The non-emission area may be an area where the light emitting element ED is not positioned and an area where no light is emitted because the light emitted from the light emitting element ED does not reach there.

[0070] The first emission area EMA1 and the second emission area EMA2 may each include an area where the light emitting element ED is positioned and an area adjacent to the light emitting element ED to emit light emitted from the light emitting element ED. For example, the first emission area EMA1 and the second emission area EMA2 may also each include an area where the light emitted from the light emitting element ED is reflected or refracted by another member and emitted. A plurality of light emitting elements ED may be positioned in each sub-pixel SPXn, and the emission area may be formed to include an area where the light emitting element ED is positioned and an area adjacent thereto.

[0071] Although the sub-pixel SPXn is shown in the drawings to have a first emission area EMA1 and a second emission area EMA2 having the same size, the present disclosure is not limited thereto. In one or more embodiments, each of the first emission area EMA1 and the second emission area EMA2 of each sub-pixel SPXn may have a different size according to the color or wavelength band of light emitted from the light emitting element ED positioned in each sub-pixel SPXn.

[0072] Each sub-pixel SPXn may further include a sub-region SA positioned in the non-emission region. The sub-region SA of the corresponding sub-pixel SPXn may be positioned above the second emission region EMA2 in the first direction DR1. The first emission region EMA1, the second emission region EMA2, and the sub-region SA may be alternately arranged along the first direction DR1. However, the present disclosure is not limited thereto, and in a plurality of pixels PX, the first emission region EMA1, the second emission region EMA2, and the sub-region SA may have the same Figure 4 The arrangement of different arrangements.

[0073] Since the light emitting element ED is not positioned in the sub-region SA, light may not be emitted from the sub-region SA, but the electrode RME positioned in each sub-pixel SPXn may be partially positioned in the sub-region SA. The electrodes RME of each of the sub-pixels SPX1, SPX2, and SPX3 may be connected to each other and extend in the first direction DR1 in the sub-region SA. For example, in the sub-region SA positioned above the second emission region EMA2 of the first pixel PX1, the first electrode RME1 and the second electrode RME2 of each of the sub-pixels SPX1, SPX2, and SPX3 of the first pixel PX1 may extend and be connected to the first electrode RME1 and the second electrode RME2 of each of the sub-pixels SPX1, SPX2, and SPX3 of the second pixel PX2 positioned on the upper side.

[0074] The bank layer BNL may be around the sub-pixel SPXn, the first emission area EMA1, the second emission area EMA2, and the sub-area SA of each of the first pixel PX1 and the second pixel PX2 (for example, it may surround the sub-pixel SPXn, the first emission area EMA1, the second emission area EMA2, and the sub-area SA of each of the first pixel PX1 and the second pixel PX2). The bank layer BNL may be positioned in the boundary between the sub-pixels SPXn adjacent to each other along the second direction DR2, and may be positioned in the boundary between the first emission area EMA1 and the second emission area EMA2 of each sub-pixel SPXn. The sub-pixels SPXn, the first emission area EMA1, and the second emission area EMA2 of the display device 10 may be distinguished by the arrangement of the bank layer BNL. For example, the bank layer BNL may be around the second emission area EMA2 of the first pixel PX1, the sub-area SA, and the first emission area EMA1 of the second pixel PX2 (for example, it may surround the second emission area EMA2 of the first pixel PX1, the sub-area SA, and the first emission area EMA1 of the second pixel PX2). A detailed description thereof will be given later.

[0075] The bank layer BNL may include a portion extending in the first direction DR1 and a portion extending in the second direction DR2 in a plan view, and may be arranged in a trapezoidal pattern across the entire surface of the display area DPA. The bank layer BNL may be positioned across a boundary of each of the sub-pixels SPXn arranged along the second direction DR2 to distinguish adjacent sub-pixels SPXn.

[0076] Figure 5 is a plan view showing electrodes of a display device according to one or more embodiments. Figure 6 is a plan view showing connection electrodes of a display device according to one or more embodiments. Figure 7 is a schematic cross-sectional view of a display device according to one or more embodiments. Figure 8 is a schematic perspective view of a light emitting element according to one or more embodiments.

[0077] Figure 5 A planar arrangement of electrodes RME ( RME1 and RME2 ) positioned in pixels PX1 and PX2 of the display device 10 is shown. Figure 6 A planar arrangement of connection electrodes CTE ( CTE1 , CTE2 , CTE3 , CTE4 , and CTE5 ) positioned in pixels PX1 and PX2 of the display device 10 is shown.

[0078] Combination Figure 4 Reference Figures 5 to 8 , the display device 10 may include a substrate SUB, a thin film transistor layer TFTL, and a light emitting element layer EML.

[0079] The substrate SUB may be an insulating substrate. The substrate SUB may be made of an insulating material such as glass, quartz, or a polymer resin. In addition, the substrate SUB may be a rigid substrate, or may be a flexible substrate that can be bent, folded, and / or rolled. The substrate SUB may include a display area ( Figure 1 ” DPA ”) and a non-display area (eg, surrounding the display area) around the display area Figure 1 'NDA'), and the display area DPA may include emission areas EMA1 and EMA2 and a non-emission area (the sub-area SA is a part of the non-emission area).

[0080] The thin film transistor layer TFTL may be positioned on the substrate SUB and may include a first metal layer MTL1, a buffer layer BF, an active layer ACTL, a gate insulating layer GI, a second metal layer MTL2, an interlayer insulating layer ILD, a third metal layer MTL3, a protective layer PV, and a via layer VIA.

[0081] The first metal layer MTL1 may include a data line DTL, a first voltage line VL1 and a vertical voltage line VVSL. The data line DTL may be used to transmit a data signal to a source electrode SE of the thin film transistor TFT. The source electrode SE of the thin film transistor TFT may be connected to the data line DTL through a connection electrode CE.

[0082] A high potential voltage (or first power voltage) may be applied to the first voltage line VL1 to be transmitted to the first electrode RME1. The first voltage line VL1 may be connected to the horizontal voltage line HVDL through a contact hole penetrating the buffer layer BF, the gate insulating layer GI, and the interlayer insulating layer ILD, and the horizontal voltage line HVDL may be connected to the first electrode RME1.

[0083] The low potential voltage (or second power voltage) may be applied to the vertical voltage line VVSL to be transmitted to the second electrode RME2. The vertical voltage line VVSL may be connected to the second electrode RME2 through a second voltage line VL2 to be described later.

[0084] The buffer layer BF may be positioned on the first metal layer MTL1 and the substrate SUB. The buffer layer BF may be formed on the substrate SUB to protect the thin film transistor TFT of each pixel PX from moisture penetrating through the substrate SUB (the substrate is susceptible to moisture penetration) and may perform a surface planarization function.

[0085] The active layer ACTL may be positioned on the buffer layer BF. The active layer ACTL may include a drain electrode DE of the thin film transistor TFT, an active region ACT, and a source electrode SE.

[0086] The active area ACT may be positioned to partially overlap the gate electrode GE to be described later in the thickness direction (e.g., the third direction DR3) of the substrate SUB. The active layer ACTL may include polycrystalline silicon, single crystal silicon, an oxide semiconductor, and the like. In one or more embodiments, the active layer ACTL may include polycrystalline silicon. The oxide semiconductor may be an oxide semiconductor containing indium (In). For example, the oxide semiconductor may be at least one of indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium oxide (IGO), indium zinc tin oxide (IZTO), indium gallium tin oxide (IGTO), indium gallium zinc oxide (IGZO), and indium gallium zinc tin oxide (IGZTO).

[0087] Although it is shown in the drawings that one thin film transistor TFT is positioned in the sub-pixel SPXn of the display device 10 , the present disclosure is not limited thereto, and the display device 10 may include a greater number of transistors.

[0088] The gate insulating layer GI is positioned on the active layer ACTL and the buffer layer BF. The gate insulating layer GI can be used as a gate insulating layer of the thin film transistor TFT. Although the gate insulating layer GI is shown in the drawings as being entirely positioned on the buffer layer BF, the present disclosure is not limited thereto. In one or more embodiments, the gate insulating layer GI may be patterned with a gate electrode GE of a second metal layer MTL2 to be described later to be partially positioned between the second metal layer MTL2 and the active layer ACTL.

[0089] The second metal layer MTL2 may be positioned on the gate insulating layer GI. The second metal layer MTL2 may include a gate electrode GE of the thin film transistor TFT. The thin film transistor TFT may be Figure 3 one of the first transistor T1, the second transistor T2 and the third transistor T3.

[0090] The interlayer insulating layer ILD is positioned on the second metal layer MTL2 and the gate insulating layer GI. The interlayer insulating layer ILD serves as an insulating layer between the second metal layer MTL2 and other layers positioned thereon, and may protect the second metal layer MTL2.

[0091] The third metal layer MTL3 may be positioned on the interlayer insulating layer ILD. The third metal layer MTL3 may include a connection electrode CE, a first anode connection electrode ANE1, a horizontal voltage line HVDL, and a second voltage line VL2.

[0092] The connection electrode CE may connect the data line DTL and the source electrode SE of the active layer ACTL. The connection electrode CE may be connected to the data line DTL through a contact hole penetrating the buffer layer BF, the gate insulating layer GI, and the interlayer insulating layer ILD. In addition, the connection electrode CE may be connected to the source electrode SE of the active layer ACTL through a contact hole penetrating the gate insulating layer GI and the interlayer insulating layer ILD.

[0093] The horizontal voltage line HVDL may connect the first voltage line VL1 and the first electrode RME1. A high potential voltage (or a first power voltage) may be applied from the first voltage line VL1 to the horizontal voltage line HVDL. The horizontal voltage line HVDL may be connected to the first voltage line VL1 through a contact hole penetrating the buffer layer BF, the gate insulating layer GI, and the interlayer insulating layer ILD.

[0094] The second voltage line VL2 can connect the vertical voltage line VVSL and the second electrode RME2. The low potential voltage (or the second power voltage) can be applied to the second electrode RME2 through the vertical voltage line VVSL and the second voltage line VL2. The second voltage line VL2 can be connected to the vertical voltage line VVSL through a contact hole penetrating the buffer layer BF, the gate insulating layer GI, and the interlayer insulating layer ILD.

[0095] The protection layer PV may be positioned on the third metal layer MTL3. The protection layer PV may serve as an insulating layer between the third metal layer MTL3 and other layers, and may protect the third metal layer MTL3.

[0096] The buffer layer BF, the gate insulating layer GI, the interlayer insulating layer ILD, and the protective layer PV may be formed of a plurality of inorganic layers stacked in an alternating manner. For example, the buffer layer BF, the gate insulating layer GI, the interlayer insulating layer ILD, and the protective layer PV may be formed as a double layer formed by stacking, or by alternately stacking layers including silicon oxide (SiO x ), Silicon Nitride (SiN x ) and silicon oxynitride (SiO x N y ) are formed of an inorganic layer of at least one of the above-mentioned insulating materials. However, the present disclosure is not limited thereto, and the buffer layer BF, the gate insulating layer GI, the interlayer insulating layer ILD, and the protective layer PV may be formed as a single inorganic layer containing the above-mentioned insulating materials. In addition, in one or more embodiments, the interlayer insulating layer ILD may be made of an organic insulating material such as polyimide (PI).

[0097] The via layer VIA may be positioned on the protective layer PV in the display area DPA. The via layer VIA may include an organic insulating material such as polyimide (PI), and may compensate for a step portion formed by a conductive layer positioned therebelow to flatten the top surface. However, in one or more embodiments, the via layer VIA may be omitted.

[0098] The light emitting element layer EML may be positioned on the via layer VIA. The light emitting element layer EML may include a plurality of electrodes RME (RME1 and RME2), a plurality of bank patterns BP1, BP2, and BP3, a bank layer BNL, a plurality of light emitting elements ED, and a plurality of connection electrodes CTE (CTE1, CTE2, CTE3, CTE4, and CTE5). In addition, the display device 10 may include a plurality of insulating layers PAS1, PAS2, and PAS3.

[0099] The plurality of bank patterns BP1, BP2, and BP3 may be positioned directly on the via layer VIA. The plurality of bank patterns BP1, BP2, and BP3 may include a first bank pattern BP1, a second bank pattern BP2, and a third bank pattern BP3.

[0100] The first dam pattern BP1 may be positioned in the first emission area EMA1 and the second emission area EMA2 of each sub-pixel SPXn. The first dam pattern BP1 may have a shape extending in the first direction DR1 and may be spaced apart from the second dam pattern BP2 and the third dam pattern BP3. The first dam pattern BP1 may form an island pattern having a narrow width across the entire surface of the display area DPA and extending in the first direction DR1 in the first emission area EMA1 and the second emission area EMA2 of each sub-pixel SPXn.

[0101] The second embankment pattern BP2 may be positioned in the first emission area EMA1 and the second emission area EMA2 of each sub-pixel SPXn, and may have a shape extending in the first direction DR1. The second embankment pattern BP2 may be positioned at one side of the first embankment pattern BP1 to be spaced apart from the first embankment pattern BP1. The second embankment pattern BP2 may form an island pattern having a narrow width across the entire surface of the display area DPA and extending in the first direction DR1 in the first emission area EMA1 and the second emission area EMA2 of each sub-pixel SPXn.

[0102] The third embankment pattern BP3 may be positioned in the first emission area EMA1 and the second emission area EMA2 of each sub-pixel SPXn, and may have a shape extending in the first direction DR1. The third embankment pattern BP3 may be positioned at the other side of the first embankment pattern BP1 to be spaced apart from the first embankment pattern BP1. The third embankment pattern BP3 may form an island pattern having a narrow width across the entire surface of the display area DPA and extending in the first direction DR1 in the first emission area EMA1 and the second emission area EMA2 of each sub-pixel SPXn.

[0103] The first dam pattern BP1 is positioned at the center of the first emission area EMA1 and the second emission area EMA2, and the second dam pattern BP2 and the third dam pattern BP3 are spaced apart from each other with the first dam pattern BP1 interposed therebetween. For example, the second dam pattern BP2 may be positioned on the left side of the first dam pattern BP1, and the third dam pattern BP3 may be positioned on the right side of the first dam pattern BP1. The first dam pattern BP1, the second dam pattern BP2, and the third dam pattern BP3 may be positioned alternately along the second direction DR2. The light emitting element ED may be positioned between the first dam pattern BP1 and the second dam pattern BP2 spaced apart from each other and between the second dam pattern BP2 and the third dam pattern BP3 spaced apart from each other.

[0104] The first, second, and third bank patterns BP1, BP2, and BP3 may have the same length in the first direction DR1 and may have the same width measured in the second direction DR2. However, the present disclosure is not limited thereto, and the first, second, and third bank patterns BP1, BP2, and BP3 may have different widths measured in the second direction DR2.

[0105] At least a portion of each of the bank patterns BP1, BP2, and BP3 may protrude relative to the top surface of the via layer VIA. The protruding portions of the bank patterns BP1, BP2, and BP3 may have inclined or curved side surfaces. Unlike shown in the drawings, each of the bank patterns BP1, BP2, and BP3 may have a semicircular shape in a cross-sectional view. The bank patterns BP1, BP2, and BP3 may include an organic insulating material such as polyimide (PI), but are not limited thereto.

[0106] A plurality of electrodes RME of each sub-pixel SPXn of each of the pixels PX1 and PX2 may be positioned on the bank patterns BP1, BP2, and BP3 and the via layer VIA. The plurality of electrodes RME may include a first electrode RME1 and a second electrode RME2. The first electrode RME1 and the second electrode RME2 may extend in a first direction DR1. The first electrode RME1 of the first sub-pixel SPX1 may be positioned between the second electrode RME2 of the first sub-pixel SPX1 and the second electrode RME2 of the second sub-pixel SPX2.

[0107] Each of the first electrode RME1 and the second electrode RME2 may cover an upper surface and an inclined side surface of one of the first dam pattern BP1, the second dam pattern BP2, and the third dam pattern BP3. Therefore, each of the first electrode RME1 and the second electrode RME2 may reflect light emitted from the first light emitting element ED1, the second light emitting element ED2, the third light emitting element ED3, and the fourth light emitting element ED4 upward (in the third direction DR3).

[0108] The first electrode RME1 and the second electrode RME2 may be alignment electrodes for aligning the first light emitting element ED1, the second light emitting element ED2, the third light emitting element ED3, and the fourth light emitting element ED4 in the manufacturing process of the display device 10. The first electrode RME1 may be connected to the horizontal voltage line HVDL of the third metal layer MTL3 through the first contact hole CNT1. The first electrode RME1 may receive a driving voltage or a high potential voltage from the horizontal voltage line HVDL. The second electrode RME2 may be connected to the second voltage line VL2 of the third metal layer MTL3 through the second contact hole CNT2. The second electrode RME2 may receive a low potential voltage from the second voltage line VL2.

[0109] Each of the electrodes RME may include a conductive material having a high reflectivity. For example, the electrode RME may include a metal such as silver (Ag), copper (Cu), and aluminum (Al), and / or may include an alloy containing aluminum (Al), nickel (Ni), lanthanum (La), etc., or a stack of metal layers and / or alloys such as titanium (Ti), molybdenum (Mo), and niobium (Nb). In one or more embodiments, the electrode RME may include a double layer or multiple layers of an alloy containing aluminum (Al) and at least one metal layer containing titanium (Ti), molybdenum (Mo), and / or niobium (Nb) stacked on each other.

[0110] However, it will be understood that the present disclosure is not limited thereto. The electrode RME may also include a transparent conductive material. For example, each of the electrodes RME may include a material such as ITO, IZO and / or ITZO. In one or more embodiments, each of the electrodes RME1 and RME2 may have a structure in which one or more layers of a transparent conductive material and one or more metal layers with high reflectivity are stacked on each other, or may be composed of a single layer including them. For example, each of the electrodes RME may have a stacked structure such as ITO / Ag / ITO, ITO / Ag / IZO or ITO / Ag / ITZO / IZO. The electrode RME may be electrically connected to the light emitting element ED, and may reflect some of the light emitted from the light emitting element ED toward the upper side of the substrate SUB (e.g., in the third direction DR3).

[0111] The first insulating layer PAS1 may be positioned on the front surface of the display area DPA, and may be positioned on the via layer VIA and the plurality of electrodes RME. The first insulating layer PAS1 may protect the plurality of electrodes RME, and may insulate different electrodes RME from each other. For example, since the first insulating layer PAS1 is positioned to cover the electrodes RME before forming the bank layer BNL, the possibility of the electrodes RME being damaged during the process of forming the bank layer BNL may be reduced or prevented. In addition, the first insulating layer PAS1 may also reduce or prevent the light emitting element ED positioned thereon from being damaged by contact with other elements.

[0112] In one or more embodiments, the first insulating layer PAS1 may have a step such that a portion of the upper surface is recessed between the electrodes RME spaced apart from each other in the second direction DR2. The light emitting element ED may be positioned at the step of the upper surface of the first insulating layer PAS1, and a space may be formed between the light emitting element ED and the first insulating layer PAS1.

[0113] The bank layer BNL may be positioned on the first insulating layer PAS1. The bank layer BNL may include a portion extending in the first direction DR1 and a portion extending in the second direction DR2, and may be around each of the sub-pixels SPXn (e.g., may surround each of the sub-pixels SPXn in a plan view). The bank layer BNL may be around the first emission area EMA1, the second emission area EMA2, and the sub-area SA of each of the sub-pixels SPXn (e.g., may surround the first emission area EMA1, the second emission area EMA2, and the sub-area SA of each of the sub-pixels SPXn in a plan view). In addition, the bank layer BNL may be around the outermost periphery of the display area DPA (e.g., may surround the outermost periphery of the display area DPA in a plan view), and may divide the display area DPA and the non-display area NDA. The bank layer BNL is positioned in the entire display area DPA to form a grid pattern, and the area exposed by the bank layer BNL in the display area DPA may be the first emission area EMA1, the second emission area EMA2, and the sub-area SA.

[0114] The bank layer BNL may have a height higher than that of the bank patterns BP1, BP2, and BP3. In one or more embodiments, the top surface of the bank layer BNL may be similar to the top surface of the bank patterns BP1, BP2, and BP3, and the thickness of the bank layer BNL may be equal to or greater than the thickness of the bank patterns BP1, BP2, and BP3. The bank layer BNL may reduce or prevent the possibility of ink overflowing to the adjacent sub-pixel SPXn in the inkjet printing process during the manufacturing process of the display device 10. Similar to the bank patterns BP1, BP2, and BP3, the bank layer BNL may include an organic insulating material such as polyimide.

[0115] A plurality of light emitting elements ED may be positioned in the first emission area EMA1 and the second emission area EMA2. A plurality of light emitting elements ED may be aligned between the first electrode RME1 and the second electrode RME2. A plurality of light emitting elements ED may be positioned in the light emitting element area EDA and may be spaced apart from each other in the first direction DR1 and the second direction DR2. A plurality of light emitting elements ED may have a shape extending in one direction, and both ends thereof may be positioned on different electrodes RME.

[0116] A plurality of light emitting elements ED may be positioned on the first insulating layer PAS1. The light emitting element ED may have a shape extending in one direction, and may be positioned so that the one direction of extension is parallel to the upper surface of the substrate SUB. As will be described later, the light emitting element ED may include a plurality of semiconductor layers positioned along the one direction of extension, and the plurality of semiconductor layers may be positioned sequentially along a direction parallel to the upper surface of the substrate SUB. However, the present disclosure is not limited thereto, and when the light emitting element ED has a different structure, the plurality of semiconductor layers may be positioned in a direction perpendicular to the substrate SUB.

[0117] The light emitting element ED positioned in each sub-pixel SPXn may emit light of different wavelength bands according to the material constituting the semiconductor layer. However, the present disclosure is not limited thereto, and the light emitting element ED arranged in each sub-pixel SPXn may include a semiconductor layer of the same material and emit light of the same color. The light emitting element ED may be electrically connected to the electrode RME and the metal layer below the via layer VIA while being in contact with the connection electrode CTE (CTE1, CTE2, CTE3, CTE4, and CTE5), and may emit light of a specific wavelength band by receiving an electrical signal.

[0118] The plurality of light emitting elements ED may include a first light emitting element ED1, a second light emitting element ED2, a third light emitting element ED3, and a fourth light emitting element ED4. The plurality of first light emitting elements ED1 may be positioned in a first light emitting element region EDA1, the plurality of second light emitting elements ED2 may be positioned in a second light emitting element region EDA2, the plurality of third light emitting elements ED3 may be positioned in a third light emitting element region EDA3, and the plurality of fourth light emitting elements ED4 may be positioned in a fourth light emitting element region EDA4.

[0119] The first and second light emitting element regions EDA1 and EDA2 may be located between the first and second electrodes RME1 and RME2 of the first subpixel SPX1. The third and fourth light emitting element regions EDA3 and EDA4 may be located between the first and second electrodes RME1 and RME2 of the first and second subpixels SPX2.

[0120] The plurality of first light emitting elements ED1, the second light emitting elements ED2, the third light emitting elements ED3, and the fourth light emitting elements ED4 may be aligned between the first electrode RME1 and the second electrode RME2 by an electric field formed by an alignment signal applied to the first electrode RME1 and the second electrode RME2. For example, the plurality of first light emitting elements ED1, the second light emitting elements ED2, the third light emitting elements ED3, and the fourth light emitting elements ED4 may be sprayed onto the first electrode RME1 and the second electrode RME2 by an inkjet printing process, and the plurality of first light emitting elements ED1, the second light emitting elements ED2, the third light emitting elements ED3, and the fourth light emitting elements ED4 dispersed in the ink may be aligned by receiving a dielectrophoretic force of the electric field formed between the first electrode RME1 and the second electrode RME2. Therefore, the plurality of first light emitting elements ED1, the second light emitting elements ED2, the third light emitting elements ED3, and the fourth light emitting elements ED4 may be aligned along the second direction DR2 between the first electrode RME1 and the second electrode RME2.

[0121] The second insulating layer PAS2 may be positioned on a plurality of light emitting elements ED, the first insulating layer PAS1, and the embankment layer BNL. The second insulating layer PAS2 extends in the first direction DR1 between the embankment patterns BP1, BP2, and BP3, and includes a pattern portion positioned on a plurality of light emitting elements ED. The pattern portion may be positioned to partially cover the outer surface (e.g., the peripheral surface or the circumferential surface) of the light emitting element ED, and both sides or both ends of the light emitting element ED may not be covered. The pattern portion may form a linear pattern or an island pattern in each sub-pixel SPXn in a plan view. The pattern portion of the second insulating layer PAS2 may protect the light emitting element ED while fixing the light emitting element ED in the manufacturing process of the display device 10. In addition, the second insulating layer PAS2 may be positioned to fill the space between the light emitting element ED and the first insulating layer PAS1 therebelow. In addition, a portion of the second insulating layer PAS2 may be positioned on the upper portion of the embankment layer BNL and in the sub-region SA.

[0122] A plurality of connection electrodes CTE (CTE1, CTE2, CTE3, CTE4, and CTE5) may be positioned on the first insulating layer PAS1, the second insulating layer PAS2, the plurality of electrodes RME, and the embankment patterns BP1, BP2, and BP3. Each of the plurality of connection electrodes CTE may have a shape extending in one direction and may be spaced apart from each other. Each of the connection electrodes CTE may contact the light emitting element ED and may be electrically connected to the third metal layer MTL3.

[0123] The plurality of connection electrodes CTE may include a first connection electrode CTE1 , a second connection electrode CTE2 , a third connection electrode CTE3 , a fourth connection electrode CTE4 , and a fifth connection electrode CTE5 .

[0124] The first connection electrode CTE1 of the first subpixel SPX1 may be positioned on the first electrode RME1 of the first subpixel SPX1 and may be connected to the first anode connection electrode ANE1 of the third metal layer MTL3 through the third contact hole CNT3. The first connection electrode CTE1 may be connected between the first anode connection electrode ANE1 and one end of the plurality of first light emitting elements ED1. The first connection electrode CTE1 may receive a driving current through the thin film transistor TFT. The first connection electrode CTE1 may supply a driving current to the plurality of first light emitting elements ED1 of the first subpixel SPX1. The first connection electrode CTE1 may correspond to the anode electrodes of the plurality of first light emitting elements ED1, but is not limited thereto.

[0125] The second connection electrode CTE2 may be positioned on the first electrode RME1 and the second electrode RME2 and overlap the first electrode RME1 and the second electrode RME2. A first portion of the second connection electrode CTE2 may be positioned on the second electrode RME2 of the first subpixel SPX1 and extend in the first direction DR1. A second portion of the second connection electrode CTE2 may extend from a lower side of the first portion and may be positioned on the first electrode RME1 of the first subpixel SPX1.

[0126] The second connection electrode CTE2 may be connected between the other ends of the plurality of first light emitting elements ED1 and one ends of the plurality of second light emitting elements ED2. The second connection electrode CTE2 may correspond to the cathode electrodes of the plurality of first light emitting elements ED1, but is not limited thereto. The second connection electrode CTE2 may correspond to the anode electrodes of the plurality of second light emitting elements ED2, but is not limited thereto.

[0127] The third connection electrode CTE3 may be positioned on the first electrode RME1 and the second electrode RME2 and overlap the first electrode RME1 and the second electrode RME2. A first portion of the third connection electrode CTE3 may be positioned on the second electrode RME2 of the first sub-pixel SPX1 and extend in the first direction DR1. A second portion of the third connection electrode CTE3 may be positioned on the first electrode RME1 of the first sub-pixel SPX1 and may be positioned to the right of the first portion.

[0128] The third connection electrode CTE3 may be connected between the other end of the second light emitting elements ED2 and one end of the third light emitting elements ED3. The third connection electrode CTE3 may correspond to cathode electrodes of the second light emitting elements ED2 and to anode electrodes of the third light emitting elements ED3, but is not limited thereto.

[0129] The fourth connection electrode CTE4 may be positioned on the first electrode RME1 of the first subpixel SPX1 and the second electrode RME2 of the second subpixel SPX2, and overlap the first electrode RME1 of the first subpixel SPX1 and the second electrode RME2 of the second subpixel SPX2. A first portion of the fourth connection electrode CTE4 may be positioned on the second electrode RME2 of the second subpixel SPX2 and extend in the first direction DR1. A second portion of the fourth connection electrode CTE4 may extend from an upper side of the first portion (an upper side in the first direction DR1) and may be positioned on the first electrode RME1 of the first subpixel SPX1.

[0130] The fourth connection electrode CTE4 may be connected between the other end of the plurality of third light emitting elements ED3 and one end of the plurality of fourth light emitting elements ED4. The fourth connection electrode CTE4 may correspond to cathode electrodes of the plurality of third light emitting elements ED3 and may correspond to anode electrodes of the plurality of fourth light emitting elements ED4, but is not limited thereto.

[0131] The fifth connection electrode CTE5 may be connected between the other ends of the plurality of fourth light emitting elements ED4 and the second voltage line VL2. The fifth connection electrode CTE5 may be positioned on the second electrode RME2 of the second sub-pixel SPX2 and extend in the first direction DR1. The fifth connection electrode CTE5 may be connected to the second voltage line VL2 of the third metal layer MTL3 through the fourth contact hole CNT4. The fifth connection electrode CTE5 may correspond to the cathode electrodes of the plurality of fourth light emitting elements ED4. The fifth connection electrode CTE5 may receive a low potential voltage through the second voltage line VL2. The fifth connection electrode CTE5 of the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 may be formed integrally, but is not limited thereto.

[0132] In the second sub-pixel SPX2, the first connection electrode CTE1 may be positioned on the first electrode RME1 of the second sub-pixel SPX2, and may be connected to the first anode connection electrode of the third metal layer MTL3 (e.g., the first anode connection electrode ANE1 positioned in the second sub-pixel SPX2) through the fifth contact hole CNT5. The first connection electrode CTE1 may be connected between the first anode connection electrode and one end of the plurality of first light-emitting elements ED1. The first connection electrode CTE1 may receive a driving current through the thin film transistor TFT. The first connection electrode CTE1 may supply a driving current to the plurality of first light-emitting elements ED1 of the second sub-pixel SPX2.

[0133] In the third sub-pixel SPX3, the first connection electrode CTE1 may be positioned on the first electrode RME1 of the third sub-pixel SPX3, and may be connected to the first anode connection electrode of the third metal layer MTL3 (e.g., the first anode connection electrode ANE1 positioned in the third sub-pixel SPX3) through the sixth contact hole CNT6. The first connection electrode CTE1 may be connected between the first anode connection electrode and one end of the plurality of first light emitting elements ED1. The first connection electrode CTE1 may receive a driving current through the thin film transistor TFT. The first connection electrode CTE1 may supply a driving current to the plurality of first light emitting elements ED1 of the third sub-pixel SPX3.

[0134] The plurality of connection electrodes CTE may include a conductive material. For example, the connection electrode CTE may include ITO, IZO, ITZO, aluminum (Al), etc. For example, the connection electrode CTE may include a transparent conductive material, and light emitted from the light emitting element ED may be transmitted through the connection electrode CTE to be emitted.

[0135] The third insulating layer PAS3 is positioned on the plurality of connection electrodes CTE and the second insulating layer PAS2. The third insulating layer PAS3 may be positioned entirely on the second insulating layer PAS2 to cover the plurality of connection electrodes CTE. The third insulating layer PAS3 may be positioned entirely on the via layer VIA. The third insulating layer PAS3 may insulate the plurality of connection electrodes CTE from each other so that they do not contact each other.

[0136] Each of the above-mentioned first insulating layer PAS1, second insulating layer PAS2 and third insulating layer PAS3 may include an inorganic insulating material and / or an organic insulating material. For example, each of the first insulating layer PAS1, second insulating layer PAS2 and third insulating layer PAS3 may include an inorganic insulating material, or the first insulating layer PAS1 and third insulating layer PAS3 may include an inorganic insulating material and the second insulating layer PAS2 may include an organic insulating material. Each of the first insulating layer PAS1, second insulating layer PAS2 and third insulating layer PAS3 or at least one of the first insulating layer PAS1, second insulating layer PAS2 and third insulating layer PAS3 may be formed in a structure in which insulating layers are alternately or repeatedly stacked on each other.

[0137] Each of the first insulating layer PAS1, the second insulating layer PAS2, and the third insulating layer PAS3 may include silicon oxide (SiO x ), Silicon Nitride (SiN x ) and silicon oxynitride (SiO x N y). The first insulating layer PAS1, the second insulating layer PAS2 and the third insulating layer PAS3 may include the same material. Optionally, some of the first insulating layer PAS1, the second insulating layer PAS2 and the third insulating layer PAS3 may include the same material and the other insulating layers may include different materials, or they may include different materials.

[0138] Reference Figure 8 , the light-emitting element ED is a particle element and may have a rod-like or cylindrical shape with a suitable aspect ratio (e.g., a predetermined aspect ratio). The light-emitting element ED may have a size ranging from nanometer scale (1 nm to 1 μm) to micrometer scale (1 μm to 1 mm). According to one or more embodiments, both the diameter and the length of the light-emitting element ED may be nanometer scale or micrometer scale. In one or more embodiments, the diameter of the light-emitting element ED may be nanometer scale, while the length of the light-emitting element ED may be micrometer scale. In one or more embodiments, the diameter and / or length of some of the light-emitting elements ED may be nanometer scale, while the diameter and / or length of some other of the light-emitting elements ED may be micrometer scale.

[0139] According to one or more embodiments of the present disclosure, the light emitting element ED may be an inorganic light emitting diode. For example, the light emitting element ED may include a semiconductor layer doped with impurities of a conductive type (e.g., p-type or n-type). The semiconductor layer may emit light of a specific wavelength band by transmitting an electrical signal applied from an external power source.

[0140] The light emitting element ED according to one or more embodiments may include a first semiconductor layer 31, a light emitting layer 36, a second semiconductor layer 32, and an electrode layer 37 sequentially stacked in a longitudinal direction. The light emitting element ED may further include an insulating layer 38 around (e.g., surrounding the outer surfaces (e.g., outer peripheral surfaces or circumferential surfaces) of the first semiconductor layer 31, the second semiconductor layer 32, and the light emitting layer 36).

[0141] The first semiconductor layer 31 may be an n-type semiconductor. When the light emitting element ED emits light in the blue wavelength band, the first semiconductor layer 31 may include Al x Ga y In (1-x-y)The first semiconductor layer 31 may be a semiconductor material having a component ratio of 0.0447 W to 0.082 W (wherein 0≤x≤1, 0≤y≤1, and 0≤x+y≤1). For example, it may be at least one of n-type doped AlGaInN, GaN, AlGaN, InGaN, AlN, and InN. The first semiconductor layer 31 may be doped with an n-type dopant, and the n-type dopant may be Si, Ge, Sn, Se, or the like. For example, the first semiconductor layer 31 may be n-GaN doped with n-type Si. The length of the first semiconductor layer 31 may be in the range of about 1.5 μm to 5 μm, but is not limited thereto.

[0142] The second semiconductor layer 32 is positioned on the light emitting layer 36 to be described later. The second semiconductor layer 32 may be a p-type semiconductor. When the light emitting element ED emits light in the blue or green wavelength band, the second semiconductor layer 32 may include Al x Ga y In (1-x-y) The second semiconductor layer 32 may be a semiconductor material having a component ratio of 1:1 to 1:1 N (where 0≤x≤1, 0≤y≤1, and 0≤x+y≤1). For example, it may be at least one of p-doped AlGaInN, GaN, AlGaN, InGaN, AlN, and InN. The second semiconductor layer 32 may be doped with a p-type dopant, and the p-type dopant may be Mg, Zn, Ca, Ba, or the like. For example, the second semiconductor layer 32 may be p-GaN doped with p-type Mg. The length of the second semiconductor layer 32 may be in the range of about 0.05 μm to 0.10 μm, but is not limited thereto.

[0143] Although the first semiconductor layer 31 and the second semiconductor layer 32 are shown in the drawings as being constructed as one layer, the present disclosure is not limited thereto. Depending on the material of the light emitting layer 36, the first semiconductor layer 31 and the second semiconductor layer 32 may also include a greater number of layers (such as a cladding layer or a tensile strain barrier reduction (TSBR) layer).

[0144] The light emitting layer 36 is positioned between the first semiconductor layer 31 and the second semiconductor layer 32. The light emitting layer 36 may include a material having a single quantum well structure or a multi-quantum well structure. When the light emitting layer 36 includes a material having a multi-quantum well structure, a plurality of quantum layers and well layers may be alternately stacked. The light emitting layer 36 may emit light by recombination of electron-hole pairs according to an electrical signal applied through the first semiconductor layer 31 and the second semiconductor layer 32. When the light emitting layer 36 emits light in a blue band, the light emitting layer 36 may include a material such as AlGaN or AlGaInN. For example, when the light emitting layer 36 has a structure in which quantum layers and well layers are alternately stacked as a multi-quantum well structure, the quantum layers may include materials such as AlGaN and / or AlGaInN, and the well layers may include materials such as GaN and / or AlInN. For example, as described above, the light emitting layer 36 may include AlGaInN as a quantum layer and AlInN as a well layer, and the light emitting layer 36 may emit blue light having a central band of about 450nm to about 495nm.

[0145] However, the present disclosure is not limited thereto, and the light emitting layer 36 may have a structure in which a semiconductor material having a large energy band gap and a semiconductor material having a small energy band gap are alternately stacked, and may include other III- to V-group semiconductor materials according to the wavelength band of the emitted light. The light emitted by the light emitting layer 36 is not limited to light in the blue wavelength band, but in some cases light in the red wavelength band or the green wavelength band may also be emitted. The length of the light emitting layer 36 may have a range of about 0.05 μm to about 0.10 μm, but is not limited thereto.

[0146] In one or more embodiments, light emitted from the light emitting layer 36 may be emitted to both side surfaces in the longitudinal direction and the outer surface of the light emitting element ED. Directivity of light emitted from the light emitting layer 36 is not limited to one direction.

[0147] The electrode layer 37 may be an ohmic contact electrode. However, the present disclosure is not limited thereto, and it may be a Schottky contact electrode. The light emitting element ED may include at least one electrode layer 37. Although Figure 8 It is shown that the light emitting element ED includes one electrode layer 37, but the present disclosure is not limited thereto. In some cases, the light emitting element ED may include a greater number of electrode layers 37, or the electrode layer 37 may be omitted. Even if the number of electrode layers 37 is different or the light emitting element further includes other structures, the following description of the light emitting element ED may be equally applied.

[0148] In the display device 10 according to one or more embodiments, when the light emitting element ED is electrically connected to the electrode or the contact electrode, the electrode layer 37 can reduce the resistance between the light emitting element ED and the electrode or the contact electrode. The electrode layer 37 may include a conductive metal. For example, the electrode layer 37 may include at least one of aluminum (Al), titanium (Ti), indium (In), gold (Au), silver (Ag), ITO, IZO, and ITZO. In addition, the electrode layer 37 may include a semiconductor material doped with n-type or p-type. The electrode layer 37 may include the same material or may include different materials, but is not limited thereto.

[0149] The insulating layer 38 is arranged around the outer surfaces (e.g., the peripheral surface or the circumferential surface) of the above-mentioned multiple semiconductor layers and electrode layers (e.g., arranged to surround the outer surfaces (e.g., the peripheral surface or the circumferential surface) of the above-mentioned multiple semiconductor layers and electrode layers. For example, the insulating layer 38 can be arranged around the outer surface (e.g., the peripheral surface or the circumferential surface) of at least the light-emitting layer 36 (arranged to surround the outer surface (e.g., the peripheral surface or the circumferential surface) of at least the light-emitting layer 36, and the light-emitting element ED can be elongated in one direction. The insulating layer 38 can play a role in protecting the member. The insulating layer 38 can be formed around the side surface of the member (e.g., formed to surround the side surface of the member) so that both ends of the light-emitting element ED in the longitudinal direction are exposed.

[0150] Although the insulating layer 38 is shown in the drawings to extend in the longitudinal direction of the light emitting element ED to cover the area from the side surface of the first semiconductor layer 31 to the side surface of the electrode layer 37, the present disclosure is not limited thereto. The insulating layer 38 may cover only the outer surfaces (e.g., the peripheral surface or the circumferential surface) of the light emitting layer 36 and some semiconductor layers, or may cover only a portion of the outer surface (e.g., the peripheral surface or the circumferential surface) of the electrode layer 37 and the outer surface (e.g., the peripheral surface or the circumferential surface) of the light emitting layer 36 to partially expose the outer surface (e.g., the peripheral surface or the circumferential surface) of the electrode layer 37. In addition, in the cross-sectional view, the insulating layer 38 may have a rounded top surface in a region adjacent to at least one end of the light emitting element ED. The thickness of the insulating layer 38 may have a range of about 10 nm to about 1.0 μm, but is not limited thereto. In one or more embodiments, the thickness of the insulating layer 38 may be about 40 nm.

[0151] The insulating layer 38 may include a material having insulating properties (such as silicon oxide (SiO x ), Silicon Nitride (SiN x ), silicon oxynitride (SiO x N y ), aluminum nitride (AlN) and / or aluminum oxide (Al 2 O 3)). Although the insulating layer 38 is shown in the drawings as being formed as a single layer, the present disclosure is not limited thereto. In one or more embodiments, the insulating layer 38 may be formed as a multilayer structure in which a plurality of layers are stacked. Therefore, the possibility of an electrical short circuit that may occur when the light emitting layer 36 is in direct contact with an electrode that transmits an electrical signal to the light emitting element ED can be reduced or prevented. In addition, since the insulating layer 38 covers the light emitting layer 36 to protect the outer surface (e.g., the outer peripheral surface or the circumferential surface) of the light emitting element ED, the degradation of the light emitting efficiency can be prevented or reduced.

[0152] In addition, the insulating layer 38 may have a surface-treated outer surface (e.g., an outer peripheral surface or a circumferential surface). The light-emitting elements ED may be aligned in such a manner that the ink in which the light-emitting elements ED are dispersed is sprayed on the electrode. Here, the surface of the insulating layer 38 may be treated in a hydrophobic or hydrophilic manner to keep the light-emitting elements ED in a dispersed state without agglomerating with other light-emitting elements ED adjacent to the ink. For example, the insulating layer 38 may be surface-treated on its outer surface (e.g., an outer peripheral surface or a circumferential surface) with a material such as stearic acid and 2,3-naphthalene dicarboxylic acid.

[0153] Fig. 9 is a plan view schematically showing electrodes, a bank layer, and a light emitting element of a display device according to one or more embodiments. Fig.10 is a plan view schematically showing a connection electrode, a bank layer, and a light emitting element of a display device according to one or more embodiments. Fig.11 is a plan view illustrating a connection electrode and a current flow of a light emitting element of a display device according to one or more embodiments. Fig.12 is a plan view illustrating a connection electrode and a current flow of a light emitting element of a display device according to one or more embodiments.

[0154] Fig. 9 and Fig.10 A first sub-pixel SPX1 of a first pixel PX1 and a first sub-pixel SPX1 of a second pixel PX2 are each shown.

[0155] Reference Fig. 9 and Fig.10 , the first pixel PX1 and the second pixel PX2 may be positioned along the first direction DR1. The first subpixel SPX1 of the first pixel PX1 and the first subpixel SPX1 of the second pixel PX2 may be positioned adjacent to each other in the first direction DR1. For example, the first subpixel SPX1 of the second pixel PX2 may be positioned above the first subpixel SPX1 of the first pixel PX1.

[0156] The first and second electrodes RME1 and RME2 may extend in the first direction DR1 to form a first subpixel SPX1 of the first pixel PX1 and a first subpixel SPX1 of the second pixel PX2 , respectively.

[0157] The bank layer BNL may be arranged in a grid shape (or a matrix shape) and divide the first emission area EMA1, the second emission area EMA2, and the sub area SA in each of the first subpixel SPX1 of the first pixel PX1 and the first subpixel SPX2 of the second pixel PX2.

[0158] The bank layer BNL may include first and second extending portions VBN1 and VBN2 extending in the first direction DR1 and spaced apart from each other, and may include first and second connecting portions HBN1 and HBN2 connecting the first and second extending portions VBN1 and VBN2 .

[0159] The first extension portion VBN1 and the second extension portion VBN2 may extend in the first direction DR1 and may be spaced apart from each other in the second direction DR2. The first extension portion VBN1 may be positioned at one side of the first subpixel SPX1 of the first pixel PX1 and the first subpixel SPX1 of the second pixel PX2, and the second extension portion VBN2 may be positioned at the other side of the first subpixel SPX1 of the first pixel PX1 and the first subpixel SPX1 of the second pixel PX2. For example, the first extension portion VBN1 may be positioned at the left side of the first subpixel SPX1 of the first pixel PX1 and the first subpixel SPX1 of the second pixel PX2, and the second extension portion VBN2 may be positioned at the right side of the first subpixel SPX1 of the first pixel PX1 and the first subpixel SPX1 of the second pixel PX2.

[0160] The first connection portion HBN1 and the second connection portion HBN2 may extend in the second direction DR2 to connect the first extension portion VBN1 and the second extension portion VBN2. The first connection portion HBN1 and the second connection portion HBN2 may be spaced apart from each other in the first direction DR1. The first connection portion HBN1 may be positioned on the first sub-pixel SPX1 of the first pixel PX1, and the second connection portion HBN2 may be positioned on the first sub-pixel SPX1 of the second pixel PX2. The first connection portion HBN1 and the second connection portion HBN2 may overlap and intersect the first electrode RME1 and the second electrode RME2, respectively.

[0161] The bank layer BNL may be around the first emission area EMA1, the second emission area EMA2, and the sub-area SA through the first extension portion VBN1, the second extension portion VBN2, the first connection portion HBN1, and the second connection portion HBN2 (e.g., may surround the first emission area EMA1, the second emission area EMA2, and the sub-area SA through the first extension portion VBN1, the second extension portion VBN2, the first connection portion HBN1, and the second connection portion HBN2 in a plan view). For example, the first sub-pixel SPX1 of the first pixel PX1 may be divided into the first emission area EMA1 and the second emission area EMA2 through the first extension portion VBN1, the second extension portion VBN2, and the first connection portion HBN1. The first emission area EMA1 of the first sub-pixel SPX1 of the first pixel PX1 may be positioned below the first connection portion HBN1 (e.g., in a direction opposite to the first direction DR1), and the second emission area EMA2 of the first sub-pixel SPX1 of the first pixel PX1 may be positioned above the first connection portion HBN1 (e.g., in the first direction DR1). The first connection portion HBN1 of the bank layer BNL may be positioned between the first emission area EMA1 and the second emission area EMA2 of the first subpixel SPX1 of the first pixel PX1.

[0162] The first subpixel SPX1 of the second pixel PX2 may be divided into a first emission area EMA1 and a second emission area EMA2 by the first extension portion VBN1, the second extension portion VBN2, and the second connection portion HBN2. The first emission area EMA1 of the first subpixel SPX1 of the second pixel PX2 may be positioned below the second connection portion HBN2 (e.g., in a direction opposite to the first direction DR1), and the second emission area EMA2 of the first subpixel SPX1 of the second pixel PX2 may be positioned above the second connection portion HBN2 (e.g., in the first direction DR1). The second connection portion HBN2 of the bank layer BNL may be positioned between the first emission area EMA1 and the second emission area EMA2 of the first subpixel SPX1 of the second pixel PX2.

[0163] The bank layer BNL may be around the second emission area EMA2 of the first subpixel SPX1 of the first pixel PX1 and the first emission area EMA1 of the first subpixel SPX1 of the second pixel PX2 (for example, may surround the second emission area EMA2 of the first subpixel SPX1 of the first pixel PX1 and the first emission area EMA1 of the first subpixel SPX1 of the second pixel PX2 in a plan view). The first extension portion VBN1, the second extension portion VBN2, the first connection portion HBN1 and the second connection portion HBN2 of the bank layer BNL may be around the second emission area EMA2 and the subarea SA of the first subpixel SPX1 of the first pixel PX1 and the first emission area EMA1 of the first subpixel SPX1 of the second pixel PX2 (for example, may surround the second emission area EMA2 and the subarea SA of the first subpixel SPX1 of the first pixel PX1 and the first emission area EMA1 of the first subpixel SPX1 of the second pixel PX2 in a plan view). The sub-area SA of the first sub-pixel SPX1 of the first pixel PX1 may be positioned between the second emission area EMA2 of the first sub-pixel SPX1 of the first pixel PX1 and the first emission area EMA1 of the first sub-pixel SPX1 of the second pixel PX2 .

[0164] A plurality of light emitting elements ED may be positioned in the first subpixel SPX1 of the first pixel PX1 and the first subpixel SPX2 of the second pixel PX2.

[0165] In the first sub-pixel SPX1 of the first pixel PX1, the plurality of light-emitting elements ED may include a first light-emitting element ED1 and a fourth light-emitting element ED4 positioned in the second emission area EMA2, and a second light-emitting element ED2 and a third light-emitting element ED3 positioned in the first emission area EMA1. The first light-emitting element ED1, the second light-emitting element ED2, the third light-emitting element ED3, and the fourth light-emitting element ED4 do not overlap with the bank layer BNL. For example, the first light-emitting element ED1, the second light-emitting element ED2, the third light-emitting element ED3, and the fourth light-emitting element ED4 do not overlap with the first connection portion HBN1 that crosses the first sub-pixel SPX1 in the second direction DR2. The first light-emitting element ED1 and the fourth light-emitting element ED4 may be positioned on one side (e.g., in the first direction DR1) relative to the first connection portion HBN1, and the second light-emitting element ED2 and the third light-emitting element ED3 may be positioned on the other side (e.g., in a direction opposite to the first direction DR1) relative to the first connection portion HBN1.

[0166] In the first sub-pixel SPX1 of the second pixel PX2, the plurality of light-emitting elements ED may include a first light-emitting element ED1 and a fourth light-emitting element ED4 positioned in the second emission area EMA2, and may include a second light-emitting element ED2 and a third light-emitting element ED3 positioned in the first emission area EMA1. The first light-emitting element ED1, the second light-emitting element ED2, the third light-emitting element ED3, and the fourth light-emitting element ED4 do not overlap with the bank layer BNL. For example, the first light-emitting element ED1, the second light-emitting element ED2, the third light-emitting element ED3, and the fourth light-emitting element ED4 do not overlap with the second connection portion HBN2 that crosses the first sub-pixel SPX1 in the second direction DR2. The first light-emitting element ED1 and the fourth light-emitting element ED4 may be positioned on one side (e.g., in the first direction DR1) relative to the second connection portion HBN2, and the second light-emitting element ED2 and the third light-emitting element ED3 may be positioned on the other side (e.g., in a direction opposite to the first direction DR1) relative to the second connection portion HBN2.

[0167] The bank layer BNL may be around the first light emitting element ED1 and the fourth light emitting element ED4 of the first sub-pixel SPX1 of the first pixel PX1 and the second light emitting element ED2 and the third light emitting element ED3 of the first sub-pixel SPX1 of the second pixel PX2 (for example, may surround the first light emitting element ED1 and the fourth light emitting element ED4 of the first sub-pixel SPX1 of the first pixel PX1 and the second light emitting element ED2 and the third light emitting element ED3 of the first sub-pixel SPX1 of the second pixel PX2 in a plan view). For example, the first extension portion VBN1, the second extension portion VBN2, the first connection portion HBN1, and the second connection portion HBN2 of the bank layer BNL may be around the first light emitting element ED1 and the fourth light emitting element ED4 of the first sub-pixel SPX1 of the first pixel PX1 and the second light emitting element ED2 and the third light emitting element ED3 of the first sub-pixel SPX1 of the second pixel PX2 (for example, may surround the first light emitting element ED1 and the fourth light emitting element ED4 of the first sub-pixel SPX1 of the first pixel PX1 and the second light emitting element ED2 and the third light emitting element ED3 of the first sub-pixel SPX1 of the second pixel PX2 in a plan view).

[0168] A plurality of connection electrodes CTE may be positioned on the first subpixel SPX1 of the first pixel PX1 and the first subpixel SPX1 of the second pixel PX2. The first connection electrode CTE1, the second connection electrode CTE2, the third connection electrode CTE3, the fourth connection electrode CTE4, and the fifth connection electrode CTE5 may be positioned in each of the first subpixel SPX1 of the first pixel PX1 and the first subpixel SPX1 of the second pixel PX2.

[0169] In the first sub-pixel SPX1 of the first pixel PX1, the first connection electrode CTE1 may be positioned at an upper side (e.g., in the first direction DR1) relative to the first connection portion HBN1 of the bank layer BNL. The first connection electrode CTE1 does not overlap with the first connection portion HBN1 of the bank layer BNL. The second connection electrode CTE2 may extend in the first direction DR1 to cross and overlap with the first connection portion HBN1 of the bank layer BNL. The third connection electrode CTE3 may be positioned at a lower side (e.g., in a direction opposite to the first direction DR1) relative to the first connection portion HBN1 of the bank layer BNL. The third connection electrode CTE3 does not overlap with the first connection portion HBN1 of the bank layer BNL. The fourth connection electrode CTE4 may extend in the first direction DR1 to cross and overlap with the first connection portion HBN1 of the bank layer BNL. The fifth connection electrode CTE5 may be positioned at an upper side (e.g., in the first direction DR1) relative to the first connection portion HBN1 of the bank layer BNL. The fifth connection electrode CTE5 does not overlap with the first connection portion HBN1 of the bank layer BNL.

[0170] In the first sub-pixel SPX1 of the second pixel PX2, the first connection electrode CTE1 may be positioned at the upper side (for example, in the first direction DR1) relative to the second connection portion HBN2 of the bank layer BNL. The first connection electrode CTE1 does not overlap with the second connection portion HBN2 of the bank layer BNL. The second connection electrode CTE2 may extend in the first direction DR1 to cross and overlap with the second connection portion HBN2 of the bank layer BNL. The third connection electrode CTE3 may be positioned at the lower side (for example, in the direction opposite to the first direction DR1) relative to the second connection portion HBN2 of the bank layer BNL. The third connection electrode CTE3 does not overlap with the second connection portion HBN2 of the bank layer BNL. The fourth connection electrode CTE4 may extend in the first direction DR1 to cross and overlap with the second connection portion HBN2 of the bank layer BNL. The fifth connection electrode CTE5 may be positioned at the upper side (for example, in the first direction DR1) relative to the second connection portion HBN2 of the bank layer BNL. The fifth connection electrode CTE5 does not overlap with the second connection portion HBN2 of the bank layer BNL.

[0171] The bank layer BNL may be around the first connection electrode CTE1, a portion of the second connection electrode CTE2, a portion of the fourth connection electrode CTE4, and the fifth connection electrode CTE5 of the first subpixel SPX1 of the first pixel PX1 (for example, may surround the first connection electrode CTE1, a portion of the second connection electrode CTE2, a portion of the fourth connection electrode CTE4, and the fifth connection electrode CTE5 of the first subpixel SPX1 of the first pixel PX1 in a plan view). For example, the first extension portion VBN1, the second extension portion VBN2, the first connection portion HBN1, and the second connection portion HBN2 of the bank layer BNL may be around the first connection electrode CTE1, a portion of the second connection electrode CTE2, a portion of the fourth connection electrode CTE4, and the fifth connection electrode CTE5 of the first subpixel SPX1 of the first pixel PX1 (for example, may surround the first connection electrode CTE1, a portion of the second connection electrode CTE2, a portion of the fourth connection electrode CTE4, and the fifth connection electrode CTE5 of the first subpixel SPX1 of the first pixel PX1 in a plan view).

[0172] In addition, the bank layer BNL may be around a portion of the second connection electrode CTE2, the third connection electrode CTE3, and a portion of the fourth connection electrode CTE4 of the first sub-pixel SPX1 of the second pixel PX2 (for example, may surround a portion of the second connection electrode CTE2, the third connection electrode CTE3, and a portion of the fourth connection electrode CTE4 of the first sub-pixel SPX1 of the second pixel PX2 in a plan view). For example, the first extension portion VBN1, the second extension portion VBN2, the first connection portion HBN1, and the second connection portion HBN2 of the bank layer BNL may be around a portion of the second connection electrode CTE2, the third connection electrode CTE3, and a portion of the fourth connection electrode CTE4 of the first sub-pixel SPX1 of the second pixel PX2 (for example, may surround a portion of the second connection electrode CTE2, the third connection electrode CTE3, and a portion of the fourth connection electrode CTE4 of the first sub-pixel SPX1 of the second pixel PX2 in a plan view).

[0173] In the display device 10 according to one or more embodiments, the light emitting elements ED may be connected in series through the connection electrodes CTE to emit light.

[0174] Reference Fig.11, the first light emitting element ED1 may emit light by a driving current applied through the first connection electrode CTE1 connected to one end and the second connection electrode CTE2 connected to the other end. The first connection electrode CTE1 may be used as an anode electrode for supplying a driving current to the first light emitting element ED1, and the second connection electrode CTE2 may be used as a cathode electrode. The second light emitting element ED2 may emit light by a driving current applied through the second connection electrode CTE2 connected to one end and the third connection electrode CTE3 connected to the other end. The second connection electrode CTE2 may be used as an anode electrode for supplying a driving current to the second light emitting element ED2, and the third connection electrode CTE3 may be used as a cathode electrode. The third light emitting element ED3 may emit light by a driving current applied through the third connection electrode CTE3 connected to one end and the fourth connection electrode CTE4 connected to the other end. The third connection electrode CTE3 may be used as an anode electrode for supplying a driving current to the third light emitting element ED3, and the fourth connection electrode CTE4 may be used as a cathode electrode. The fourth light emitting element ED4 may emit light by a driving current applied through the fourth connection electrode CTE4 connected to one end and the fifth connection electrode CTE5 connected to the other end. The fourth connection electrode CTE4 may function as an anode electrode for supplying a driving current to the fourth light emitting element ED4 , and the fifth connection electrode CTE5 may function as a cathode electrode.

[0175] According to one or more embodiments, the bank layer BNL may be around the second emission area EMA2 and sub-area SA of the first pixel PX1 and the first emission area EMA1 of the second pixel PX2 (e.g., may surround the second emission area EMA2 and sub-area SA of the first pixel PX1 and the first emission area EMA1 of the second pixel PX2).

[0176] The light-emitting element ED may be sprayed (or applied) in the form of ink to the region separated by the bank layer BNL by an inkjet printing process. The solvent and the light-emitting element ED are included in the ink, and the possibility that the light-emitting element ED is not included in the ink is very low. If there is no light-emitting element ED in the ink, the current flow between the connection electrodes CTE cannot be achieved through the light-emitting element ED, and driving defects (e.g., black spots) may occur.

[0177] The bank layer BNL may divide a region including a portion of the first sub-pixel SPX1 of the first pixel PX1 and a portion of the first sub-pixel SPX1 of the second pixel PX2 to form a region where ink is ejected.

[0178] like Fig.12As shown in , the following may occur: the light emitting element ED exists in the ink in the first emission area EMA1 partitioned to be ejected into the second pixel PX2, and the light emitting element ED does not exist in the ink in the second emission area EMA2 partitioned to be ejected into the second pixel PX2. In this case, since the light emitting element ED does not exist in the second emission area EMA2 of the second pixel PX2, the driving current applied to the first connection electrode CTE1 does not flow. Therefore, the light emitting element ED positioned in the first emission area EMA1 of the second pixel PX2 is not connected in series, and therefore does not emit light.

[0179] On the other hand, since the light emitting element ED is positioned in the first emission area EMA1 and the second emission area EMA2 of the first pixel PX1, the first pixel PX1 can emit light normally. That is, in the area where the first emission area EMA1 of the second pixel PX2 and the second emission area EMA2 of the first pixel PX1 are separated, the second emission area EMA2 of the first pixel PX1 can emit light. Therefore, since light is emitted from one unit (e.g., a light emitting unit) of light separated by the bank layer BNL, the occurrence of dark spots can be prevented or reduced.

[0180] In the display device 10 according to one or more embodiments, the sub-pixels SPXn positioned in the first direction DR1 may all emit light of the same color, and the bank layer BNL may be formed to respectively surround some of the sub-pixels positioned adjacent to the first direction DR1. Therefore, even if a defect occurs because the light emitting element ED is not positioned in one or more of the sub-pixels SPXn, generation of dark spots may be prevented or reduced by emitting light from a sub-pixel above or below the corresponding sub-pixel SPXn.

[0181] Fig.13 is a plan view showing a connection electrode, a bank layer, and a light emitting element of a display device according to one or more embodiments. Fig.14 is a plan view illustrating a connection electrode and a current flow of a light emitting element of a display device according to one or more embodiments.

[0182] Reference Fig.13 and Fig.14 , the corresponding one or more embodiments are different from the above-mentioned embodiments in that the number and shape of the connection electrodes CTE are different. Hereinafter, the description repeated with the above-mentioned embodiments will be omitted, and the differences will be described.

[0183] The plurality of connection electrodes CTE may include first, second and third connection electrodes CTE1, CTE2 and CTE3. Although the arrangement of the connection electrodes CTE is described using the first subpixel SPX1 of the first pixel PX1, it will be noted that the connection electrodes CTE of the first subpixel SPX1 of the second pixel PX2 have the same arrangement.

[0184] The first connection electrode CTE1 may extend in the first direction DR1 and may cross and overlap the first connection portion HBN1 of the bank layer BNL. The first connection electrode CTE1 may be positioned across the first emission area EMA1 and the second emission area EMA2 of the first subpixel SPX1. The first connection electrode CTE1 may supply a driving current to the first light emitting element ED1 positioned in the first light emitting element area EDA1 and the second light emitting element ED2 positioned in the second light emitting element area EDA2.

[0185] The second connection electrode CTE2 may extend in a direction opposite to the first direction DR1, may be bent in the second direction DR2 and may extend in the first direction DR1 again. The second connection electrode CTE2 may be positioned in a shape surrounding the first connection electrode CTE1. For example, the second connection electrode CTE2 may be formed in a U-shape on a plane. The first and second portions of the second connection electrode CTE2 may be parallel to and correspond to the first connection electrode CTE1, and the third portion thereof may connect the first and second portions. The second connection electrode CTE2 may cross and overlap the first connection portion HBN1 of the bank layer BNL. The second connection electrode CTE2 may be positioned across the first emission area EMA1 and the second emission area EMA2 of the first sub-pixel SPX1. The second connection electrode CTE2 may be used as a cathode electrode of the first light emitting element ED1 positioned in the first light emitting element area EDA1 and the second light emitting element ED2 positioned in the second light emitting element area EDA2. In addition, the second connection electrode CTE2 may be used as an anode electrode of the third light emitting element ED3 positioned in the third light emitting element area EDA3 and the fourth light emitting element ED4 positioned in the fourth light emitting element area EDA4.

[0186] The third connection electrode CTE3 may extend in the first direction DR1 and may cross and overlap the first connection portion HBN1 of the bank layer BNL. The third connection electrode CTE3 may be positioned across the first emission area EMA1 and the second emission area EMA2 of the first subpixel SPX1. The third connection electrode CTE3 may serve as a cathode electrode of the fourth light emitting element ED4 positioned in the fourth light emitting element area EDA4 and the third light emitting element ED3 positioned in the third light emitting element area EDA3.

[0187] Among the light emitting elements ED, the first light emitting element ED1 and the fourth light emitting element ED4 may be positioned in the first emission area EMA1, and the second light emitting element ED2 and the third light emitting element ED3 may be positioned in the second emission area EMA2. The first emission area EMA1 and the second emission area EMA2 may be positioned adjacent to each other with the bank layer BNL interposed therebetween. Therefore, the first light emitting element ED1 and the fourth light emitting element ED4 may be positioned adjacent to the second light emitting element ED2 and the third light emitting element ED3 with the bank layer BNL interposed therebetween.

[0188] According to one or more embodiments, the bank layer BNL may be around the first emission area EMA1 and the sub-area SA of the first sub-pixel SPX1 of the first pixel PX1 and the second emission area EMA2 of the first sub-pixel SPX1 of the second pixel PX2 (for example, may surround the first emission area EMA1 and the sub-area SA of the first sub-pixel SPX1 of the first pixel PX1 and the second emission area EMA2 of the first sub-pixel SPX1 of the second pixel PX2). The sub-area SA may not overlap with the bank layer BNL and the light emitting element ED.

[0189] Reference Fig.14 , the light emitting element ED may be sprayed (or applied) in the form of ink to the area separated by the bank layer BNL by an inkjet printing process. The solvent and the light emitting element ED are included in the ink, and the possibility that the light emitting element ED is not included in the ink is very low. For example, in the area separated by the bank layer BNL, the light emitting element ED may not be positioned in the fourth light emitting element area EDA4 of the first sub-pixel SPX1 of the first pixel PX1 and the third light emitting element area EDA3 of the first sub-pixel SPX1 of the second pixel PX2.

[0190] In this case, because the second connection electrode CTE2 and the third connection electrode CTE3 of the first subpixel SPX1 of the first pixel PX1 are positioned to span the third light-emitting element area EDA3 and the fourth light-emitting element area EDA4, even if the light-emitting element is not positioned in the fourth light-emitting element area EDA4, the driving current can flow through the third light-emitting element ED3 positioned in the third light-emitting element area EDA3, and the first subpixel SPX1 of the first pixel PX1 can emit light normally.

[0191] Similarly, because the second connection electrode CTE2 and the third connection electrode CTE3 of the first subpixel SPX1 of the second pixel PX2 are positioned across the third light-emitting element area EDA3 and the fourth light-emitting element area EDA4, even if the light-emitting element is not positioned in the third light-emitting element area EDA3, the driving current can flow through the fourth light-emitting element ED4 positioned in the fourth light-emitting element area EDA4, and the first subpixel SPX1 of the second pixel PX2 can emit light normally.

[0192] In the display device 10 according to one or more embodiments, the bank layer BNL may be formed to surround a portion of each of two sub-pixels SPXn adjacent to each other in the first direction DR1. Therefore, even when the light emitting element ED is not positioned in the light emitting element area EDA of the sub-pixel SPXn, the driving current may flow to other light emitting element areas of the corresponding sub-pixel SPXn, thereby preventing or reducing the occurrence of dark spots.

[0193] In summarizing the detailed description, it will be appreciated by those skilled in the art that many changes and modifications may be made to the embodiments without departing substantially from the principles of the present disclosure. Therefore, the embodiments of the present disclosure are used in a general and descriptive sense only and not for the purpose of limitation.

Claims

1. A display device, characterized in that: The display device comprises: a substrate including a first pixel and a second pixel adjacent to each other in a first direction, the first pixel including a sub-pixel, and the second pixel including a sub-pixel; A first electrode and a second electrode, which are above the substrate and extend in the first direction, the first electrode and the second electrode being in the sub-pixel; a first insulating layer, over the first electrode and the second electrode; a light emitting element, between the first electrode and the second electrode and above the first insulating layer; a bank layer over the first insulating layer and dividing a first emission region and a second emission region of one of the sub-pixels and dividing a sub-region of the first pixel and a sub-region of the second pixel; and a first connection electrode and a second connection electrode, wherein in the sub-pixel, the first connection electrode is connected to a first end of the light-emitting element, and the second connection electrode is connected to a second end of the light-emitting element, The bank layer is around the first emission region and the sub-region of the sub-pixel of the first pixel and the second emission region of the sub-pixel of the second pixel.

2. The display device according to claim 1, characterized in that The bank layer comprises: a first extending portion and a second extending portion extending in the first direction and spaced apart in a second direction intersecting the first direction; and The first connecting portion and the second connecting portion connect the first extending portion and the second extending portion and are spaced apart from each other in the first direction.

3. The display device according to claim 2, characterized in that: The first extension portion is on one side of the sub-pixel of the first pixel and the second pixel, and The second extension portion is located at the other side of the sub-pixel of the first pixel and the second pixel.

4. The display device according to claim 2, characterized in that: The first connection portion is between the first emission region and the second emission region of the subpixel of the first pixel in the subpixel of the first pixel, and wherein the first connection electrode of the sub-pixel of the first pixel does not overlap with the first connection portion, and The second connection electrode of the sub-pixel of the first pixel overlaps with the first connection portion.

5. The display device according to claim 2, characterized in that: The second connection portion is between the first emission region and the second emission region of the sub-pixel of the second pixel in the sub-pixel of the second pixel, and wherein the first connection electrode of the sub-pixel of the second pixel does not overlap with the second connection portion, and The second connection electrode of the sub-pixel of the second pixel overlaps with the second connection portion.

6. The display device according to claim 2, characterized in that: The first extension portion, the second extension portion, the first connection portion, and the second connection portion are around the second emission region and the sub-region of the sub-pixel of the first pixel and the first emission region of the sub-pixel of the second pixel, and The sub-region of the sub-pixel of the first pixel is between the second emission region of the sub-pixel of the first pixel and the first emission region of the sub-pixel of the second pixel.

7. The display device according to claim 6, characterized in that: The light emitting elements are in the sub-pixels of the first pixel and the second pixel and include a first light emitting element and a second light emitting element, and The first light emitting element and the second light emitting element do not overlap with the first connection portion and the second connection portion of the bank layer.

8. A display device, characterized in that: The display device comprises: a substrate including a first sub-pixel and a second sub-pixel spaced apart from each other in a first direction; a bank layer, which is above the substrate and divides the first emission region and the second emission region of the first sub-pixel and the first emission region and the second emission region of the second sub-pixel; a first connection electrode, a second connection electrode, and a third connection electrode in the first sub-pixel and the second sub-pixel and extending across the first emission region and the second emission region; and A light emitting element is disposed above the substrate and between the first connection electrode and the second connection electrode and between the second connection electrode and the third connection electrode, The first connecting electrode, the second connecting electrode and the third connecting electrode cross and overlap the bank layer.

9. The display device according to claim 8, characterized in that: The bank layer is around the first emission region of the first sub-pixel and the second emission region of the second sub-pixel, wherein, in the first sub-pixel and the second sub-pixel, the light-emitting element includes a first light-emitting element and a second light-emitting element between the first connecting electrode and the second connecting electrode, and a third light-emitting element and a fourth light-emitting element between the second connecting electrode and the third connecting electrode, and wherein the first light emitting element and the fourth light emitting element are in the first emission region, and Wherein, the second light emitting element and the third light emitting element are in the second emission area.

10. The display device according to claim 8, characterized in that: The display device further includes a sub-region between the first emission region of the first sub-pixel and the second emission region of the second sub-pixel and not overlapping the bank layer and the light emitting element.

Images