Test structure for doped polycrystalline silicon layer of solar cell and silicon wafer

Abstract

The utility model relates to a test structure for a doped polycrystalline silicon layer of a solar cell and a silicon wafer. The test structure comprises a to-be-tested main body and an electrode main body. The to-be-tested main body comprises a silicon substrate, a passivation dielectric layer and a doped polycrystalline silicon layer which are stacked in sequence, and the passivation dielectric layer is located between the silicon substrate and the doped polycrystalline silicon layer; and the electrode main body is located at the corner position of the main body to be detected, penetrates through the doped polycrystalline silicon layer and is in contact with the passivation dielectric layer. The passivation dielectric layer can enable the electrode main body not to contact with the silicon substrate after penetrating through the doped polycrystalline silicon layer, so that a current conduction path is prevented from being formed between the doped polycrystalline silicon layer and the silicon substrate, parallel connection between the doped polycrystalline silicon layer and the silicon substrate is avoided, an insulation effect can be achieved, the doped polycrystalline silicon layer is prevented from being short-circuited by the silicon substrate, and the service life of the electrode main body is prolonged. The current path meets the Hall effect test, so that the electrode main body is matched with a Hall effect tester to test Hall data such as carrier concentration and carrier mobility of the doped polycrystalline silicon layer.

Description

Technical Field

[0001] The present application relates to the field of photovoltaic technology, and in particular to a test structure of a doped polysilicon layer of a solar cell and a silicon wafer. Background Art

[0002] The doped polysilicon layer (poly layer) plays an extremely important role in passivation and carrier transport in solar cells, which can improve the photoelectric conversion efficiency of solar cells. The Hall data of the doped polysilicon film layer, such as carrier concentration and carrier mobility, are important evaluation parameters for the passivation and electrical properties of the doped polysilicon film layer. How to accurately characterize the passivation quality and carrier transport effect of the doped polysilicon film layer is an urgent problem to be solved in the current industrial production. Utility Model Content

[0003] Based on this, the present application provides a test structure for a doped polysilicon layer of a solar cell and a silicon wafer.

[0004] A test structure for a doped polysilicon layer of a solar cell, comprising:

[0005] A subject to be tested, comprising a silicon substrate, a passivation dielectric layer and a doped polysilicon layer stacked in sequence, wherein the passivation dielectric layer is located between the silicon substrate and the doped polysilicon layer; and

[0006] The electrode body is located at the corner of the subject to be measured and penetrates the doped polysilicon layer to contact the passivation dielectric layer.

[0007] In one embodiment, the electrode body includes a first end and a second end opposite to each other along the thickness direction of the doped polysilicon layer, at least a portion of the surface of the electrode body located at the first end is exposed outside the surface of the doped polysilicon layer, and at least a portion of the surface of the electrode body located at the second end is in contact with the passivation dielectric layer.

[0008] In one embodiment, along the thickness direction of the doped polysilicon layer, at least a portion of the first end of the electrode body extends in a direction away from the doped polysilicon layer to protrude out of the doped polysilicon layer.

[0009] In one of the embodiments, along the thickness direction of the doped polysilicon layer, at least a portion of the second end of the electrode body extends toward the interior of the passivation dielectric layer so that the second end is located inside the passivation dielectric layer.

[0010] In one embodiment, the electrode bodies include at least two, and all of the electrode bodies are spaced apart from each other and arranged at corners of the subject to be measured.

[0011] In one embodiment, the subject to be measured is square, and there are at least four electrode bodies, wherein the four electrode bodies are disposed at four corners of the subject to be measured.

[0012] In one of the embodiments, along a direction perpendicular to the thickness of the doped polysilicon layer, a plurality of the electrode bodies are electrically connected at least through the doped polysilicon layer.

[0013] In one embodiment, the passivation dielectric layer is a silicon dioxide layer;

[0014] And / or, the electrode body is a silver electrode;

[0015] And / or, the test structure is used to measure carrier mobility and doping concentration in the doped polysilicon layer.

[0016] In one embodiment, the thickness of the silicon substrate is 50 μm to 200 μm;

[0017] And / or, the thickness of the passivation dielectric layer is 10nm ~ 1000nm;

[0018] And / or, the thickness of the doped polysilicon layer is 10 nm to 200 nm;

[0019] And / or, when the subject to be measured is square, the width of the subject to be measured is 10 mm to 15 mm;

[0020] And / or, the number of the subjects to be tested is 1 to 100.

[0021] In a second aspect, a silicon wafer includes a plurality of test structures as described in the first aspect distributed in an array.

[0022] In the above test structure, the passivation dielectric layer is arranged between the silicon substrate and the doped polysilicon layer, which can prevent the electrode body from contacting the silicon substrate after penetrating the doped polysilicon layer, thereby avoiding the formation of a current conduction path between the doped polysilicon layer and the silicon substrate, playing an insulating effect, avoiding the doped polysilicon layer from being short-circuited by the silicon substrate, and making the current path meet the Hall effect test, so that the electrode body cooperates with the Hall effect tester to test Hall data such as the carrier concentration and carrier mobility of the doped polysilicon layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 A top view of a silicon wafer provided in an embodiment of the present application.

[0024] Figure 2 A top view of a test structure provided in an embodiment of the present application.

[0025] Figure 3A cross-sectional view of a test structure provided in an embodiment of the present application.

[0026] Explanation of the accompanying drawings: 100, silicon wafer; 10, test structure; 1, subject to be tested; 11, silicon substrate; 111, first surface; 112, second surface; 12, passivation dielectric layer; 121, third surface; 122, fourth surface; 13, doped polysilicon layer; 131, fifth surface; 132, sixth surface; 131, groove; 14, first edge; 15, second edge; 16, third edge; 17, fourth edge; 2, electrode body; 21, first end; 22, second end; 23, first electrode body; 24, second electrode body; 25, third electrode body; 26, fourth electrode body. DETAILED DESCRIPTION

[0027] In order to make the above-mentioned purposes, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are described in detail below in conjunction with the accompanying drawings. In the following description, many specific details are set forth to facilitate a full understanding of the present application. However, the present application can be implemented in many other ways different from those described herein, and those skilled in the art can make similar improvements without violating the connotation of the present application, so the present application is not limited by the specific embodiments disclosed below.

[0028] The doped polysilicon layer (poly layer) plays an extremely important role in passivation and carrier transport in solar cells, which can improve the photoelectric conversion efficiency of solar cells. Hall resistance, resistivity, carrier concentration, and carrier mobility are important evaluation parameters for the passivation effect and electrical properties of the doped polysilicon layer. Current testing equipment can only characterize parameters such as the film thickness and resistance of the doped polysilicon layer, which affects the accurate judgment of the performance of solar cells.

[0029] Based on the above issues, first of all, please refer to Figure 2 The present application embodiment provides a test structure 10, including a subject to be tested 1 and a plurality of electrode bodies 2. Figure 3The subject 1 to be tested includes a silicon substrate 11, a passivation dielectric layer 12 and a doped polysilicon layer 13 stacked in sequence, the passivation dielectric layer 12 is located between the silicon substrate 11 and the doped polysilicon layer 13, and the electrode body 2 is located at the corner of the subject 1 to be tested, and penetrates the doped polysilicon layer 13 and contacts the passivation dielectric layer 12. In the above test structure 10, the passivation dielectric layer 12 is arranged between the silicon substrate 11 and the doped polysilicon layer 13, so that the electrode body 2 does not contact the silicon substrate 11 after penetrating the doped polysilicon layer 13, thereby avoiding the formation of a current conduction path between the doped polysilicon layer 13 and the silicon substrate 11, avoiding the parallel connection between the doped polysilicon layer 13 and the silicon substrate 11, and playing an insulating effect, thereby avoiding the doped polysilicon layer 13 from being short-circuited by the silicon substrate 11, so that the current path meets the test of the Hall effect, so that the electrode body 2 cooperates with the Hall effect tester to test the Hall data such as the carrier concentration and carrier mobility of the doped polysilicon layer 13.

[0030] When testing the doped polysilicon layer 13, the Hall effect tester determines the Hall resistance, resistivity, carrier concentration and carrier mobility by applying a magnetic field and measuring the Hall voltage. Specifically, an external magnetic field perpendicular to the current direction is applied to the doped polysilicon layer 13, and the external magnetic field deflects the carriers in the doped polysilicon layer 13, so that the doped polysilicon layer 13 generates a Hall electric field, and the Hall electric field generates a Hall voltage. Combined with parameters such as current density and magnetic field strength, the Hall resistance, resistivity, carrier concentration and carrier mobility in the doped polysilicon layer 13 can be determined.

[0031] See also Figure 1 , multiple test structures 10 may be tested to reduce test errors. In some embodiments, the number of test structures 10 is 1 to 100. For example, the number may be 4, 9, 16, 25, 36, 64, 81, etc. In order to reduce test variables, the outline dimensions and outline sizes of the multiple test structures 10 are kept consistent.

[0032] See also Figure 2 , the outline size and outline shape of the silicon substrate 11, the passivation dielectric layer 12 and the doped polysilicon layer 13 are consistent, with unified size, which is convenient for calculation and analysis, and is conducive to improving the accuracy of the test results. The silicon substrate 11, the passivation dielectric layer 12 and the doped polysilicon layer 13 can be square, rectangular, circular, diamond or bridge-shaped at the same time. Preferably, the shape of the above-mentioned layers is square, and the side length of each layer is 10mm to 15mm, so that the subject to be tested 1 is also square, and its width is also 10mm to 15mm. The square subject to be tested 1 can further improve the uniformity of current distribution. The side length can be, for example, 10mm, 11mm, 12mm, 13mm, 14mm, 15mm.

[0033] The silicon substrate 11 can be an N-type silicon substrate or a P-type silicon substrate. The silicon substrate 11 of the present application is a polished silicon substrate to reduce defects and impurities on the surface of the subject 1 to be tested. The flat surface of the polished silicon substrate can evenly distribute the current to the entire surface of the subject 1 to be tested, and can also accurately measure the resistance value in each direction and position, reduce errors, and make the Hall effect test results more accurate and reliable.

[0034] In some embodiments, the thickness of the silicon substrate 11 is 50 μm to 200 μm, for example, 50 μm, 60 μm, 70 μm, 100 μm, 120 μm, 150 μm, 180 μm, 200 μm, etc.

[0035] Optionally, the passivation dielectric layer 12 may be a tunneling oxide layer. The tunneling oxide layer may be an aluminum oxide layer, a silicon dioxide layer, a silicon nitride layer or a zinc oxide layer. The tunneling oxide layer can reduce the recombination of carriers and improve the open circuit voltage and fill factor of the solar cell. The passivation dielectric layer 12 may also be a composite of a tunneling oxide layer and an intrinsic non-polycrystalline silicon layer, wherein the intrinsic non-polycrystalline silicon layer is disposed between the silicon substrate 11 and the tunneling oxide layer, and the tunneling oxide layer is disposed between the intrinsic non-polycrystalline silicon layer and the doped polycrystalline silicon layer 13. The intrinsic non-polycrystalline silicon layer can cooperate with the tunneling oxide layer to further increase the light absorption and current collection capabilities of the solar cell.

[0036] In some embodiments, the thickness of the passivation dielectric layer 12 is 10 nm to 1000 nm. For example, it can be 10 nm, 20 nm, 30 nm, 50 nm, 100 nm, 200 nm, 500 nm, 800 nm, 1000 nm, etc. When the thickness of the passivation dielectric layer 12 is less than 10 nm, its insulation effect will be affected. When the thickness of the passivation dielectric layer 12 is greater than 1000 nm, the test time and test cost will be increased.

[0037] The doping degree of the doped polysilicon layer 13 may be heavy doping or light doping. The doping type may be N-type doping or P-type doping. Exemplarily, when the substrate is P-type doped, the doped polysilicon layer 13 may be an N-type doped polysilicon layer; when the substrate is N-type doped, the doped polysilicon layer 13 may be a P-type doped polysilicon layer for forming a PN junction.

[0038] In some embodiments, the thickness of the doped polysilicon layer 13 is 10 nm to 200 nm. For example, it can be 10 nm, 20 nm, 30 nm, 50 nm, 100 nm, 150 nm or 200 nm. If the thickness of the doped polysilicon layer 13 is less than 10 nm, its resistance will be too large, making it difficult to test the results. If the thickness is greater than 200 nm, the test time and test cost will increase.

[0039] Preferably, the thickness of the passivation dielectric layer 12 is greater than the thickness of the doped polysilicon layer 13, so as to reduce the electrode penetrating the passivation dielectric layer 12 to contact the silicon substrate 11. The electrode body 2 is prepared by high-temperature sintered silver paste, and the thick passivation dielectric layer 12 provides sufficient burn-through buffer medium for the high-temperature silver paste, so that the silver paste will not burn through the passivation dielectric layer 12 after high-temperature sintering, and further avoid the formation of a conductive path between the doped polysilicon layer 13 and the silicon substrate 11.

[0040] See also Figure 2 In some embodiments, the number of electrode bodies 2 is at least four, wherein the four electrode bodies 2 are disposed at the four corners of the subject 1 to be measured, which can avoid current concentration, reduce excessive current density, and disperse the current to make the current density at various locations of the subject 1 to be measured more uniform, thereby improving the measurement accuracy.

[0041] See also Figure 2 , the subject to be tested 1 includes a first side 14, a second side 15, a third side 16 and a fourth side 17 connected to each other. The first side 14 and the third side 16 are arranged opposite to each other, and the second side 15 and the fourth side 17 are arranged opposite to each other. The four electrode bodies 2 are respectively a first electrode body 232, a second electrode body 242, a third electrode body 252 and a fourth electrode body 262. The first electrode body 23 is arranged at the angle formed by the first side 14 and the second side 15, and the center of the first electrode body 23 has the same first spacing with the first side 14 and the second side 15. The second electrode body 24 is arranged at the angle formed by the second side 15 and the third side 16, and the center of the second electrode body 24 has the same second spacing with the second side 15 and the third side 16. The third electrode body 25 is arranged at the angle formed by the third side 16 and the fourth side 17, and the center of the third electrode body 25 has the same third spacing with the second side 15 and the third side 16. The fourth electrode body 26 is disposed at the angle formed by the fourth side 17 and the first side 14, and the center of the fourth electrode body 26 has the same fourth spacing with the fourth side 17 and the first side 14. The first spacing, the second spacing, the third spacing and the fourth spacing are equal.

[0042] See also Figure 3 The silicon substrate 11 has a relative first surface 111 and a second surface 112 along its own thickness direction, the passivation dielectric layer 12 has a relative third surface 121 and a fourth surface 122 along its own thickness direction, the third surface 121 is in contact with the second surface 112, the doped polysilicon layer 13 has a relative fifth surface 131 and a sixth surface 132 along its own thickness direction, the fifth surface 131 is in contact with the fourth surface 122, and the doped polysilicon layer 13 penetrates the fifth surface 131 and the sixth surface 132.

[0043] See also Figure 3In some embodiments, the electrode body 2 includes a first end 21 and a second end 22 opposite to each other along the thickness direction of the doped polysilicon layer 13, and at least a portion of the surface of the electrode body 2 at the first end 21 is exposed relative to the doped polysilicon layer 13 to facilitate electrical coupling with the Hall effect tester. At least a portion of the surface of the electrode body 2 at the second end 22 is in contact with the passivation dielectric layer 12 to achieve insulation between the doped polysilicon layer 13 and the silicon substrate 11.

[0044] See also Figure 3 , the portion of the electrode body 2 located at the first end 21 has the following configuration modes but is not limited thereto: the surface of the electrode body 2 located at the first end 21 is flush with the sixth surface 132 of the doped polysilicon layer 13. Alternatively, the surface of the electrode body 2 located at the first end 21 is recessed toward the inside of the doped polysilicon layer 13 and is located between the fifth surface 131 and the sixth surface 132. Alternatively, in some embodiments, along the thickness direction of the doped polysilicon layer 13, at least a portion of the first end 21 of the electrode body 2 extends in a direction away from the doped polysilicon layer 13 to protrude outside the sixth surface 132 of the doped polysilicon layer 13 for ease of testing.

[0045] See also Figure 3 The portion of the electrode body 2 at the second end 22 has the following configurations but is not limited thereto: the surface of the electrode body 2 at the second end 22 is flush with the fourth surface 122 of the passivation dielectric layer 12. Alternatively, the surface of the second end 22 is located between the third surface 121 and the fourth surface 122 of the passivation dielectric layer 12, which can ensure that the electrode is fully cured at high temperature and avoids contact with the silicon substrate 11.

[0046] See also Figure 3 In some embodiments, along the thickness direction perpendicular to the subject 1 to be tested, a plurality of electrode bodies 2 are electrically connected at least through the doped polysilicon layer 13, which can improve the current conduction effect of the doped polysilicon layer 13. When the surface of the second end 22 of the electrode body 2 is flush with the fourth surface 122 of the passivation dielectric layer 12, the electrode bodies 2 are connected through the doped polysilicon layer 13. When the surface of the second end 22 of the electrode body 2 is located between the third surface 121 and the fourth surface 122 of the passivation dielectric layer 12, the electrode bodies 2 are connected through the doped polysilicon layer 13 and the passivation dielectric layer 12.

[0047] See also Figure 1In a second aspect, an embodiment of the present application further provides a silicon wafer 100, at least a portion of which includes a silicon substrate 11, a passivation dielectric layer 12, a doped polysilicon layer 13, and an electrode body 2. The silicon wafer 100 includes a plurality of test structures 10 as in the first aspect distributed in an array. The test structures 10 are distributed in an array on the silicon wafer 100 along a first direction (direction A) and a second direction (direction B), the first direction and the second direction are located on the surface of the silicon wafer 100, and the second direction is configured as a direction perpendicular to the first direction. The number of test structures 10 arrayed along the first direction and the second direction is the same. The silicon wafer 100 can be prepared into a plurality of test structures 10 by laser cutting or grinding.

[0048] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0049] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.

Claims

1. A test structure (10) for a doped polysilicon layer of a solar cell, used for testing Hall data, characterized in that: include: A subject to be tested (1) comprises a silicon substrate (11), a passivation dielectric layer (12) and a doped polysilicon layer (13) stacked in sequence, wherein the passivation dielectric layer (12) is located between the silicon substrate (11) and the doped polysilicon layer (13); as well as The electrode body (2) is located at a corner of the subject to be measured (1), and penetrates the doped polysilicon layer (13) to contact the passivation dielectric layer (12).

2. The test structure (10) according to claim 1, characterized in that The electrode body (2) comprises a first end (21) and a second end (22) which are opposite to each other along the thickness direction of the doped polysilicon layer (13); at least a portion of the surface of the electrode body (2) located at the first end (21) is exposed outside the surface of the doped polysilicon layer (13); and at least a portion of the surface of the electrode body (2) located at the second end (22) is in contact with the passivation dielectric layer (12).

3. The test structure (10) according to claim 2, characterized in that Along the thickness direction of the doped polysilicon layer (13), at least part of the first end (21) of the electrode body (2) extends in a direction away from the doped polysilicon layer (13) so as to protrude outside the doped polysilicon layer (13).

4. The test structure (10) according to claim 2, characterized in that Along the thickness direction of the doped polysilicon layer (13), at least part of the second end (22) of the electrode body (2) extends toward the interior of the passivation dielectric layer (12), so that the second end (22) is located inside the passivation dielectric layer (12).

5. The test structure (10) according to claim 1, characterized in that The electrode bodies (2) include at least two, and all of the electrode bodies (2) are arranged at intervals from each other at the corners of the subject to be measured (1).

6. The test structure (10) according to claim 5, characterized in that The subject to be measured (1) is square, and there are at least four electrode subjects (2), wherein the four electrode subjects (2) are arranged at four corners of the subject to be measured (1).

7. The test structure (10) according to claim 1, characterized in that Along a thickness direction perpendicular to the doped polysilicon layer (13), a plurality of the electrode bodies (2) are electrically connected at least through the doped polysilicon layer (13).

8. The test structure (10) according to any one of claims 1 to 7, characterized in that The passivation dielectric layer (12) is a silicon dioxide layer; And / or, the electrode body (2) is a silver electrode; And / or, the test structure (10) is used to measure carrier mobility and doping concentration in the doped polysilicon layer (13).

9. The test structure (10) according to any one of claims 1 to 7, characterized in that: The thickness of the silicon substrate (11) is 50 μm to 200 μm; And / or, the thickness of the passivation dielectric layer (12) is 10nm~1000nm; And / or, the thickness of the doped polysilicon layer (13) is 10 nm to 200 nm; And / or, when the subject to be measured (1) is square, the width of the subject to be measured (1) is 10 mm to 15 mm; And / or, the number of the subjects to be tested (1) is 1 to 100.

10. A silicon wafer (100), characterized in that: The invention comprises a plurality of test structures (10) as claimed in any one of claims 1 to 9 distributed in an array.

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