Chip packaging structure

Abstract

The utility model provides a chip packaging structure. The chip packaging structure includes: a substrate; a chip stacking structure, which is located on the surface of the substrate, and the chip stacking structure includes a plurality of chip layers stacked in sequence in a direction perpendicular to the surface of the substrate, each chip layer includes a chip and a support layer surrounding the side of the chip, and on one side of the chip stacking structure, the plurality of chip layers are arranged in a stepped manner, and the latter chip layer of two adjacent chip layers exposes part of the upper surface of the chip in the former chip layer, and on the other side of the chip stacking structure, the chip of the latter chip layer has a suspended part relative to the chip of the former chip layer, and the support layer of the former chip layer supports the suspended part and the support layer of the chip of the latter chip layer. The above technical solution sets a support layer in the chip layer to support the suspended part of the chip, so as to avoid abnormalities such as chip jumping or solder joint detachment during the wire bonding process of the stacked chips.

Description

Technical Field

[0001] The utility model relates to the field of chip packaging, in particular to a chip packaging structure. Background Art

[0002] Traditional packaging can achieve the purpose of expanding storage capacity by stacking multiple layers of chips. However, since the multi-layer chip stacking structure is composed of chips stacked together, the chip stacking structure will cause chip jumping during wire bonding due to the lack of support for the suspended part of the chip, resulting in abnormalities such as solder joints falling off. Therefore, the number of stacking layers is limited by the suspension distance, which greatly reduces the utilization rate of the substrate and limits the increase in storage capacity.

[0003] Therefore, how to improve the stability of chip stacking packaging, reduce the restrictions on the number of stacking layers caused by the suspension distance, and improve the utilization rate of the substrate are the problems that need to be solved at present. Summary of the invention

[0004] The technical problem to be solved by the utility model is how to improve the stability of stacked packaging, reduce the restriction of the suspended distance on the number of stacked layers, improve the utilization rate of the substrate, and provide a chip packaging structure.

[0005] In order to solve the above problems, the utility model provides a chip packaging structure, including: a substrate; a chip stacking structure, located on the surface of the substrate, the chip stacking structure includes a plurality of chip layers stacked in sequence along a direction perpendicular to the surface of the substrate, each chip layer includes a chip and a support layer surrounding at least one side of the chip, and the plurality of chip layers are arranged in a stepped manner, the latter chip layer of two adjacent chip layers exposes the welding area of ​​the chip in the previous chip layer, and the latter chip has a suspended portion on the side away from the welding area, and the support layer of the previous chip layer supports the suspended portion of the chip of the latter chip layer; a welding wire, connecting the welding areas of two adjacent chips.

[0006] In some embodiments, all the supporting layers are flush at edges on a side away from the chip.

[0007] In some embodiments, the welding area of ​​the chip has at least one conductive pad, and the bonding wire connects the two adjacent chips by connecting the conductive pads in the two adjacent chips.

[0008] In some embodiments, the support layer in each of the chip layers is in the same layer as the chip.

[0009] In some embodiments, each of the chip layers further includes a film layer located on the lower surface of the chip and the support layer.

[0010] In some embodiments, the support layer of the chip layer having the smallest distance from the substrate surface also surrounds the lower surface of the chip.

[0011] In some embodiments, the adhesive film layer of the chip layer that is at the shortest distance from the surface of the substrate is located on the lower surface of the supporting layer.

[0012] In some embodiments, the support layer surrounds a side of the chip away from the bonding region of the chip.

[0013] In some embodiments, the support layer surrounds a side surface of the chip away from the welding region of the chip and two side surfaces connected to the side surface.

[0014] In some embodiments, the support layer is a pre-molding layer.

[0015] The above technical solution sets a support layer in the chip layer to support the suspended part of the chip, provides good support in the wire bonding process of the chip stacking structure, prevents the chip from shaking, and avoids abnormalities such as chip jumping or solder joint falling off during the wire bonding process of the stacked chip, thereby improving the product yield. At the same time, it also avoids the limitation of the suspension distance on the number of stacking layers and increases the storage capacity.

[0016] It should be understood that the above general description and the detailed description below are only exemplary and explanatory and cannot limit the present invention. The techniques, methods and devices known to ordinary technicians in the relevant field may not be discussed in detail, but in appropriate cases, the techniques, methods and devices should be considered as part of the authorization specification. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the specific implementation of the utility model, the following is a brief introduction to the drawings required for the description of the specific implementation. Obviously, the drawings described below are only some specific implementations of the utility model. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0018] Figure 1 The figure is a schematic diagram of the structure of a chip packaging structure.

[0019] Figure 2 The figure is a schematic diagram of the structure of a chip packaging structure.

[0020] Figure 3A It is a structural schematic diagram of an embodiment of the chip packaging structure of the present invention.

[0021] Figure 3B for Figure 3A Top view of the .

[0022] Figure 4 It is a structural schematic diagram of another embodiment of the chip packaging structure of the present invention. DETAILED DESCRIPTION

[0023] The technical scheme in the embodiment of the utility model will be described clearly and completely below in conjunction with the accompanying drawings. Obviously, the described embodiment is only a part of the embodiment of the utility model, not all of the embodiments. Based on the embodiment of the utility model, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the utility model.

[0024] See also Figure 1-2 , are schematic diagrams of a chip packaging structure. Figure 1-2 As shown in the figure, the chip packaging structure includes: a substrate 10 and a chip 11. When the chip 11 on the top of the multi-layer stacked chips is subjected to the wire bonding process, when the suspended part of the chip 11 is subjected to ultrasonic wire bonding (as shown by the black arrow in the figure), since the suspended part has no support, the chip 11 on the top of the stacked chips may jump during wire bonding. Since the adhesive film is relatively soft, the chip 11 may tilt (as shown in the figure). Figure 1 or when bonding wires, the suspended portion of the chip 11 breaks, causing the solder joint to fall off (as shown in FIG. Figure 2 As shown in FIG. 1 , the chip 11 is damaged. The above two problems limit the number of stacked layers by the suspension distance, greatly reducing the utilization rate of the substrate and limiting the increase of storage capacity.

[0025] In order to solve the above problems, the utility model provides a chip packaging structure to improve the stability of stacked packaging, reduce the limitation of the suspension distance on the number of stacked layers, and improve the utilization rate of the substrate.

[0026] See also Figure 3A to Figure 3B ,in, Figure 3A This is a schematic structural diagram of an embodiment of the chip packaging structure of the present invention. Figure 3B for Figure 3A A top view of the Figure 3A to Figure 3BAs shown, the chip packaging structure includes: a substrate 30, a chip stacking structure 31 and a bonding wire 328. The chip stacking structure 31 is located on the surface of the substrate 30. The chip stacking structure 31 includes a plurality of chip layers 32 stacked in sequence along a direction perpendicular to the surface of the substrate 30, each of the chip layers 32 includes a chip 320 and a support layer 321 surrounding at least one side of the chip 320. The plurality of chip layers 32 are arranged in a stepped manner, and the latter chip layer 32 of two adjacent chip layers 32 exposes the bonding area 327 of the chip 320 in the former chip layer 32, and the latter chip 320 has a suspended portion 329 on a side away from the bonding area 327, and the support layer 321 of the former chip layer 32 supports the suspended portion 329 of the chip 320 of the latter chip layer 32. The bonding wire 328 connects the bonding areas 327 of the two adjacent chips 320.

[0027] The above technical solution sets a support layer in the chip layer to support the suspended part of the chip, provides good support in the wire bonding process of the chip stacking structure, prevents the chip from shaking, and avoids abnormalities such as chip jumping or solder joint falling off during the wire bonding process of the stacked chip, thereby improving the product yield. At the same time, it also avoids the limitation of the suspension distance on the number of stacking layers and increases the storage capacity.

[0028] In some embodiments, the substrate 30 is a substrate for electrically connecting the semiconductor chip to other external devices, and the substrate 30 may include circuit traces in the substrate body of the dielectric material layer. The substrate 30 may also be in the form of a printed circuit board (PCB).

[0029] In some embodiments, the chip 320 may be a memory chip, wherein the memory integrated circuit is such as a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a flash memory device, a magnetic random access memory (MRAM) device, a resistive random access memory (ReRAM) device, a ferroelectric random access memory (FeRAM) device, or a phase change random access memory (PcRAM) device.

[0030] In some embodiments, all the support layers 321 are flush at the edges of a side away from the chip 320 to save space on the surface of the substrate 30 .

[0031] In some embodiments, the welding area 327 of the chip 320 has at least one conductive pad, and the bonding wire 328 connects two adjacent chips 320 by connecting the conductive pads in the two adjacent chips 320. The conductive pad is used to connect to the external circuit to realize the chip function. In the same chip 320, the conductive pad used to connect the previous chip 320 and the conductive pad used to connect the next chip 320 may be the same or different conductive pads.

[0032] In some embodiments, the support layer 321 in each chip layer 32 is in the same layer as the chip 320. The thickness of the support layer 321 is the same as that of the chip 320, which ensures the support strength without increasing the thickness of the chip layer 32, thus saving space.

[0033] In some embodiments, each chip layer 32 further includes a film layer 323, which is located on the lower surface of the chip 320 and the support layer 321. The film layer 323 is used to realize the mounting between adjacent chip layers 32. In this embodiment, the film layer is a die attach film (DAF). The DAF film can effectively isolate the interference between circuits, reduce the mutual interference of signals, and improve the stability and reliability of the overall system. At the same time, the DAF film can also prevent the circuit from being polluted by impurities and dust in the external environment, ensuring the long-term use effect of the device.

[0034] In some embodiments, the support layer 321 surrounds a side surface 326 of the chip 320 away from the welding region 327 of the chip 320 .

[0035] like Figure 3B As shown, in some embodiments, the support layer 321 surrounds the side 326 of the chip 320 away from the welding area 327 of the chip 320 and two side surfaces 325 connected to the side 326. In this embodiment, the two side surfaces 325 connected to the side 326 are two side surfaces 325 perpendicular to the side 326 of the welding area 327 away from the chip 320. The support layer 321 surrounds three sides of the chip 320, providing more reliable wrapping support for the side surfaces of the chip to provide sufficiently high support strength. In other embodiments, the support layer 321 may also only surround the side 326 of the welding area 327 away from the chip 320 and one side surface 325 perpendicular to the side 326 of the welding area 327 away from the chip 320, so as to meet different packaging process requirements.

[0036] In some embodiments, the support layer 321 is a pre-molded layer. The chips 320 are pre-molded and then stacked. The pre-molded layer can provide sufficient support for the suspended portion 329 of the stacked chips 320 to prevent the chips from shaking, thereby avoiding abnormalities such as chip jumping or solder joint detachment during the wire bonding process of the stacked chips, thereby improving the product yield, and also avoiding the limitation of the suspended distance on the number of stacked layers, thereby increasing the storage capacity.

[0037] It is worth noting that the support layer 321 in the present invention is different from the support material filled in the suspended part 329 of the chip 320 after the chip stacking is completed. Compared with the latter, the support layer 321 in the present invention is pre-molded, which can better fill the suspended part 329 of the next chip 320. In addition, the adhesive film layer 323 not only bonds the adjacent chips 320, but also bonds the pre-molded support layer 321. The adhesive film layer 323 further strengthens the stability of the chip 320 and the support layer 321 in the same chip layer 32 to prevent them from falling off.

[0038] In order to further improve the supporting strength of the bottom layer chip, the utility model also provides another embodiment.

[0039] See also Figure 4 , which is a schematic diagram of another embodiment of the chip packaging structure of the utility model. Figure 4 As shown, the chip packaging structure includes: a substrate 40, a chip stacking structure 41 and a bonding wire 428. The chip stacking structure 41 is located on the surface of the substrate 40. The chip stacking structure 41 includes a plurality of chip layers 42 stacked in sequence along a direction perpendicular to the surface of the substrate 40, each of the chip layers 42 includes a chip 420 and a support layer 421 surrounding at least one side of the chip 420. The plurality of chip layers 42 are arranged in a stepped manner, the latter chip layer 42 of two adjacent chip layers 42 exposes the bonding area 427 of the chip 420 in the previous chip layer 42, and the chip 420 of the latter chip layer 42 has a suspended portion 429 relative to the chip 420 of the previous chip layer 42, and the support layer 421 of the previous chip layer 42 supports the suspended portion 429 of the chip 420 of the latter chip layer 42. The bonding wire 428 connects the bonding areas 427 of the two adjacent chips 420.

[0040] This embodiment and Figure 3A to Figure 3BThe embodiment shown is different in that the support layer 421 of the chip layer 42 which is the smallest distance from the surface of the substrate 40 also surrounds the lower surface of the chip 420. At least one side surface and the bottom surface of the bottom chip 420 are encapsulated to improve the support strength of the bottom chip 420 and avoid the connection between the bottom chip 420 and the support layer 421 from breaking during the wire bonding process.

[0041] Accordingly, in some embodiments, the adhesive film layer 423 of the chip layer 42 which is at the shortest distance from the surface of the substrate 40 is located on the lower surface of the support layer 421 .

[0042] In addition, in some embodiments, all the support layers 421 are flush at the edges of a side away from the chip 420 to save space on the surface of the substrate 40 .

[0043] In some embodiments, the support layer 421 in each chip layer 42 is in the same layer as the chip 420. The thickness of the support layer 421 is the same as that of the chip 420, which ensures the support strength without increasing the thickness of the chip layer 42, thus saving space.

[0044] In some embodiments, the support layer 421 is a pre-molded layer. By pre-molding the chips 420 and stacking the pre-molded chips 420, the pre-molded layer can provide sufficient support for the suspended portion 429 of the stacked chips 420 to prevent the chips from shaking, so as to avoid abnormalities such as chip jumping or solder joint falling off during the wire bonding process of the stacked chips, thereby improving the product yield, and also avoiding the limitation of the suspended distance on the number of stacked layers, thereby increasing the storage capacity.

[0045] It is worth noting that the support layer 421 in the present invention is different from the support material filled in the suspended part 429 of the chip 420 after the chip stacking is completed. Compared with the latter, the support layer 421 in the present invention is pre-molded, which can better fill the suspended part 429 of the chip 420 after bonding. In addition, the adhesive film layer 423 not only bonds the chip 420, but also bonds the pre-molded support layer 421. The adhesive film layer 423 further strengthens the stability of the chip 420 and the support layer 421 in the same chip layer 42 to prevent them from falling off.

[0046] The above technical solution sets a support layer in the chip layer to support the suspended part of the chip, provides good support in the wire bonding process of the chip stacking structure, prevents the chip from shaking, and avoids abnormalities such as chip jumping or solder joint falling off during the wire bonding process of the stacked chip, thereby improving the product yield. At the same time, it also avoids the limitation of the suspension distance on the number of stacking layers and increases the storage capacity.

[0047] It should be noted that references in the specification to "an embodiment", "an embodiment", "an exemplary embodiment", "some embodiments", etc. indicate that the described embodiment may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment. In addition, when a particular feature, structure, or characteristic is described in conjunction with an embodiment, whether or not explicitly described, it is within the knowledge of a technician in the relevant art to implement such feature, structure, or characteristic in conjunction with other embodiments.

[0048] Typically, a term can be understood at least in part from usage in context. For example, the term "one or more" as used herein depends at least in part on the context and can be used to describe any feature, structure or characteristic in a singular sense, or can be used to describe a combination of features, structures or features in a plural sense. Similarly, terms such as "one", "a" or "the" can also be understood to express singular usage or to express plural usage, depending at least in part on the context. In addition, the term "based on" can be understood to not necessarily be intended to express a set of exclusive factors, but can alternatively, also at least in part depending on the context, allow for the presence of other factors that are not necessarily explicitly described. It should also be noted in this specification that "connected / coupled" refers not only to the direct coupling of one component to another component, but also to the indirect coupling of one component to another component through an intermediate component.

[0049] It should be noted that the terms "including" and "having" and their variations involved in the documents of the present utility model are intended to cover non-exclusive inclusions. The terms "first", "second", etc. are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. Unless the context clearly indicates otherwise, it should be understood that the data used in this way can be interchanged under appropriate circumstances. In addition, the embodiments of the present utility model and the features in the embodiments can be combined with each other unless there is a conflict. In addition, in the above description, the description of well-known components and technologies is omitted to avoid unnecessary confusion of the concepts of the present utility model. In the above-mentioned embodiments, each embodiment focuses on the differences from other embodiments, and the same / similar parts between the embodiments can be referred to each other.

[0050] The above is only a preferred embodiment of the present invention. It should be pointed out that ordinary technicians in this technical field can make several improvements and modifications without departing from the principle of the present invention. These improvements and modifications should also be regarded as the protection scope of the present invention.

Claims

1. A chip packaging structure, characterized in that: include: substrate; A chip stacking structure is located on the surface of the substrate, the chip stacking structure comprises a plurality of chip layers stacked in sequence along a direction perpendicular to the surface of the substrate, each of the chip layers comprises a chip and a support layer surrounding at least one side of the chip, each of the chip layers further comprises a film layer located on the lower surface of the chip and the support layer, the plurality of chip layers are arranged in a stepped manner, the latter chip layer of two adjacent chip layers exposes the welding area of ​​the chip in the former chip layer, and the latter chip has a suspended portion on a side away from the welding area, and the support layer of the former chip layer supports the suspended portion of the chip in the latter chip layer; A bonding wire connects the bonding areas of two adjacent chips.

2. The chip packaging structure according to claim 1, characterized in that: All the support layers are flush at the edges of a side away from the chip.

3. The chip packaging structure according to claim 1, characterized in that: The welding area of ​​the chip has at least one conductive pad, and the welding wire connects the two adjacent chips by connecting the conductive pads in the two adjacent chips.

4. The chip packaging structure according to claim 1, characterized in that: The support layer in each chip layer is in the same layer as the chip.

5. The chip packaging structure according to claim 1, characterized in that: The support layer of the chip layer having the smallest distance from the substrate surface also surrounds the lower surface of the chip.

6. The chip packaging structure according to claim 5, characterized in that: The adhesive film layer of the chip layer which is at the shortest distance from the surface of the substrate is located on the lower surface of the supporting layer.

7. The chip packaging structure according to claim 1, characterized in that: The supporting layer surrounds a side of the chip away from the bonding area of ​​the chip.

8. The chip packaging structure according to claim 1, characterized in that: The supporting layer surrounds a side surface of the chip away from the welding area of ​​the chip and two side surfaces connected to the side surface.

9. The chip packaging structure according to claim 1, characterized in that: The supporting layer is a pre-plastic sealing layer.

Images